WO2018099066A1 - Method of fabricating thin film transistor, thin film transistor, and display apparatus - Google Patents

Method of fabricating thin film transistor, thin film transistor, and display apparatus Download PDF

Info

Publication number
WO2018099066A1
WO2018099066A1 PCT/CN2017/091081 CN2017091081W WO2018099066A1 WO 2018099066 A1 WO2018099066 A1 WO 2018099066A1 CN 2017091081 W CN2017091081 W CN 2017091081W WO 2018099066 A1 WO2018099066 A1 WO 2018099066A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate insulating
insulating layer
channel region
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/091081
Other languages
English (en)
French (fr)
Inventor
Zhen Song
Wei Li
Guoying Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2018504672A priority Critical patent/JP7045983B2/ja
Priority to US15/741,741 priority patent/US10431668B2/en
Priority to KR1020187002481A priority patent/KR102103428B1/ko
Priority to EP17828831.2A priority patent/EP3549157A4/en
Publication of WO2018099066A1 publication Critical patent/WO2018099066A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to display technology, more particularly, to a method of fabricating a thin film transistor, a thin film transistor, and a display apparatus.
  • Display devices such as liquid crystal display (LCD) and organic light-emitting diode (OLED) have been widely used.
  • LCD and OLED display devices use thin film transistor (TFT) to control pixels in the display panel.
  • TFT thin film transistor
  • Examples of TFT include amorphous silicon TFT, polycrystalline silicon TFT, single crystal silicon TFT, and metal oxide TFT.
  • a thin film transistor may be classified into a top gate type or a bottom gate type.
  • the present invention provides a method of fabricating a thin film transistor, comprising forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, on a base substrate; forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer is formed in a region outside that corresponding to the channel region; forming an insulating material layer on a side of the first photoresist layer distal to the base substrate; forming a first conductive metal material layer on a side of the insulating material layer distal to the first photoresist layer; and removing the first photoresist layer, the insulating material layer, the first conductive metal material layer, in the region outside that corresponding to the channel region by a lift-off method, a portion of the insulating material layer in a region corresponding to the channel region remains thereby forming a first gate insulating layer, a portion of the first conductive metal material layer in the region corresponding
  • the active layer, the first gate insulating layer, and the gate electrode are formed so that boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially align with edges of the first gate insulating layer and the gate electrode.
  • the active layer, the first gate insulating layer, and the gate electrode are formed so that a projection of the gate electrode on the base substrate substantially overlaps with that of the channel region, the projection of the gate electrode on the base substrate and that of the channel region are substantially coextensive with each other.
  • the method further comprises forming a second gate insulating layer between the channel region of the active layer and the first gate insulating layer, the second gate insulating layer is formed to be in contact with the channel region of the active layer; wherein the second gate insulating layer is formed to have a resistivity higher than that of the first gate insulating layer; a projection of the second gate insulating layer on the base substrate substantially overlaps with that of the channel region, the projection of the second gate insulating layer on the base substrate and that of the channel region are substantially coextensive with each other.
  • the method further comprises forming a source electrode, a drain electrode, and the second gate insulating layer in a single process, the source electrode and the drain electrode are formed on a side of the active layer distal to the base substrate; wherein forming the source electrode, the drain electrode, and the second gate insulating layer comprises forming a second conductive metal material layer on a side of the active layer distal to the base substrate, the second conductive metal material layer is formed to comprises a first portion in a region corresponding to the source electrode contact region of the active layer, a second portion in a region corresponding to the drain electrode contact region of the active layer, and a third portion in a region corresponding to the channel region of the active layer; forming the first photoresist layer on a side of the second conductive metal material layer distal to the active layer, the first photoresist layer is formed in the region outside that corresponding to the channel region; and oxidizing the third portion of the second conductive metal material layer thereby forming the second gate insulating layer, the first portion
  • the active layer and the second conductive metal material layer are formed in a single patterning process; forming the active layer and the second conductive metal material layer comprises forming a semiconductor material layer on the base substrate; forming a third conductive metal material layer on a side of the semiconductor material layer distal to the base substrate; forming a second photoresist layer on a side of the third conductive metal material layer distal to the semiconductor material layer, the second photoresist layer is formed in a region corresponding to the active layer; removing a portion of the third conductive metal material layer outside a region corresponding to the second photoresist layer thereby forming the second conductive metal material layer; and removing a portion of the semiconductor material layer outside the region corresponding to the second photoresist layer thereby forming the active layer.
  • oxidizing the third portion of the second conductive metal material layer is performed by anodic oxidization, annealing in an oxygen atmosphere, oxygen plasma treatment, or a combination thereof.
  • the second conductive metal material layer is formed using hafnium, or tantalum, or a combination thereof.
  • the second gate insulating layer is formed using Hf x O y , or Ta x O y , Hf x O y N z , or Ta x O y N z , or a combination thereof, x > 0, y > 0, z > 0.
  • the method further comprises etching the second gate insulating layer to reduce a thickness of the second gate insulating layer.
  • the first gate insulating layer is formed using Si x O y , Si x N y , Si x O y N z , or a combination thereof, x > 0, y > 0, z > 0.
  • the present invention provides a thin film transistor comprising an active layer having a channel region, a source electrode contact region, and a drain electrode contact region on a base substrate; a first gate insulating layer on a side of the active layer distal to the base substrate; and a gate electrode on a side of the first gate insulating layer distal to the active layer; wherein boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially align with edges of the first gate insulating layer and the gate electrode.
  • a projection of the gate electrode on the base substrate substantially overlaps with that of the channel region, the projection of the gate electrode on the base substrate and that of the channel region are substantially coextensive with each other.
  • the thin film transistor further comprises a second gate insulating layer between the channel region of the active layer and the first gate insulating layer, the second gate insulating layer is in contact with the channel region of the active layer; wherein the second gate insulating layer has a resistivity higher than that of the first gate insulating layer; and a projection of the second gate insulating layer on the base substrate substantially overlaps with that of the channel region, the projection of the second gate insulating layer on the base substrate and that of the channel region are substantially coextensive with each other.
  • the thin film transistor further comprises a source electrode and a drain electrode made of a metal material comprising M1, M1 is a single metal or a combination of metals; wherein the second gate insulating layer is made of a material comprising M1O m N n , m > 0, n ⁇ 0; the source electrode, the drain electrode, and the second gate insulating layer are in a same layer.
  • M1 comprises hafnium, or tantalum, or a combination thereof; and M1O m N n comprises Hf x O y , or Ta x O y , Hf x O y N z , or Ta x O y N z , or a combination thereof.
  • the source electrode and the drain electrode are on a side of the active layer distal to the base substrate.
  • a projection of the gate electrode on the base substrate substantially overlaps with that of the channel region, the first gate insulating layer, and the second gate insulating layer; and the projection of the gate electrode on the base substrate and those of the channel region, the first gate insulating layer, and the second gate insulating layer are substantially coextensive with each other.
  • a height of a surface of the second gate insulating layer distal to the base substrate relative to a surface of the base substrate is less than a height of a surface of the source electrode and the drain electrode distal to the base substrate relative to the surface of the base substrate.
  • the present invention provides a display apparatus comprising the thin film transistor described herein or fabricated by a method described herein.
  • FIG. 1 is a flow chart illustrating a method of fabricating a thin film transistor in some embodiments according to the present disclosure.
  • FIG. 2 is a schematic diagram illustrating the structure of a thin film transistor in some embodiments according to the present disclosure.
  • FIGs. 3 to 7 illustrates a process of fabricating a thin film transistor in some embodiments according to the present disclosure.
  • the conventional top-gate type thin film transistors have relatively small parasitic capacitance, thus a pixel circuit having a top-gate type thin film transistor has a higher on/off speed.
  • the gate electrode is formed by a wet etching process. Due to the critical dimension bias during the wet etching process, the gate electrode is typically formed to be smaller than the channel region of the thin film transistor, resulting in offset regions on two sides of the channel region of the active layer.
  • the existence of offset regions in the conventional top-gate type thin film transistor results in a higher on/off current ratio and a decreased current during the “on” period of the thin film transistor because the offset regions is in direct contact with and adjacent to the source electrode contact region. Moreover, the existence of offset regions in the conventional top-gate type thin film transistor leads to an increased parasitic resistance in the source terminal and the drain terminal. Further, the existence of offset regions in the conventional top-gate type thin film transistor leads to an increased ohmic contact resistance between the source electrode and the active layer and between the drain electrode and the active layer. To decrease the ohmic contact resistance, the active layer is typically conductorized using high- power helium or hydrogen plasma. However, the active layer conductorization often is not effective in decreasing the ohmic contact resistance.
  • the present disclosure provides, inter alia, a method of fabricating a thin film transistor, a thin film transistor, and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
  • the present disclosure provides a method of fabricating a thin film transistor.
  • FIG. 1 is a flow chart illustrating a method of fabricating a thin film transistor in some embodiments according to the present disclosure. Referring to FIG.
  • the method in some embodiments includes forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, on a base substrate; forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer being in a region outside that corresponding to the channel region; forming an insulating material layer on a side of the first photoresist layer distal to the base substrate; forming a first conductive metal material layer on a side of the insulating material layer distal to the first photoresist layer; and removing the first photoresist layer, the insulating material layer, the first conductive metal material layer, in the region outside that corresponding to the channel region by a lift-off method, a portion of the insulating material layer in a region corresponding to the channel region remains thereby forming a first gate insulating layer, a portion of the first conductive metal material layer in the region corresponding to the channel region remains thereby forming a gate electrode.
  • the method further includes forming a source electrode and a drain electrode.
  • the source electrode and the drain electrode are formed on a side of the active layer distal to the base substrate.
  • the source electrode and the drain electrode are formed on a side of the active layer proximal to the base substrate.
  • the first photoresist layer is formed on a side of the active layer, the source electrode, and the drain electrode distal to the base substrate.
  • the first photoresist layer is formed in the region outside that corresponding to the channel region, e.g., exposing a region corresponding to the channel region of the active layer.
  • the first photoresist layer is formed in a region corresponding to the source electrode contact region and the drain electrode contact region. Boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially align with edges of the first photoresist layer.
  • the insulating material layer and the first conductive metal material layer are sequentially formed on a side of the active layer and the first photoresist layer distal to the base substrate.
  • the gate electrode formed according to the present method self-aligns with the boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially, e.g., the gate electrode self-aligns with the source electrode and the drain electrode, achieving high placement accuracy.
  • the present thin film transistor is substantially free of any offset regions in the active layer, which is observed in the conventional thin film transistor having a gate electrode formed by wet-etching.
  • the present thin film transistor substantially obviates the parasitic resistance introduced by the offset regions.
  • the gate electrode and the first gate insulating layer are formed in a single patterning process, greatly simplifying the fabrication process.
  • the source electrode and the drain electrode abut the channel region, achieving greatly improved electrical characteristics of the thin film transistor.
  • the total resistance between the source electrode and the drain electrode can be minimized as compared to that in the conventional thin film transistors (e.g., by conductorizing the active layer) , thus obviating additional fabrication step such as the active layer conductorization step.
  • the selection of the source electrode material and the drain electrode material is not strictly limited by the ohmic contact resistance between the electrode and the active layer, further lowering the fabrication costs.
  • the active layer, the first gate insulating layer, and the gate electrode are formed so that boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially align with edges of the first gate insulating layer and the gate electrode.
  • the active layer, the first gate insulating layer, and the gate electrode are formed so that a projection of the gate electrode on the base substrate substantially overlaps with that of the channel region, the projection of the gate electrode on the base substrate and that of the channel region are substantially coextensive with each other.
  • a semiconductor material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma-enhanced chemical vapor deposition
  • appropriate semiconductor materials for making the active layer includes, but are not limited to, metal oxides (e.g., IGZO, ITO, IZTO, IGTO, AZO) , amorphous silicon, polycrystalline silicon, etc.
  • the method further includes forming a second gate insulating layer between the channel region of the active layer and the first gate insulating layer.
  • the second gate insulating layer is formed to be in contact with the channel region of the active layer.
  • the second gate insulating layer is formed to have a resistivity higher than that of the first gate insulating layer.
  • a projection of the second gate insulating layer on the base substrate substantially overlaps with that of the channel region, the projection of the second gate insulating layer on the base substrate and that of the channel region are substantially coextensive with each other.
  • the electrical characteristics of the thin film transistor are significantly enhanced.
  • first gate insulating layer Various appropriate insulating materials and various appropriate fabricating methods may be used to make the first gate insulating layer.
  • an insulating material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma-enhanced chemical vapor deposition
  • the first gate insulating layer may be made using a material that is highly oxygen-resistant and moist-resistant.
  • appropriate insulating materials for making the first gate insulating layer include, but are not limited to, Si x O y , Si x N y , Si x O y N z , or a combination thereof.
  • the second gate insulating layer may be formed by oxidizing a metal material thereby forming a metal oxide insulating layer.
  • the oxidation of the metal material may be performed by anodic oxidization, annealing in an oxygen atmosphere, oxygen plasma treatment, or a combination thereof.
  • appropriate insulating materials for making the second gate insulating layer include, but are not limited to, a metal oxide having a high dielectric constant.
  • the second gate insulating layer may be formed using Hf x O y , Ta x O y , or a combination thereof, x > 0, y > 0.
  • the second gate insulating layer made using these metal oxides has a high resistivity.
  • Other metal oxides with high dielectric constant include Zr x O y , Al x O y , La x O y , Y x O y , Ce x O y , and Ti x O y .
  • the second gate insulating layer may be formed by oxynitriding a metal material thereby forming a metal oxynitride insulating layer.
  • the oxynitridation of the metal material may be performed by, e.g., annealing in an oxygen-nitrogen mixed atmosphere, plasma treatment in an oxygen-nitrogen mixed atmosphere, or a combination thereof.
  • appropriate insulating materials for making the second gate insulating layer include, but are not limited to, a metal oxynitride having a high dielectric constant.
  • the second gate insulating layer may be formed using Hf x O y N z , Ta x O y N z , or a combination thereof, x > 0, y > 0, z > 0.
  • metal oxynitrides with high dielectric constant include Zr x O y N z , Al x O y N z , La x O y N z , Y x O y N z , Ce x O y N z , and Ti x O y N z .
  • the method further includes forming a source electrode and a drain electrode.
  • the source electrode, the drain electrode, and the second gate insulating layer are formed in a single process.
  • the source electrode and the drain electrode are formed on a side of the active layer distal to the base substrate.
  • the step of forming the source electrode, the drain electrode, and the second gate insulating layer includes forming a second conductive metal material layer on a side of the active layer distal to the base substrate, the second conductive metal material layer is formed to include a first portion in a region corresponding to the source electrode contact region of the active layer, a second portion in a region corresponding to the drain electrode contact region of the active layer, and a third portion in a region corresponding to the channel region of the active layer; forming the first photoresist layer on a side of the second conductive metal material layer distal to the active layer, the first photoresist layer is formed in the region outside that corresponding to the channel region; and oxidizing the third portion of the second conductive metal material layer thereby forming the second gate insulating layer, the first portion remains substantially unoxidized thereby forming the source electrode, the second portion remains substantially unoxidized thereby forming the drain electrode.
  • the second conductive metal material layer includes a metal material.
  • suitable metal materials for making the second conductive metal material layer include a metal or an alloy, when oxidized or oxynitridized, whose oxides or oxynitrides have a high dielectric constant, e.g., greater than 3.9.
  • the second conductive metal material layer includes hafnium, tantalum, or a combination thereof.
  • the step of oxidizing the third portion of the second conductive metal material layer is performed by anodic oxidization, annealing in an oxygen atmosphere, oxygen plasma treatment, or a combination thereof.
  • the second gate insulating layer has a thickness in a range of approximately 30 nm to approximately 40 nm.
  • the active layer and the second conductive metal material layer are formed in a single patterning process.
  • patterning generally refers to processes of making a pattern.
  • a patterning process typically includes photoresist coating, exposing, developing, etching and photoresist peeling.
  • the step of forming the active layer and the second conductive metal material layer includes forming a semiconductor material layer on the base substrate; forming a third conductive metal material layer on a side of the semiconductor material layer distal to the base substrate; forming a second photoresist layer on a side of the third conductive metal material layer distal to the semiconductor material layer, the second photoresist layer being in a region corresponding to the active layer; removing a portion of the third conductive metal material layer outside a region corresponding to the second photoresist layer thereby forming the second conductive metal material layer; and removing a portion of the semiconductor material layer outside the region corresponding to the second photoresist layer thereby forming the active layer.
  • the active layer and the second conductive metal material layer By forming the active layer and the second conductive metal material layer in a single patterning process, the active layer and the second conductive metal material layer have a same pattern, e.g., a projection of the second conductive metal material layer on the base substrate substantially overlaps with that of the active layer, the projection of the second conductive metal material layer on the base substrate and that of the active layer are substantially coextensive with each other. Subsequently, the third portion of the second conductive metal material layer is oxidized to form the second gate insulating layer, as discussed above.
  • the second gate insulating layer is formed in a process separate from that for the source electrode and the drain electrode.
  • the step of forming the second gate insulating layer includes providing a metal oxide material or a metal oxynitride material, and forming the second gate insulating layer using the metal oxide material or a metal oxynitride material by, e.g., vapor deposition.
  • the second gate insulating layer is formed to be in contact with the channel region of the active layer.
  • the second gate insulating layer is formed using a metal oxide or a metal oxynitride material having a high dielectric constant, e.g., greater than 3.9.
  • the second gate insulating layer may be formed using Hf x O y , Ta x O y , Hf x O y N z , Ta x O y N z , or a combination thereof, x > 0, y > 0, z > 0.
  • the method further includes adjusting a thickness of the second gate insulating layer.
  • the step of adjusting the thickness of the second gate insulating layer includes etching the second gate insulating layer to reduce a thickness of the second gate insulating layer.
  • FIG. 2 is a schematic diagram illustrating the structure of a thin film transistor in some embodiments according to the present disclosure.
  • FIGs. 3 to 7 illustrates a process of fabricating a thin film transistor in some embodiments according to the present disclosure.
  • the fabrication process in some embodiments includes forming a semiconductor material layer 200 on the base substrate 10, forming a third conductive metal material layer 201 on a side of the semiconductor material layer 200 distal to the base substrate 10, and forming a second photoresist layer 30 on a side of the third conductive metal material layer 201 distal to the semiconductor material layer 200.
  • the second photoresist layer 30 is formed in a region corresponding to the active layer.
  • the step of forming the second photoresist layer 30 includes forming a photoresist material layer on a side of the third conductive metal material layer 201 distal to the semiconductor material layer 200, exposing the photoresist material layer using a mask plate having a pattern corresponding to the active layer, and developing the exposed photoresist material layer.
  • the exposed portion of the photoresist material layer (which is outside the region corresponding to the active layer) is removed, the unexposed portion of the photoresist material layer remains, thereby forming the second photoresist layer 30.
  • a portion of the third conductive metal material layer 201 outside a region corresponding to the second photoresist layer 30 is removed thereby forming a second conductive metal material layer 5, and a portion of the semiconductor material layer 200 outside the region corresponding to the second photoresist layer 30 is removed thereby forming the active layer 1.
  • the second conductive metal material layer 5 is made of a first metal such as hafnium, tantalum, or a combination thereof.
  • An oxidized first metal e.g., Hf x O y , Ta x O y , or a combination thereof, has a relatively high dielectric constant and a relatively high resistivity.
  • the process in some embodiments further includes forming a first photoresist layer 20 on a side of the second conductive metal material layer 5 and the active layer 1 distal to the base substrate 10.
  • the first photoresist layer 20 is formed in a region outside that corresponding to the channel region R3, e.g., in a region corresponding to at least the source electrode contact region R1 and the drain electrode contact region R2.
  • the step of forming the first photoresist layer 20 includes forming a photoresist material layer on a side of the second conductive metal material layer 5 and the active layer 1 distal to the base substrate 10, exposing the photoresist material layer using a mask plate having a pattern corresponding to the channel region R3 of the active layer 1, and developing the exposed photoresist material layer.
  • the exposed portion of the photoresist material layer (which corresponding to the channel region R3 of the active layer 1) is removed, the unexposed portion of the photoresist material layer remains, thereby forming the first photoresist layer 20.
  • the second conductive metal material layer 5 includes a first portion in a region corresponding to the source electrode contact region R1 of the active layer 1, a second portion in a region corresponding to the drain electrode contact region R2 of the active layer 1, and a third portion in a region corresponding to the channel region R3 of the active layer 1.
  • the first portion and the second portion of the second conductive metal material layer 5 are covered by the first photoresist layer 20, and the third portion of the second conductive metal material layer 5 is exposed.
  • the third portion of the second conductive metal material layer 5 is then oxidized thereby forming the second gate insulating layer 101, as shown in FIG. 6.
  • the first portion of the second conductive metal material layer 5 remains substantially unoxidized thereby forming the source electrode 2
  • the second portion of the second conductive metal material layer 5 remains substantially unoxidized thereby forming the drain electrode 3, as shown in FIG. 6.
  • the source electrode 2, the drain electrode 3, and the second gate insulating layer 101 constitute an integral structure.
  • the process in some embodiments further includes forming an insulating material layer 102 on a side of the first photoresist layer 20 distal to the base substrate 10; and forming a first conductive metal material layer 202 on a side of the insulating material layer 102 distal to the first photoresist layer 20. Subsequently, the first photoresist layer 20, the insulating material layer 102, the first conductive metal material layer 202, in the region outside that corresponding to the channel region R3 are removed by a lift-off method.
  • a portion of the insulating material layer 102 in a region corresponding to the channel region R3 remains thereby forming a first gate insulating layer 102
  • a portion of the first conductive metal material layer 202 in the region corresponding to the channel region R3 remains thereby forming a gate electrode 4, as shown in FIG. 2.
  • the active layer 1 and the second conductive metal material layer 5 in FIG. 4 may be formed by a different patterning process, e.g., the active layer 1 and the second conductive metal material layer 5 may be formed in two separate patterning processes.
  • the second gate insulating layer 101 in FIG. 6 may be formed by directly depositing a metal oxide material or a metal oxynitride material on the substrate, instead of oxidizing or oxynitridizing the third portion of the second conductive metal material layer 5.
  • the active layer is formed on a side of the source electrode and the drain electrode distal to the base substrate. Subsequently, a second gate insulating layer is formed in a region corresponding to the channel region of the active layer, the second gate insulating layer is formed to be in contact with the channel region of the active layer. A first gate insulating layer is then formed on a side of the second gate insulating layer distal to the active layer.
  • the second gate insulating layer has a resistivity higher than that of the first gate insulating layer.
  • the second gate insulating layer is made of a material having a relatively high dielectric constant, e.g., greater than 3.9.
  • the second gate insulating layer includes Hf x O y , Ta x O y , or a combination thereof.
  • the first gate insulating layer includes Si x O y , Si x N y , Si x O y N z , or a combination thereof.
  • the method includes forming a source electrode and a drain electrode on a base substrate; forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region on a side of the source electrode and the drain electrode distal to the base substrate; forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer is formed in a region outside that corresponding to the channel region; sequentially forming a second insulating material layer, a first insulating material layer, and a first conductive metal material layer on a side of the first photoresist layer and the active layer distal to the base substrate; and removing the first photoresist layer, the second insulating material layer, the first insulating material layer, and the first conductive metal material layer in the region outside that corresponding to the channel region by a lift-off method.
  • a portion of the second insulating material layer in a region corresponding to the channel region remains thereby forming a second gate insulating layer.
  • Aportion of the first insulating material layer in a region corresponding to the channel region remains thereby forming a first gate insulating layer.
  • a portion of the first conductive metal material layer in the region corresponding to the channel region remains thereby forming a gate electrode.
  • the present disclosure provides a thin film transistor fabricated by the method described herein.
  • the present disclosure provides a thin film transistor.
  • the thin film transistor in some embodiments includes a base substrate 10; an active layer 1 having a channel region R3, a source electrode contact region R1, and a drain electrode contact region R2 on the base substrate 10; a first gate insulating layer 102 on a side of the active layer 1 distal to the base substrate 10; and a gate electrode 4 on a side of the first gate insulating layer 102 distal to the active layer 1.
  • the boundary B1 between the source electrode contact region R1 and the channel region R3 and the boundary B2 between the drain electrode contact region R2 and the channel region R3 substantially align with edges of the first gate insulating layer 102 and the gate electrode 4. As shown in FIG.
  • the first gate insulating layer 102 has a first edge e3 and a second edge e4, and the gate electrode 4 has a first edge e1 and a second edge e2.
  • the first edge e1 of the gate electrode 4 and the first edge e3 of the first gate insulating layer 102 align with the boundary B1 between the source electrode contact region R1 and the channel region R3, the second edge e2 of the gate electrode 4 and the second edge e4 of the first gate insulating layer 102 align with the boundary B2 between the drain electrode contact region R2 and the channel region R3.
  • the gate electrode 4 and the first gate insulating layer 102 have a substantially the same pattern, e.g., a same pattern as that of the channel region R3 of the active layer 1.
  • a projection of the gate electrode 4 on the base substrate 10 substantially overlaps with that of the channel region R3, the projection of the gate electrode 4 on the base substrate 10 and that of the channel region R3 are substantially coextensive with each other.
  • a projection of the first gate insulating layer 102 on the base substrate 10 substantially overlaps with that of the channel region R3, the projection of the first gate insulating layer 102 on the base substrate 10 and that of the channel region R3 are substantially coextensive with each other.
  • the thin film transistor further includes a second gate insulating layer 101 between the channel region R3 of the active layer 1 and the first gate insulating layer 102, the second gate insulating layer 101 is in contact with the channel region R3 of the active layer 1.
  • the second gate insulating layer 101 has a resistivity higher than that of the first gate insulating layer 102.
  • boundaries between the source electrode contact region R1 and the channel region R3 and between the drain electrode contact region R2 and the channel region R3 substantially align with edges of the second gate insulating layer 101.
  • a projection of the second gate insulating layer 101 on the base substrate 10 substantially overlaps with that of the channel region R3, and the projection of the second gate insulating layer 101 on the base substrate 10 and that of the channel region R3 are substantially coextensive with each other.
  • the gate electrode substantially aligns with the boundaries between the source electrode contact region and the channel region and between the drain electrode contact region and the channel region substantially, e.g., the gate electrode self-aligns with the source electrode and the drain electrode, achieving high placement accuracy. Accordingly, the present thin film transistor is substantially free of any offset regions in the active layer, which is observed in the conventional thin film transistor having a gate electrode formed by wet-etching. Thus, the present thin film transistor substantially obviates the parasitic resistance introduced by the offset regions. Moreover, in the present thin film transistor, the source electrode and the drain electrode abut the channel region, achieving greatly improved electrical characteristics of the thin film transistor.
  • the total resistance between the source electrode and the drain electrode can be minimized as compared to that in the conventional thin film transistors (e.g., by conductorizing the active layer) , thus obviating additional fabrication step such as the active layer conductorization step.
  • the selection of the source electrode material and the drain electrode material is not strictly limited by the ohmic contact resistance between the electrode and the active layer, further lowering the fabrication costs.
  • the thin film transistor further includes a source electrode 2 and a drain electrode 3.
  • the source electrode 2 and the drain electrode 3 are made of a metal material comprising M1, M1 is a single metal or a combination of metals.
  • the second gate insulating layer is made of a material comprising M1O m N n , m > 0, n ⁇ 0.
  • the source electrode 2, the drain electrode 3, and the second gate insulating layer 101 are in a same layer.
  • the source electrode 2, the drain electrode 3, and the second gate insulating layer 101 constitute an integral structure.
  • the term “same layer” refers to the relationship between the layers simultaneously formed in the same step.
  • the source electrode 2, the drain electrode 3, and the second gate insulating layer 101 are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a same layer of material.
  • the source electrode 2, the drain electrode 3, and the second gate insulating layer 101 can be formed in a same layer by simultaneously performing the step of forming the second gate insulating layer 101 and the step of forming the source electrode 2 and the drain electrode 3.
  • the term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.
  • the M1O m N n includes a metal oxide or a metal oxynitride having a high dielectric constant, e.g., greater than 3.9, and the M1 includes a metal or an alloy, oxide or oxynitride of which has a high dielectric constant, e.g., greater than 3.9.
  • the M1 includes hafnium, tantalum, or a combination thereof; and M1O m N n includes Hf x O y , Ta x O y , Hf x O y N z , Ta x O y N z , or a combination thereof.
  • the first gate insulating layer 102 is not in direct contact with the active layer 1. Thus, whether or not the insulating material for the first gate insulating layer 102 will introduce hydrogen is not much of a concern, as the first gate insulating layer 102 is isolated from the active layer 1 by the second gate insulating layer 101.
  • the first gate insulating layer 102 includes a highly oxygen-resistant and moist-resistant insulating material.
  • the first gate insulating layer includes Si x O y , or Si x N y , or Si x O y N z , or a combination thereof, x > 0, y > 0.
  • the source electrode 2 and the drain electrode 3 in some embodiments are on a side of the active layer 1 distal to the base substrate 10.
  • the active layer 1 is on a side of the source electrode 2 and the drain electrode 3 distal to the base substrate 10.
  • a projection of the gate electrode 4 on the base substrate 10 substantially overlaps with that of the channel region R3, the first gate insulating layer 102, and the second gate insulating layer 101.
  • the projection of the gate electrode 4 on the base substrate 10 and those of the channel region R3, the first gate insulating layer 102, and the second gate insulating layer 101 are substantially coextensive with each other.
  • the second gate insulating layer 101 has a thickness substantially the same as those of the source electrode 2 and the drain electrode 3.
  • a height of a surface s2 of the second gate insulating layer 101 distal to the base substrate 10 relative to a surface s4 of the base substrate 10 is substantially the same as a height of a surface s1 of the source electrode and a surface s3 of the drain electrode distal to the base substrate 10 relative to the surface s4 of the base substrate 10.
  • the second gate insulating layer 101 has a thickness different from (e.g., less than) those of the source electrode 2 and the drain electrode 3.
  • a height of a surface s2 of the second gate insulating layer 101 distal to the base substrate 10 relative to a surface s4 of the base substrate 10 is less than a height of a surface s1 of the source electrode 2 and the surface s3 of the drain electrode 3 distal to the base substrate 10 relative to the surface s4 of the base substrate 10.
  • the present disclosure provides an array substrate having a thin film transistor described herein or fabricated by a method described herein.
  • the present disclosure provides a display panel having a thin film transistor described herein or fabricated by a method described herein.
  • the present disclosure provides a display apparatus having a thin film transistor described herein or fabricated by a method described herein.
  • Examples of appropriate display apparatuses includes, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc.
  • the term “the invention” , “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred.
  • the invention is limited only by the spirit and scope of the appended claims.
  • these claims may refer to use “first” , “second” , etc. following with noun or element.
  • Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/CN2017/091081 2016-11-30 2017-06-30 Method of fabricating thin film transistor, thin film transistor, and display apparatus Ceased WO2018099066A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018504672A JP7045983B2 (ja) 2016-11-30 2017-06-30 薄膜トランジスタの製造方法、薄膜トランジスタ及び表示装置
US15/741,741 US10431668B2 (en) 2016-11-30 2017-06-30 Method of fabricating thin film transistor, thin film transistor, and display apparatus
KR1020187002481A KR102103428B1 (ko) 2016-11-30 2017-06-30 박막 트랜지스터를 제조하는 방법, 박막 트랜지스터 및 디스플레이 장치
EP17828831.2A EP3549157A4 (en) 2016-11-30 2017-06-30 METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR, THIN FILM TRANSISTOR AND DISPLAY APPARATUS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611082799.9A CN108122759B (zh) 2016-11-30 2016-11-30 薄膜晶体管及其制作方法、阵列基板及显示装置
CN201611082799.9 2016-11-30

Publications (1)

Publication Number Publication Date
WO2018099066A1 true WO2018099066A1 (en) 2018-06-07

Family

ID=62226314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/091081 Ceased WO2018099066A1 (en) 2016-11-30 2017-06-30 Method of fabricating thin film transistor, thin film transistor, and display apparatus

Country Status (6)

Country Link
US (1) US10431668B2 (enExample)
EP (1) EP3549157A4 (enExample)
JP (1) JP7045983B2 (enExample)
KR (1) KR102103428B1 (enExample)
CN (1) CN108122759B (enExample)
WO (1) WO2018099066A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11315963B2 (en) * 2019-07-03 2022-04-26 Boe Technology Group Co., Ltd. Display substrate and method for preparing the same, and display device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860107B (zh) * 2019-01-31 2021-03-16 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN110265303B (zh) * 2019-06-12 2021-04-02 深圳市华星光电半导体显示技术有限公司 一种显示面板的制作方法
CN113972236B (zh) * 2020-07-23 2024-12-10 合肥鑫晟光电科技有限公司 显示基板及其制备方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120018718A1 (en) * 2010-07-21 2012-01-26 National Chiao Tung University Self-aligned top-gate thin film transistors and method for fabricating same
CN102522337A (zh) * 2011-12-16 2012-06-27 北京大学 一种顶栅氧化锌薄膜晶体管的制备方法
CN103346089A (zh) * 2013-06-13 2013-10-09 北京大学深圳研究生院 一种自对准双层沟道金属氧化物薄膜晶体管及其制作方法
CN103730514A (zh) * 2014-01-23 2014-04-16 苏州大学 薄膜晶体管
US8759186B2 (en) * 2011-11-21 2014-06-24 Industrial Technology Research Institute Semiconductor device and method for manufacturing the same
US20140191331A1 (en) 2011-06-27 2014-07-10 Pragmatic Printing Ltd Transistor and Its Method of Manufacture
CN106024608A (zh) * 2016-05-26 2016-10-12 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、衬底基板及显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167372A (ja) * 1984-02-09 1985-08-30 Seiko Epson Corp 薄膜トランジスタの製造方法
KR970006254B1 (ko) * 1994-03-18 1997-04-25 엘지전자 주식회사 박막트랜지스터의 제조방법
JPH0888363A (ja) * 1994-09-16 1996-04-02 Fujitsu Ltd 半導体装置及びその製造方法
US6278130B1 (en) * 1998-05-08 2001-08-21 Seung-Ki Joo Liquid crystal display and fabricating method thereof
KR20060000508A (ko) * 2004-06-29 2006-01-06 네오폴리((주)) 보호막을 이용한 금속유도측면 결정화방법 및 이를 이용한 박막 트랜지스터의 제조방법
JP5127183B2 (ja) * 2006-08-23 2013-01-23 キヤノン株式会社 アモルファス酸化物半導体膜を用いた薄膜トランジスタの製造方法
JP5512144B2 (ja) * 2009-02-12 2014-06-04 富士フイルム株式会社 薄膜トランジスタ及びその製造方法
JP5604938B2 (ja) * 2010-03-31 2014-10-15 凸版印刷株式会社 薄膜トランジスタ及びその製造方法
JP2012160679A (ja) * 2011-02-03 2012-08-23 Sony Corp 薄膜トランジスタ、表示装置および電子機器
GB2489682B (en) * 2011-03-30 2015-11-04 Pragmatic Printing Ltd Electronic device and its method of manufacture
US8952377B2 (en) * 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8569121B2 (en) * 2011-11-01 2013-10-29 International Business Machines Corporation Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same
JP6168795B2 (ja) * 2012-03-14 2017-07-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR102511325B1 (ko) * 2014-04-18 2023-03-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 그 동작 방법
KR102424445B1 (ko) * 2016-05-03 2022-07-22 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN106128963B (zh) * 2016-09-23 2019-07-23 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120018718A1 (en) * 2010-07-21 2012-01-26 National Chiao Tung University Self-aligned top-gate thin film transistors and method for fabricating same
US20140191331A1 (en) 2011-06-27 2014-07-10 Pragmatic Printing Ltd Transistor and Its Method of Manufacture
US8759186B2 (en) * 2011-11-21 2014-06-24 Industrial Technology Research Institute Semiconductor device and method for manufacturing the same
CN102522337A (zh) * 2011-12-16 2012-06-27 北京大学 一种顶栅氧化锌薄膜晶体管的制备方法
CN103346089A (zh) * 2013-06-13 2013-10-09 北京大学深圳研究生院 一种自对准双层沟道金属氧化物薄膜晶体管及其制作方法
CN103730514A (zh) * 2014-01-23 2014-04-16 苏州大学 薄膜晶体管
CN106024608A (zh) * 2016-05-26 2016-10-12 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、衬底基板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3549157A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11315963B2 (en) * 2019-07-03 2022-04-26 Boe Technology Group Co., Ltd. Display substrate and method for preparing the same, and display device

Also Published As

Publication number Publication date
KR102103428B1 (ko) 2020-04-23
JP2019536255A (ja) 2019-12-12
JP7045983B2 (ja) 2022-04-01
EP3549157A1 (en) 2019-10-09
US20190081159A1 (en) 2019-03-14
US10431668B2 (en) 2019-10-01
EP3549157A4 (en) 2020-06-24
CN108122759B (zh) 2021-01-26
KR20180086405A (ko) 2018-07-31
CN108122759A (zh) 2018-06-05

Similar Documents

Publication Publication Date Title
CN101110429B (zh) 电子装置、显示装置、图像显示系统及其制造方法
CN110036458B (zh) 形成结晶半导体层的方法、制造薄膜晶体管的方法、薄膜晶体管和显示设备
WO2018054122A1 (en) Thin-film transistor, manufacturing method thereof, and array substrate
WO2018176829A1 (en) Thin film transistor and display substrate, fabrication method thereof, and display device
JP2010205987A (ja) 薄膜トランジスタおよびその製造方法並びに表示装置
US10431668B2 (en) Method of fabricating thin film transistor, thin film transistor, and display apparatus
CN107068770A (zh) 一种薄膜晶体管及其制备方法、阵列基板、显示面板
US10431694B2 (en) Thin film transistor, display apparatus having the same, and fabricating method thereof
CN108198825A (zh) 一种阵列基板及其制备方法、显示面板
TWI497689B (zh) 半導體元件及其製造方法
US20170170309A1 (en) Thin film transistor, array substrate and display device having the same, and method thereof
US11244970B2 (en) Thin film transistor, array substrate, display apparatus, and method of fabricating thin film transistor
CN110034178A (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
CN104992947B (zh) 一种氧化物半导体tft阵列基板及其制备方法
CN106997892A (zh) 显示装置以及该显示装置的制造方法
US11081501B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, display device
WO2016155189A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN106935657A (zh) 一种薄膜晶体管及其制造方法、显示装置
US10475822B2 (en) Array substrate, display panel and display apparatus having the same, and fabricating method thereof
US10700097B2 (en) Array substrate and fabricating method thereof

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20187002481

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2018504672

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17828831

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2017828831

Country of ref document: EP

Effective date: 20190701

WWW Wipo information: withdrawn in national office

Ref document number: 2017828831

Country of ref document: EP