CN106024608A - 一种薄膜晶体管及其制作方法、衬底基板及显示装置 - Google Patents

一种薄膜晶体管及其制作方法、衬底基板及显示装置 Download PDF

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CN106024608A
CN106024608A CN201610362366.2A CN201610362366A CN106024608A CN 106024608 A CN106024608 A CN 106024608A CN 201610362366 A CN201610362366 A CN 201610362366A CN 106024608 A CN106024608 A CN 106024608A
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CN106024608B (zh
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刘凤娟
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种薄膜晶体管及其制作方法、衬底基板及显示装置。制作方法包括：在衬底基板上形成半导体层，半导体层包括：第一金属氧化物图形和覆盖该第一金属氧化物图形的第二金属氧化物图形；通过掩膜版，使用酸性刻蚀液，对未落入该掩膜版区域的第二金属氧化物图形刻蚀；掩膜版落入第二金属氧化物图形区域内，刻蚀液与未落入掩膜版区域的第一金属氧化物图形的表面发生化学反应，形成作为源/漏极的导体。相比于现有的顶栅型氧化物薄膜晶体管的等离子体处理等导体化技术，本发明的化学方法所生成的导体电阻更稳定，且由两个图层组成的半导体结构可进一步降低薄膜晶体管的关态电流。

Description

一种薄膜晶体管及其制作方法、衬底基板及显示装置
技术领域
本发明涉及显示器的制作领域，特别是指一种薄膜晶体管及其制作方法、衬底基板及显示装置。
背景技术
如图1所示，在现有显示器的顶栅型金属氧化物薄膜晶体管的制作方法中，一般是先在衬底基板1上沉积一层半导体图形2，之后在该半导体图形上方形成栅极G，并以栅极G为掩膜版，通过等离子体处理等导体化工艺，对未被栅极G遮挡的半导体图层2区域进行导体化处理，以形成源极S和漏极D。该方法的好处是制作工艺以及薄膜晶体管的图层结构都相对简单。
但是，等离子体处理的方法获得的导体化效果不稳定，后期会存在源漏电阻增大的风险，从而影响器件的可靠性。并且从图1中可以看出，通过该方法制作的薄膜晶体管，源极S、漏极D以及其之间的半导体层是由一个图层结构形成的，该结构会使关态电流较大，薄膜晶体管工作的稳定性降低，最终影响画面的显示效果。
发明内容
本发明的目的是提供一种能够改善薄膜晶体管关态电流及稳定性的技术方案。
为实现上述发明目的，一方面，本发明提供一种薄膜晶体管的制作方法，用包括：
在衬底基板上形成半导体层，所述半导体层依次包括：第一金属氧化物图形和第二金属氧化物图形，所述第二金属氧化物图形覆盖所述第一金属氧化物图形；
通过掩膜版，使用酸性的刻蚀液，对未落入该掩膜版区域的第二金属氧化物图形进行刻蚀；其中，所述掩膜版落入所述第二金属氧化物图形区域内，所述酸性的刻蚀液与未落入掩膜版区域的第一金属氧化物图形的表面发生化学反应，形成作为源极和漏极的导体。
可选地，本发明的制作方法还包括：
在形成有所述半导体层的衬底基板上，依次形成栅绝缘层和栅极；
其中，所述栅绝缘层落入所述栅极的区域内，并将所述栅极与所述第二金属氧化物相隔；所述栅极作为刻蚀第二金属氧化物图形的掩膜版。
可选地，在形成有所述半导体层的衬底基板上，依次形成栅绝缘层和栅极，包括：
在形成有所述半导体层的衬底基板上，依次沉积绝缘材料层和导电材料层；
通过构图工艺，对所述导电材料层进行图案化处理，得到栅极；
以所述栅极为掩膜版，对未落入所述栅极区域内的绝缘材料层进行刻蚀，得到栅绝缘层。
可选地，所述第一金属氧化物的材料为含锡金属氧化物(In2O3)a(SnO2)b(MO)c(ZnO)d；其中，0≤a≤1、0<b≤1、0≤c≤1、0≤d≤1，且a+b+c+d＝1；M为Ga、Al、Mg中的任一种元素，所述第二金属氧化物的材料为(In2O3)e(NO)f(ZnO)g；其中，0≤e≤1、0≤f≤1、0≤g≤1，且e+f+g＝1；N为Ga、Al、Mg中的任一种元素。
可选地，所述酸性的刻蚀液为醋酸系、磷酸系和硝酸系的混合溶液。
另一方面，本发明还提供一种薄膜晶体管，包括：
半导体层、源极和漏极；
所述半导体层包括：第一金属氧化物图形和第二金属氧化物图形；所述第二金属氧化物图形落入所述第一金属氧化物图形的区域内，且所述第一金属氧化物未被所述第二金属氧化物图形覆盖的区域的表面形成有作为所述源极和所述漏极的导体。
可选地，本发明的薄膜晶体管还包括：
栅极以及栅绝缘层；
所述栅绝缘层落入所述栅极的区域内，并将所述栅极与所述第二金属氧化物相隔，所述第二金属氧化物图形落入所述栅极的区域内。
此外，本发明还提供一种包括有上述薄膜晶体管的阵列基板。
可选地，上述阵列基板还包括：
在形成所述半导体层与所述衬底基板之间的缓冲层。
可选地，上述阵列基板还包括：
覆盖所述半导体层的平坦层，以及形成在所述平坦层上的数据线和像素电极；
所述平坦层具有第一过孔和第二过孔，所述第一过孔与所述源极相对设置，所述第二过孔与所述漏极相对设置，所述数据线通过所述第一过孔与所述源极连接，所述像素电极通过所述第二过孔与所述漏极连接。
此外，本发明还提供一种包括上述阵列基板的显示装置。
本发明的上述技术方案的有益效果如下：
在本发明的方案中，依次沉积两种不同的金属氧化物图形作为半导体层。巧妙利用酸性刻蚀溶液，对上层金属氧化物图形进行刻蚀，并与暴露出来的下层金属氧化物图形发生化学反应，形成作为源极和漏极的导体。相比于顶栅结构金属氧化物薄膜晶体管现有技术通过等离子体处理工艺形成源极和漏极的技术方案，本发明化学方法生成的导体的电阻更稳定，且源漏极和薄膜晶体管的沟道层不位于同一层，该结构能够有效降低薄膜晶体管的关态电流。
附图说明
图1为现有的通过等离子体处理工艺在半导体层形成源极和漏极的示意图；
图2A-图2C为本发明的薄膜晶体管的制作方法的流程示意图；
图3为通过本发明的制作方法形成顶栅薄膜晶体管的示意图；
图4A-图4E为发明的制作方法制作顶栅薄膜晶体管的详细流程图；
图5为通过本发明的阵列基板的结构示意图。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明针对现有顶栅型氧化物薄膜晶体管的关态电流较大和器件可靠度差的技术问题，提供一种解决方案。
一方面，本发明的实施例提供一种薄膜晶体管的制作方法，包括：
步骤1，参考图2A，在衬底基板1上形成的半导体层2；该半导体层2依次包括：第一金属氧化物图形21和第二金属氧化物图形22，第二金属氧化物图形22覆盖第一金属氧化物图形21；
步骤2，参考图2A，通过掩膜版mask，使用酸性的刻蚀液，对未落入该掩膜版mask区域的第二金属氧化物图形22进行刻蚀；其中，参考图2C，酸性的刻蚀液还与未落入掩膜版mask区域的第一金属氧化物图形21的表面发生化学反应，生成作为源极S和漏极D的导体。
作为示例性介绍，本实施例的所述第一金属氧化物的材料为含锡金属氧化物(In2O3)a(SnO2)b(MO)c(ZnO)d；其中，0≤a≤1、0<b≤1、0≤c≤1、0≤d≤1，且a+b+c+d＝1；M为Ga、Al、Mg中的任一种元素，所述第二金属氧化物的材料为(In2O3)e(NO)f(ZnO)g；其中，0≤e≤1、0≤f≤1、0≤g≤1，且e+f+g＝1；N为Ga、Al、Mg中的任一种元素。
对应上述半导体层的材料，本实施例的酸性刻蚀液可以是醋酸系、磷酸系和硝酸系的混合溶液，能够有效溶解掉上述第二金属氧化物(In2O3)e(NO)f(ZnO)g，并与第一金属氧化物(In2O3)a(SnO2)b(MO)c(ZnO)d发生化学反应，在其表面生成一层导电性更高的富锡层。
显然，通过图2C可以看出，本实施例的未被刻蚀掉的第二金属氧化物图形22作为半导体图形一部分要高于源极S、漏极D，采用该结构设计可以使源极S和漏极D的关态电流得到有效降低，从而有效提高薄膜晶体管的开关率。
进一步地，参考图3，本实施例的制作方法在步骤2之前还包括：在形成有半导体层的衬底基板上，依次形成栅绝缘层3和栅极4；其中，本实施例的栅绝缘层3落入栅极4的区域内，并将栅极4与半导体层21、22相隔。
在上述步骤2中，本实施例复用栅极4的图形作为掩膜版使用，对第二金属氧化物图形22进行刻蚀。由于该刻蚀步骤并没有引用新的掩膜版，因此在制作成本上得到了有效降低，具有很高的实用价值。
下面结合一个实际应用，对本实施例的薄膜晶体管的制作方法进行详细介绍。
在本实际应用中，薄膜晶体管的制作流程包括：
步骤41，参考图4A，在衬底基板上依次沉积第一金属氧化物层和第二金属氧化物层，并通过一次构图工艺，对第一金属氧化物层和第二金属氧化物层进行图案化处理，得到由第一金属氧化物层所形成的第一金属氧化物图形21，以及由第二金属氧化物层形成的第二金属氧化物图形22(当然作为步骤41的其他可行方案，可以通过一次构图工艺先形成第一金属氧化物图形21，之后直接沉积能够覆盖该第一金属氧化物图形21的第二金属氧化物图形22即可)；
步骤42，参考图4B，依次沉积绝缘材料层3和导电材料层4；
步骤43，参考图4C，通过一次构图工艺，对导电材料层4进行图案化处理，形成栅极G；
步骤44，参考图4D，以栅极G为掩膜版，对未落入所述栅极G区域内的绝缘材料层3进行刻蚀，得到落入栅极G区域内的栅绝缘层3；
步骤45，参考图4E，以栅极G为掩膜版，使用酸性的刻蚀液，刻蚀掉未落入栅极G区域内的第二金属氧化物图形22。在刻蚀过程中，刻蚀掉的第二金属氧化物图形22会暴露出来的第一金属氧化物图形21，酸性刻蚀液与该暴露出来的第一金属氧化物图形21发生化学反应，使其表面生成源极S和漏极D；
显然，通过上述步骤41-步骤45的描述可以知道，本实施例巧妙地利用酸性刻蚀液，对第二金属化物图形进行刻蚀，并同时对第一金属化物图形的部分区域进行导体化处理，形成源极和漏极。该方法工艺简单，且使用栅极作为掩膜版，因此成本低廉。
此外，需要说明的是，作为上述实际应用的另一可行方案，本实施例在在对栅极进行图案化处理后，可以保留刻蚀栅极所使用的光刻胶，在后续以栅极作为掩膜版，刻蚀栅绝缘层和第二金属氧化物图形时，该掩膜版可以是指栅极以及保留的光刻胶的整体结构。
此外，本发明的另一实施例还提供一种对应上述制作方法的薄膜晶体管，如图4E所示，包括：
由第一金属氧化物图形21和第二金属氧化物图形22形成的半导体层、源极S和漏极D；
其中，第二金属氧化物图形22覆盖第一金属氧化物图形21的部分区域，且第一金属氧化物21未被第二金属氧化物图形22覆盖的区域的表面形成有作为上述源极S和上述漏极D的导体。
具体地，本实施例的薄膜晶体管还包括有栅极G以及栅绝缘层3；该栅绝缘层3落入栅极G的区域内，并将栅极G与半导体层相隔，且第二金属氧化物图形22落入栅极G的区域内。
显然，本实施例的薄膜晶体管是通过本发明上一实施例制作方法所制作得到的，因此均能够实现相同的技术效果。
此外，本发明的另一实施例还提供一种包括有上述薄膜晶体管的阵列基板。在实际应用中，假设本实施例的阵列基板采用图4中在衬底基板1上形成的薄膜晶体管结构，进一步参考图5，本实施例在衬底基板1与薄膜晶体管之间又加入缓冲层buffer，该缓冲层buffer能够隔绝衬底基板1热应力对薄膜晶体管造成的破坏。
进一步地，本实施例的阵列基板还包括有：
覆盖半导体层的平坦层51，以及形成在平坦层51上的数据线52和像素电极53；
其中，平坦层5具有第一过孔和第二过孔，该第一过孔与薄膜晶体管中的源极相对设置，第二过孔与薄膜晶体管中的漏极相对设置，数据线52通过第一过孔与源极连接，像素电极53通过第二过孔与漏极连接。
此外，本发明还提供包括有上述阵列基板的显示面板，由于采用了本发明所提供的薄膜晶体管，因此能够提供更加稳定的显示画面，提升了用户的体验效果。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

1.一种薄膜晶体管的制作方法，其特征在于，包括：
在衬底基板上形成半导体层，所述半导体层依次包括：第一金属氧化物图形和第二金属氧化物图形，所述第二金属氧化物图形覆盖所述第一金属氧化物图形；
通过掩膜版，使用酸性的刻蚀液，对未落入该掩膜版区域的第二金属氧化物图形进行刻蚀；其中，所述掩膜版落入所述第二金属氧化物图形区域内，所述酸性的刻蚀液与未落入掩膜版区域的第一金属氧化物图形的表面发生化学反应，形成作为源极和漏极的导体。
2.根据权利要求1所述的制作方法，其特征在于，还包括：
在形成有所述半导体层的衬底基板上，依次形成栅绝缘层和栅极；
其中，所述栅绝缘层落入所述栅极的区域内，并将所述栅极与所述第二金属氧化物相隔；所述栅极作为刻蚀第二金属氧化物图形的掩膜版。
3.根据权利要求2所述的制作方法，其特征在于，
在形成有所述半导体层的衬底基板上，依次形成栅绝缘层和栅极，包括：
在形成有所述半导体层的衬底基板上，依次沉积绝缘材料层和导电材料层；
通过构图工艺，对所述导电材料层进行图案化处理，得到栅极；
以所述栅极为掩膜版，对未落入所述栅极区域内的绝缘材料层进行刻蚀，得到栅绝缘层。
4.根据权利要求1所述的制作方法，其特征在于，
所述第一金属氧化物的材料为含锡金属氧化物(In2O3)a(SnO2)b(MO)c(ZnO)d；其中，0≤a≤1、0<b≤1、0≤c≤1、0≤d≤1，且a+b+c+d＝1；M为Ga、Al、Mg中的任一种元素，所述第二金属氧化物的材料为(In2O3)e(NO)f(ZnO)g；其中，0≤e≤1、0≤f≤1、0≤g≤1，且e+f+g＝1；N为Ga、Al、Mg中的任一种元素。
5.根据权利要求4所述的制作方法，其特征在于，
所述酸性的刻蚀液为醋酸系、磷酸系和硝酸系的混合溶液。
6.一种薄膜晶体管，其特征在于，包括：
半导体层、源极和漏极；
所述半导体层包括：第一金属氧化物图形和第二金属氧化物图形；所述第二金属氧化物图形落入所述第一金属氧化物图形的区域内，且所述第一金属氧化物未被所述第二金属氧化物图形覆盖的区域的表面形成有作为所述源极和所述漏极的导体。
7.根据权利要求6所述的薄膜晶体管，其特征在于，还包括：
栅极以及栅绝缘层；
所述栅绝缘层落入所述栅极的区域内，并将所述栅极与所述第二金属氧化物相隔，所述第二金属氧化物图形落入所述栅极的区域内。
8.一种阵列基板，其特征在于，包括：
衬底基板，以及在所述衬底基板上形成的如权利要求6或7所述的薄膜晶体管。
9.根据权利要求8所述的阵列基板，其特征在于，还包括：
设置在半导体层与衬底基板之间的缓冲层。
10.根据权利要求8所述的阵列基板，其特征在于，还包括：
覆盖所述半导体层的平坦层，以及形成在所述平坦层上的数据线和像素电极；
所述平坦层具有第一过孔和第二过孔，所述第一过孔与所述源极相对设置，所述第二过孔与所述漏极相对设置，所述数据线通过所述第一过孔与所述源极连接，所述像素电极通过所述第二过孔与所述漏极连接。
11.一种显示装置，其特征在于，包括如权利要求8-10任一项所述的阵列基板。
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