WO2018094924A1 - 一种可编程分频器及计算机存储介质 - Google Patents

一种可编程分频器及计算机存储介质 Download PDF

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Publication number
WO2018094924A1
WO2018094924A1 PCT/CN2017/077770 CN2017077770W WO2018094924A1 WO 2018094924 A1 WO2018094924 A1 WO 2018094924A1 CN 2017077770 W CN2017077770 W CN 2017077770W WO 2018094924 A1 WO2018094924 A1 WO 2018094924A1
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output
signal
unit
clock
input
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French (fr)
Inventor
李超林
刘凌霄
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Definitions

  • the present invention relates to the field of frequency dividers, and in particular to a programmable frequency divider and a computer storage medium.
  • the frequency division ratio of the clock channel divider can be arbitrarily configured.
  • the output duty ratio of the frequency division structure changes with the change of the frequency division configuration, and the delay of the input and output is uncontrollable. The more the frequency division stage, the larger the clock delay of the output, and the more noise introduced to the clock path. many.
  • embodiments of the present invention provide a programmable frequency divider and a computer storage medium.
  • the embodiment of the invention provides a programmable frequency divider, the programmable frequency divider comprising a state machine unit, a logic unit and a clock output unit; the state number of the state machine unit is adapted to the frequency division number;
  • the state machine unit is connected to the logic unit, configured to control a state jump when an input clock source period expires, and output a clock signal characterizing the state machine unit state based on a state jump of the state machine unit;
  • the logic unit is coupled to the clock output unit and configured to obtain a representation of the state machine a clock signal of a state, based on a state of the state machine, outputting a control signal to the clock output unit and the state machine unit; wherein, when the state of the state machine satisfies a preset state, the output control signal is used for control
  • the clock signal output by the clock output unit is inverted and the state machine unit is controlled to be set; and configured to control the output clock signal to perform duty correction when the frequency division number is an odd number;
  • the clock output unit is configured to output a divided clock signal of an equal duty ratio based on the control signal when the frequency division number is an even number; and when the frequency division number is an odd number, control a clock signal output based on the control signal to perform a duty ratio Corrected to output a divided clock signal with equal duty.
  • the state machine unit is specifically a subtraction counting unit configured to decrease the control count value by one when the input clock source period expires, and the change of the count value is used as a state jump;
  • the control signal corresponding to the state of the state machine satisfies the preset state, the control count value jumps to the initial value;
  • the subtraction counting unit includes a first input end, a second input end, a clock source input end, a first signal output end, and a second signal output end; the first signal output end and/or the second signal The output end is connected to the logic unit; the first signal output end is connected to the second input end; and the second signal output end is connected to the first input end;
  • the first signal outputted by the first signal output end and/or the second signal outputted by the second signal output end are input to the logic unit; and the first signal input end output by the first signal output end a second input terminal; the second signal outputted by the second signal output terminal is input to the first input end.
  • the subtraction counting unit includes a first selector, a second selector, and a first D flip-flop; wherein
  • An output of the first selector is coupled to a first input of the second selector; the first selector is configured to select the first signal or location based on a first control signal input by a control signal input Translating the second signal as a first input signal into the first input of the second selector end;
  • a second input of the second selector for inputting a configuration number signal
  • an output of the second selector is coupled to an input of the first D flip-flop
  • the second selector is configured to be based on control
  • the control signal input by the signal input terminal selects the first input signal or the configuration number signal to be output to the first D flip-flop
  • a first signal output end and a second signal output end of the first D flip-flop are respectively connected to a second input end and a first input end of the first selector; the first D flip-flop is configured to be based on a clock A clock source signal input from the source input outputs the first signal and/or the second signal.
  • the programmable frequency divider further includes an OR gate processing unit configured to perform a logical OR operation on the first signal outputted by the first stage of the first D flip-flop, and input the operation result as an input to the The first control signal of the first selector.
  • the first output end of the logic unit is connected to the control signal input end of the clock output unit; the first output end of the logic unit is further connected to the control signal input end of the subtraction counting unit a control signal outputted from an output end of the logic unit is input to the clock output unit and the subtraction counting unit, respectively, configured to control a clock signal output by the clock output unit to be inverted based on the control signal, and to control the state machine Unit set;
  • the logic unit also includes a second output for outputting a selection signal, the second output being coupled to the clock output unit.
  • the clock output unit is configured to: when the frequency division number is 2M+1, the first frequency-divided signal output based on the control signal satisfies a duty ratio of M/(2M+1); An integer; a first frequency-divided signal satisfying the M/(2M+1) duty ratio is input to a duty ratio correction (DCC) correction unit for duty correction.
  • DCC duty ratio correction
  • the clock output unit includes a third selector, a second D flip-flop, a DCC correction unit, and a fourth selector;
  • the third selector includes a first input, a second input, and a control a signal input end and an output end; a first input end and a second input of the third selector
  • the terminals are respectively connected to the first signal output end and the second signal output end of the subtraction counting unit;
  • the output end of the third selector is connected to the input end of the second D flip-flop;
  • the second D trigger The signal output end of the device is respectively connected to the first input end of the fourth selector and the input end of the DCC correction unit;
  • the output end of the DCC correction unit is connected to the second input end of the fourth selector
  • the output of the fourth selector outputs a divided clock signal of equal duty ratio;
  • the fourth selector further includes a selection signal input terminal coupled to the second output end of the logic unit, configured to select a clock signal output by the second D flip-flop based on a selection signal output by the second output terminal As the frequency-divided clock signal, or the DCC correction unit is selected to perform the duty-corrected clock signal as the divided clock signal.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions for performing processing in the programmable frequency divider according to the embodiment of the invention. logic.
  • the programmable frequency divider includes a state machine unit, a logic unit and a clock output unit; the number of bits of the state machine unit is adapted to the frequency division number;
  • the state machine unit is connected to the logic unit, configured to control a state jump when an input clock source period expires, and output a clock signal characterizing the state machine unit state based on a state jump of the state machine unit;
  • the logic unit is coupled to the clock output unit, configured to obtain a clock signal characterizing the state machine state, and output a control signal to the clock output unit and the control unit based on a state of the state machine; wherein, when When the state of the state machine satisfies the preset state, the output control signal is used to control the clock signal output by the clock output unit to be inverted and to control the state machine unit to be set; and is also configured to control the control unit when the frequency division number is an odd number.
  • a clock signal output by the clock output unit is input to a DCC correction unit for duty correction;
  • the clock output unit is configured to When the frequency division number is even, the frequency-divided clock signal of the equal duty ratio is output based on the control signal; when the frequency division number is an odd number, the output clock signal is input to the DCC correction unit for duty correction based on the control signal, Output equal duty ratio Divided clock signal.
  • the technical solution of the embodiment of the present invention solves the problem of the arbitrary frequency division, and realizes that the duty ratio of the output clock signal is maintained at 50%; when the state machine jumps to the state, when the state machine jumps to the frequency division ratio according to the frequency division ratio
  • the logic unit controls the state machine to set and outputs a control signal to invert the output clock signal, which greatly reduces the output delay and the delay amount is fixed at the same time, and the output noise is greatly reduced;
  • the clock output unit controls the output clock signal to be inverted according to the state of the state machine.
  • the critical path can be judged by 1 bit, the delay of the control logic is minimized, and the high-speed clock frequency division of the frequency divider is realized.
  • FIG. 1 is a schematic structural diagram of a programmable frequency divider according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a state machine unit implemented by a subtraction counting unit in a programmable frequency divider according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of line connection of a state machine unit implemented by a subtraction counting unit in a programmable frequency divider according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing line connections of logic units in a programmable frequency divider according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of line connection of a clock output unit in a programmable frequency divider according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram showing the structure and circuit connection of a DCC correction unit in a programmable frequency divider according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a clock corrected by using a DCC correction unit according to an embodiment of the present invention.
  • Figure 8 is a schematic diagram of a state machine jump.
  • Embodiments of the present invention provide a programmable frequency divider.
  • 1 is a schematic structural diagram of a programmable frequency divider according to an embodiment of the present invention; as shown in FIG. 1, the programmable frequency divider includes a subtraction method. a state machine unit 11, a logic unit 12 and a clock output unit 13; the state number of the state machine unit 11 is adapted to the frequency division number;
  • the state machine unit 11 is connected to the logic unit 12, configured to control a state jump when the input clock source period expires, and characterize the state machine unit 11 state based on the state jump output of the state machine unit 11. Clock signal
  • the logic unit 12 is coupled to the clock output unit 13 and configured to obtain a clock signal characterizing the state machine state, and output a control signal to the clock output unit 13 and the state machine unit based on the state of the state machine 11; wherein, when the state of the state machine satisfies a preset state, the output control signal is used to control the clock signal output by the clock output unit 13 to be inverted and to control the state machine unit 11 to be set; When the frequency is an odd number, the clock signal of the output is controlled to perform duty correction;
  • the clock output unit 13 is configured to output a divided clock signal of an equal duty ratio based on the control signal when the frequency division number is an even number; and when the frequency division number is an odd number, control the output clock signal based on the control signal to perform duty Ratio correction to output equal-divided clock signals.
  • the state machine unit 11 is specifically implemented by a subtraction counting unit, and the subtraction counting unit is configured to decrease the control count value by one when the input clock source period expires, and the change of the count value is used as a state. Jumping; also configured to control the count value to jump to an initial value when receiving a control signal corresponding to the state of the state machine that satisfies the preset state.
  • the subtraction counting unit includes a first input end, a second input end, a clock source input end, a first signal output end, and a second signal output end; the first signal output end and/or the The second signal output terminal is connected to the logic unit 12; the first signal output end is connected to the second input end; the second signal output end is connected to the first input end; wherein a first signal outputted by the first signal output terminal and/or a second signal outputted by the second signal output terminal is input to the logic unit 12; and a first signal outputted by the first signal output terminal is input to the second signal An input end; the second signal outputted by the second signal output terminal is input to the first input end.
  • each of the count values in the subtraction counting unit represents a state; when the clock source period of each input reaches (for example, the rising edge of the clock) after the power-on reset, the counting of the subtraction counting unit The value is decremented by one, and a clock signal characterizing the state of the subtraction counter is output to the logic unit 12 based on the count value.
  • the subtraction counting unit includes a first selector (for example, represented by MA) a second selector (eg, represented by MB) and a first D flip-flop (eg, represented by DFF); wherein the output of the first selector and the first input of the second selector (0)
  • the first selector is configured to select the first signal or the second signal as the first input signal to be input to the first of the second selectors based on the first control signal input by the control signal input terminal An input (0 terminal); a second input (1 terminal) of the second selector for inputting a configuration number (for example, a DIV ⁇ N> representation) signal; an output of the second selector and the first An input (D terminal) of a D flip-flop is connected; the second selector is configured to select the first input signal or configuration based on the control signal input by a control signal
  • the programmable frequency divider further includes an OR gate processing unit configured to obtain a logical OR operation of the first signal outputted by the first stage of the first D flip-flop, and input the operation result as the input to the first selection.
  • the first control signal of the device may be represented as CLK_OUT ⁇ 1>OR CLK_OUT ⁇ 2>OR...OR CLK_OUT ⁇ N-1>; wherein CLK_OUT ⁇ 1>, CLK_OUT ⁇ 2>... ..., CLK_OUT ⁇ N-1> are respectively the first signals outputted by the first stage of the first D flip-flop; OR represents a logical OR operation.
  • the number of stages of the subtraction counting unit in the programmable frequency divider is adapted to the frequency division number of the frequency divider; when the frequency division number is N (N is a positive integer), the subtraction counting unit The number of stages is at least (N-1).
  • FIG. 3 is a schematic diagram of line connection of a state machine unit implemented by a subtraction counting unit in a programmable frequency divider according to an embodiment of the present invention; in combination with the subtraction counting unit shown in FIG. 2 and FIG. 3, the second one in FIG.
  • the subtraction counting unit 112 (the N-1th stage) is taken as an example for explanation.
  • the two signals output by the second subtraction counting unit 112 are: a first signal (for example, CLK_OUTP ⁇ N-1>) and a second signal (for example, CLK_OUTN ⁇ N-1>) are input as the cyclic input signal to the first
  • the two subtraction counting units 112, specifically, the first signal (for example, CLK_OUTP ⁇ N-1>) and the second signal (for example, CLK_OUTN ⁇ N-1>) output by the first D flip-flop (DFFN1) are cyclically input to the first selection. (MAN1).
  • the first control signal of the first selector is a logical OR operation processing result of the first signal outputted by the first D flip-flop obtained by the OR gate processing unit, for example, the control signal is CLK_OUTP ⁇ 1> the result of the operation of the logical OR operation of CLK_OUTP ⁇ N-2>; of course, in other embodiments, the first control signal may also be the first D flip-flop obtained by the gate processing unit
  • the processing result of the logical OR operation processing of the second signal outputted by the previous stage for example, the operation result of the logical OR operation of the control signal being CLK_OUTN ⁇ 1> up to CLK_OUTN ⁇ N-2>; CLK_OUT ⁇ 1>OR CLK_OUT ⁇ 2>...OR CLK_OUT ⁇ N-2> may specifically be a logical OR operation result of the first signal outputted from the previous stage, or may be a second signal outputted by the previous stage.
  • the related processing rule of the third subtraction counting unit 113 can refer to the related
  • the first selector (MAN1) controls the input first signal or the second signal as the first input signal to the second selector (MBN1) based on the first control signal;
  • the second selector (MBN1) is based on the control signal (SET) generated by the logic unit.
  • the first input signal or the configuration number signal is selected to be output to the first D flip-flop (DFFN1); wherein the control signal is a control signal (SET signal) output by the logic unit 12.
  • the configuration number input in the configuration number signal is externally configured based on the frequency divider N, for example, DIV ⁇ 1>, DIV ⁇ N-1>, and DIV ⁇ N> shown in FIG.
  • the frequency division number N is related.
  • the input clock of the first D flip-flop is an input clock source, and the output first signal and second signal are re-entered on the one hand to the first selector, and on the other hand, the first signal and/or the second signal It is input to the logic unit 12 as an input signal.
  • the first-stage subtraction counting unit 111 may not have the first selector, that is, only have the second selector and the first D-trigger; the second selector and the first
  • the connection manner of the D flip-flop is the same as that described above, and will not be described again here.
  • FIG. 4 is a schematic diagram of a line connection of a logic unit in a programmable frequency divider according to an embodiment of the present invention
  • an output end of the logic unit 12 and the clock output unit 13 a control signal (SET) input is connected; an output of the logic unit 12 is further connected to a control signal (SET) input of the subtraction counting unit; wherein a control signal (SET) outputted by the output of the logic unit 12
  • SET control signal
  • the output control signal is used to control the clock signal output of the clock output unit to be inverted and used to control the state machine unit to be set; and is also configured to control the output clock when the frequency division number is an odd number.
  • the signal is duty cycle corrected; the logic unit 12 further includes a second output for outputting
  • the logic unit 12 is pre-configured with a preset state set based on the frequency division number to determine whether the counting state of the subtraction counting unit reaches the clock state when the clock signal characterizing the counting state of the subtraction counting unit is obtained. Determining a preset state, determining that the count state reaches the stated state In the preset state, a control signal is output, and the control signal is used to control the clock signal output of the clock output unit and to control the state machine unit to be set.
  • the clock output unit 13 is specifically configured to: when the frequency division number is 2M+1, the first frequency-divided signal output based on the control signal satisfies a duty ratio of M/(2M+1); A positive integer; a first frequency-divided signal satisfying the M/(2M+1) duty ratio is input to the DCC correction unit for duty correction.
  • FIG. 5 is a schematic diagram of line connection of a clock output unit in a programmable frequency divider according to an embodiment of the present invention
  • the clock output unit 13 includes a third selector (for example, MO represents), a second D flip-flop (eg, DFFO can be represented), a DCC correction unit, and a fourth selector;
  • the third selector includes a first input (0 end) and a second input (1 end) a control signal input end (the control signal is a SET) and an output end; the first input end and the second input end of the third selector respectively and the first signal output end and the second signal of the subtraction counting unit
  • the output terminal is connected; that is, the 0th end and the 1st end of the third selector (MO) are respectively connected to the CLK_OUTP ⁇ N> signal and the CLK_OUTN ⁇ N> signal; the output end of the third selector and the second D
  • the input terminal (D terminal) of the flip-flop is connected; the second D flip-flop further
  • the first signal output by the subtraction counting unit for example, CLK_OUTP ⁇ 1>...CLK_OUTP ⁇ N-1>, CLK_OUTP ⁇ N> is taken as The input signal of the logic unit 12; as another embodiment, the second signal output by the subtraction counting unit, for example, CLK_OUTN ⁇ 1>...CLK_OUTN ⁇ N-1>, CLK_OUTN ⁇ N> may also be used as the logic unit An input signal of 12; of course, the first signal and the second signal may also collectively serve as an input signal to the logic unit 12.
  • the logic unit 12 processes the input signal by an internal logic gate module for logic determination to output a control signal (eg, a SET signal); the control signal (eg, SET signal) is mainly used to count based on the subtraction counting unit Whether the state satisfies the preset state controls the selection of the input clock signals (for example, CLK_OUTP and CLK_OUTN) by the clock output unit 13, thereby controlling the inversion of the output clock signal.
  • a control signal eg, a SET signal
  • the logic unit 12 pre-configures a preset value, and determines, by the logic gate module for logic determination, the logical judgment of the input clock signal characterizing the state of the subtraction counting unit, and determines that the subtraction counting unit is
  • the count value reaches the preset value
  • the clock signal selected by the clock output unit 13 is controlled to be inverted by the output control signal to achieve the frequency division function.
  • the frequency division number is 2M
  • the corresponding frequency division is M:M
  • the corresponding frequency division is M:(M+1).
  • the output clock can be guaranteed to be a duty ratio of M/(2M+1); in order to obtain an equal duty ratio, in this embodiment, the clock output unit 13 of the programmable frequency divider A DCC correction unit is further disposed, configured to perform duty correction on the output frequency-divided clock signal when the frequency division number is an odd number, to obtain a frequency-divided clock signal of equal duty ratio.
  • the DCC correction unit can be specifically referred to as shown in FIG.
  • the duty ratio is predictable, and the duty correction unit shown in FIG. 6 corrects the duty ratio of M/(2M+1), that is, the divided clock signal for which the high-order signal and the low-order signal are different by one cycle. A correction is made to obtain a divided duty clock signal of equal duty ratio.
  • a schematic diagram of the clock after frequency division can be referred to FIG.
  • FIG. 8 is a schematic diagram of a state machine jump of a frequency divider; in the present diagram, a frequency division configuration of 7 (3'b111) (where b represents a bit and "111" is 7) is used as an example.
  • the state machine of the frequency converter jumps, as shown in Figure 8.
  • the state of the state machine to be used is 2 bits. After the power is turned on, the reset (RST) terminal is released.
  • the state is (2'b00), the output of the divider is in the low state, and then the first input clock rising edge comes, the state machine jumps to (2'b11), and the output of the divider Change to the high state; according to the pre-configuration, when the rising edge of the second input clock arrives, the state machine jumps to (2'b10), the output of the divider remains high; the third input clock rises When it arrives, the state machine jumps to (2'b01), the output of the divider remains in the high state; when the rising edge of the fourth input clock arrives, the logic unit controls the state machine to jump to (2'b11), while The output of the divider becomes low; when the rising edge of the fifth input clock arrives, the state machine jumps to (2'b 10), the output of the divider remains low; when the rising edge of the sixth input clock arrives, the state machine jumps to (2'b01), the output of the divider remains low; the seventh input clock rises When it arrives, the state machine jumps to 2'b00), the output of the divider remains low;
  • the preset value in the logic module in the embodiment of the present invention may be pre-configured, so that the divided clock signal of any duty ratio (including equal duty ratio) can be obtained.
  • the following is a combination of the structure of the programmable frequency divider of the embodiment of the present invention, which is constructed by logic gates.
  • the subtraction counter implements a state machine, and the processing flow of the programmable frequency divider of the embodiment of the present invention will be described.
  • the external configuration number is DIV ⁇ N:0>
  • the input clock signal is CLK_IN
  • the output clock signal is CLK_OUT
  • 0 indicates a low state
  • 1 indicates a high state.
  • the N bit subtraction counter is decremented by 1 and the output of the divider remains unchanged until the value of DIV ⁇ 0> is 0, the subtraction counter will count N'b001, when the value of DIV ⁇ 0> is 1, the subtraction counter will count to N'b00; after the rising edge of the next input clock, the value of DIV ⁇ N:1> is rewritten to N.
  • the output is reset to 1, at which point a complete division cycle is completed. Then, according to the configuration value DIV ⁇ 0> is 1 or 0, it is determined whether the frequency division is odd or even to determine whether to perform DCC processing on the output signal. If it is an odd frequency division, the DCC correction unit shown in FIG. 6 is needed, thereby A 50% duty cycle divided clock signal is obtained.
  • the technical solution of the embodiment of the present invention solves the problem of the arbitrary frequency division, and realizes that the duty ratio of the output clock signal is maintained at 50%; when the state machine jumps to the state, when the state machine jumps to the frequency division ratio according to the frequency division ratio
  • the logic unit controls the state machine to set and outputs a control signal to invert the output clock signal, which greatly reduces the output delay and fixes the delay amount when arbitrarily dividing. Equally, the output noise is greatly reduced.
  • the clock output unit controls the output clock signal to be inverted according to the state of the state machine.
  • the critical path can be judged by 1 bit, the delay of the control logic is minimized, and the frequency division is realized.
  • the high speed clock is divided.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions for performing processing in the programmable frequency divider according to the embodiment of the invention. logic.
  • the computer executable instructions are configured to: when the input clock source period expires, control the state machine unit state jump, and output a clock characterizing the state machine unit state based on the state jump of the state machine unit And obtaining a clock signal characterizing the state machine state, outputting a control signal to the clock output unit and the state machine unit based on a state of the state machine; wherein, when a state of the state machine satisfies a preset state And outputting a control signal for controlling a clock signal output of the clock output unit to be turned over and controlling the state machine unit to be set; when the frequency division number is an even number, controlling the clock output unit output equal duty ratio based on the control signal The divided clock signal; when the frequency division number is an odd number, the clock signal output by the clock output unit is controlled based on the control signal to perform duty correction to
  • the computer executable instructions are further configured to: when the frequency division number is an even number, control, according to the control signal, the clock output unit to output a frequency-divided clock signal of an equal duty ratio; when the frequency division number is an odd number, based on the control signal
  • the clock signal output by the clock output unit is controlled to perform duty correction to output a divided clock signal of equal duty ratio.
  • the computer executable instructions are further configured to: when the input clock source period expires, control the count value of the state machine unit to decrease by one, the change of the count value as a state jump; when receiving the corresponding state machine When the state satisfies the control signal of the preset state, the count value of the state machine unit is controlled to jump to the initial value.
  • the disclosed programmable frequency divider can be implemented in other manners.
  • the device embodiments described above are merely illustrative, For example, the division of the unit is only a logical function division, and the actual implementation may have another division manner, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be ignored. Or not.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk.
  • optical disk A medium that can store program code.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. Enabling a computer device (which may be a personal computer, server, or network device, etc.) to perform all of the methods of the various embodiments of the present invention or section.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.
  • the technical solution of the embodiment of the present invention solves the problem of the arbitrary frequency division, and realizes that the duty ratio of the output clock signal is maintained at 50%; when the state machine jumps to the state, when the state machine state jumps to the setting according to the frequency division ratio
  • the logic unit controls the state machine to set and outputs a control signal to invert the output clock signal, which greatly reduces the output delay and the delay amount is fixed at the same time, and the output noise is greatly reduced; in addition, the clock The output unit controls the output clock signal to be inverted according to the state of the state machine.
  • the critical path can be judged by 1 bit, the delay of the control logic is minimized, and the high-speed clock frequency division of the frequency divider is realized.

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Abstract

本发明实施例公开了一种可编程分频器及计算机存储介质。所述可编程分频器包括：状态机单元，配置为当输入的时钟源周期到时，控制状态跳转，基于所述状态跳转输出表征所述状态机单元状态的时钟信号；所述状态机单元的状态数与分频数相适应；逻辑单元，配置为获得表征所述状态机状态的时钟信号，输出控制信号至所述时钟输出单元；当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转；还配置为当分频数为奇数时，控制输出的时钟信号进行占空比修正；时钟输出单元，配置为当分频数为偶数时，输出等占空比的分频时钟信号；当分频数为奇数时，控制输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。

Description

一种可编程分频器及计算机存储介质 技术领域
本发明涉及分频器领域，具体涉及一种可编程分频器及计算机存储介质。
背景技术
在通用时钟芯片中，由于应用广泛，对时钟的输出提出了更高的要求，在压控振荡器(VCO)输出频率不变的情况下，时钟通道分频器的分频比任意可配置成了唯一的解决方案。现有技术中可以完成任意分频功能的技术方案，均有一些不足之处。例如分频结构的输出占空比随着分频配置的变化而变化，输入输出的延时不可控，分频级数越多，输出的时钟延时越大，同时对时钟通路引入的噪声越多。
发明内容
为解决现有存在的技术问题，本发明实施例提供了一种可编程分频器及计算机存储介质。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种可编程分频器，所述可编程分频器包括状态机单元、逻辑单元和时钟输出单元；所述状态机单元的状态数与分频数相适应；
所述状态机单元与所述逻辑单元连接，配置为当输入的时钟源周期到时，控制状态跳转，基于所述状态机单元的状态跳转输出表征所述状态机单元状态的时钟信号；
所述逻辑单元与所述时钟输出单元连接，配置为获得表征所述状态机 状态的时钟信号，基于所述状态机的状态输出控制信号至所述时钟输出单元和所述状态机单元；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；还配置为当分频数为奇数时，控制输出的时钟信号进行占空比修正；
所述时钟输出单元，配置为当分频数为偶数时，基于所述控制信号输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号控制输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。
在一实施例中，所述状态机单元具体为减法计数单元，配置为当输入的时钟源周期到时，控制计数值减一，所述计数值的变化作为状态跳转；还配置为当接收到对应于状态机的状态满足预设状态的控制信号时，控制计数值跳转至初始值；
其中，所述减法计数单元包括第一输入端、第二输入端、时钟源输入端、第一信号输出端和第二信号输出端；所述第一信号输出端和/或所述第二信号输出端与所述逻辑单元连接；所述第一信号输出端与所述第二输入端连接；所述第二信号输出端与所述第一输入端连接；
其中，所述第一信号输出端输出的第一信号和/或所述第二信号输出端输出的第二信号输入所述逻辑单元；以及所述第一信号输出端输出的第一信号输入所述第二输入端；所述第二信号输出端输出的第二信号输入所述第一输入端。
在一实施例中，所述减法计数单元包括第一选择器、第二选择器和第一D触发器；其中，
所述第一选择器的输出端与所述第二选择器的第一输入端连接；所述第一选择器配置为基于控制信号输入端输入的第一控制信号选择所述第一信号或所述第二信号作为第一输入信号输入所述第二选择器的第一输入 端；
所述第二选择器的第二输入端用于输入配置数信号；所述第二选择器的输出端与所述第一D触发器的输入端连接；所述第二选择器配置为基于控制信号输入端输入的所述控制信号选择所述第一输入信号或配置数信号输出至第一D触发器；
所述第一D触发器的第一信号输出端和第二信号输出端分别与所述第一选择器的第二输入端和第一输入端连接；所述第一D触发器配置为基于时钟源输入端输入的时钟源信号输出所述第一信号和/或所述第二信号。
在一实施例中，所述可编程分频器还包括或门处理单元，配置为获得所述第一D触发器上一级输出的第一信号进行逻辑或运算，将运算结果作为输入至所述第一选择器的所述第一控制信号。
在一实施例中，所述逻辑单元的第一输出端与所述时钟输出单元的控制信号输入端连接；所述逻辑单元的第一输出端还与所述减法计数单元的控制信号输入端连接；所述逻辑单元的输出端输出的控制信号分别输入所述时钟输出单元和所述减法计数单元，配置为基于所述控制信号控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；
所述逻辑单元还包括用于输出选择信号的第二输出端，所述第二输出端与所述时钟输出单元连接。
在一实施例中，所述时钟输出单元，配置为当分频数为2M+1时，基于所述控制信号输出的第一分频信号满足占空比为M/(2M+1)；M为正整数；将满足M/(2M+1)占空比的第一分频信号输入至占空比修正(DCC)校正单元进行占空比修正。
在一实施例中，所述时钟输出单元包括第三选择器、第二D触发器、DCC校正单元和第四选择器；所述第三选择器包括第一输入端、第二输入端、控制信号输入端和输出端；所述第三选择器的第一输入端和第二输入 端分别与所述减法计数单元的第一信号输出端和第二信号输出端连接；所述第三选择器的输出端与所述第二D触发器的输入端连接；所述第二D触发器的信号输出端分别与所述第四选择器的第一输入端和所述DCC校正单元的输入端连接；所述DCC校正单元的输出端与所述第四选择器的第二输入端连接；所述第四选择器的输出端输出等占空比的分频时钟信号；
所述第四选择器还包括与所述逻辑单元的第二输出端连接的选择信号输入端，配置为基于所述第二输出端输出的选择信号选择所述第二D触发器输出的时钟信号作为分频时钟信号，或选择所述DCC校正单元进行占空比修正后的时钟信号作为分频时钟信号。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的可编程分频器中的处理逻辑。
本发明实施例提供的可编程分频器及计算机存储介质，所述可编程分频器包括状态机单元、逻辑单元和时钟输出单元；所述状态机单元的位数与分频数相适应；所述状态机单元与所述逻辑单元连接，配置为当输入的时钟源周期到时，控制状态跳转，基于所述状态机单元的状态跳转输出表征所述状态机单元状态的时钟信号；所述逻辑单元与所述时钟输出单元连接，配置为获得表征所述状态机状态的时钟信号，基于所述状态机的状态输出控制信号至所述时钟输出单元和所述控制单元；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；还配置为当分频数为奇数时，控制所述时钟输出单元输出的时钟信号输入至DCC校正单元进行占空比修正；所述时钟输出单元，配置为当分频数为偶数时，基于所述控制信号输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号将输出时钟信号输入至DCC校正单元进行占空比修正，以输出等占空比的 分频时钟信号。采用本发明实施例的技术方案，解决了任意分频的同时，实现了输出时钟信号的占空比保持在50％；通过状态机跳转状态，当状态机的状态跳转至根据分频比设定的预设状态时，逻辑单元控制状态机置位并输出控制信号使输出时钟信号翻转，大大降低了输出延时且任意分频时延时量固定相等，还大大减少了输出噪声；另外，时钟输出单元是根据状态机的状态控制输出时钟信号翻转，在具体实现时可将关键路径通过1比特判断，使控制逻辑的延迟最低，实现了分频器的高速时钟分频。
附图说明
图1为本发明实施例的可编程分频器的组成结构示意图；
图2为本发明实施例的可编程分频器中的由减法计数单元实现的状态机单元的组成结构示意图；
图3为本发明实施例的可编程分频器中的由减法计数单元实现的状态机单元的线路连接示意图；
图4为本发明实施例的可编程分频器中的逻辑单元的线路连接示意图；
图5为本发明实施例的可编程分频器中的时钟输出单元的线路连接示意图；
图6为本发明实施例的可编程分频器中的DCC校正单元的组成结构以及线路连接示意图；
图7为本发明实施例中采用DCC校正单元校正后的时钟示意图；
图8为状态机跳转的一种示意图。
具体实施方式
下面结合附图及具体实施例对本发明作进一步详细的说明。
本发明实施例提供了一种可编程分频器。图1为本发明实施例的可编程分频器的组成结构示意图；如图1所示，所述可编程分频器包括减法状 态机单元11、逻辑单元12和时钟输出单元13；所述状态机单元11的状态数与分频数相适应；
所述状态机单元11与所述逻辑单元12连接，配置为当输入的时钟源周期到时，控制状态跳转，基于所述状态机单元11的状态跳转输出表征所述状态机单元11状态的时钟信号；
所述逻辑单元12与所述时钟输出单元13连接，配置为获得表征所述状态机状态的时钟信号，基于所述状态机的状态输出控制信号至所述时钟输出单元13和所述状态机单元11；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元13输出的时钟信号翻转以及控制所述状态机单元11置位；还配置为当分频数为奇数时，控制输出的时钟信号进行占空比修正；
所述时钟输出单元13，配置为当分频数为偶数时，基于所述控制信号输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号控制输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。
本实施例中，所述状态机单元11具体可通过减法计数单元实现，所述减法计数单元，配置为当输入的时钟源周期到时，控制计数值减一，所述计数值的变化作为状态跳转；还配置为当接收到对应于状态机的状态满足预设状态的控制信号时，控制计数值跳转至初始值。
作为一种实施方式，所述减法计数单元包括第一输入端、第二输入端、时钟源输入端、第一信号输出端和第二信号输出端；所述第一信号输出端和/或所述第二信号输出端与所述逻辑单元12连接；所述第一信号输出端与所述第二输入端连接；所述第二信号输出端与所述第一输入端连接；其中，所述第一信号输出端输出的第一信号和/或所述第二信号输出端输出的第二信号输入所述逻辑单元12；以及所述第一信号输出端输出的第一信号输入所述第二输入端；所述第二信号输出端输出的第二信号输入所述第一输入 端。
具体的，所述减法计数单元中的每个计数值均表示一个状态；当上电复位后，每个输入的时钟源周期到(例如时钟的上升沿到)时，所述减法计数单元的计数值减一，基于所述计数值输出表征所述减法计数器状态的时钟信号至所述逻辑单元12。
图2为本发明实施例的可编程分频器中的由减法计数单元实现的状态机单元的组成结构示意图；如图2所示，所述减法计数单元包括第一选择器(例如通过MA表示)、第二选择器(例如通过MB表示)和第一D触发器(例如通过DFF表示)；其中，所述第一选择器的输出端与所述第二选择器的第一输入端(0端)连接；所述第一选择器配置为基于控制信号输入端输入的第一控制信号选择所述第一信号或所述第二信号作为第一输入信号输入所述第二选择器的第一输入端(0端)；所述第二选择器的第二输入端(1端)用于输入配置数(例如DIV<N>表示)信号；所述第二选择器的输出端与所述第一D触发器的输入端(D端)连接；所述第二选择器配置为基于控制信号输入端输入的所述控制信号(所述控制信号通过SET表示)选择所述第一输入信号或配置数信号输出至第一D触发器；所述第一D触发器的第一信号输出端(Q端)和第二信号输出端(
Figure PCTCN2017077770-appb-000001
端)分别与所述第一选择器的第二输入端(1端)和第一输入端(0端)连接；所述第一D触发器配置为基于时钟源输入端输入的时钟源信号输出所述第一信号和/或所述第二信号；其中，所述第一D触发器的R端为重置(Reset)端。其中，所述可编程分频器还包括或门处理单元，配置为获得所述第一D触发器上一级输出的第一信号进行逻辑或运算，将运算结果作为输入至所述第一选择器的所述第一控制信号，所述第一控制信号可表示为CLK_OUT<1>OR CLK_OUT<2>OR……OR CLK_OUT<N-1>；其中，CLK_OUT<1>、CLK_OUT<2>……、CLK_OUT<N-1>分别为所述第一D触发器上一级输出 的第一信号；OR表示逻辑或运算。
本实施例中，可编程分频器中的减法计数单元的级数与分频器的分频数相适应；当分频位数为N(N为正整数)时，所述减法计数单元的级数至少为(N-1)。
图3为本发明实施例的可编程分频器中的由减法计数单元实现的状态机单元的线路连接示意图；结合图2和图3所示的减法计数单元，以图3中的第二个减法计数单元112(第N-1级)为例进行说明。具体的，第二个减法计数单元112输出的两个信号：第一信号(例如CLK_OUTP<N-1>)和第二信号(例如CLK_OUTN<N-1>)作为循环输入信号输入至所述第二个减法计数单元112，具体是第一D触发器(DFFN1)输出的第一信号(例如CLK_OUTP<N-1>)和第二信号(例如CLK_OUTN<N-1>)循环输入至第一选择器(MAN1)。所述第一选择器的第一控制信号为或门处理单元获得的所述第一D触发器上一级输出的第一信号进行逻辑或运算处理后的处理结果，例如所述控制信号为CLK_OUTP<1>一直到CLK_OUTP<N-2>的逻辑或运算的运算结果；当然，在其他实施方式中，所述第一控制信号也可以为所述门处理单元获得的所述第一D触发器上一级输出的第二信号进行逻辑或运算处理后的处理结果，例如所述控制信号为CLK_OUTN<1>一直到CLK_OUTN<N-2>的逻辑或运算的运算结果；在图3中所述的CLK_OUT<1>OR CLK_OUT<2>……OR CLK_OUT<N-2>具体可以是上一级输出的第一信号进行逻辑或运算的运算结果，也可以是上一级输出的第二信号进行逻辑或运算的运算结果。第三个减法计数单元113的相关处理规则可参照上述第二个减法计数单元112的相关描述，这里不再赘述。
作为一种实施方式，所述第一选择器(MAN1)基于所述第一控制信号控制输入的第一信号或第二信号作为第一输入信号输入至第二选择器(MBN1)；所述第二选择器(MBN1)基于逻辑单元产生的控制信号(SET) 选择所述第一输入信号或配置数信号输出至第一D触发器(DFFN1)；其中，所述控制信号为所述逻辑单元12输出的控制信号(SET信号)。其中，所述配置数信号中输入的配置数为外部基于分频器位数N进行配置，例如图3中所示的DIV<1>、DIV<N-1>、DIV<N>，具体与分频位数N相关。第一D触发器的输入时钟为输入的时钟源，输出的第一信号和第二信号一方面重新输入至所述第一选择器，另一方面，所述第一信号和/或第二信号作为输入信号输入至所述逻辑单元12。
需要说明的是，如图3所示，第一级减法计数单元111可不具有第一选择器，即仅具有第二选择器和第一D触发器；所述第二选择器和所述第一D触发器的连接方式与上述描述相同，这里不再赘述。
作为一种实施方式，图4为本发明实施例的可编程分频器中的逻辑单元的线路连接示意图；如图4所示，所述逻辑单元12的输出端与所述时钟输出单元13的控制信号(SET)输入端连接；所述逻辑单元12的输出端还与所述减法计数单元的控制信号(SET)输入端连接；其中，所述逻辑单元12的输出端输出的控制信号(SET)分别输入所述时钟输出单元13和所述减法计数单元，配置为基于所述减法计数单元的计数状态输出控制信号至所述时钟输出单元和所述状态机单元；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及用于控制所述状态机单元置位；还配置为当分频数为奇数时，控制输出的时钟信号进行占空比修正；所述逻辑单元12还包括用于输出选择信号(例如图中所示的ODD_EVEN信号)的第二输出端，所述第二输出端与所述时钟输出单元连接。
具体的，所述逻辑单元12预先配置有基于分频数设置的预设状态，以当获得表征所述减法计数单元的计数状态的时钟信号时，判断所述减法计数单元的计数状态是否达到所述预设状态，在判定所述计数状态达到所述 预设状态时，输出控制信号，所述控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及用于控制所述状态机单元置位。
本实施例中，所述时钟输出单元13，具体配置为当分频数为2M+1时，基于所述控制信号输出的第一分频信号满足占空比为M/(2M+1)；M为正整数；将满足M/(2M+1)占空比的第一分频信号输入至DCC校正单元进行占空比修正。
作为一种实施方式，图5为本发明实施例的可编程分频器中的时钟输出单元的线路连接示意图；如图5所示，所述时钟输出单元13包括第三选择器(例如可通过MO表示)、第二D触发器(例如可通过DFFO表示)、DCC校正单元和第四选择器；所述第三选择器包括第一输入端(0端)、第二输入端(1端)、控制信号输入端(所述控制信号为SET)和输出端；所述第三选择器的第一输入端和第二输入端分别与所述减法计数单元的第一信号输出端和第二信号输出端连接；即所述第三选择器(MO)的0端和1端分别接入CLK_OUTP<N>信号和CLK_OUTN<N>信号；所述第三选择器的输出端与所述第二D触发器的输入端(D端)连接；所述第二D触发器还包括时钟源输入端，用于输入时钟源信号(CLK_IN)，所述时钟源信号与所述减法计数单元中输入第一D触发器中的时钟源信号为同一时钟源信号；所述第二D触发器的信号输出端(Q端)分别与所述第四选择器的第一输入端(0端)和所述DCC校正单元的输入端连接；所述DCC校正单元的输出端与所述第四选择器的第二输入端(1端)连接；所述第四选择器的输出端输出等占空比的分频时钟信号(输出的分频时钟信号表示为CLKOUT)；所述第四选择器还包括与所述逻辑单元的第二输出端连接的选择信号输入端，配置为基于所述第二输出端输出的选择信号(例如ODD_EVEN信号)选择所述第二D触发器输出的时钟信号作为分频时钟信号，或选择所述DCC校正单元进行占空比修正后的时钟信号作为分频时钟 信号。
结合图4、图5以及图2和图3所示，作为一种示例，所述减法计数单元输出的第一信号，例如CLK_OUTP<1>……CLK_OUTP<N-1>、CLK_OUTP<N>作为所述逻辑单元12的输入信号；作为其他实施方式，所述减法计数单元输出的第二信号，例如CLK_OUTN<1>……CLK_OUTN<N-1>、CLK_OUTN<N>也可作为所述逻辑单元12的输入信号；当然，所述第一信号和所述第二信号也可共同作为所述逻辑单元12的输入信号。所述逻辑单元12通过内部的用于逻辑判断的逻辑门模块对输入信号进行处理输出控制信号(例如SET信号)；所述控制信号(例如SET信号)主要用于基于所述减法计数单元的计数状态是否满足预设状态控制时钟输出单元13对输入的时钟信号(例如CLK_OUTP和CLK_OUTN)的选择，从而控制输出的时钟信号的翻转。具体的，所述逻辑单元12内预先配置一预设值，通过用于逻辑判断的逻辑门模块对输入的表征所述减法计数单元状态的时钟信号的逻辑判断，判定当所述减法计数单元的计数值达到所述预设值，也可以理解为所述减法计数单元的状态达到预设状态时，通过输出的控制信号控制所述时钟输出单元13选择的时钟信号翻转，以达到分频的作用。具体的，当分频数为2M时，对应分频为M：M；当分频数为2M+1时，对应分频为M：(M+1)。
进一步地，当分频数为2M时，输出的时钟可保证为M/2M＝50％的占空比，即所述时钟输出单元13直接输出等占空比(即50％)的时钟分频信号；当分频数为2M+1时，输出的时钟可保证为M/(2M+1)的占空比；为得到等占空比，本实施例中，所述可编程分频器的时钟输出单元13中还设置有DCC校正单元，配置为当所述分频数为奇数时，对输出的分频时钟信号进行占空比修正，获得等占空比的分频时钟信号。
本实施例中，所述DCC校正单元具体可参照图6所示，由于输出的占 空比是可以预知的，图6所示的占空比修正单元对M/(2M+1)的占空比进行修正，也即用于对高位信号和低位信号相差一个周期的分频时钟信号进行修正，从而获得等占空比的分频时钟信号。采用分频后的时钟示意图可参照图7所示。
图8为分频器的状态机跳转的一种示意图；本示意中以7(3’b111)(其中，b表示比特，“111”为7表示的二进制数)分频配置为例说明分频器的状态机跳转，如图8所示，当配置为7分频时，需要用到的状态机的状态为2bit，上电完成后，复位(RST)端释放，此时状态机的状态为(2’b00)，分频器的输出为低位(low)状态，再之后第一个输入时钟上升沿到来的时候，状态机跳转到(2’b11)，同时分频器的输出变为高位(high)状态；根据预先配置，第二个输入时钟上升沿到来的时候，状态机跳转到(2’b10)，分频器的输出保持high状态；第三个输入时钟上升沿到来的时候，状态机跳转到(2’b01)，分频器的输出保持high状态；第四个输入时钟上升沿到来的时候，逻辑单元控制状态机跳转到(2’b11)，同时分频器的输出变为low状态；第五个输入时钟上升沿到来的时候，状态机跳转到(2’b10)，分频器的输出保持low状态；第六个输入时钟上升沿到来的时候，状态机跳转到(2’b01)，分频器的输出保持low状态；第七个输入时钟上升沿到来的时候，状态机跳转到2’b00)，分频器的输出保持low状态；第八个输入时钟上升沿到来的时候，逻辑单元控制状态机跳转到(2’b11)，同时分频器的输出跳变为high状态，此时的状态和第一个输入时钟上升沿到来的时候相同，分频器的工作状态如此往复，这样在输出端就得到了一个输出占空比为3/7的分频输出时钟。
基于上述描述可预先配置本发明实施例中逻辑模块中的预设值，以此可获得任意占空比(包括等占空比)的分频时钟信号。
下面结合本发明实施例的可编程分频器的组成结构，用逻辑门搭建的 减法计数器实现状态机，对本发明实施例的可编程分频器的处理流程进行说明。
假设目前的分频器设计为N位，则需要搭建N位的减法计数器，外部配置数为DIV<N:0>，输入时钟信号为CLK_IN，输出时钟信号为CLK_OUT，0表示低电平状态，1表示高电平状态。
首先，上电后到复位(RST)信号释放之前，所有D触发器的状态均为0，CLK_OUT输出为0。
RST释放，释放后第一个CLK_IN的上升沿到来之后，此时DIV<N:1>的值写入到N bit的减法计数器中，具体是通过第二选择器写入第一D触发器中，同时将分频器的输出变为1；进一步地，CLK_IN的上升沿到来之后，N bit的减法计数器做减1操作，分频器的输出为1保持不变；当CLK_IN的上升沿到来之后，N bit的减法计数器计数为N’b001时，下一个输入时钟的上升沿来之后，此时DIV<N:1>的值重新写入到N bit的减法计数器中，分频器的输出变为0，接下来的CLK_IN上升沿到来后，N bit的减法计数器做减1操作，分频器的输出保持0不变，直至当DIV<0>的值为0的时候，减法计数器会计数到N’b001，当DIV<0>的值为1的时候，减法计数器会计数到N’b00；下一个输入时钟的上升沿来之后，此时DIV<N:1>的值重新写入到N bit的减法计数器中，输出重新为1，此时一个完整的分频周期完成。再根据配置值DIV<0>为1或0，判断分频为奇数还是偶数从而决定是否对输出信号做DCC处理，如果为奇数分频的话，就需要采用图6所示的DCC校正单元，从而得到50％占空比的分频时钟信号。
采用本发明实施例的技术方案，解决了任意分频的同时，实现了输出时钟信号的占空比保持在50％；通过状态机跳转状态，当状态机的状态跳转至根据分频比设定的预设状态时，逻辑单元控制状态机置位并输出控制信号使输出时钟信号翻转，大大降低了输出延时且任意分频时延时量固定 相等，还大大减少了输出噪声；另外，时钟输出单元是根据状态机的状态控制输出时钟信号翻转，在具体实现时可将关键路径通过1比特判断，使控制逻辑的延迟最低，实现了分频器的高速时钟分频。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的可编程分频器中的处理逻辑。具体的，所述计算机可执行指令用于执行：当输入的时钟源周期到时，控制状态机单元状态跳转，基于所述状态机单元的状态跳转输出表征所述状态机单元状态的时钟信号；获得表征所述状态机状态的时钟信号，基于所述状态机的状态输出控制信号至所述时钟输出单元和所述状态机单元；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；当分频数为偶数时，基于所述控制信号控制所述时钟输出单元输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号控制所述时钟输出单元输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。
所述计算机可执行指令还用于执行：当分频数为偶数时，基于所述控制信号控制所述时钟输出单元输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号控制所述时钟输出单元输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。
所述计算机可执行指令还用于执行：当输入的时钟源周期到时，控制所述状态机单元的计数值减一，所述计数值的变化作为状态跳转；当接收到对应于状态机的状态满足预设状态的控制信号时，控制所述状态机单元的计数值跳转至初始值。
在本申请所提供的几个实施例中，应该理解到，所揭露的可编程分频器，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的， 例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或 部分。而前述的存储介质包括：移动存储设备、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本发明实施例的技术方案解决了任意分频的同时，实现了输出时钟信号的占空比保持在50％；通过状态机跳转状态，当状态机的状态跳转至根据分频比设定的预设状态时，逻辑单元控制状态机置位并输出控制信号使输出时钟信号翻转，大大降低了输出延时且任意分频时延时量固定相等，还大大减少了输出噪声；另外，时钟输出单元是根据状态机的状态控制输出时钟信号翻转，在具体实现时可将关键路径通过1比特判断，使控制逻辑的延迟最低，实现了分频器的高速时钟分频。

Claims (8)

  1. 一种可编程分频器，所述可编程分频器包括状态机单元、逻辑单元和时钟输出单元；所述状态机单元的状态数与分频数相适应；
    所述状态机单元与所述逻辑单元连接，配置为当输入的时钟源周期到时，控制状态跳转，基于所述状态机单元的状态跳转输出表征所述状态机单元状态的时钟信号；
    所述逻辑单元与所述时钟输出单元连接，配置为获得表征所述状态机状态的时钟信号，基于所述状态机的状态输出控制信号至所述时钟输出单元和所述状态机单元；其中，当所述状态机的状态满足预设状态时，输出的控制信号用于控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；还配置为当分频数为奇数时，控制输出的时钟信号进行占空比修正；
    所述时钟输出单元，配置为当分频数为偶数时，基于所述控制信号输出等占空比的分频时钟信号；当分频数为奇数时，基于所述控制信号控制输出的时钟信号进行占空比修正，以输出等占空比的分频时钟信号。
  2. 根据权利要求1所述的可编程分频器，其中，所述状态机单元具体为减法计数单元，配置为当输入的时钟源周期到时，控制计数值减一，所述计数值的变化作为状态跳转；还配置为当接收到对应于状态机的状态满足预设状态的控制信号时，控制计数值跳转至初始值；
    其中，所述减法计数单元包括第一输入端、第二输入端、时钟源输入端、第一信号输出端和第二信号输出端；所述第一信号输出端和/或所述第二信号输出端与所述逻辑单元连接；所述第一信号输出端与所述第二输入端连接；所述第二信号输出端与所述第一输入端连接；
    其中，所述第一信号输出端输出的第一信号和/或所述第二信号输出端输出的第二信号输入所述逻辑单元；以及所述第一信号输出端输出的第一 信号输入所述第二输入端；所述第二信号输出端输出的第二信号输入所述第一输入端。
  3. 根据权利要求2所述的可编程分频器，其中，所述减法计数单元包括第一选择器、第二选择器和第一D触发器；其中，
    所述第一选择器的输出端与所述第二选择器的第一输入端连接；所述第一选择器配置为基于控制信号输入端输入的第一控制信号选择所述第一信号或所述第二信号作为第一输入信号输入所述第二选择器的第一输入端；
    所述第二选择器的第二输入端用于输入配置数信号；所述第二选择器的输出端与所述第一D触发器的输入端连接；所述第二选择器配置为基于控制信号输入端输入的所述控制信号选择所述第一输入信号或配置数信号输出至第一D触发器；
    所述第一D触发器的第一信号输出端和第二信号输出端分别与所述第一选择器的第二输入端和第一输入端连接；所述第一D触发器配置为基于时钟源输入端输入的时钟源信号输出所述第一信号和/或所述第二信号。
  4. 根据权利要求3所述的可编程分频器，其中，所述可编程分频器还包括或门处理单元，配置为获得所述第一D触发器上一级输出的第一信号进行逻辑或运算，将运算结果作为输入至所述第一选择器的所述第一控制信号。
  5. 根据权利要求2所述的可编程分频器，其中，所述逻辑单元的第一输出端与所述时钟输出单元的控制信号输入端连接；所述逻辑单元的第一输出端还与所述减法计数单元的控制信号输入端连接；所述逻辑单元的输出端输出的控制信号分别输入所述时钟输出单元和所述减法计数单元，配置为基于所述控制信号控制所述时钟输出单元输出的时钟信号翻转以及控制所述状态机单元置位；
    所述逻辑单元还包括用于输出选择信号的第二输出端，所述第二输出端与所述时钟输出单元连接。
  6. 根据权利要求1所述的可编程分频器，其中，所述时钟输出单元，配置为当分频数为2M+1时，基于所述控制信号输出的第一分频信号满足占空比为M/(2M+1)；M为正整数；将满足M/(2M+1)占空比的第一分频信号输入至DCC校正单元进行占空比修正。
  7. 根据权利要求5所述的可编程分频器，其中，所述时钟输出单元包括第三选择器、第二D触发器、DCC校正单元和第四选择器；所述第三选择器包括第一输入端、第二输入端、控制信号输入端和输出端；所述第三选择器的第一输入端和第二输入端分别与所述减法计数单元的第一信号输出端和第二信号输出端连接；所述第三选择器的输出端与所述第二D触发器的输入端连接；所述第二D触发器的信号输出端分别与所述第四选择器的第一输入端和所述DCC校正单元的输入端连接；所述DCC校正单元的输出端与所述第四选择器的第二输入端连接；所述第四选择器的输出端输出等占空比的分频时钟信号；
    所述第四选择器还包括与所述逻辑单元的第二输出端连接的选择信号输入端，配置为基于所述第二输出端输出的选择信号选择所述第二D触发器输出的时钟信号作为分频时钟信号，或选择所述DCC校正单元进行占空比修正后的时钟信号作为分频时钟信号。
  8. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至7任一项所述的可编程分频器中的处理逻辑。
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