WO2018094599A1 - 一种隧穿场效应晶体管制备方法及其隧穿场效应晶体管 - Google Patents

一种隧穿场效应晶体管制备方法及其隧穿场效应晶体管 Download PDF

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WO2018094599A1
WO2018094599A1 PCT/CN2016/106896 CN2016106896W WO2018094599A1 WO 2018094599 A1 WO2018094599 A1 WO 2018094599A1 CN 2016106896 W CN2016106896 W CN 2016106896W WO 2018094599 A1 WO2018094599 A1 WO 2018094599A1
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semiconductor substrate
field effect
type
effect transistor
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PCT/CN2016/106896
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English (en)
French (fr)
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蔡皓程
徐挽杰
张臣雄
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华为技术有限公司
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Priority to PCT/CN2016/106896 priority Critical patent/WO2018094599A1/zh
Priority to CN201680064326.8A priority patent/CN108352406A/zh
Publication of WO2018094599A1 publication Critical patent/WO2018094599A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present application relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor manufacturing method and a tunneling field effect transistor.
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the gate length is reduced to below 45 nm, which is limited by the carrier Boltzmann heat distribution.
  • the subthreshold swing (English name: Subthreshold Swing, abbreviation: SS) seriously affects the switching rate of the MOSFET device at the corresponding gate voltage, so that the leakage current of the MOSFET device increases exponentially with the decrease of the power supply voltage, thus the MOSFET device Static power consumption has grown exponentially.
  • the tunneling field effect transistor (English name: Tunneling Field Effect Transistor, abbreviation: TFET) is proposed as a potential replacement for MOSFET devices. Its working principle is fundamentally different from that of traditional MOSFET devices.
  • the working principle of MOSFET is to utilize The diffusion drift mechanism of carriers, and the working principle of TFET is the tunneling mechanism.
  • the tunneling mechanism is roughly divided into point tunneling and line tunneling according to the tunneling mode. Line tunneling provides larger tunneling. The area can thus increase the tunneling probability and increase the turn-on current.
  • the sub-negative current is not limited by the carrier heat distribution, and a relatively small SS can be realized, thereby reducing the operation of the device. Voltage, which reduces the device's shutdown current and reduces the device's static power dissipation.
  • a conventional tunneling field effect transistor has a structure as shown in FIG. 1 and is a field-effect transistor of a fin structure (English name: Fin Field-Effect Transistor, abbreviated as FinFET), as shown in FIG. 1a and FIG. 1b.
  • FinFET Fin Field-Effect Transistor
  • Embodiments of the present application provide a tunneling field effect transistor manufacturing method and a tunneling field effect transistor thereof, which can effectively control source and drain doping diffusion to an epitaxial layer of a device, thereby stably controlling a tunneling field effect.
  • the parameters of the transistor are described below.
  • the first aspect of the embodiments of the present application provides a method for fabricating a tunneling field effect transistor, the method comprising: providing a semiconductor substrate; respectively forming a drain region and a source region on both sides of the semiconductor substrate; An epitaxial layer is deposited on the surface of the substrate; a gate region is formed on the epitaxial layer, the gate region is in contact with the drain region and the source region through the epitaxial layer; and a tunneling region is formed in a region where the gate region and the source region overlap.
  • the drain region and the source region of the tunneling field effect transistor are first prepared, and then the epitaxial layer is deposited on the surface of the semiconductor substrate, and finally the gate region is prepared.
  • the doping diffusion of the source region and the drain region to the epitaxial layer can be effectively controlled, that is, the doping diffusion of the source region and the drain region can be effectively reduced to the epitaxial layer, thereby effectively controlling the tunneling field effect transistor. parameter.
  • the forming the drain region and the source region on both sides of the semiconductor substrate respectively means: performing a first doping type ion doping to form a drain region in a first region of the semiconductor substrate, A second doping type ion doping is performed on the second region of the semiconductor substrate to form a source region, the first region and the second region being different regions in the semiconductor substrate.
  • forming the drain region and the source region on both sides of the semiconductor substrate respectively means: forming a first doping type epitaxial layer in the first region of the semiconductor substrate by using a hard mask process, using The hard mask process forms a second doped type epitaxial layer in the second region of the semiconductor substrate, the first region and the second region being different regions in the semiconductor substrate.
  • the first doping type is a P type
  • the second doping type is an N type
  • a first doping The impurity type is N type
  • the second doping type is P type.
  • the doping range of the source region is greater than the doping range of the drain region.
  • an epitaxial layer is deposited on the surface of the semiconductor substrate, specifically by depositing an epitaxial layer of silicon on the surface of the drain region and the source region.
  • the semiconductor substrate used in the method for fabricating the tunneling field effect transistor in the embodiment of the present application is a fin structure semiconductor substrate, or a planar structure semiconductor substrate, or an insulator silicon (English name: Silicon) On Insulator, abbreviation: SOI) substrate.
  • a second aspect of the present application provides a tunneling field effect transistor, the tunneling field effect transistor comprising: a semiconductor substrate; a drain region and a source region respectively formed on both sides of the semiconductor substrate; and a semiconductor substrate An epitaxial layer deposited on the surface; a gate region formed on the epitaxial layer, the gate region is in contact with the drain region and the source region through the epitaxial layer; and a tunneling region formed in a region where the gate region and the source region overlap .
  • the tunneling field effect crystal drain region in the embodiment of the present application is formed by first doping type ion doping of the first region of the semiconductor substrate, and the source region is semiconductor based.
  • the second region of the material is subjected to a second doping type ion doping formation, wherein the first region and the second region are different regions in the semiconductor substrate.
  • the drain region of the tunneling field effect transistor in the embodiment of the present application is a first doping type epitaxial layer formed on a semiconductor substrate by a hard mask process, and the source region is utilized.
  • Hard mask process A second doped type epitaxial layer formed on a semiconductor substrate.
  • the first doping type is P-type
  • the second doping type is N-type
  • the first doping type is N-type
  • the second doping type is P-type
  • the doping range of the source region of the tunneling field effect transistor in the embodiment of the present application is greater than the doping range of the drain region.
  • the tunneling field effect transistor in the embodiment of the present application has an epitaxial layer of intrinsic silicon epitaxial layer deposited on the drain region and the surface of the source region.
  • the semiconductor substrate of the tunneling field effect transistor in the embodiment of the present application is a fin structure semiconductor substrate, or a planar structure semiconductor substrate, or an SOI substrate.
  • the drain region and the source region of the tunneling field effect transistor are first prepared, and then the epitaxial layer is deposited on the surface of the semiconductor substrate, and finally
  • the gate region can be prepared to effectively control the doping diffusion of the source region and the drain region to the epitaxial layer, that is, the doping diffusion of the source region and the drain region can be effectively reduced to the epitaxial layer, thereby effectively controlling the tunnel.
  • the parameters of the field effect transistor are first prepared, and then the epitaxial layer is deposited on the surface of the semiconductor substrate, and finally the gate region can be prepared to effectively control the doping diffusion of the source region and the drain region to the epitaxial layer, that is, the doping diffusion of the source region and the drain region can be effectively reduced to the epitaxial layer, thereby effectively controlling the tunnel.
  • 1a is a schematic structural view of a conventional tunneling field effect transistor
  • FIG. 1b is a schematic diagram of another structure of a conventional tunneling field effect transistor
  • FIG. 2 is a schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present application.
  • FIG. 3 is a schematic flow chart of an embodiment of a tunneling field effect transistor according to an embodiment of the present application.
  • 4a-4f are schematic diagrams showing various process steps in a method for fabricating a tunneling field effect transistor according to an embodiment of the present application.
  • the embodiment of the present application provides a method for fabricating a tunneling field effect transistor and a tunneling field effect transistor thereof, which can effectively control source and drain doping diffusion to an epitaxial layer, thereby stably controlling a tunneling field effect transistor. parameter.
  • FIG. 2 is a schematic structural diagram of an N-type tunneling field effect transistor (NTFET) and a P-type tunneling field effect transistor (PTFET) in the embodiment of the present application.
  • NFET N-type tunneling field effect transistor
  • P-type tunneling field effect transistor P-type tunneling field effect transistor
  • FIG. 2 is a schematic diagram of an embodiment of a tunneling field effect transistor according to an embodiment of the present application.
  • the tunneling field effect transistor includes:
  • a semiconductor substrate 201 a drain region 202 and a source region 203 formed on both sides of the semiconductor substrate 201; an epitaxial layer 204 deposited on the surface of the semiconductor substrate 201; a gate region 205 formed on the epitaxial layer, a gate
  • the polar region is in contact with the drain region and the source region through the epitaxial layer; and a tunneling region formed in a region where the gate region and the source region overlap.
  • the tunneling field effect crystal drain region 202 in the embodiment of the present application is formed by the first doping type ion doping of the first region of the semiconductor substrate 201, and the source region 203 is A second doping type ion doping is performed from a second region of the semiconductor substrate, wherein the first region 202 and the second region 203 are different regions in the semiconductor substrate 201.
  • the drain region 202 of the tunneling field effect transistor in the embodiment of the present application is a first doping type epitaxial layer formed on a semiconductor substrate by a hard mask process, and the source region 203 A second doped type epitaxial layer formed on a semiconductor substrate using a hard mask process.
  • the first doping type is P-type
  • the second doping type is N-type
  • the first doping type is N-type
  • the second doping type is P-type
  • the doping range of the source region 203 of the tunneling field effect transistor in the embodiment of the present application is greater than the doping range of the drain region 202.
  • the tunneling field effect transistor in the embodiment of the present application has an epitaxial layer epitaxial silicon epitaxial layer deposited on the drain region and the surface of the source region.
  • the semiconductor substrate of the tunneling field effect transistor in the embodiment of the present application is a fin structure semiconductor substrate, or a planar structure semiconductor substrate, or an SOI substrate, which is not limited herein.
  • the structure of the tunneling field effect transistor in the embodiment of the present application can effectively increase the gate control area, that is, the area of the tunneling region 206, thereby increasing the tunneling field effect transistor. Turn on the current.
  • the embodiment of the present application further provides a method for preparing a tunneling field effect transistor.
  • the tunneling field effect transistor manufacturing method of the embodiment of the present application may be used for separately preparing a P-type tunneling field effect crystal, or may be used for separately preparing an N-type tunneling field effect transistor, or may be used for At the same time, N-type and P-type tunneling field effect transistors are prepared.
  • the following embodiments will describe the process of simultaneously preparing N-type and P-type tunneling field effect transistors:
  • FIG. 3 is a schematic flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present application, including:
  • a semiconductor substrate 3011 is provided, which respectively provides an N semiconductor substrate 3012 and a P-type semiconductor substrate 3013, which are separated by a shallow trench (English name: Shallow Trench Isolation, STI) 3014, and A thin oxide layer 3015 is applied over the N semiconductor substrate 3012 and the P-type semiconductor substrate 3013.
  • a shallow trench English name: Shallow Trench Isolation, STI
  • the semiconductor substrate 3011 may be a semiconductor material such as bulk silicon, silicon on insulator, germanium or a III-V compound.
  • the semiconductor substrate may be a fin structure semiconductor substrate, a planar structure transistor, or an SOI substrate, or may be a semiconductor substrate of other structures, which is not limited herein. Since the fin structure can make the tunneling area larger, the fin semiconductor substrate is selected in the embodiment of the present application.
  • drain region and the source region are respectively formed on both sides of the semiconductor substrate:
  • the regions are different regions in the semiconductor substrate, wherein the first doping type is P-type and the second doping type is N-type; or the first doping type is N-type and the second doping type is P-type.
  • the range of source regions is greater than the range of drain levels.
  • P-type doping forms a drain region in the first region 3021 of the P-type semiconductor substrate.
  • P-type doping forms a source-level region in the second region 3022 of the N-type semiconductor substrate.
  • a source region is formed by N-type doping in the second region 3023 of the P-type semiconductor substrate.
  • a first region 3024 of the N-type semiconductor substrate is N-doped to form a drain region.
  • the drain region and the source region may be prepared by using a hard mask technique, as follows: a first doping type epitaxial layer is formed in a first region of the semiconductor substrate by a hard mask process to form a drain region, using a hard The mask process forms a second doped type epitaxial layer in the second region of the semiconductor substrate to form a source region, the first region and the second region being different regions in the semiconductor substrate.
  • the first doping type is P type
  • the second doping type is N type
  • the first doping type is N type
  • the second doping type is P type.
  • the range of source regions is greater than the doping range.
  • a P-type semiconductor substrate is taken as an example, and a P-type epitaxial layer is formed in the first region 3021 of the P-type semiconductor substrate to form a drain region.
  • a P-type epitaxial layer is formed in the second region 3022 of the N-type semiconductor substrate to form a source region.
  • an N-type epitaxial layer is formed in the second region 3023 of the P-type semiconductor substrate to form a source region; and for the N-type semiconductor substrate, the N-type semiconductor substrate is The first region 3024 is N-doped to form a drain region.
  • the P-type epitaxial layer may be SiGe, and the N-type epitaxial layer may be SiP, which is not limited herein.
  • the first doping type ion doping is performed in the first region of the semiconductor substrate to form the drain region, and the second doping type ion doping is performed in the second region of the semiconductor substrate to form the source region.
  • the first region and the second region are different regions in the semiconductor substrate.
  • an epi-layer is deposited on the semiconductor substrate, and the epitaxial layer can be specifically Silicon epitaxial layer.
  • the conventional semiconductor fabrication process is continued, and a high dielectric layer (such as HfO2, SiO2, etc.) and a gate (such as Poly-Si) are deposited, that is, a layer is superimposed on the completed drain region and the source region.
  • a gate region 3041 is formed on the epitaxial layer, wherein the gate region passes through the epitaxial layer. Contact with the drain region and the source region.
  • the RMG process and the subsequent metal wiring process are then continued, which are not described here.
  • the drain region and the source region of the tunneling field effect transistor are first prepared, and the epitaxial layer is deposited on the surface of the drain region and the source region.
  • the gate region is prepared, that is, the Source-Drain First process, which can effectively control the doping diffusion of the source region and the drain region to the epitaxial layer, that is, the doping diffusion of the source region and the drain region can be effectively reduced.
  • the parameters of the tunneling field effect transistor can be effectively controlled.
  • the source-Drain First process is used to make the final alignment process of the transistor simple, and the overlap between the source region and the gate region can be effectively controlled.
  • the region, that is, the tunneling region can effectively control the tunneling area, thereby effectively controlling the parameters of the tunneling field effect transistor.
  • the disclosed systems, modules, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated modules when implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium.
  • this application Technical Solution In essence or in part that contributes to the prior art, or all or part of the technical solution may be embodied in the form of a software product, the computer software product is stored in a storage medium, including a plurality of instructions for making A computer device (which may be a personal computer, server, or network device, etc.) performs all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read only memory (English full name: Read-Only Memory abbreviation: ROM), a random access memory (English name: Random Access Memory, abbreviation: RAM), a disk or a disk. And other media that can store program code.

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Abstract

提供一种隧穿场效应晶体管的制备方法以及隧穿场效应晶体管。制备方法包括：提供半导体基材（201）；分别在半导体基材两侧形成漏极区域（202）以及源极区域（203）；在半导体基材表面沉积外延层（204）；在外延层上形成栅极区域（205），栅极区域通过外延层，与漏极区域以及源极区域接触；在栅极区域以及源极区域重叠的区域形成隧穿区域（206）。可以有效地减少源极区域以及漏极区域的掺杂扩散至外延层，从而可以有效地控制隧穿场效应晶体管的参数。

Description

一种隧穿场效应晶体管制备方法及其隧穿场效应晶体管 技术领域
本申请涉及半导体技术领域，尤其涉及到一种隧穿场效应晶体管制备方法以及隧穿场效应晶体管。
背景技术
如今，随着金属-氧化物-半导体场效应晶体管(英文全称：Metal-Oxide-Semiconductor Field Effect Transistor，缩写：MOSFET)的栅长缩小到45nm以下，受载流子波尔兹曼热分布限制的亚阈值摆幅(英文全称：Subthreshold Swing，缩写：SS)严重影响了MOSFET器件在相应的栅电压下的开关速率，使得MOSFET器件的漏电流随着电源电压的降低呈指数增长，从而MOSFET器件的静态功耗呈指数增长。隧穿场效应晶体管(英文全称：Tunneling Field Effect Transistor，缩写：TFET)是作为MOSFET器件的潜在替代者而提出来的，它的工作原理与传统MOSFET器件有着根本的不同，MOSFET的工作原理是利用载流子的扩散漂移机制，而TFET的工作原理是隧穿机制，其中，隧穿机制根据隧穿的方式大致又分为点隧穿和线隧穿方式，线隧穿提供较大的隧穿面积，因而可以提高隧穿机率，增加开启电流。应理解，从TFET的工作原理上来看，由于TFET的开启电流与温度没有指数依赖关系，因此亚阂值电流不受载流子热分布的限制，可以实现比较小的SS，从而降低器件的工作电压，减小器件的关断电流，降低器件的静态功耗。
一种现有的隧穿场效应晶体管的结构如图1所示，是一种鳍式结构的场效应晶体管(英文全称：Fin Field-Effect Transistor，缩写：FinFET)，如图1a以及图1b所示，为现有技术中的一种TFET结构示意图，现有技术在制作图1a以及图1b所示的TFET方法中，是在制作栅极(Dummy gate)之后，再利用热驱动的方式将源极以及漏级掺杂驱入通道内，此制程将难以控制源极以及漏级掺杂扩散至器件的外延层(epitaxial layer)，从而无法精准控制隧穿场效应晶体管的参数。
发明内容
本申请实施例提供了一种隧穿场效应晶体管制备方法及其隧穿场效应晶体管，可以有效地控制源极以及漏级掺杂扩散至器件的外延层，从而可以稳定的控制隧穿场效应晶体管的参数。
有鉴于此，本申请实施例第一方面提出了一种隧穿场效应晶体管制备方法，该方法包括：提供半导体基材；分别在半导体基材两侧形成漏极区域以及源极区域；在半导体基材表面上沉积外延层；在外延层上形成栅极区域，栅极区域通过外延层，与漏极区域以及源极区域接触；在栅极区域以及源极区域重叠的区域形成隧穿区域。
即本申请实施例中，在制备隧穿场效应晶体管时，先是制备隧穿场效应晶体管的漏极区域以及源极区域，再在半导体基材表面上沉积外延层，最后才制备栅极区域，可以有效地控制源极区域以及漏级区域的掺杂扩散至外延层，即可以有效地减少源极区域以及漏级区域的掺杂扩散至外延层，从而可以有效地控制隧穿场效应晶体管的参数。
在一种可能的实现中，上述分别在半导体基材两侧形成漏极区域以及源极区域具体是指：在半导体基材的第一区域进行第一掺杂类型离子掺杂形成漏极区域，在半导体基材的第二区域进行第二掺杂类型离子掺杂形成源极区域，第一区域和第二区域为半导体基材中不同的区域。
在一种可能的实现中，分别在半导体基材两侧形成漏极区域以及源极区域具体是指：利用硬掩膜工艺在半导体基材的第一区域形成第一掺杂类型外延层，利用硬掩膜工艺在半导体基材的第二区域形成第二掺杂类型外延层，第一区域和第二区域为半导体基材中不同的区域。
结合上述实现，在一种可能的实现中，在本申请实施例的隧穿场效应晶体管制备方法中，上述第一掺杂类型为P型，第二掺杂类型为N型；或者第一掺杂类型为N型，第二掺杂类型为P型。
在一种可能的实现中，源极区域的掺杂范围大于漏极区域的掺杂范围。
在一种可能的实现中，在半导体基材表面上沉积外延层，具体是指在漏极区域以及源极区域表面上沉积本证硅外延层。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管制备方法所采用的半导体基材为鱼鳍结构半导体基材，或平面结构半导体基材，或绝缘体硅(英文全称：Silicon on Insulator，缩写：SOI)基材。
本申请实施例第二方面提供了一种隧穿场效应晶体管，该隧穿场效应晶体管包括：半导体基材；分别在半导体基材两侧形成的漏极区域以及源极区域；在半导体基材表面上沉积的外延层；在外延层上形成的栅极区域，栅极区域通过外延层，与漏极区域以及源极区域接触；在栅极区域以及源极区域重叠的区域形成的隧穿区域。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体漏极区域由半导体基材的第一区域进行第一掺杂类型离子掺杂形成的，而源极区域为由半导体基材的第二区域进行第二掺杂类型离子掺杂形成，其中，第一区域和第二区域为半导体基材中不同的区域。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管的漏极区域为利用硬掩膜工艺在半导体基材上形成的第一掺杂类型外延层，而源极区域为利用硬掩膜工艺在半导体基材上形成的第二掺杂类型外延层。
在一种可能的实现中，上述第一掺杂类型为P型，第二掺杂类型为N型；或者第一掺杂类型为N型，第二掺杂类型为P型。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管的源极区域的掺杂范围大于漏极区域的掺杂范围。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管在漏极区域以及源极区域表面上沉积的外延层为本征硅外延层。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管的半导体基材为鱼鳍结构半导体基材，或平面结构半导体基材，或SOI基材。
由以上方案可见，在本申请实施例中，在制备隧穿场效应晶体管时，先是制备隧穿场效应晶体管的漏极区域以及源极区域，再在半导体基材表面上沉积外延层，最后才制备栅极区域，可以有效地控制源极区域以及漏级区域的掺杂扩散至外延层，即可以有效地减少源极区域以及漏级区域的掺杂扩散至外延层，从而可以有效地控制隧穿场效应晶体管的参数。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，还可以根据这些附图获得其他的附图。
图1a为一种现有的隧穿场效应晶体管的一个结构示意图；
图1b一种现有的隧穿场效应晶体管的另一结构示意图；
图2为本申请实施例中一种隧穿场效应晶体管的结构示意图；
图3为本申请实施例一种隧穿场效应晶体管制备一个实施例流程示意图；
图4a至图4f为本申请实施例一种隧穿场效应晶体管制备方法中各个工艺步骤的示意图。
具体实施方式
本申请实施例提供了一种隧穿场效应晶体管制备方法及其隧穿场效应晶体管，可以有效地控制源极以及漏级掺杂扩散至外延层，从而可以稳定的控制隧穿场效应晶体管的参数。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，都应当属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
如图2所示，为本申请实施例中的N型隧穿场效应晶体管(NTFET)以及P型隧穿场效应晶体管(PTFET)的结构示意图，为了便于叙述，下面将以N型隧穿场效应晶体管为例对本申请中的隧穿场效应晶体管进行描述，请参阅图2，图2为本申请实施例一种隧穿场效应晶体管一个实施例示意图，该隧穿场效应晶体管包括：
半导体基材201；分别在半导体基材201两侧形成的漏极区域202以及源极区域203；在半导体基材201表面上沉积的外延层204；在外延层上形成的栅极区域205，栅极区域通过外延层，与漏极区域以及源极区域接触；在栅极区域以及源极区域重叠的区域形成的隧穿区域。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体漏极区域202由半导体基材201的第一区域进行第一掺杂类型离子掺杂形成的，而源极区域203为由半导体基材的第二区域进行第二掺杂类型离子掺杂形成，其中，第一区域202和第二区域203为半导体基材201中不同的区域。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管的漏极区域202为利用硬掩膜工艺在半导体基材上形成的第一掺杂类型外延层，而源极区域203为利用硬掩膜工艺在半导体基材上形成的第二掺杂类型外延层。
在一种可能的实现中，上述第一掺杂类型为P型，第二掺杂类型为N型；或者第一掺杂类型为N型，第二掺杂类型为P型。
在一种可能的实现中，本申请实施例中的隧穿场效应晶体管的源极区域203的掺杂范围大于漏极区域202的掺杂范围。
可选地，本申请实施例中的隧穿场效应晶体管在漏极区域以及源极区域表面上沉积的外延层为本征硅外延层。
可选地，本申请实施例中的隧穿场效应晶体管的半导体基材为鱼鳍结构半导体基材，或平面结构半导体基材，或SOI基材，具体此处不做限定。
其中，上述是对于N型隧穿场效应晶体管的结构进行了描述，其中，P型隧穿场效应晶体管与N型隧穿场效应晶体管，具体可参照N型隧穿场效应晶体管以及图2，具体此处不再赘述。
由此可见，采用本申请实施例中的隧穿场效应晶体管的结构，能有效地增加栅极控制面积，即隧穿区域206的面积，从而可以增加隧穿场效应晶体管的 开启电流。
对应的，针对上述隧穿场效应晶体管，本申请实施例还提供了一种隧穿场效应晶体管制备方法。需要说明的是，本申请实施例的隧穿场效应晶体管制备方法可以用于单独制备P型隧穿场效应晶体中，也可以用于单独制备N型隧穿场效应晶体管中，也可以用于同时制备N型以及P型隧穿场效应晶体管，为了便于理解，下面的实施例中将以同时制备N型以及P型隧穿场效应晶体管的过程进行叙述：
请参阅图3，图3为本申请实施例一种隧穿场效应晶体管制备方法一个实施例流程示意图，包括：
301、提供半导体衬底以及半导体基材；
如图4a所示，提供一半导体衬底3011，分别提供N半导体基材3012以及P型半导体基材3013，两者间通过浅槽隔离(英文全称：Shallow Trench Isolation，缩写：STI)3014，并在N半导体基材3012以及P型半导体基材3013上敷上一层薄氧化层3015。
其中，所述半导体衬底3011可以为体硅、绝缘体上的硅、锗或III-V族化合物等半导体材料。
另外需要说明说明的是，上述半导体基材可以为鳍式结构半导体基材，或平面结构晶体管，或SOI基材，还可以是其他结构的半导体基材，具体此处不做限定。由于鳍式结构可以使得隧穿面积更大，本申请实施例中选择鳍式半导体基材。
302、分别在所述半导体基材两侧形成漏极区域以及源极区域。
其中，分别在所述半导体基材两侧形成漏极区域以及源极区域具体有如下方式：
在半导体基材的第一区域进行第一掺杂类型离子掺杂形成漏极区域，在半导体基材的第二区域进行第二掺杂类型离子掺杂形成源极区域，第一区域和第二区域为半导体基材中不同的区域，其中，第一掺杂类型为P型，第二掺杂类型为N型；或者第一掺杂类型为N型，第二掺杂类型为P型。在本申请的一些实施例中，源极区域的范围大于漏级的范围。
具体的，如图4b所示，以P型半导体基材为例，即利用P+S/D光罩技术， 在P型半导体基材的第一区域3021进行P型掺杂形成漏级区域。以N型半导体基材为例，在N型半导体基材的第二区域3022进行P型掺杂形成源级区域。接着，如图4c所示，对于P型半导体基材，在P型半导体基材的第二区域3023进行N型掺杂形成源极区域。对于N型半导体基材，在N型半导体基材的第一区域3024进行N型掺杂形成漏级区域。
或者，也可以利用硬掩模技术来制备漏级区域以及源极区域，如下：利用硬掩膜工艺在半导体基材的第一区域制作第一掺杂类型外延层以形成漏级区域，利用硬掩膜工艺在半导体基材的第二区域形成第二掺杂类型外延层以形成源极区域，第一区域和第二区域为半导体基材中不同的区域。其中，第一掺杂类型为P型，第二掺杂类型为N型；或者第一掺杂类型为N型，第二掺杂类型为P型。并且在一些实施例中，源极区域的范围大于的掺杂范围。
参照上述掺杂例子的方式，具体的，如图4b所示，以P型半导体基材为例，在P型半导体基材的第一区域3021制作P型外延层以形成漏级区域。以N型半导体基材为例，在N型半导体基材的第二区域3022制作P型外延层以形成源极区域。接着，如图4c所示，对于P型半导体基材，在P型半导体基材的第二区域3023制作N型外延层以形成源极区域；对于N型半导体基材，N型半导体基材的第一区域3024进行N型掺杂形成漏级区域。
需要说明的是，P型外延层可以为SiGe，N型外延层可以为SiP，具体此处不做限定。另外需要说明的是，在半导体基材的第一区域进行第一掺杂类型离子掺杂形成漏极区域，在半导体基材的第二区域进行第二掺杂类型离子掺杂形成源极区域，第一区域和第二区域为半导体基材中不同的区域。
303、在所述漏极区域以及源极区域表面沉积外延层。
如图4d所示，在完成漏级区域以及源极区域后，即完成漏级以及源极后，在半导体基材上面沉积一层外延层(epi-layer)，具体的该外延层可以为本证硅外延层。
304、在所述外延层上形成栅极区域。
如图4e所示，接著继续传统的半导体制作工艺，沉积高介电层(如HfO2、SiO2等)和栅(如Poly-Si)，即在完成制备漏级区域以及源极区域上叠加一层外延层后，在外延层上形成栅极区域3041，其中，该栅极区域通过外延层， 与漏极区域以及源极区域接触。
305、完成RMG(Replace Metal Gate)工艺。
如图4f所示，然后继续完成RMG工艺和后续的金属连线工艺，具体此处不在赘述。
由以上方案可见，在本申请实施例中，在制备隧穿场效应晶体管时，先是制备隧穿场效应晶体管的漏极区域以及源极区域，再在漏极区域以及源极区域表面沉积外延层，最后才制备栅极区域，即Source-Drain First工艺，可以有效地控制源极区域以及漏级区域的掺杂扩散至外延层，即可以有效地减少源极区域以及漏级区域的掺杂扩散至外延层，从而可以有效地控制隧穿场效应晶体管的参数，另外，采用Source-Drain First工艺，使得晶体管最后的对准工艺较为简单，而且能有效地控制源极区域与栅极区域的重叠区域，即隧穿区域，可以有效地控制隧穿面积，从而有效地控制隧穿场效应晶体管的参数。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，模块和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的模块果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请 的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(英文全称：Read-Only Memory缩写：ROM)、随机存取存储器(英文全称：Random Access Memory，缩写：RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (14)

  1. 一种隧穿场效应晶体管的制备方法，其特征在于，包括：
    提供半导体基材；
    分别在所述半导体基材两侧形成漏极区域以及源极区域；
    在所述半导体基材表面沉积外延层；
    在所述外延层上形成栅极区域，所述栅极区域通过所述外延层，与所述漏极区域以及源极区域接触；
    在所述栅极区域以及源极区域重叠的区域形成隧穿区域。
  2. 根据权利要求1所述的方法，其特征在于，所述分别在所述半导体基材两侧形成漏极区域以及源极区域，包括：
    在所述半导体基材的第一区域进行第一掺杂类型离子掺杂形成所述漏极区域，在所述半导体基材的第二区域进行第二掺杂类型离子掺杂形成所述源极区域，所述第一区域和第二区域为所述半导体基材中不同的区域。
  3. 根据权利要求1所述的方法，其特征在于，所述分别在所述半导体基材两侧形成漏极区域以及源极区域，包括：
    利用硬掩膜工艺在所述半导体基材的第一区域形成第一掺杂类型外延层，利用所述硬掩膜工艺在所述半导体基材的第二区域形成第二掺杂类型外延层，所述第一区域和第二区域为所述半导体基材中不同的区域。
  4. 根据权利要求2或3所述的方法，其特征在于，所述第一掺杂类型为P型，所述第二掺杂类型为N型；或者所述第一掺杂类型为N型，所述第二掺杂类型为P型。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述源极区域的范围大于所述漏极区域的范围。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，在所述漏极区域以及源极区域表面上沉积外延层，包括：
    在所述漏极区域以及源极区域表面上沉积本证硅外延层。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，所述半导体基材为鱼鳍结构半导体基材，或平面结构半导体基材，或绝缘体硅SOI基材。
  8. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括：
    半导体基材；
    分别在所述半导体基材两侧形成的漏极区域以及源极区域；
    在所述半导体基材表面上沉积的外延层；
    在所述外延层上形成的栅极区域，所述栅极区域通过所述外延层，与所述漏极区域以及源极区域接触；
    在所述栅极区域以及源极区域重叠的区域形成的隧穿区域。
  9. 根据权利要求8所述的隧穿场效应晶体管，其特征在于，所述漏极区域由所述半导体基材的第一区域进行第一掺杂类型离子掺杂形成，所述源极区域为由所述半导体基材的第二区域进行第二掺杂类型离子掺杂形成，所述第一区域和第二区域为所述半导体基材中不同的区域。
  10. 根据权利要求8所述的隧穿场效应晶体管，其特征在于，所述漏极区域为利用硬掩膜工艺在所述半导体基材上形成的第一掺杂类型外延层，所述源极区域为利用所述硬掩膜工艺在所述半导体基材上形成的第二掺杂类型外延层。
  11. 根据权利要求9或10所述的隧穿场效应晶体管，其特征在于，所述第一掺杂类型为P型，所述第二掺杂类型为N型；或者所述第一掺杂类型为N型，所述第二掺杂类型为P型。
  12. 根据权利要求8至11中任一项所述的隧穿场效应晶体管，其特征在于，所述源极区域的范围大于所述漏极区域的范围。
  13. 根据权利要求8至12中任一项所述的隧穿场效应晶体管，其特征在于，在所述漏极区域以及源极区域表面上沉积的外延层为本征硅外延层。
  14. 根据权利要求8至13中任一项所述的场效应晶体管，其特征在于，所述半导体基材为鱼鳍结构半导体基材，或平面结构半导体基材，或SOI基材。
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