WO2022133652A1 - 场效应晶体管及其制造方法 - Google Patents

场效应晶体管及其制造方法 Download PDF

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WO2022133652A1
WO2022133652A1 PCT/CN2020/138044 CN2020138044W WO2022133652A1 WO 2022133652 A1 WO2022133652 A1 WO 2022133652A1 CN 2020138044 W CN2020138044 W CN 2020138044W WO 2022133652 A1 WO2022133652 A1 WO 2022133652A1
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Prior art keywords
field effect
inner isolation
effect transistor
isolation layer
channel region
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PCT/CN2020/138044
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English (en)
French (fr)
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詹瞻
刘燕翔
马小龙
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华为技术有限公司
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Priority to PCT/CN2020/138044 priority Critical patent/WO2022133652A1/zh
Priority to CN202080108008.3A priority patent/CN116635985A/zh
Publication of WO2022133652A1 publication Critical patent/WO2022133652A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to field effect transistors and methods for manufacturing the same.
  • an inner spacer needs to be grown on the outside of the gate to separate the gate and source/drain.
  • the channel region covered under the inner isolation layer cannot be directly covered and controlled by the gate, and this region is called an ineffective gate control region.
  • the resistance of the inactive gated region will not decrease with the increase of gate voltage, so the resistance of this region will become the resistance bottleneck from source to drain.
  • One solution is to use a highly doped low-resistance material in the channel region between the source and drain to reduce the resistance of the channel region.
  • this approach will increase the carrier scattering in the channel region covered by the gate (also known as the effective gated region), thereby reducing the mobility of carriers and sacrificing the performance of the transistor; on the other hand, the small Random fluctuations of impurities in the channel under the dimensions can also cause stronger random variations in device performance. Therefore, there is an urgent need in the industry for a solution that can better solve the problem of increased on-resistance of the channel region caused by the ineffective gate control region.
  • the present application provides a field effect transistor and a manufacturing method thereof, which can reduce the on-resistance of the channel region of the field effect transistor and maintain high carrier mobility in the channel region, thereby improving the performance of the field effect transistor.
  • a field effect transistor comprising: a source electrode, a drain electrode and a gate electrode; a channel region is provided between the source electrode and the drain electrode; the gate electrode and the source electrode and the An inner isolation layer is arranged between the gate electrode and the drain electrode, and the inner isolation layer covers a part of the channel region; wherein, the inner isolation layer includes a donor impurity or an acceptor impurity.
  • the partial area covered by the inner isolation layer may be referred to as an ineffective gated area.
  • the inner isolation layer is composed of insulating materials to isolate the gate electrode and the drain electrode, as well as the gate electrode and the source electrode.
  • the inner isolation layer may be a mixture (eg, phosphosilicate glass or borosilicate glass) or compound composed of donor impurities or acceptor impurities, and other elements (eg, silicon, oxygen, nitrogen, etc.).
  • the present application provides a field effect transistor, and an inner isolation layer of the transistor includes a donor impurity or an acceptor impurity.
  • the above-mentioned donor impurities or acceptor impurities can diffuse into the ineffective gated region covered by the inner isolation layer to form a low resistance state under high doping, and the ineffective gated region covered by the inner isolation layer can be formed.
  • the semiconductor doping can be precisely modulated to reduce the resistance of the region, and the rest of the channel region (or, in other words, the effective gated region) can still maintain a high resistance state with low doping, thereby maintaining a high load in the channel.
  • the carrier mobility improves the performance of field effect transistors.
  • the donor impurities include at least one of the following: phosphorus, arsenic, and antimony.
  • the acceptor impurities include at least one of the following: boron, indium, and aluminum.
  • the inner isolation layer includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.
  • the field effect transistor includes a gate-all-around field effect transistor GAAFET, the channel region is a first channel region, and a source electrode and a drain electrode are provided between the source electrode and the drain electrode.
  • GAAFET gate-all-around field effect transistor
  • the first channel region is any one of the plurality of stacked channel regions
  • the inner isolation layer is a first inner isolation layer
  • the A plurality of stacked inner isolation layers are arranged between the gate electrode and the source electrode and the gate electrode and the drain electrode
  • the first inner isolation layer is any one of the plurality of stacked inner isolation layers Inner isolation layer.
  • the field effect transistor includes a fin field effect transistor FinFET.
  • a method for manufacturing a field effect transistor comprising: obtaining a silicon-based original wafer; and generating an inner isolation layer of the field-effect transistor on the silicon-based original wafer, where the inner isolation layer is used for The gate electrode and the source electrode and the gate electrode and the drain electrode of the field effect transistor are isolated and covered on a part of the channel region, and the inner isolation layer includes a donor impurity or an acceptor impurity.
  • the part of the area covered by the inner isolation layer may be referred to as an ineffective gate control area.
  • the present application provides a method for fabricating a field effect transistor.
  • the method uses a material containing a donor impurity or an acceptor impurity to fabricate an inner isolation layer.
  • the above-mentioned donor impurities or acceptor impurities can diffuse into the ineffective gated region covered by the inner isolation layer to form a low resistance state under high doping, and the ineffective gated region covered by the inner isolation layer can be formed.
  • the semiconductor doping can be precisely modulated to reduce the resistance of the region, and the rest of the channel region (or, in other words, the effective gated region) can still maintain a high resistance state with low doping, thereby maintaining a high load in the channel.
  • the carrier mobility improves the performance of field effect transistors.
  • the donor impurities include at least one of the following: phosphorus, arsenic, and antimony.
  • the acceptor impurities include at least one of the following: boron, indium, and aluminum.
  • the dielectric material includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.
  • the field effect transistor includes a gate-all-around field effect transistor GAAFET, the channel region is a first channel region, and a source electrode and a drain electrode are provided between the source electrode and the drain electrode.
  • GAAFET gate-all-around field effect transistor
  • the first channel region is any one of the plurality of stacked channel regions
  • the inner isolation layer is a first inner isolation layer
  • the A plurality of stacked inner isolation layers are arranged between the gate electrode and the source electrode and the gate electrode and the drain electrode
  • the first inner isolation layer is any one of the plurality of stacked inner isolation layers Inner isolation layer.
  • the field effect transistor includes a fin field effect transistor FinFET.
  • an electronic device including the field effect transistor described in the first aspect and any possible implementation manner of the first aspect.
  • FIG. 1 is a schematic structural diagram of a FinFET 10 according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a GAAFET 20 according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a GAAFET 30 according to an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a FinFET 40 according to an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a GAAFET 50 according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of a FinFET 60 according to yet another embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of a GAAFET 70 according to an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method for manufacturing a field effect transistor according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a FinFET 10 according to an embodiment of the present application.
  • the channel region 11 is a fin-shaped semiconductor surrounded by a gate (gate, G) 12 , that is, the gate surrounds three sides of the channel region 11 .
  • Two ends of the channel region 11 are a source (source, S) and a drain (drain, D) (not shown in the figure).
  • the structure in which the gate 12 wraps the channel region 11 enhances the control capability of the gate, provides better electrical control for the channel region 11, and suppresses the short-channel effect.
  • one side of the channel region 11 is still connected to the silicon substrate 16, when the transistor is in an off state, there will be an additional leakage current path.
  • the dielectric may include the inner isolation layer 110 hereinafter.
  • FIG. 2 and FIG. 3 are respectively schematic structural diagrams of GAAFETs ( 20 , 30 ) according to an embodiment of the present application.
  • the channel region 11 in FIG. 2 is a nanowire structure
  • the channel region 11 in FIG. 3 is a nanosheet structure.
  • GAAFETs can be classified into nanowire structures and nanosheet structures according to the different aspect ratios of the channel region between the source (S) and drain (D).
  • a plurality of nanowires or a plurality of nanosheets are in a stacked state and serve as the channel region 11 to connect the source and drain electrodes (not shown in the figure), so that the gate (G) 12 can surround all sides of the channel region 11, The goal that the gate 12 completely includes the channel region 11 is achieved.
  • This structure can achieve better control over the channel region 11, further reduce leakage current, and improve parasitic capacitance and resistance problems.
  • FIG. 4 is a schematic cross-sectional view of a FinFET 40 according to an embodiment of the present application.
  • the FinFET 40 includes a source electrode 13 , a drain electrode 14 and a gate electrode 12 .
  • the channel region 11 is provided between the source electrode 13 and the drain electrode 14 .
  • an inner spacer 110 is further provided between the source/drain (13, 14) and the gate 12.
  • the inner isolation layer 110 is composed of a dielectric material, which is used to isolate the source/drain ( 13 , 14 ) and the gate 12 . Due to the existence of the inner isolation layer 110 , the channel region 11 is divided into an ineffective gated region 120 and an effective gated region 130 .
  • the channel region 11 covered under the inner isolation layer 110 is called an ineffective gate control region 120 , and this region cannot be directly covered and controlled by the gate electrode 12 .
  • the area directly covered by the gate 12 is referred to as the effective gated area 130 , which can be directly covered and controlled by the gate 12 .
  • a gate dielectric layer 140 is further disposed between the gate electrode 12 and the channel region 11 . The gate dielectric layer 140 is used to isolate the gate 12 from the channel region 11 . Below the channel region 11 is a silicon base wafer 16 .
  • FIG. 5 is a schematic cross-sectional view of a GAAFET 50 according to an embodiment of the present application.
  • the GAAFET 50 includes a source electrode 13 , a drain electrode 14 and a gate electrode 12 .
  • the channel region 11 is formed by a plurality of stacked nanosheets or nanowires in the GAAFET 50, as shown in FIG. A plurality of stacked channel regions 11 .
  • a plurality of stacked inner isolation layers 110 and a plurality of stacked gate dielectric layers 140 are also disposed between the source electrode 13 and the drain electrode 14 .
  • the channel material is generally made of low-doped and high-resistance semiconductor materials, while the source/drain (13, 14) High-doped semiconductor materials are usually used, and the resistance itself is low.
  • the gate 12 does not cover the inactive gated region 120 , the gate voltage can only effectively control the active gated region 130 , but cannot effectively control the inactive gated region 120 .
  • the resistance of the inactive gated region 120 will not completely decrease with the increase of the gate voltage, so that the resistance of the inactive gated region 120 will become the resistance from the source 13 to the drain 14 bottleneck, which affects the device performance of GAAFET.
  • a solution to the above problem is to use a low-resistance material in a highly doped state in all channel regions 11 in FinFETs and GAAFETs to reduce the resistance of the entire channel regions 11 .
  • this approach reduces the resistance in the non-effective gated region 120, the high concentration of impurities in the material will increase the carrier scattering in the effective gated region 130, thereby reducing the mobility of carriers and sacrificing the cost of performance of transistors; on the other hand, random fluctuations of impurities in the channel under small dimensions will also cause more intense random changes in device performance.
  • the embodiments of the present application provide a manufacturing solution for a field effect transistor, which can precisely modulate the semiconductor doping of the non-effective gate control region 120 covered by the inner isolation layer 110, reduce the resistance of the region, and The rest of the channel region (ie, the effective gated region 130 ) can still maintain a high resistance state with low doping, thereby maintaining high carrier mobility in the channel region.
  • the above-mentioned field effect transistors include, but are not limited to, FinFETs and GAAFETs.
  • FIG. 6 is a schematic cross-sectional view of a FinFET 60 according to an embodiment of the present application.
  • the FinFET 60 includes a source electrode 13 , a drain electrode 14 and a gate electrode 12 , and a channel region 11 is provided between the source electrode 13 and the drain electrode 14 .
  • An inner isolation layer 110 is provided between the gate electrode 12 and the source electrode 13, the gate electrode 12 and the drain electrode 14, and the channel region 11 includes an effective gate control region 130 and an ineffective gate control region 120,
  • the inactive gated region 120 is the region in the channel region 11 covered by the inner isolation layer 110 ;
  • the effective gated region 130 is the region in the channel region 11 covered by the gate 12 .
  • the inner isolation layer 110 may be prepared by using a material containing a donor impurity or an acceptor impurity.
  • the inner isolation layer is composed of insulating materials to isolate the gate electrode and the drain electrode, as well as the gate electrode and the source electrode.
  • the inner isolation layer may be a mixture (eg, phosphosilicate glass or borosilicate glass) or compound composed of donor impurities or acceptor impurities, and other elements (eg, silicon, oxygen, nitrogen, etc.).
  • the donor impurity usually refers to the V group element (for example, phosphorus, arsenic, antimony, etc.), after the donor impurity is doped into the semiconductor silicon, it can replace the position of a part of the silicon atom, and each replaced one silicon atom will have an extra valence electron, to form an N-type semiconductor.
  • the acceptor impurities can usually refer to III group elements (for example, boron, indium, aluminum). After the acceptor impurities are introduced into the semiconductor silicon, they replace the position of part of the silicon atoms, and each replaced silicon atom will have an extra space. hole.
  • the above-mentioned donor impurities or acceptor impurities can diffuse into the adjacent semiconductor material. Since the inner isolation layer 110 is closely adjacent to the ineffective gate control region 120, the donor impurities or acceptor impurities can be accurately Diffusion to the inactive gated region 120 , thereby reducing the resistance of the inactive gated region 120 by increasing the doping degree in the inactive gated region 120 , thereby reducing the resistance of the inactive gated portion 130 in the channel region 11 .
  • the inner isolation layer 110 is not adjacent to the effective gate control region 130, the diffusion range of the donor impurities or acceptor impurities to the effective gate control region 130 is limited, and the doping degree of the effective gate control region 130 is not affected. Therefore, the mobility of carriers in the effective gate control region 130 will not be degraded, and the electrical conductivity of the effective gate control region 130 is maintained.
  • the above-mentioned subsequent high-temperature preparation processes include, but are not limited to: a high-temperature process of source-drain epitaxial growth; a high-temperature process of source-drain impurity activation; post-metallization anneal (PMA) after the completion of the high-K metal gate .
  • PMA post-metallization anneal
  • the above-mentioned donor impurities include, but are not limited to, at least one of the following: phosphorus, arsenic, and antimony.
  • acceptor impurities include, but are not limited to: boron, indium, and aluminum.
  • the above-mentioned inner isolation layer 110 may include, but is not limited to, phosphosilicate glass, borosilicate glass, and arsenic silicate glass.
  • phosphosilicate glass, borosilicate glass, and arsenic silicate glass may respectively refer to silicon dioxide doped with phosphorus, boron or arsenic.
  • Phosphosilicate glass, arsenic silicate glass can provide donor impurities phosphorus and arsenic.
  • borosilicate glass can provide the acceptor impurity boron.
  • the above-mentioned inner isolation layer may also be formed of other materials, as long as it is a dielectric material containing donor impurities or acceptor impurities, which will not be enumerated here.
  • the present application provides a method for fabricating a field effect transistor.
  • the method uses a material containing a donor impurity or an acceptor material to fabricate an inner isolation layer.
  • the above-mentioned donor impurities or acceptor impurities can diffuse into the ineffective gated region covered by the inner isolation layer to form a low resistance state under high doping, and the ineffective gated region covered by the inner isolation layer can be formed.
  • the semiconductor doping can be precisely modulated to reduce the resistance of the region, and the rest of the channel region (or, in other words, the effective gated region) can still maintain a high resistance state with low doping, thereby maintaining a high load in the channel.
  • the carrier mobility improves the performance of field effect transistors.
  • FIG. 7 is a schematic structural diagram of a GAAFET 70 according to an embodiment of the present application.
  • the GAAFET 70 includes a source electrode 13, a drain electrode 14 and a gate electrode 12, and a plurality of stacked channel regions 11 are arranged between the source electrode 13 and the drain electrode 14.
  • a plurality of inner isolation layers 110 are disposed between the gate electrode 12 and the source electrode 13, the gate electrode 12 and the drain electrode 14, and each channel region 11 includes an effective gate control region 130 and an ineffective gate
  • the inactive gated region 120 is the region covered by the inner isolation layer 110 in the channel region 11 ; the effective gated region 130 is the channel region 11 covered by the gate 12 covered area.
  • the plurality of stacked channel regions 11 may be nanowire structures or nanosheet structures.
  • the inner isolation layer 110 in the GAAFET 70 when the inner isolation layer 110 in the GAAFET 70 is prepared, the inner isolation layer 110 may be prepared by using a material containing a donor impurity or an acceptor impurity. In the subsequent high-temperature preparation process, the above-mentioned donor impurities or acceptor impurities can diffuse into the adjacent semiconductor material. Since the inner isolation layer 110 is closely adjacent to the ineffective gate control region 120, the donor impurities or acceptor impurities can diffuse into the non-effective gate control region 120. The effective gated region 120 is diffused, thereby reducing the resistance of the ineffective gated region 120 by increasing the doping degree in the ineffective gated region 120, thereby reducing the resistance of the entire channel region.
  • a gate dielectric layer 140 is further disposed between the gate electrode 12 and the channel region 11 .
  • the gate dielectric layer 140 is used to isolate the gate and channel regions.
  • the gate 12 may be a high-k metal gate (HKMG), and HKMG is a gate manufacturing process adopted in the case that the feature size of transistors is continuously reduced.
  • a high-k (high-k) gate dielectric is combined with a metal gate (MG).
  • the high-k process refers to partially replacing conventional silicon dioxide (SiO 2 ) with a material with a high dielectric constant as the gate dielectric layer 140 .
  • the MG process refers to the use of metal materials to replace polysilicon as the gate.
  • HKMG technology can effectively suppress the depletion effect of traditional gate polysilicon, and reduce the leakage current of the gate while enhancing the control ability of the gate to the channel.
  • the field effect transistor may be arranged in a well 17 implanted on the silicon base original wafer 16 , and the well 17 may refer to doping N-type impurities or P-type impurities in the silicon base original wafer 16
  • the regions can be called N-well and P-well, respectively.
  • a shallow trench isolation (STI) 18 is also provided in the well 17.
  • the STI 18 is usually made of an insulating material, such as SiO 2 , which functions to separate two adjacent transistors.
  • FIG. 8 is a schematic flowchart of a method for manufacturing a field effect transistor according to an embodiment of the present application. As shown in Figure 8, the method includes:
  • the inner isolation layer includes a donor impurity or an acceptor impurity.
  • the inner isolation layer is formed on the silicon-based original wafer, other processes for fabricating field effect transistors can be continued on the silicon-based original wafer.
  • the above steps include, but are not limited to: source-drain growth, removal of polysilicon dummy gates, gate oxidation, generation of high-K dielectric metal gates, and the like.
  • the present application provides a method for fabricating a field effect transistor.
  • the method uses a material containing a donor impurity or an acceptor material to fabricate an inner isolation layer.
  • the above-mentioned donor impurities or acceptor impurities can diffuse into the ineffective gated region covered by the inner isolation layer to form a low resistance state under high doping, and the ineffective gated region covered by the inner isolation layer can be formed.
  • the semiconductor doping is precisely modulated to reduce the resistance of the region, and the rest of the channel region (ie, the effective gated region) can still maintain the high resistance state under the low doping situation, thereby maintaining high carriers in the channel. mobility, improving the performance of field effect transistors.
  • a fin-shaped (Fin) pattern is etched by photolithography using a mask.
  • the inner isolation layer includes a donor impurity or an acceptor impurity.
  • a donor impurity or an acceptor impurity for the specific description of the inner isolation layer, reference may be made to the foregoing description, which is not repeated here for brevity.
  • the subsequent manufacturing process of the GAAFET may be continued, and for the sake of brevity, the subsequent manufacturing process will not be repeated.

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Abstract

一种场效应晶体管及其制造方法，该场效应晶体管包括：源极（13）、漏极（14）和栅极（12）；源极（13）和漏极（14）之间设置有沟道区域（11）；栅极（12）和源极（13）以及栅极（12）和漏极（14）之间设置有内隔离层（110），内隔离层（110）覆盖于沟道区域（11）的部分区域上，其中，内隔离层（110）中包括施主杂质或受主杂质。该结构能够降低场效应晶体管的沟道区域（11）的导通电阻，并且维持沟道区域（11）中的高载流子迁移率，从而提高场效应晶体管的性能。

Description

场效应晶体管及其制造方法 技术领域
本申请涉及半导体制造领域，尤其涉及场效应晶体管及其制造方法。
背景技术
过去几十年，半导体技术发展一直遵循着摩尔定律晶体管的特征尺寸在不断地缩小，当今半导体芯片已经迈入5纳米(nm)技术节点。从22纳米的节点开始，半导体器件的主流结构的位置被鳍式场效应晶体管(fin field-effect transistor，FinFET)占据，但到了5纳米节点之后，FinFET已经很难满足晶体管所需的静电控制，漏电现象也随着尺寸的缩小而急剧恶化。在这种情况下，全环栅场效应晶体管(gate all around field-effect transistor，GAAFET)被广泛认为是FinFET的下一代半导体晶体管的接任者。
在FinFET和GAAFET的制造过程中，需要在栅极外侧生长内隔离层(inner spacer)，以隔开栅极和源/漏极。但是由于内隔离层的存在，导致内隔离层之下覆盖的沟道区域不能被栅极直接覆盖和控制，这个区域被称为非有效栅控区域。在晶体管开启的时候，非有效栅控区域的电阻不会随着栅电压的增加而降低，因此该区域的电阻将成为从源极到漏极之间的电阻瓶颈。
一种解决方案是在源漏之间的沟道区域采用高掺杂状态的低阻材料，以降低沟道区域的电阻。但是这种做法一方面将增加栅覆盖的沟道区域(也可以称为有效栅控区域)的载流子散射，从而降低了载流子的迁移率，牺牲了晶体管的性能；另一方面小尺寸下沟道中杂质的随机涨落也同时会造成器件性能更强烈的无规则变化。因此，业界亟待一种能够更好的解决非有效栅控区域导致的沟道区域导通电阻增加的问题。
发明内容
本申请提供一种场效应晶体管及其制造方法，能够降低场效应晶体管的沟道区域的导通电阻，并且维持沟道区域中的高载流子迁移率，从而提高场效应晶体管的性能。
第一方面，提供了一种场效应晶体管，包括：源极、漏极和栅极；所述源极和漏极之间设置有沟道区域；所述栅极和所述源极以及所述栅极和所述漏极之间设置有内隔离层，所述内隔离层覆盖于所述沟道区域的部分区域上；其中，所述内隔离层中包括施主杂质或受主杂质。
可选地，内隔离层覆盖的部分区域可称为非有效栅控区域。所述内隔离层是由绝缘的物质组成，用以隔离栅极和漏极，以及隔离栅极和源极。所述内隔离层可以是由施主杂质或受主杂质，与其他元素(比如硅、氧、氮等)组成的混合物(比如，磷硅玻璃或者硼硅玻璃)或化合物。
本申请提供了一种场效应晶体管，该晶体管的内隔离层中包括施主杂质或受主杂质。在后续的高温过程中，上述施主杂质或受主杂质可以扩散至内隔离层覆盖的非有效栅控区 域中，形成高掺杂下的低阻态，对内隔离层覆盖的非有效栅控区域的半导体掺杂进行精准调制，降低该区域的电阻，并且沟道区域的其余部分(或者说，有效栅控区域)仍然可以维持低掺杂情形下的高阻态，从而维持沟道中的高载流子迁移率，提高了场效应晶体管的性能。
结合第一方面，在一种可能的实现方式中，所述施主杂质包括以下至少一种：磷、砷、锑。
结合第一方面，在一种可能的实现方式中，所述受主杂质包括以下至少一种：硼、铟、铝。
结合第一方面，在一种可能的实现方式中，，所述内隔离层包括以下至少一种：磷硅玻璃、硼硅玻璃、砷硅玻璃。
结合第一方面，在一种可能的实现方式中，所述场效应晶体管包括全环栅场效应晶体管GAAFET，所述沟道区域为第一沟道区域，所述源极和漏极之间设置有多个堆叠的沟道区域，所述第一沟道区域为所述多个堆叠的沟道区域中的任一沟道区域；以及，所述内隔离层为第一内隔离层，所述栅极和所述源极以及所述栅极和所述漏极之间设置有多个堆叠的内隔离层，所述第一内隔离层为所述多个堆叠的内隔离层中的任一内隔离层。
结合第一方面，在一种可能的实现方式中，所述场效应晶体管包括鳍式场效应晶体管FinFET。
第二方面，提供了一种用于场效应晶体管的制造方法，包括：获取硅基原片；在所述硅基原片上生成所述场效应晶体管的内隔离层，所述内隔离层用于隔离所述场效应晶体管的栅极和源极、以及所述栅极和漏极，且覆盖于所述沟道区域的部分区域上，所述内隔离层中包括施主杂质或受主杂质。
其中，内隔离层覆盖的部分区域可称为非有效栅控区域。
本申请提供了一种场效应晶体管的制造方法，该方法在采用包含有施主杂质或受主杂质的材料制作内隔离层。在后续的高温过程中，上述施主杂质或受主杂质可以扩散至内隔离层覆盖的非有效栅控区域中，形成高掺杂下的低阻态，对内隔离层覆盖的非有效栅控区域的半导体掺杂进行精准调制，降低该区域的电阻，并且沟道区域的其余部分(或者说，有效栅控区域)仍然可以维持低掺杂情形下的高阻态，从而维持沟道中的高载流子迁移率，提高了场效应晶体管的性能。
结合第二方面，在一种可能的实现方式中，所述施主杂质包以下至少一种：磷、砷、锑。
结合第二方面，在一种可能的实现方式中，所述受主杂质包括以下至少一种：硼、铟、铝。
结合第二方面，在一种可能的实现方式中，所述介质材料包括以下至少一种：磷硅玻璃、硼硅玻璃、砷硅玻璃。
结合第二方面，在一种可能的实现方式中，所述场效应晶体管包括全环栅场效应晶体管GAAFET，所述沟道区域为第一沟道区域，所述源极和漏极之间设置有多个堆叠的沟道区域，所述第一沟道区域为所述多个堆叠的沟道区域中的任一沟道区域；以及，所述内隔离层为第一内隔离层，所述栅极和所述源极以及所述栅极和所述漏极之间设置有多个堆叠的内隔离层，所述第一内隔离层为所述多个堆叠的内隔离层中的任一内隔离层。
结合第二方面，在一种可能的实现方式中，所述场效应晶体管包括鳍式场效应晶体管FinFET。
第三方面，提供了一种电子器件，包括如第一方面以及第一方面中的任一种可能的实现方式中所述的场效应晶体管。
附图说明
图1是本申请一实施例的FinFET 10的结构示意图。
图2是本申请一实施例的GAAFET 20的结构示意图。
图3是本申请一实施例的GAAFET 30的结构示意图。
图4是本申请一实施例的FinFET 40的横截面示意图。
图5是本申请一实施例的GAAFET 50的横截面示意图。
图6是本申请又一实施例的FinFET60的横截面示意图。
图7是本申请一实施例的GAAFET 70的横截面示意图。
图8是本申请一实施例的场效应晶体管的制造方法的流程示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
为了便于理解，下文中首先结合附图，介绍FinFET和GAAFET的结构。
图1是本申请一实施例的FinFET 10的结构示意图。如图1所示，在FinFET 10设计中，沟道区域11是一个被栅极(gate，G)12包裹的鳍状半导体，即栅极围绕在沟道区域11的三侧。沟道区域11的两端为源极(source，S)和漏极(drain，D)(图中未示出)。栅极12包裹沟道区域11的结构增强了栅的控制能力，对沟道区域11提供了更好的电学控制，抑制短沟道效应。但是由于沟道区域11还有一侧还与硅基原片16相连，因此在晶体管处于关断状态时，还会存在额外的泄漏电流通路。
另外需要说明的是，本领域人员能够理解，为了更清楚地说明沟道区域11的形状，图1中并未示出源极、漏极、电介质等组成部分。上述组成部分的构造方式可以参见图4所示的内容。其中，电介质可以包括下文中的内隔离层110。
自从半导体工艺节点发展到5纳米以下之后，业界亟需一个新的解决方案在未来的工艺节点中替代FinFET结构。尽管各种新型的晶体管方案不断被提出，但出于节约生产成本的目的，业界更青睐于能够继续沿用现有设备以及技术成果的方案。基于这一原因，GAAFET被广泛认为是下一代晶体管的发展方向。GAAFET的生产工艺与FinFET相似，关键工艺步骤基本相同，并且GAAFET实现了栅极对沟道区域的四面环绕，从而增强了栅控能力，进一步减少了泄漏电流。
图2和图3分别是本申请一实施例的GAAFET(20，30)的结构示意图。其中，图2中的沟道区域11为纳米线结构，图3中的沟道区域11为纳米片结构。
如图2和图3所示，根据源极(S)和漏极(D)之间的沟道区域的长宽比不同，GAAFET可以分为纳米线结构和纳米片结构。多个纳米线或多个纳米片呈堆叠状态，并作为沟道区域11连接源极和漏极(图中未示出)，从而栅极(G)12可以包围沟道区域11的所有侧面，实现了栅极12完全包括沟道区域11的目标。这种结构可以实现对沟道区域11更好 的控制，进一步减少泄漏电流，并且改善寄生电容和电阻的问题。
另外需要说明的是，本领域人员能够理解，为了更清楚地说明沟道区域11的形状，图2和图3中并未示出源极、漏极、电介质等组成部分。上述组成部分的构造方式可以参见图5或图6所示的内容。
图4是本申请一实施例的FinFET 40的横截面示意图。如图4所示，FinFET 40中包括源极13、漏极14和栅极12。其中，源极13和漏极14之间设置有沟道区域11。
为了避免栅极12和源/漏极(13，14)直接导通，在源/漏极(13，14)与栅极12之间还设置有内隔离层(inner spacer)110。内隔离层110由介质材料构成，其用于隔离源/漏极(13，14)与栅极12。由于内隔离层110的存在，沟道区域11被分为非有效栅控区域120和有效栅控区域130。其中，内隔离层110之下覆盖的沟道区域11被称为非有效栅控区域120，该区域不能被栅极12直接覆盖和控制。栅极12直接覆盖的区域被称为有效栅控区域130，该区域可以被栅极12直接覆盖和控制。栅极12与沟道区域11之间还设置有栅介电层140。栅介电层140用于隔离栅极12与沟道区域11。沟道区域11的下方为硅基原片16。
图5是本申请一实施例的GAAFET 50的横截面示意图。如图5所示，GAAFET 50中包括源极13、漏极14和栅极12。与图4中的FinFET 40不同的是，由于GAAFET 50中由多个堆叠的纳米片或者纳米线构成沟道区域11，因此，如图5所示，源极13和漏极14之间设置有多个堆叠的沟道区域11。
相应地，在GAAFET的横截面方向上，源极13和漏极14之间也设置有多个堆叠的内隔离层110以及多个堆叠的栅介质层140。
在FinFET和GAAFET制造过程中，为了抑制沟道中载流子迁移率衰减以及降低沟道杂质涨落的影响，沟道材料一般采用低掺杂高阻半导体材料制备，而源/漏极(13，14)通常采用高掺杂的半导体材料，电阻本身较低。
在晶体管开启状态下，基于栅电压的调制，理想状态下整个沟道区域11应该处于低阻态。但是，由于栅极12未覆盖非有效栅控区域120，因此栅电压只能有效地控制有效栅控区域130，而不能有效地控制非有效栅控区域120。在晶体管开启的时候，非有效栅控区域120的电阻不会完全地随着栅电压的增加而降低，从而非有效栅控区域120的电阻将成为从源极13到漏极14之间的电阻瓶颈，影响了GAAFET的器件性能。
一种解决上述问题的方案是在FinFET和GAAFET中的全部沟道区域11中采用高掺杂状态的低阻材料，以降低整个沟道区域11的电阻。这种做法虽然降低了非有效栅控区域120中的电阻，但是由于材料中高浓度的杂质将会增加有效栅控区域130中的载流子散射，从而降低了载流子的迁移率，牺牲了晶体管的性能；另一方面小尺寸下沟道中杂质的随机涨落也同时会造成器件性能更强烈的无规则变化。
基于上述问题，本申请实施例提供了一种场效应晶体管的制造方案，该方案可以对内隔离层110覆盖的非有效栅控区域120的半导体掺杂进行精准调制，降低该区域的电阻，并且沟道区域的其余部分(即有效栅控区域130)仍然可以维持低掺杂情形下的高阻态，从而维持沟道区域中的高载流子迁移率。上述场效应晶体管包括但不限于FinFET和GAAFET。
接下来将以FinFET和GAAFET为例，分别结合附图介绍本申请实施例中的场效应晶 体管及其制造方法。
图6是本申请一实施例的FinFET 60的截面示意图。如图6所示，FinFET 60中包括源极13、漏极14和栅极12，源极13和漏极14之间设置有沟道区域11。所述栅极12和所述源极13、所述栅极12和所述漏极14之间设置有内隔离层110，沟道区域11包括有效栅控区域130和非有效栅控区域120，所述非有效栅控区域120为所述沟道区域11中被所述内隔离层110覆盖的区域；有效栅控区域130为所述沟道区域11中被所述栅极12覆盖的区域。
在制备FinFET 60中的内隔离层110时，可采用包含有施主杂质或受主杂质的材料制备内隔离层110。所述内隔离层是由绝缘的物质组成，用以隔离栅极和漏极，以及隔离栅极和源极。所述内隔离层可以是由施主杂质或受主杂质，与其他元素(比如硅、氧、氮等)组成的混合物(比如，磷硅玻璃或者硼硅玻璃)或化合物。
其中，施主杂质通常指V族元素(例如，磷，砷，锑等)，施主杂质在掺入半导体硅之后，可以替代一部分硅原子的位置，并且每替代一个硅原子将多出来一个价电子，以形成N型半导体。而受主杂质通常可以指III族元素(例如，：硼、铟、铝)，受主杂质在传入半导体硅之后，替代了部分硅原子的位置，并且每替代一个硅原子将多出一个空穴。
在后续高温制备过程中，上述施主杂质或受主杂质可以向邻近的半导体材料中扩散，由于内隔离层110与非有效栅控区域120紧密相邻，因此，施主杂质或受主杂质可以精准地向非有效栅控区域120扩散，从而通过提高非有效栅控区域120中的掺杂度来降低非有效栅控区域120的电阻，进而降低了沟道区域11中非有效栅控部分130的电阻。
另外，由于内隔离层110并不与有效栅控区域130相邻，因而施主杂质或受主杂质向有效栅控区域130的扩散范围有限，并不会影响有效栅控区域130的掺杂度，从而不会造成有效栅控区域130中载流子迁移率的衰退，维持了有效栅控区域130的导电性能。
在一些示例中，上述后续的高温制备过程包括但不限于：源漏外延生长的高温过程；源漏杂质激活的高温过程；高K金属栅完成后的后金属化退火(post metallization anneal，PMA)。
作为示例，上述施主杂质包括但不限于以下至少一项：磷、砷、锑。
作为示例，上述受主杂质包括但不限于：硼、铟、铝。
作为示例，上述内隔离层110可以包括但不限于：磷硅玻璃、硼硅玻璃、砷硅玻璃。其中，磷硅玻璃、硼硅玻璃、砷硅玻璃可以分别指掺杂有磷、硼或者砷的二氧化硅。磷硅玻璃、砷硅玻璃可以提供施主杂质磷和砷。其中，硼硅玻璃可以提供受主杂质硼。
应理解，上述内隔离层也可以由其它材料构成，只要其为包含施主杂质或受主杂质的介质材料即可，此处不再一一枚举。
本申请提供了一种场效应晶体管的制造方法，该方法在采用包含有施主杂质或受主材质的材料制作内隔离层。在后续的高温过程中，上述施主杂质或受主杂质可以扩散至内隔离层覆盖的非有效栅控区域中，形成高掺杂下的低阻态，对内隔离层覆盖的非有效栅控区域的半导体掺杂进行精准调制，降低该区域的电阻，并且沟道区域的其余部分(或者说，有效栅控区域)仍然可以维持低掺杂情形下的高阻态，从而维持沟道中的高载流子迁移率，提高了场效应晶体管的性能。
图7是本申请一实施例的GAAFET 70的结构示意图。如图7所示，GAAFET 70中包 括源极13、漏极14和栅极12，源极13和漏极14之间设置有多个堆叠的沟道区域11。所述栅极12和所述源极13、所述栅极12和所述漏极14之间设置有多个内隔离层110，每个沟道区域11包括有效栅控区域130和非有效栅控区域120，所述非有效栅控区域120为所述沟道区域11中被所述内隔离层110覆盖的区域；有效栅控区域130为所述沟道区域11中被所述栅极12覆盖的区域。
可选地，所述多个堆叠的沟道区域11可以为纳米线结构，也可以为纳米片结构。
与图6相同，在制备GAAFET 70中的内隔离层110时，可采用包含有施主杂质或受主杂质的材料制备内隔离层110。在后续高温制备过程中，上述施主杂质或受主杂质可以向邻近的半导体材料中扩散，由于内隔离层110与非有效栅控区域120紧密相邻，因此，施主杂质或受主杂质可以向非有效栅控区域120扩散，从而通过提高非有效栅控区域120中的掺杂度来降低非有效栅控区域120的电阻，进而降低了整个沟道区域的电阻。
为了简洁，图7中与图6相同或相似的内容，此处不再赘述。
如图6和图7所示，栅极12与沟道区域11之间还设置有栅介电层140。栅介电层140用于隔离栅极与沟道区域。
作为示例，栅极12可以为高K介质金属栅(high-k metal gate，HKMG)，HKMG是在晶体管的特征尺寸不断缩小的情况下采用的一种栅极制造工艺，其在晶体管制造过程中将高k值(high-k)的栅介电层和金属栅极(metal gate，MG)相结合。其中，high-k工艺是指使用高介电常数的物质部分替代传统的二氧化硅(SiO 2)作为栅介电层140。MG工艺是指采用金属材料取代多晶硅作为栅极。HKMG技术可以有效抑制传统栅极多晶硅耗尽效应，在增强栅极对沟道的控制能力的同时减小栅极的泄漏电流。
如图6和图7所示，场效应晶体管可以设置在硅基原片16上注入的阱(well)17中，阱17可以指在硅基原片16中掺杂N型杂质或P型杂质的区域，可分别称为N阱和P阱。阱17中还设置有浅沟隔绝(shallow trench isolation,STI)18，STI 18通常由绝缘材料构成，例如SiO 2，其作用为隔开两个相邻的晶体管。
图8是本申请一实施例的场效应晶体管的制造方法的流程示意图。如图8所示，该方法包括：
S801、获取硅基原片。
S802、在所述硅基原片上制作所述场效应晶体管的内隔离层，所述内隔离层用于隔离所述场效应晶体管的栅极和源极、以及所述栅极和漏极，且覆盖于所述沟道区域的部分区域上，所述内隔离层中包括施主杂质或受主杂质。
本领域人员能够理解，在硅基原片制作内隔离层之前，还可以在硅基原片执行制造场效应晶体管的其它工序。上述工序包括但不限于：外延生成叠层材料、光刻蚀出鳍状(Fin)的图形、进行STI的物质填充、淀积多晶硅、刻蚀多晶硅假(dummy)栅等。
在硅基原片生成内隔离层之后，还可以继续在硅基原片上执行制造场效应晶体管的其它工序。上述工序包括但不限于：源漏生长、去除多晶硅假(dummy)栅、栅氧化、生成高K介质金属栅等。
本申请提供了一种场效应晶体管的制造方法，该方法在采用包含有施主杂质或受主材质的材料制作内隔离层。在后续的高温过程中，上述施主杂质或受主杂质可以扩散至内隔离层覆盖的非有效栅控区域中，形成高掺杂下的低阻态，对内隔离层覆盖的非有效栅控区 域的半导体掺杂进行精准调制，降低该区域的电阻，并且沟道区域的其余部分(即有效栅控区域)仍然可以维持低掺杂情形下的高阻态，从而维持沟道中的高载流子迁移率，提高了场效应晶体管的性能。
接下来以场效应晶体管为GAAFET为例，描述GAAFET的具体制作方法900。
S901、获取硅基原片。
S902、在硅基原片的半导体衬底上外延生长SiGe(硅锗)/Si(硅)的叠层材料。
S903、利用掩膜板光刻蚀出鳍状(Fin)的图形。
S904、进行STI的物质填充。
S905、淀积多晶硅，并利用掩膜板在多晶硅上光刻蚀出多晶硅假栅。
S906、生成内隔离层。
其中，所述内隔离层中包括施主杂质或受主杂质。关于内隔离层的具体描述可参见前文，为了简洁，此处不再赘述。
S907、进行嵌入式的源漏生长，并进行源漏离子注入。
S908、去除多晶硅假栅。
S909、选择性腐蚀沟道并留下沟道材料。
S910、进行栅氧化、高K介质金属栅生成以及功函数金属沉积。
S911、打开源漏栅极，以进行引出。
可选地，在S911之后，还可以继续执行GAAFET的后续制造过程，为了简洁，其后续制造工艺不再赘述。
本领域人员能够理解，上述方法900仅作为示例描述GAAFET的制作过程，在实践中，可以适当地增加或减少部分步骤。
应理解，FinFET与GAAFET的生产工艺以及关键步骤相似，只需调整部分步骤即可。例如，在制造FinFET的过程中，可以省略方法900中的步骤S903和S909。为了简洁，此处不再描述FinFET的制造方法。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。。

Claims (13)

  1. 一种场效应晶体管，其特征在于，包括：源极、漏极和栅极；
    所述源极和漏极之间设置有沟道区域；
    所述栅极和所述源极以及所述栅极和所述漏极之间设置有内隔离层，所述内隔离层覆盖于所述沟道区域的部分区域上，其中，所述内隔离层中包括施主杂质或受主杂质。
  2. 如权利要求1所述的场效应晶体管，其特征在于，所述施主杂质包括以下至少一种：磷、砷、锑。
  3. 如权利要求1或2所述的场效应晶体管，其特征在于，所述受主杂质包括以下至少一种：硼、铟、铝。
  4. 如权利要求1至3中任一项所述的场效应晶体管，其特征在于，所述内隔离层包括以下至少一种：磷硅玻璃、硼硅玻璃、砷硅玻璃。
  5. 如权利要求1至4中任一项所述的场效应晶体管，其特征在于，所述场效应晶体管包括全环栅场效应晶体管GAAFET，所述沟道区域为第一沟道区域，所述源极和漏极之间设置有多个堆叠的沟道区域，所述第一沟道区域为所述多个堆叠的沟道区域中的任一沟道区域；以及，
    所述内隔离层为第一内隔离层，所述栅极和所述源极以及所述栅极和所述漏极之间设置有多个堆叠的内隔离层，所述第一内隔离层为所述多个堆叠的内隔离层中的任一内隔离层。
  6. 如权利要求1至5中任一项所述的场效应晶体管，其特征在于，所述场效应晶体管包括鳍式场效应晶体管FinFET。
  7. 一种用于场效应晶体管的制造方法，其特征在于，包括：
    获取硅基原片；
    在所述硅基原片上生成所述场效应晶体管的内隔离层，所述内隔离层用于隔离所述场效应晶体管的栅极和源极、以及所述栅极和漏极，且覆盖于所述沟道区域的部分区域上，所述内隔离层中包括施主杂质或受主杂质。
  8. 如权利要求7所述的方法，其特征在于，所述施主杂质包括以下至少一种：磷、砷、锑。
  9. 如权利要求7或8所述的方法，其特征在于，所述受主杂质包括以下至少一种；硼、铟、铝。
  10. 如权利要求7至9中任一项所述的方法，其特征在于，所述内隔离层包括以下至少一种：磷硅玻璃、硼硅玻璃、砷硅玻璃。
  11. 如权利要求7至10中任一项所述的方法，其特征在于，所述场效应晶体管包括全环栅场效应晶体管GAAFET，所述沟道区域为第一沟道区域，所述源极和漏极之间设置有多个堆叠的沟道区域，所述第一沟道区域为所述多个堆叠的沟道区域中的任一沟道区域；以及，
    所述内隔离层为第一内隔离层，所述栅极和所述源极以及所述栅极和所述漏极之间设置有多个堆叠的内隔离层，所述第一内隔离层为所述多个堆叠的内隔离层中的任一内隔离 层。
  12. 如权利要求7至11中任一项所述的方法，其特征在于，所述场效应晶体管包括鳍式场效应晶体管FinFET。
  13. 一种电子器件，其特征在于，包括如权利要求1至5中任一项所述的场效应晶体管。
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