WO2018078705A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2018078705A1 WO2018078705A1 PCT/JP2016/081492 JP2016081492W WO2018078705A1 WO 2018078705 A1 WO2018078705 A1 WO 2018078705A1 JP 2016081492 W JP2016081492 W JP 2016081492W WO 2018078705 A1 WO2018078705 A1 WO 2018078705A1
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- wiring member
- semiconductor device
- semiconductor chip
- resin
- joint
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- Semiconductor devices are used in inverters or regenerative converters that control motors for electric cars or trains.
- a semiconductor device an emitter electrode on an upper surface of a semiconductor chip and a wiring member are soldered (for example, see Patent Document 1).
- the emitter electrode may be separated into a plurality of parts. There are a plurality of junctions between the plurality of emitter electrodes and the wiring member. Since the junctions close to each other form a tunnel, the resin flows in from both openings of the tunnel when the resin is sealed, and air is trapped to form bubbles. Due to the bubbles, there is a problem that reliability is lowered and insulation is lowered.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of suppressing the generation of bubbles in a resin at low cost and a method for manufacturing the same.
- a semiconductor device includes a semiconductor chip, first and second electrodes provided on an upper surface of the semiconductor chip and spaced apart from each other, a first bonding portion bonded to the first electrode, A wiring member having a second bonding portion bonded to a second electrode; and a resin that seals the semiconductor chip, the first and second electrodes, and the wiring member.
- a hole that vertically penetrates the wiring member is provided between the joint and the second joint.
- the air between the first and second joints escapes upward from the hole of the wiring member during resin sealing. Thereby, generation
- FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.
- 1 is a plan view showing a main part of a semiconductor device according to a first embodiment of the present invention.
- FIG. 3 is a cross-sectional view taken along the line II of FIG.
- FIG. 4 is a cross-sectional view taken along the line III-IV in FIG. 2.
- It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention.
- It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention.
- It is a top view which shows the principal part of the semiconductor device which concerns on a comparative example.
- FIG. 1 is a perspective view showing a semiconductor device according to Embodiment 1 of the present invention.
- the inside of the case 1 is sealed with a resin 2.
- Case 1 has a structure in which resin 2 does not leak.
- the case 1 is provided with a collector output unit 3, an emitter output unit 5, and a signal terminal 6.
- FIG. 2 is a plan view showing the main part of the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view taken along the line II of FIG.
- FIG. 4 is a cross-sectional view taken along the line III-IV in FIG.
- the substrate 7 is bonded to the bottom surface of the case 1.
- the electrode 8 of the substrate 7 is connected to the collector output unit 3.
- the collector electrode 10 on the lower surface of the semiconductor chip 9 is joined to the electrode 8 of the substrate 7 by solder 11.
- the semiconductor chip 9 is an IGBT, but may be a MOSFET, SBD, PN diode, or the like.
- the first and second emitter electrodes 12 and 13 spaced apart from each other are provided on the upper surface of the semiconductor chip 9. Between the first emitter electrode 12 and the second emitter electrode 13, a wiring 14 not connected to the first and second emitter electrodes 12, 13 is provided on the upper surface of the semiconductor chip 9.
- the wiring 14 is connected to a temperature sense or a gate. Because of the wiring 14, the emitter electrode is separated into the first and second emitter electrodes 12 and 13.
- the wiring 14 is connected to the signal terminal 6 by an aluminum wire (not shown). Therefore, an input signal is input to the gate of the semiconductor chip 9 through the signal terminal 6 and the wiring 14, or a temperature output signal is output from the semiconductor chip 9.
- the first joint 15 a of the wiring member 15 is joined to the first emitter electrode 12 by the solder 16.
- the second joint portion 15 b of the wiring member 15 is joined to the second emitter electrode 13 by the solder 17.
- the wiring member 15 is connected to the emitter output unit 5.
- Resin 2 seals the semiconductor chip 9, the first and second emitter electrodes 12, 13, the wiring member 15, and the like.
- a hole 18 penetrating the wiring member 15 vertically is provided between the first joint 15a and the second joint 15b.
- 5 and 6 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 5 and 6 correspond to the cross-sectional view of FIG.
- a hole 18 penetrating the wiring member 15 vertically is formed between the first joint portion 15a and the second joint portion 15b of the wiring member 15.
- the first and second emitter electrodes 12 and 13 provided on the upper surface of the semiconductor chip 9 and spaced apart from each other are bonded to the first and second bonding portions 15a and 15b of the wiring member 15, respectively. Thereby, it will be in the state before resin sealing shown in FIG.
- FIG. 6 when the resin 2 is injected from the side of the wiring member 15, the air in the tunnel between the first and second joint portions 15 a and 15 b escapes upward from the hole 18 of the wiring member 15. .
- FIG. 7 is a plan view showing a main part of a semiconductor device according to a comparative example.
- the hole 18 is not formed in the wiring member 15.
- 8 to 10 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the comparative example. 8 to 10 correspond to the cross-sectional view of FIG. FIG. 8 shows a state before resin sealing.
- Resin 2 generally has high viscosity and poor fluidity even before being cured. Therefore, as shown in FIG. 9, when the resin 2 is injected from the side of the wiring member 15, the resin 2 flows on the wiring member 15 before the gap below the wiring member 15. For this reason, the resin 2 flows in from both openings of the tunnel between the first and second joint portions 15 a and 15 b, and air is confined under the wiring member 15 to form bubbles 19. This bubble reduces reliability and reduces insulation.
- the air between the first and second joint portions 15a and 15b escapes upward from the hole 18 of the wiring member 15 during resin sealing.
- production of the bubble in resin 2 can be suppressed at low cost.
- the hole 18 a long hole extending along the tunnel between the first and second joint portions 15a and 15b, air can be more easily removed.
- FIG. FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.
- the resin 2 is injected from the hole 18 toward the lower side of the wiring member 15 to seal the semiconductor chip 9, the first and second emitter electrodes 12 and 13, and the wiring member 15. Other steps are the same as those in the first embodiment. Since the air below the wiring member 15 is pushed out by the resin 2, the generation of bubbles in the resin 2 can be suppressed.
- FIG. 12 is a cross-sectional view showing the main part of the semiconductor device according to the third embodiment of the present invention.
- one side in the width direction of the wiring member 15 is bent upward.
- FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.
- the bent portion of the wiring member 15 becomes a dam to temporarily block the resin 2 flowing on the wiring member 15. Accordingly, since the wraparound of the resin 2 is delayed, the generation of bubbles in the resin 2 can be suppressed by flowing the resin 2 from one side into the tunnel below the wiring member 15 and pushing out the air. Even if the wiring member 15 does not have the hole 18, the same effect can be obtained.
- FIG. 14 is a cross-sectional view showing the main part of the semiconductor device according to the fourth embodiment of the present invention.
- the wiring member 15 protrudes upward in a chimney shape around the hole 18.
- FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.
- the resin 2 flowing on the wiring member 15 is not easily covered on the hole 18 by the portion protruding upward in a chimney shape. For this reason, air easily escapes from the hole 18, and generation of bubbles in the resin 2 can be suppressed.
- the semiconductor chip 9 is not limited to being formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon.
- the wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond.
- a semiconductor chip formed of such a wide band gap semiconductor has high withstand voltage and allowable current density, and can be downsized.
- a semiconductor device incorporating this semiconductor chip can also be miniaturized. Further, since the heat resistance of the semiconductor chip is high, the heat dissipating fins of the heat sink can be reduced in size, and the water cooling part can be cooled in the air, so that the semiconductor device can be further reduced in size. Further, since the power loss of the semiconductor chip is low and the efficiency is high, the efficiency of the semiconductor device can be increased.
Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す斜視図である。ケース1の内部は樹脂2で封止されている。ケース1は樹脂2が漏れないような構造になっている。ケース1には、コレクタ出力部3、エミッタ出力部5及び信号端子6が設けられている。
図11は、本発明の実施の形態2に係る半導体装置の製造工程を示す断面図である。本実施の形態では、穴18から配線部材15の下方に向かって樹脂2を注入して半導体チップ9、第1及び第2のエミッタ電極12,13、及び配線部材15を封止する。その他の工程は実施の形態1と同様である。配線部材15の下方の空気は樹脂2により外側へ押し出されるため、樹脂2内の気泡の発生を抑制できる。
図12は、本発明の実施の形態3に係る半導体装置の主要部を示す断面図である。本実施の形態では、配線部材15の幅方向の片側が上方に折り曲げられている。
図14は、本発明の実施の形態4に係る半導体装置の主要部を示す断面図である。本実施の形態では、穴18の周囲において配線部材15が煙突状に上方に突き出している。
Claims (7)
- 半導体チップと、
前記半導体チップの上面に設けられ、互いに離間した第1及び第2の電極と、
前記第1の電極に接合された第1の接合部と、前記第2の電極に接合された第2の接合部とを有する配線部材と、
前記半導体チップ、前記第1及び第2の電極、及び前記配線部材を封止する樹脂とを備え、
前記第1の接合部と前記第2の接合部との間において前記配線部材を上下に貫通する穴が設けられていることを特徴とする半導体装置。 - 前記第1の電極と前記第2の電極との間において前記半導体チップの前記上面に設けられ、前記第1及び第2の電極に接続されていない配線を更に備えることを特徴とする請求項1に記載の半導体装置。
- 前記穴は長穴であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記配線部材の幅方向の片側が上方に折り曲げられていることを特徴とする請求項1~3の何れか1項に記載の半導体装置。
- 前記穴の周囲において前記配線部材が煙突状に上方に突き出していることを特徴とする請求項1~3の何れか1項に記載の半導体装置。
- 前記半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~5の何れか1項に記載の半導体装置。
- 配線部材の第1の接合部と第2の接合部との間において前記配線部材を上下に貫通する穴を形成する工程と、
半導体チップの上面に設けられ互いに離間した第1及び第2の電極をそれぞれ前記配線部材の前記第1及び第2の接合部に接合する工程と、
前記穴から前記配線部材の下方に向かって樹脂を注入して前記半導体チップ、前記第1及び第2の電極、及び前記配線部材を封止する工程とを備えることを特徴とする半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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KR1020197002474A KR102170867B1 (ko) | 2016-10-24 | 2016-10-24 | 반도체 장치 및 그 제조 방법 |
PCT/JP2016/081492 WO2018078705A1 (ja) | 2016-10-24 | 2016-10-24 | 半導体装置及びその製造方法 |
DE112016007372.0T DE112016007372T5 (de) | 2016-10-24 | 2016-10-24 | Halbleitervorrichtung und Herstellungsverfahren dafür |
JP2018546956A JP6777157B2 (ja) | 2016-10-24 | 2016-10-24 | 半導体装置及びその製造方法 |
CN201680090273.7A CN109844936B (zh) | 2016-10-24 | 2016-10-24 | 半导体装置及其制造方法 |
US16/319,975 US10707141B2 (en) | 2016-10-24 | 2016-10-24 | Semiconductor device and manufacturing method thereof |
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PCT/JP2016/081492 WO2018078705A1 (ja) | 2016-10-24 | 2016-10-24 | 半導体装置及びその製造方法 |
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US (1) | US10707141B2 (ja) |
JP (1) | JP6777157B2 (ja) |
KR (1) | KR102170867B1 (ja) |
CN (1) | CN109844936B (ja) |
DE (1) | DE112016007372T5 (ja) |
WO (1) | WO2018078705A1 (ja) |
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JP2021009970A (ja) * | 2019-07-03 | 2021-01-28 | 住友電気工業株式会社 | 半導体装置 |
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JP2006190728A (ja) * | 2005-01-04 | 2006-07-20 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2006202885A (ja) * | 2005-01-19 | 2006-08-03 | Mitsubishi Electric Corp | 半導体装置 |
JP2013179229A (ja) * | 2012-02-29 | 2013-09-09 | Rohm Co Ltd | パワーモジュール半導体装置 |
JP2014017318A (ja) * | 2012-07-06 | 2014-01-30 | Toyota Industries Corp | 半導体装置 |
JP2016134540A (ja) * | 2015-01-21 | 2016-07-25 | 三菱電機株式会社 | 電力用半導体装置 |
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WO2005024933A1 (ja) | 2003-08-29 | 2005-03-17 | Renesas Technology Corp. | 半導体装置の製造方法 |
JP4659534B2 (ja) | 2005-07-04 | 2011-03-30 | 三菱電機株式会社 | 半導体装置 |
JP2007242727A (ja) * | 2006-03-06 | 2007-09-20 | Sharp Corp | ヘテロ接合バイポーラトランジスタ及びこれを用いた電力増幅器 |
CN104412382B (zh) * | 2012-07-05 | 2017-10-13 | 三菱电机株式会社 | 半导体装置 |
JP5910456B2 (ja) | 2012-10-22 | 2016-04-27 | 株式会社豊田自動織機 | 半導体装置 |
US20180190556A1 (en) * | 2016-12-30 | 2018-07-05 | Texas Instruments Incorporated | Methods and apparatus for spark gap devices within integrated circuits |
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- 2016-10-24 KR KR1020197002474A patent/KR102170867B1/ko active IP Right Grant
- 2016-10-24 DE DE112016007372.0T patent/DE112016007372T5/de active Pending
- 2016-10-24 CN CN201680090273.7A patent/CN109844936B/zh active Active
- 2016-10-24 WO PCT/JP2016/081492 patent/WO2018078705A1/ja active Application Filing
- 2016-10-24 JP JP2018546956A patent/JP6777157B2/ja active Active
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Patent Citations (5)
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JP2006190728A (ja) * | 2005-01-04 | 2006-07-20 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2006202885A (ja) * | 2005-01-19 | 2006-08-03 | Mitsubishi Electric Corp | 半導体装置 |
JP2013179229A (ja) * | 2012-02-29 | 2013-09-09 | Rohm Co Ltd | パワーモジュール半導体装置 |
JP2014017318A (ja) * | 2012-07-06 | 2014-01-30 | Toyota Industries Corp | 半導体装置 |
JP2016134540A (ja) * | 2015-01-21 | 2016-07-25 | 三菱電機株式会社 | 電力用半導体装置 |
Cited By (2)
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JP2021009970A (ja) * | 2019-07-03 | 2021-01-28 | 住友電気工業株式会社 | 半導体装置 |
JP7247791B2 (ja) | 2019-07-03 | 2023-03-29 | 住友電気工業株式会社 | 半導体装置 |
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KR20190022756A (ko) | 2019-03-06 |
CN109844936B (zh) | 2023-12-15 |
DE112016007372T5 (de) | 2019-07-11 |
JPWO2018078705A1 (ja) | 2019-06-24 |
JP6777157B2 (ja) | 2020-10-28 |
US10707141B2 (en) | 2020-07-07 |
KR102170867B1 (ko) | 2020-10-28 |
CN109844936A (zh) | 2019-06-04 |
US20190267297A1 (en) | 2019-08-29 |
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