CN109844936A - 半导体装置及其制造方法 - Google Patents
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Abstract
在半导体芯片(9)的上表面设有相互分离的第1以及第2发射极电极(12、13)。配线部件(15)具有与第1发射极电极(12)接合的第1接合部(15a)、以及与第2发射极电极(13)接合的第2接合部(15b)。树脂(2)对半导体芯片(9)、第1以及第2发射极电极(12、13)、以及配线部件(15)进行封装。在第1接合部(15a)和第2接合部(15b)之间,设有将配线部件(15)上下贯穿的孔(18)。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
在对电动汽车或电车等的电动机进行控制的逆变器或再生用转换器中使用半导体装置。在半导体装置处,半导体芯片的上表面的发射极电极和配线部件进行焊料接合(例如,参照专利文献1)。
专利文献1:日本特开2014-86501号公报
发明内容
在半导体芯片的上表面具有温度传感器或栅极等的配线,因此,有时发射极电极被分离为多个。多个发射极电极和配线部件的接合部也变成多个。由于相互接近的接合部之间变成隧道(tunnel),所以在进行树脂封装时树脂从隧道的两个开口部流入而将空气封入,变成气泡。由于该气泡,存在可靠性降低、绝缘性降低的问题。
作为其对策,虽然也能够在减压气氛下进行树脂注入、或是在对树脂和产品进行了加热的状态下降低树脂的粘度而使树脂容易绕入,但是存在设备成本和加工成本上升的问题。
本发明就是为了解决上述课题而提出的,其目的在于得到能够以低成本抑制树脂内的气泡的产生的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于,具备:半导体芯片;第1以及第2电极,它们设于所述半导体芯片的上表面,相互分离;配线部件,其具有与所述第1电极接合的第1接合部以及与所述第2电极接合的第2接合部;以及树脂,其对所述半导体芯片、所述第1及第2电极、以及所述配线部件进行封装,在所述第1接合部和所述第2接合部之间设有将所述配线部件上下贯穿的孔。
发明的效果
在本发明中,在进行树脂封装时,第1以及第2接合部之间的空气从配线部件的孔逸出至上方。由此,能够以低成本抑制树脂内的气泡的产生。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的斜视图。
图2是表示本发明的实施方式1涉及的半导体装置的主要部分的俯视图。
图3是沿图2的Ⅰ-Ⅱ的剖视图。
图4是沿图2的Ⅲ-Ⅳ的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图7是表示对比例涉及的半导体装置的主要部分的俯视图。
图8是表示对比例涉及的半导体装置的制造工序的剖视图。
图9是表示对比例涉及的半导体装置的制造工序的剖视图。
图10是表示对比例涉及的半导体装置的制造工序的剖视图。
图11是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图12是表示本发明的实施方式3涉及的半导体装置的主要部分的剖视图。
图13是表示本发明的实施方式3涉及的半导体装置的制造工序的剖视图。
图14是表示本发明的实施方式4涉及的半导体装置的主要部分的剖视图。
图15是表示本发明的实施方式4涉及的半导体装置的制造工序的剖视图。
具体实施方式
参照附图说明本发明的实施方式涉及的半导体装置及其制造方法。对于相同或对应的结构要素标注相同的标号,有时省略重复说明。
实施方式1
图1是表示本发明的实施方式1涉及的半导体装置的斜视图。壳体1的内部由树脂2封装。壳体1是不会使树脂2漏出的构造。在壳体1设有集电极输出部3、发射极输出部5以及信号端子6。
图2是表示本发明的实施方式1涉及的半导体装置的主要部分的俯视图。图3是沿图2的Ⅰ-Ⅱ的剖视图。图4是沿图2的Ⅲ-Ⅳ的剖视图。
基板7与壳体1的底面粘接。基板7的电极8与集电极输出部3连接。半导体芯片9的下表面的集电极(collector)电极(electrode)10通过焊料11与基板7的电极8接合。半导体芯片9是IGBT,但也可以是MOSFET、SBD或PN二极管等。
在半导体芯片9的上表面设有相互分离的第1以及第2发射极电极12、13。在第1发射极电极12和第2发射极电极13之间在半导体芯片9的上表面,设有未与第1以及第2发射极电极12、13连接的配线14。配线14与温度传感器或栅极等连接。由于该配线14的存在,所以发射极电极被分离为第1以及第2发射极电极12、13。配线14通过未图示的铝线等与信号端子6连接。因此,通过信号端子6以及配线14,将输入信号输入至半导体芯片9的栅极,或者从半导体芯片9输出温度输出信号。
配线部件15的第1接合部15a通过焊料16与第1发射极电极12接合。配线部件15的第2接合部15b通过焊料17与第2发射极电极13接合。配线部件15与发射极输出部5连接。
树脂2对半导体芯片9、第1以及第2发射极电极12、13、以及配线部件15等进行封装。在第1接合部15a和第2接合部15b之间设有将配线部件15上下贯穿的孔18。
接着,说明本实施方式涉及的半导体装置的制造方法。图5以及图6是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。图5以及图6与图4的剖视图对应。
首先,在配线部件15的第1接合部15a和第2接合部15b之间形成将配线部件15上下贯穿的孔18。然后,将在半导体芯片9的上表面设置的相互分离的第1以及第2发射极电极12、13分别与配线部件15的第1以及第2接合部15a、15b接合。由此,成为图5所示的树脂封装前的状态。然后,如图6所示,如果从配线部件15的侧方注入树脂2,则第1以及第2接合部15a、15b之间的隧道内的空气从配线部件15的孔18逸出至上方。
接着,与对比例进行比较而说明本实施方式的效果。图7是表示对比例涉及的半导体装置的主要部分的俯视图。在对比例中,在配线部件15没有形成孔18。图8至图10是表示对比例涉及的半导体装置的制造工序的剖视图。图8至图10与图4的剖视图对应。图8表示树脂封装前的状态。
通常,就树脂2而言,即使在固化前,也是粘度高、流动性差。因此,如图9所示,如果从配线部件15的侧方注入树脂2,则与配线部件15之下的间隙相比先流进配线部件15之上。因此,从第1以及第2接合部15a、15b之间的隧道的两个开口部流入树脂2,在配线部件15之下封入了空气而成为气泡19。由于该气泡,可靠性降低,绝缘性降低。
与此相对,在本实施方式中,在进行树脂封装时,第1以及第2接合部15a、15b之间的空气从配线部件15的孔18逸出至上方。由此,能够以低成本抑制树脂2内的气泡的产生。另外,通过将孔18设为沿着第1以及第2接合部15a、15b之间的隧道延伸的长孔,从而使空气更容易逸出。
实施方式2
图11是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。在本实施方式中,从孔18向配线部件15的下方注入树脂2,对半导体芯片9、第1以及第2发射极电极12、13、以及配线部件15进行封装。其他工序与实施方式1相同。由于配线部件15的下方的空气被树脂2挤向外侧,所以能够抑制树脂2内的气泡的产生。
实施方式3
图12是表示本发明的实施方式3涉及的半导体装置的主要部分的剖视图。在本实施方式中,配线部件15的宽度方向的单侧向上方弯折。
图13是表示本发明的实施方式3涉及的半导体装置的制造工序的剖视图。配线部件15的弯折部分成为阻挡物,将流过配线部件15之上的树脂2暂时阻挡住。由此,树脂2的绕入延迟,所以通过使树脂2从单侧流入至配线部件15的下方的隧道而将空气挤出,从而能够抑制树脂2内的气泡的产生。此外,即使在配线部件15没有孔18,也能够得到相同的效果。
实施方式4
图14是表示本发明的实施方式4涉及的半导体装置的主要部分的剖视图。在本实施方式中,在孔18的周围,配线部件15呈烟囱状向上方凸出。
图15是表示本发明的实施方式4涉及的半导体装置的制造工序的剖视图。流过配线部件15之上的树脂2由于呈烟囱状向上方凸出的部分而难以覆盖到孔18之上。因此,空气容易从孔18逸出,能够抑制树脂2内的气泡的产生。
此外,半导体芯片9不限于由硅形成,也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或金刚石。由这样的宽带隙半导体形成的半导体芯片的耐电压性、容许电流密度高,因此能够小型化。通过使用该小型化后的半导体芯片,组装有该半导体芯片的半导体装置也能够小型化。另外,由于半导体芯片的耐热性高,所以能够将散热器的散热鳍片小型化,由于能够将水冷部进行风冷化,所以能将半导体装置进一步小型化。另外,由于半导体芯片的电力损耗低而高效,所以能够使半导体装置高效化。
标号的说明
2树脂,9半导体芯片,12第1发射极电极,13第2发射极电极,14配线,15配线部件,15a第1接合部,15b第2接合部,18孔。
Claims (7)
1.一种半导体装置,其特征在于,具备:
半导体芯片;
第1以及第2电极,它们设于所述半导体芯片的上表面,相互分离;
配线部件,其具有与所述第1电极接合的第1接合部以及与所述第2电极接合的第2接合部;以及
树脂,其对所述半导体芯片、所述第1及第2电极、以及所述配线部件进行封装,
在所述第1接合部和所述第2接合部之间设有将所述配线部件上下贯穿的孔。
2.根据权利要求1所述的半导体装置,其特征在于,
还具备配线,该配线在所述第1电极和所述第2电极之间设置在所述半导体芯片的所述上表面,未与所述第1以及第2电极连接。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述孔是长孔。
4.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
所述配线部件的宽度方向的单侧向上方弯折。
5.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
在所述孔的周围,所述配线部件呈烟囱状向上方凸出。
6.根据权利要求1至5中任一项所述的半导体装置,其特征在于,
所述半导体芯片由宽带隙半导体形成。
7.一种半导体装置的制造方法,其特征在于,具备以下工序:
在配线部件的第1接合部和第2接合部之间形成将所述配线部件上下贯穿的孔;
将在半导体芯片的上表面设置的相互分离的第1以及第2电极分别与所述配线部件的所述第1以及第2接合部接合;以及
从所述孔向所述配线部件的下方注入树脂,对所述半导体芯片、所述第1以及第2电极、以及所述配线部件进行封装。
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JP2006202885A (ja) * | 2005-01-19 | 2006-08-03 | Mitsubishi Electric Corp | 半導体装置 |
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JP2013179229A (ja) * | 2012-02-29 | 2013-09-09 | Rohm Co Ltd | パワーモジュール半導体装置 |
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