CN109564918A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109564918A
CN109564918A CN201680088300.7A CN201680088300A CN109564918A CN 109564918 A CN109564918 A CN 109564918A CN 201680088300 A CN201680088300 A CN 201680088300A CN 109564918 A CN109564918 A CN 109564918A
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circuit pattern
semiconductor chip
repeat circuit
semiconductor device
semiconductor
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CN109564918B (zh
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林田幸昌
津田亮
伊达龙太郎
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Mitsubishi Electric Corp
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Abstract

在绝缘基板(1)之上设置有第1及第2电路图案(5、6)。在第1电路图案(5)之上设置有第1及第2半导体芯片(7、8)。在绝缘基板(1)之上，在第1半导体芯片(7)与第2半导体芯片(8)之间设置有中继电路图案(10)。导线(11)连续地连接至沿一个方向依次排列的第1半导体芯片(7)、中继电路图案(10)、第2半导体芯片(8)及第2电路图案(6)。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
高可靠性半导体装置的封装尺寸、芯片尺寸均在推进小型化，搭载的半导体芯片的集成度也不断升高。半导体芯片在通电时发热，因此将半导体芯片彼此连接的导线接合部的热疲劳决定半导体装置的寿命。存在如下担心，即，半导体芯片彼此的发热干涉而引起温度上升，与半导体芯片连接的导线的温度也上升，使半导体装置的寿命降低。对此，提出在相对的半导体芯片之间设置有中继电路图案的半导体装置(例如，参照专利文献1)。
专利文献1：日本特开2013－21107号公报
发明内容
但是，由于通过导线分别将相对的半导体芯片和中继电路图案连接，因此中继电路图案处的导线键合部位变成两个。与其相应地需要导线键合空间，无法将半导体芯片搭载区域扩大。另外，从中继电路图案起向相对的半导体芯片的导线键合的方向是相反的，因此在制造工艺时会耗费改变方向的时间，生产率降低。
另外，将从中继电路图案(例如，参照专利文献1的发射极配线106)获取信号的电极(例如，参照专利文献1的发射极电极接合部201e)配置在相对的半导体芯片彼此之间。如果要避开该电极，则导线键合工具的角度变得复杂，因此难以将导线连续地连接至相对的半导体芯片和中继电路图案。即使将导线连续地连接，也需要在某半导体芯片将导线切断，因此有可能使质量降低。
本发明就是为了解决上述课题而提出的，其目的在于得到一种半导体装置，该半导体装置能够防止寿命及质量的降低，削减导线键合空间，提高生产率。
本发明涉及的半导体装置的特征在于，具有：绝缘基板；第1及第2电路图案，其设置在所述绝缘基板之上；第1及第2半导体芯片，其设置在所述第1电路图案之上；中继电路图案，其在所述绝缘基板之上，设置在所述第1半导体芯片与所述第2半导体芯片之间；以及导线，其连续地连接至沿一个方向依次排列的所述第1半导体芯片、所述中继电路图案、所述第2半导体芯片及所述第2电路图案。
发明的效果
在本发明中，在第1半导体芯片与第2半导体芯片之间设置有中继电路图案。由此，发热源彼此的距离远，因此能够避免相对的第1及第2半导体芯片彼此的热干涉的影响而抑制温度上升。并且，通过使导线与中继电路图案连接，从而能够通过中继电路图案对导线进行冷却。其结果，能够防止半导体装置的寿命的降低。
另外，导线连续地连接至沿一个方向依次排列的第1半导体芯片、中继电路图案、第2半导体芯片及第2电路图案。因此，中继电路图案处的导线键合部位变成1个，因此能够削减导线键合空间。并且，能够将获取信号的电极形成于第2电路图案，因此不需要用于避开该电极的复杂的导线键合。因此，导线键合方向成为一个方向，因此能够提高生产率。并且，只要在第2电路图案将导线切断即可，因此能够防止质量的降低。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I－II的剖视图。
图3是表示本发明的实施方式3涉及的半导体装置的剖视图。
图4是表示本发明的实施方式4涉及的半导体装置的剖视图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。图2是沿图1的I－II的剖视图。绝缘基板1的下表面电极2通过焊料3等与散热板4连接。在绝缘基板1之上设置有第1及第2电路图案5、6。第1及第2电路图案5、6彼此分离。
在第1电路图案5之上沿一个方向依次排列地设置有第1、第2及第3半导体芯片7、8、9。第1及第2半导体芯片7、8为IGBT(Insulated Gate Bipolar Transistor)或MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)。第3半导体芯片9为二极管(Di)或肖特基势垒二极管(Schottky Barrier Diode：SBD)。
在绝缘基板1之上，在第1半导体芯片7与第2半导体芯片8之间设置有中继电路图案10。中继电路图案10设置在第1电路图案5的开口内，与第1电路图案5分离。导线11连续地连接至沿一个方向依次排列的第1半导体芯片7、中继电路图案10、第2半导体芯片8及第2电路图案6。即，第1半导体芯片7为导线键合的起点，第2电路图案6为导线键合的终点。另外，获取信号的电极12设置于第2电路图案6。
在本实施方式中，在第1半导体芯片7与第2半导体芯片8之间设置有中继电路图案10。由此，发热源彼此的距离远，因此能够避免相对的第1及第2半导体芯片7、8彼此的热干涉的影响而抑制温度上升。并且，通过使导线11与中继电路图案10连接，从而能够通过中继电路图案10对导线11进行冷却。其结果，能够防止半导体装置的寿命的降低。
另外，导线11连续地连接至沿一个方向依次排列的第1半导体芯片7、中继电路图案10、第2半导体芯片8、第3半导体芯片9及第2电路图案6。由此，中继电路图案10处的导线键合部位为1个，因此能够削减导线键合空间。并且，能够将获取信号的电极12形成于第2电路图案6，因此不需要用于避开该电极12的复杂的导线键合。因此，导线键合方向成为一个方向，因此能够提高生产率。并且，只要在第2电路图案6将导线11切断即可，因此能够防止质量的降低。
另外，第1及第2半导体芯片7、8分别横向排列地设置有多个。针对多个第1及第2半导体芯片7、8一体化地设置有1个中继电路图案10。并且，中继电路图案10与多个第1及第2半导体芯片7、8的上表面电极电连接而成为发射极电位或源极电位，使多个第1及第2半导体芯片7、8的上表面电极的电位相同。因此，能够使多个第1及第2半导体芯片7、8的通电电流平衡一致。因此，每1个芯片的电流量一致，能够实现电气性能提高，即实现通断不平衡(switching unbalance)对策。
实施方式2.
在本实施方式中，中继电路图案10与第1及第2电路图案5、6相比导热率高。例如，中继电路图案10的材料为Ag、Cu、Au或Al，第1及第2电路图案5、6的材料为Fe、SuS、Cu/Mo或Mo。由此，导线11的冷却能力提高，因此能够使导线11的接合部的寿命更长。在这里，如果将第1及第2电路图案5、6也设为Ag或Au等高导热率的材料，则部件成本大幅度增加，且难以确保第1、第2及第3半导体芯片7、8、9的接合材料、接合性及H/C可靠性。另一方面，就中继电路图案10而言，仅考虑导线接合性即可，因此能够使用高导热率的材料。
实施方式3.
图3是表示本发明的实施方式3涉及的半导体装置的剖视图。在本实施方式中，在中继电路图案10之上，通过镀覆等设置有与中继电路图案10、第1及第2电路图案5、6相比导热率高的高导热率膜13。高导热率膜13的材料为Ag、Cu、Au或Al，中继电路图案10及第1及第2电路图案5、6的材料为Fe、SuS、Cu/Mo或Mo。由此，能够获得与实施方式2相同的效果。
实施方式4.
图4是表示本发明的实施方式4涉及的半导体装置的剖视图。在本实施方式中，中继电路图案10的厚度大于第1及第2电路图案6的厚度。中继电路图案10的上表面的高度大于或等于第1及第2半导体芯片7、8的上表面的高度。由此，能够缩短导线11的长度，因此能够减少导线11的发热，使导线11的接合部的寿命更长。
此外，在实施方式1～4中，第1、第2及第3半导体芯片7、8、9并不限定于由硅形成，也可以由带隙比硅大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。为了形成中继电路图案10及第2电路图案6而使图案面积增大，但也可以通过将第1、第2及第3半导体芯片7、8、9设为宽带隙半导体而使芯片面积小型化。
另外，由宽带隙半导体形成的半导体芯片的耐电压性及容许电流密度高，因此能够实现小型化。通过使用该小型化的半导体芯片，从而安装有该元件的半导体装置也能够实现小型化。另外，由于半导体芯片的耐热性高，因此能够使散热器的散热鳍片小型化，能够将水冷部空冷化，因此能够使半导体装置进一步小型化。另外，由于半导体芯片的电力损耗低且高效，因此能够使半导体装置高效化。
标号的说明
1绝缘基板，5第1电路图案，6第2电路图案，7第1半导体芯片，8第2半导体芯片，10中继电路图案，11导线，13高导热率膜。

Claims (5)

1.一种半导体装置，其特征在于，具有：
绝缘基板；
第1及第2电路图案，其设置在所述绝缘基板之上；
第1及第2半导体芯片，其设置在所述第1电路图案之上；
中继电路图案，其在所述绝缘基板之上，设置在所述第1半导体芯片与所述第2半导体芯片之间；以及
导线，其连续地连接至沿一个方向依次排列的所述第1半导体芯片、所述中继电路图案、所述第2半导体芯片及所述第2电路图案。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第1及第2半导体芯片分别设置有多个，
所述中继电路图案与多个所述第1及第2半导体芯片的上表面电极电连接，使多个所述第1及第2半导体芯片的上表面电极的电位相同。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述中继电路图案与所述第1及第2电路图案相比导热率高。
4.根据权利要求1或2所述的半导体装置，其特征在于，
还具有高导热率膜，该高导热率膜设置在所述中继电路图案之上，与所述中继电路图案及所述第1及第2电路图案相比导热率高。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述中继电路图案的厚度大于所述第1及第2电路图案的厚度，
所述中继电路图案的上表面的高度大于或等于所述第1及第2半导体芯片的上表面的高度。
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