WO2018076261A1 - 场效应晶体管及其制造方法 - Google Patents

场效应晶体管及其制造方法 Download PDF

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Publication number
WO2018076261A1
WO2018076261A1 PCT/CN2016/103695 CN2016103695W WO2018076261A1 WO 2018076261 A1 WO2018076261 A1 WO 2018076261A1 CN 2016103695 W CN2016103695 W CN 2016103695W WO 2018076261 A1 WO2018076261 A1 WO 2018076261A1
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specified
region
pattern
channel layer
ratio
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PCT/CN2016/103695
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English (en)
French (fr)
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赵冲
张臣雄
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华为技术有限公司
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Priority to CN201680086755.5A priority Critical patent/CN109314138B/zh
Priority to PCT/CN2016/103695 priority patent/WO2018076261A1/zh
Publication of WO2018076261A1 publication Critical patent/WO2018076261A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a field effect transistor and a method of fabricating the same.
  • the gate length of field effect transistors is continuously decreasing, and as the gate length is reduced, the channel of the field effect transistor is getting shorter and shorter.
  • the channel resistance is also getting smaller and smaller.
  • the channel resistance R CH decreases continuously due to the contact resistance R C and the channel layer between the source, drain and channel layers.
  • the resistor R A that is not subjected to gate modulation cannot be reduced as the channel becomes shorter, so when R CH is continuously reduced, R C and R A will dominate, that is, the field effect transistor performance The result will no longer be the nature of R CH , but the nature of R C and R A , causing the field effect transistor to lose its original field effect. Therefore, in order to avoid the field effect transistor losing the original field effect effect when the gate length is reduced, it is necessary to reduce the contact resistance between the source, the drain and the channel layer.
  • a field effect transistor including a substrate layer, a channel layer, a source, a drain, a dielectric layer and a gate; the channel layer covers an upper surface of the substrate layer, the channel The layer includes a first region and a second region, each of the first region and the second region includes at least one via hole, each via hole is used to penetrate the channel layer to expose the substrate layer, and each of the via holes has a shape a rectangular shape; the source is located above the first region of the channel layer, and the source is directly connected to the substrate layer at at least one via location of the first region; the drain is located in the channel layer Above the two regions, the drain is directly connected to the substrate layer at at least one via location of the second region; the dielectric layer covers the upper surface of the channel layer and is between the source and the drain The gate is above the dielectric layer.
  • the source and the drain are generally formed of a metal, and the contact resistance of the metal in contact with the edge of the channel layer material is smaller than that when contacting the top layer of the channel layer material, both in the first region and the second region Providing at least one via hole increases the contact length between the metal and the channel layer material, thereby increasing the edge contact between the metal and the channel layer material, and reducing the contact resistance between the metal and the channel layer material, that is, Yes, the contact resistance between the source, drain and channel layers is reduced.
  • the top layer contact means that the metal is located at the top of the channel layer material
  • the edge contact means that the metal is located at the edge of the channel layer material.
  • the black mesh portion is the channel layer material and the white portion is the rectangular via hole
  • the first region and the first region The area occupied by the channel layer material in the two regions is greatly reduced, thereby causing a large increase in the resistance of the first region and the second region itself, and therefore, the contact between the source, the drain and the channel layer at this time.
  • the resistance is reduced, but in the case where the resistance of the first region and the second region itself is increased, the resistance outside the channel resistance is still dominant, affecting the field effect effect of the field effect transistor.
  • the present invention provides a field effect transistor and a method of fabricating the same.
  • a field effect transistor comprising a substrate layer, a channel layer, a source, a drain, a dielectric layer, and a gate;
  • the channel layer covers an upper surface of the substrate layer, the channel layer includes a first region and a second region, each of the first region and the second region includes at least one via hole, each of which has a hole for penetrating the channel layer to expose the substrate layer, and the shape of each of the via holes is a fractal pattern, the fractal pattern is determined based on a specified pattern, and the fractal pattern and the specified pattern are The ratio of the circumference is greater than the ratio of the area of the fractal pattern to the specified pattern;
  • the source is located above the first region in the channel layer, and the source is directly connected to the substrate layer at the at least one via location of the first region;
  • the drain a pole is located above the second region in the channel layer, and the drain is directly connected to the substrate layer at the at least one via location of the second region;
  • the dielectric layer covers an upper surface of the channel layer and is between the source and the drain; the gate is located above the dielectric layer.
  • the ratio of the perimeter of the fractal graphic to the specified graphic is greater than the ratio of the area of the fractal graphic to the specified graphic, that is, in the process of determining the fractal graphic based on the specified graphic, the increasing proportion of the graphic perimeter is greater than the graphic area.
  • the increase ratio can effectively control the increase of the via area while increasing the perimeter of the via hole, thereby avoiding a large reduction in the area occupied by the channel layer material in the first region and the second region, and avoiding the first region.
  • the resistance of the second region itself is greatly increased, so that the contact resistance is effectively reduced, and no additional excessive resistance is generated, so that the field effect effect of the field effect transistor can be ensured.
  • the fractal graphic is to perform the specified graphic according to a specified iteration rule.
  • the specified iteration rule is to replace at least one edge of the graphic with a corresponding generated curve, wherein the generated curve is a curve having a specified shape;
  • the ratio of the perimeter between the iterative graph and the specified graph is not less than the ratio of the area of the iterative graph to the specified graph
  • the iterative graph is that the specified graph is iterated according to the specified iteration rule.
  • the N is a natural number not less than 1;
  • the ratio of the circumference of the specified figure is equal to the ratio of the area of the iterative pattern to the specified pattern, the N is a natural number not less than 2.
  • the specified graphic is iterated N times according to the specified iteration rule to obtain a fractal graphic.
  • a fractal graphic having an infinite circumference and a limited area is actually obtained. Therefore, the perimeter of the via hole can be greatly increased under the premise that the via area is limited, that is, the contact length is reduced under the premise that the area occupied by the channel layer material in the first region and the second region is limited. It can be greatly increased to ensure that the contact resistance is reduced without generating any additional excessive resistance.
  • the channel layer is made of one of graphene, molybdenum disulfide, tungsten disulfide, boron nitride, black phosphorus or other two-dimensional materials.
  • the graphene may include a single layer of graphene, a double layer graphene, and a multilayer graphene.
  • a method of fabricating a field effect transistor comprising:
  • each via hole for penetrating the channel layer to expose the substrate layer, and shapes of the respective via holes a fractal graphic, wherein the fractal graphic is determined based on a specified graphic, and a ratio of a perimeter of the fractal graphic to the specified graphic is greater than a ratio of an area of the fractal graphic to the specified graphic;
  • drain Forming a drain over the second region in the channel layer, the drain being directly connected to the substrate layer at the at least one via location of the second region;
  • a gate is formed over the dielectric layer.
  • the increase of the graphic perimeter is greater than the graphic.
  • the increase ratio of the area can effectively control the increase of the via area while increasing the perimeter of the via hole, thereby avoiding a large reduction in the area occupied by the channel layer material in the first region and the second region, and avoiding the first region.
  • the resistance of the second region itself is greatly increased, so that the contact resistance is effectively reduced, and no additional excessive resistance is generated, so that the field effect effect of the field effect transistor can be ensured.
  • the fractal graphic is obtained by performing N iterations according to a specified iteration rule, and the specified iteration rule is to replace at least one edge of the graphic with a corresponding generated curve, the generated curve Is a curve with a specified shape;
  • the ratio of the perimeter between the iterative graph and the specified graph is not less than the ratio of the area of the iterative graph to the specified graph
  • the iterative graph is that the specified graph is iterated according to the specified iteration rule.
  • the N is a natural number not less than 1;
  • the ratio of the circumference of the specified figure is equal to the ratio of the area of the iterative pattern to the specified pattern, the N is a natural number not less than 2.
  • the specified graphic is iterated N times according to the specified iteration rule to obtain a fractal graphic.
  • a fractal graphic having an infinite circumference and a limited area is actually obtained. Therefore, the perimeter of the via hole can be greatly increased under the premise that the via area is limited, that is, the contact length is reduced under the premise that the area occupied by the channel layer material in the first region and the second region is limited. It can be greatly increased to ensure that the contact resistance is reduced without generating any additional excessive resistance.
  • the channel layer is made of one of graphene, molybdenum disulfide, tungsten disulfide, boron nitride, black phosphorus or other two-dimensional materials.
  • the graphene may include a single layer of graphene, a double layer graphene, and a multilayer graphene.
  • the invention provides a field effect transistor including a substrate layer, a channel layer, a source, a drain, a dielectric layer and a gate, and the first region of the channel layer and
  • the shape of each via in the second region is a fractal pattern, since the ratio of the perimeter of the fractal pattern to the specified pattern is greater than the ratio of the area of the fractal pattern to the specified pattern, that is, in the process of determining the fractal pattern based on the specified pattern,
  • the increase ratio of the circumference of the pattern is larger than the increase ratio of the area of the pattern, so that the increase of the area of the via hole can be effectively controlled while increasing the circumference of the via hole, thereby avoiding the first area and the second area.
  • the area occupied by the channel layer material in the domain is greatly reduced, and the resistance of the first region and the second region itself is prevented from being greatly increased, so that the contact resistance is effectively reduced, and no additional excessive resistance is generated.
  • the field effect effect of the field effect transistor can be guaranteed.
  • 1A is a schematic structural diagram of a field effect transistor according to related art
  • 1B is a schematic diagram of a first area and a second area provided by the related art
  • FIG. 2 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • 3(a) is a schematic diagram of a Cork curve provided by an embodiment of the present invention.
  • FIG. 3(b) is a schematic diagram of a Minkowski curve according to an embodiment of the present invention.
  • FIG. 4(a) is a schematic diagram of an iterative graph provided by an embodiment of the present invention.
  • FIG. 4(b) is a schematic diagram of an iterative process according to an embodiment of the present invention.
  • FIG. 5(a) is a schematic diagram of another iterative graph provided by an embodiment of the present invention.
  • FIG. 5(b) is a schematic diagram of another iterative process provided by an embodiment of the present invention.
  • FIG. 6(a) is a schematic diagram of still another iterative graph according to an embodiment of the present invention.
  • FIG. 6(b) is a schematic diagram of still another iterative process according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating a field effect transistor according to an embodiment of the present invention.
  • FIG. 8(a) is a schematic diagram of a substrate layer according to an embodiment of the present invention.
  • FIG. 8(b) is a schematic diagram of forming a channel layer according to an embodiment of the present invention.
  • FIG. 8(c) is a schematic diagram of forming a via hole according to an embodiment of the present invention.
  • FIG. 8(d) is a schematic diagram of forming a source and a drain according to an embodiment of the present invention.
  • FIG. 8(e) is a schematic diagram of forming a dielectric layer according to an embodiment of the present invention.
  • FIG. 8(f) is a schematic diagram of forming a gate according to an embodiment of the present invention.
  • 1 substrate layer; 2: channel layer; 21: first region; 22: second region; 3: source; Pole; 5: dielectric layer; 6: gate.
  • FIG. 2 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • the field effect transistor includes a substrate layer 1, a channel layer 2, a source 3, a drain 4, a dielectric layer 5, and a gate electrode 6;
  • the channel layer 2 covers the upper surface of the substrate layer 1, and the channel layer 2 includes a first region 21 and a second region 22.
  • Each of the first region 21 and the second region 22 includes at least one via hole, and each via hole is used for Through the channel layer 2 to expose the substrate layer 1;
  • the source 3 is located above the first region 21 in the channel layer 2, and the source 3 is directly connected to the substrate layer 1 at at least one via location of the first region 21;
  • the drain 4 is located in the channel layer 2 Above the region 22, and the drain 4 is directly connected to the substrate layer 1 at at least one via location of the second region 22;
  • the dielectric layer 5 covers the upper surface of the channel layer 2 and is located between the source 3 and the drain 4; the gate 6 is located above the dielectric layer 5.
  • the channel layer adopts one of graphene, molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), boron nitride (BN), black phosphorus or other two-dimensional materials, that is,
  • the channel layer material may be one of graphene, MoS 2 , WS 2 , BN, black phosphorus or other two-dimensional materials.
  • the graphene may include a single layer of graphene, a double layer graphene, and a multilayer graphene.
  • the source and the drain are generally formed of a metal, and the contact resistance of the metal in contact with the edge of the channel layer material is smaller than that when contacting the top layer of the channel layer material, the first region and the second region are Providing at least one via hole in the middle increases the contact length between the metal and the channel layer material, thereby increasing the edge contact between the metal and the channel layer material, and reducing the contact resistance between the metal and the channel layer material. That is, the contact resistance between the source, the drain and the channel layer is reduced, thereby preventing the field effect transistor from losing the original field effect effect when the gate length is reduced.
  • the shape of each via is a fractal graphic
  • the fractal graphic is determined based on the specified graphic
  • the ratio of the fractal shape to the perimeter of the specified graphic is greater than the ratio of the fractal graphic to the area of the specified graphic.
  • the specified graphic may be preset, for example, the specified graphic may be a square, a rectangle, a triangle, a pentagon, a hexagon, or the like.
  • each via hole is a rectangle
  • a plurality of rectangular via holes are often added.
  • the total circumference of the via hole and the total area of the via hole actually Is increasing in proportion, that is, increasing the circumference by several times, it will also increase the area several times, which will greatly reduce the channel layer material in the first region and the second region while increasing the contact length.
  • the area occupied causes a substantial increase in the resistance of the first region and the second region itself.
  • the ratio of the perimeter of the fractal graphic to the specified graphic is greater than the ratio of the area of the fractal graphic to the specified graphic, that is, in the process of determining the fractal graphic based on the specified graphic, the increasing proportion of the graphic perimeter is greater than the graphic area.
  • the increase ratio can effectively control the increase of the via area while increasing the perimeter of the via hole, thereby avoiding a large reduction in the area occupied by the channel layer material in the first region and the second region, and avoiding the first region.
  • the resistance of the second region itself is greatly increased, so that the contact resistance is effectively reduced, and no additional excessive resistance is generated, so that the field effect effect of the field effect transistor can be ensured.
  • the specified graphic when the fractal graphic is determined based on the specified graphic, the specified graphic may be subjected to N iterations according to the specified iteration rule to obtain a fractal graphic, and the specified iteration rule is to replace at least one edge of the graphic with the corresponding generated curve.
  • the iterative graph that is, the iterative graph is obtained by replacing at least one edge of the specified graph with the corresponding generated curve.
  • the ratio of the perimeter between the iterative graph and the specified graph is not less than the ratio of the area of the iterative graph to the specified graph to ensure that the ratio of the contour of the subsequently obtained fractal graph to the specified graph is greater than the ratio of the fractal graph to the area of the specified graph.
  • N can be a natural number not less than one.
  • the ratio of the iteration pattern to the perimeter of the specified graph is equal to the ratio of the area of the iterative graph to the area of the specified graph, at least two iterations are required to obtain the fractal graph that satisfies the requirement, and then N may be a natural number not less than 2.
  • the length of the generated curve corresponding to a certain edge may be a specified numerical multiple of the length of the edge, and the generated curve may be a curve having a specified shape, and the specified value and the specified shape may be preset, and the specified value may be according to the specified shape. Make settings.
  • the generated curve is a Koch curve as shown in FIG. 3(a).
  • the intermediate segment is removed and used. Two lines of equal length to the line segment are substituted. Then at this point, the length of the Koch curve is the length of the side. Times, that is, the specified value is
  • the specified shape is a Minkowski curve shape
  • the generated curve is a Minkowski curve as shown in FIG. 3(b)
  • the Minkowski curve is divided into four segments, and the middle two are The segment is removed and replaced with six segments of equal length to the segment. Then, it can be known that the length of the Minkowski curve is twice the length of the side, that is, the specified value is 2.
  • the specified graphic is N iterations according to the specified iteration rule to obtain a fractal graphic.
  • a fractal graphic having an infinite circumference and a limited area is actually obtained. Therefore, the perimeter of the via hole can be greatly increased under the premise that the via area is limited, that is, the contact length is reduced under the premise that the area occupied by the channel layer material in the first region and the second region is limited. It can be greatly increased to ensure that the contact resistance is reduced without generating any additional excessive resistance.
  • the specified iteration rule is to replace each edge of the graph with a corresponding generated curve, and the specified graph is an equilateral triangle, and the generated curve is a Koch curve, which can be as shown in FIG. 3(a). Iterates over the specified graph according to the specified iteration rules.
  • Figure 4 (a) is an iterative graph obtained by performing an iteration of the specified image according to the specified iteration rule. It can be seen that the ratio of the circumference of the iterative graph to the specified graph is equal to the ratio of the area of the iterative graph to the specified graph, and therefore, it is necessary to continue Iterating to obtain a fractal graph that satisfies the requirements, FIG.
  • 4(b) is a graph obtained by continuing to perform 2 iterations, 3 iterations, and the like according to a specified rule, in which the graph perimeter is The proportion is increasing, the area of the graph is The proportion is increasing. It can be seen that as the number of iterations increases, the perimeter of the graph has been increasing indefinitely, while the graph area has increased less and less, tending to be limited.
  • the iteration rule is specified to replace each edge of the graphic with a corresponding generated curve
  • the specified graphic is a square
  • the generated curve is a Minkowski curve
  • the Minkowski curve can be as shown in FIG. 3(b)
  • FIG. 5( a ) is an iterative graph obtained after one iteration of the specified image according to the specified iteration rule. It can be seen that the ratio of the circumference of the iterative graph to the specified graph is greater than the ratio of the area of the iterative graph to the specified graph.
  • the iterative graph can be directly determined as a fractal graph.
  • FIG. 5(b) is a graph obtained by continuing to perform 2 iterations of the specified graph according to a specified rule.
  • the perimeter of the graph is increasing at a ratio of 2 N , and the area of the graph is not increased. It can be seen that as the number of iterations increases, the perimeter of the graph continues to increase indefinitely, while the graph area remains unchanged. changing.
  • the specified iteration rule is to replace any two sides of the graphic with the corresponding generated curve, the specified graphic is a square, and the generated curve is a Minkowski curve, and the Minkowski curve can be as shown in FIG. 3(b). Iterates over the specified graph according to the specified iteration rules.
  • FIG. 6( a ) is an iterative graph obtained after one iteration of the specified image according to the specified iteration rule. It can be seen that the ratio of the circumference of the iterative graph to the specified graph is greater than the ratio of the area of the iterative graph to the specified graph.
  • the iterative graph can be directly determined as a fractal graph. Of course, iteration can be continued to obtain a better quality fractal graph.
  • FIG. 6(b) is to continue to perform 2 iterations and 3 iterations according to the specified rule. After the obtained graph, it can be seen that as the number of iterations increases, the perimeter of the graph continues to increase indefinitely, while the graph area remains unchanged.
  • the specified iteration rule can be flexibly set.
  • the edge of the graph a can be replaced with the corresponding generated curve in one iteration, and the b edges of the graph can be correspondingly used in the second iteration.
  • the generation curve is replaced.
  • the c edges of the graph can be replaced with the corresponding generated curves... wherein a, b, c... can be the same or different, that is, each iteration
  • the number of sides to be replaced may be the same or different.
  • the selection of the edge to be replaced in the graphics in each iteration may be randomly selected, or may be selected according to a certain strategy according to actual requirements, which is not specifically limited in the embodiment of the present invention.
  • the curve design can be complicated to be based on the generated music.
  • the fractal pattern obtained by the line has more corners, so that the atomic weight at the corner of the via layer in the channel layer material is increased, and the atoms in the channel layer material which are bonded to the metal are increased, so that the contact resistance can be further reduced.
  • the field effect transistor provided in the embodiment of the present invention includes a substrate layer, a channel layer, a source, a drain, a dielectric layer and a gate, and the shapes of the respective via holes in the first region and the second region of the channel layer are
  • the ratio of the perimeter of the fractal graphic to the specified graphic is larger than the ratio of the area of the fractal graphic to the specified graphic, that is, in the process of determining the fractal graphic based on the specified graphic, the increase ratio of the graphic perimeter is larger than the increase of the graphic area.
  • the ratio can be used to effectively control the increase of the via area while increasing the perimeter of the via hole, thereby avoiding a large reduction in the area occupied by the channel layer material in the first region and the second region, avoiding the first region and the second region.
  • the resistance of the region itself is greatly increased, so that the contact resistance is effectively reduced, and no additional excessive resistance is generated, so that the field effect effect of the field effect transistor can be ensured.
  • FIG. 7 is a flowchart of a method for fabricating a field effect transistor according to an embodiment of the present invention. The manufacturing method includes the following steps:
  • Step 701 Providing a substrate layer.
  • a substrate layer 1 is provided.
  • the substrate layer material may be silicon, quartz, silicon on an insulating substrate (Silicon-On-Insulator (SOI), silicon carbide (SiC). ) and other materials.
  • Step 702 forming a channel layer over the substrate layer.
  • the channel layer material may be transferred onto the substrate layer 1 to form the channel layer 2; or the substrate layer 1 may be processed by a chemical vapor deposition (CVD) process or the like.
  • the channel layer 2 is formed on the above, which is not specifically limited in the embodiment of the present invention.
  • the channel layer is made of one of graphene, MoS2, WS2, BN, black phosphorus or other two-dimensional materials, that is, the channel layer material may be graphene, MoS2, WS2, BN, black.
  • the graphene may include a single layer of graphene, a double layer graphene, and a multilayer graphene.
  • Step 703 Form at least one via hole in both the first region and the second region in the channel layer.
  • each via hole is used to penetrate the channel layer to expose the substrate layer, and the shape of each via hole is a fractal pattern, and the fractal pattern is determined based on the specified pattern, and the ratio of the fractal pattern to the perimeter of the specified pattern is larger than the fractal pattern. The ratio to the area of the specified graphic.
  • the first region 21 and the second region 22 in the channel layer 2 when at least one via hole is formed in both the first region 21 and the second region 22 in the channel layer 2, it may be first at both ends of the channel layer 2 (ie, the first region 21) And the second region 22) defines the shape and position of the via hole, and after defining the shape and position of the via hole, the regions of the first region 21 and the second region 22 except the via hole position are protected by the protective glue, and then The first region 21 and the second region 22 are etched to obtain respective via holes in the first region 21 and the second region 22.
  • the shape and position of the via hole can be defined by a photolithography process, such as by a photolithography process such as electron beam exposure or optical exposure.
  • the protective glue may be an etch-resistant glue, poly(methyl methacrylate), PMMA or the like.
  • etching may be performed by a reactive ion etching (RIE), an oxygen plasma etching, or the like.
  • RIE reactive ion etching
  • Step 704 forming a source over the first region in the channel layer and forming a drain over the second region in the channel layer.
  • the source and the substrate layer are directly connected at at least one via position of the first region, and the drain and the substrate layer are directly connected at at least one via position of the second region.
  • the positions of the source 3 and the drain 4 are respectively defined at both ends of the channel layer 2 (ie, the first region 21 and the second region 22), and the drain 3 and the drain 4 are separated by a pre-preparation.
  • the metal for forming the source 3 is deposited to obtain the source 3
  • the metal for forming the drain 4 is deposited to obtain the drain 4.
  • the source and drain positions can be defined by a photolithography process, such as by a photolithography process such as electron beam exposure or optical exposure.
  • the metal forming the source or the drain may be a simple metal, a layered stack of different metals, a carbide metal, or the like, wherein the metal element may be platinum (Pt), copper (Cu), nickel (Ni), gold ( Au), etc., the layered stack of different metals may be titanium/gold (Ti/Au), chromium/gold (Cr/Au), etc., and the carbide metal may be molybdenum carbide (Mo 2 C), tantalum carbide (TaC), Tungsten carbide (WC), etc.
  • the metal element may be platinum (Pt), copper (Cu), nickel (Ni), gold ( Au), etc.
  • the layered stack of different metals may be titanium/gold (Ti/Au), chromium/gold (Cr/Au), etc.
  • the carbide metal may be molybdenum carbide (Mo 2 C), tantalum carbide (TaC), Tungsten carbide (WC), etc.
  • deposition of a metal for forming a source or a drain may be performed by a process such as electron beam evaporation.
  • Step 705 forming a dielectric layer over the channel layer and between the source and the drain.
  • a high k may be deposited over the channel layer 2 and between the source 3 and the drain 4.
  • a dielectric material is used to obtain a dielectric layer 5, where k is a dielectric constant.
  • deposition may be performed by a process such as atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the high-k dielectric material may be hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), or the like.
  • Step 706 Forming a gate over the dielectric layer.
  • the position of the gate electrode 6 is defined on the dielectric layer 5, and after the position of the gate electrode 6 is defined, the metal for forming the gate electrode 6 is deposited to obtain the gate electrode 6.
  • the gate position when defining the gate position, it can be defined by a photolithography process, such as by a photolithography process such as electron beam exposure or optical exposure.
  • deposition of a metal for forming a gate electrode may be performed by a process such as electron beam evaporation.
  • the metal forming the gate electrode may be Au, palladium (Pd), tungsten (W) or other metals.
  • At least one via hole is formed in both the first region and the second region in the channel layer of the field effect transistor, and the shape of each via hole is set as a fractal pattern due to fractal
  • the ratio of the circumference of the graphic to the specified graphic is larger than the ratio of the fractal graphic to the area of the specified graphic, that is, in the process of determining the fractal graphic based on the specified graphic, the increase ratio of the graphic perimeter is larger than the increase ratio of the graphic area, so that the increase may be increased.
  • the increase of the via area is effectively controlled, thereby avoiding a large reduction in the area occupied by the channel layer material in the first region and the second region, and avoiding a large resistance of the first region and the second region itself.
  • the increase makes it possible to effectively reduce the contact resistance without generating other extra excessive resistance, thereby ensuring the field effect effect of the field effect transistor.

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Abstract

提供了一种场效应晶体管及其制造方法，涉及电子技术领域。场效应晶体管包括衬底层（1）、沟道层（2）、源极（3）、漏极（4）、电介质层（5）和栅极（6）；沟道层（2）覆盖于衬底层（1）的上表面，沟道层（2）包括第一区域（21）和第二区域（22），第一区域（21）和第二区域（22）中均包括至少一个过孔，各个过孔用于贯穿沟道层（2）以暴露出衬底层（1），且各个过孔的形状为分形图形，分形图形基于指定图形确定得到，且分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比；源极（3）位于沟道层（2）中第一区域（21）的上方，且源极（3）与衬底层（1）在第一区域（21）的至少一个过孔位置处直接相连；漏极（4）位于沟道层（2）中第二区域（22）的上方，且漏极（4）与衬底层（1）在第二区域（22）的至少一个过孔位置处直接相连。这种场效应晶体管有效减小源极、漏极与沟道层之间的接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。

Description

场效应晶体管及其制造方法 技术领域
本发明涉及电子技术领域，特别涉及一种场效应晶体管及其制造方法。
背景技术
随着电子技术的发展，为了提高大规模集成电路的集成度及性能，场效应晶体管的栅极长度不断减小，且随着栅极长度的减小，场效应晶体管的沟道越来越短，沟道电阻也越来越小。如图1A所示，随着场效应晶体管的栅极长度不断减小，沟道电阻RCH不断减小，而由于源极、漏极与沟道层之间的接触电阻RC和沟道层中不受栅极调制的电阻RA不能随着沟道变短而减小，所以当RCH不断减小时，RC和RA将会占据主导地位，也即是，此时场效应晶体管表现出的将不再是RCH的性质，而是RC和RA的性质，从而导致场效应晶体管失去原有的场效应效果。因此，为了避免场效应晶体管在栅极长度减小的情况下失去原有的场效应效果，需要减小源极、漏极与沟道层之间的接触电阻。
目前，提供了一种场效应晶体管，该场效应晶体管包括衬底层、沟道层、源极、漏极、电介质层和栅极；该沟道层覆盖于该衬底层的上表面，该沟道层包括第一区域和第二区域，第一区域和第二区域中均包括至少一个过孔，各个过孔用于贯穿该沟道层以暴露出该衬底层，且该各个过孔的形状均为长方形；该源极位于该沟道层中第一区域的上方，且该源极与该衬底层在第一区域的至少一个过孔位置处直接相连；该漏极位于该沟道层中第二区域的上方，且该漏极与该衬底层在第二区域的至少一个过孔位置处直接相连；该电介质层覆盖于该沟道层的上表面且位于该源极与该漏极之间；该栅极位于该电介质层的上方。
由于源极和漏极一般由金属形成，且金属与沟道层材料边缘接触时的接触电阻会比与沟道层材料顶层接触时的电阻小，因此，在第一区域和第二区域中均设置至少一个过孔，会增加金属与沟道层材料之间的接触长度，从而增加金属与沟道层材料之间的边缘接触，减小金属与沟道层材料之间的接触电阻，也即是，减小源极、漏极与沟道层之间的接触电阻。其中，顶层接触是指金属位于沟道层材料的顶部，边缘接触是指金属位于沟道层材料的边缘。
然而，如图1B所示(其中黑色网格部分为沟道层材料，白色部分为长方形过孔)，随着第一区域和第二区域中的长方形过孔数量的增多，第一区域和第二区域中的沟道层材料所占面积大大减小，从而会导致第一区域和第二区域本身的电阻大幅度增加，因此，此时虽然源极、漏极与沟道层之间的接触电阻减小了，但是在第一区域和第二区域本身的电阻增加的情况下，仍然会导致沟道电阻之外的电阻占据主导地位，影响场效应晶体管的场效应效果。
发明内容
为了解决相关技术的问题，本发明提供了一种场效应晶体管及其制造方法。
第一方面，提供了一种场效应晶体管，所述场效应晶体管包括衬底层、沟道层、源极、漏极、电介质层和栅极；
所述沟道层覆盖于所述衬底层的上表面，所述沟道层包括第一区域和第二区域，所述第一区域和所述第二区域中均包括至少一个过孔，各个过孔用于贯穿所述沟道层以暴露出所述衬底层，且所述各个过孔的形状为分形图形，所述分形图形基于指定图形确定得到，且所述分形图形与所述指定图形的周长之比大于所述分形图形与所述指定图形的面积之比；
所述源极位于所述沟道层中所述第一区域的上方，且所述源极与所述衬底层在所述第一区域的所述至少一个过孔位置处直接相连；所述漏极位于所述沟道层中所述第二区域的上方，且所述漏极与所述衬底层在所述第二区域的所述至少一个过孔位置处直接相连；
所述电介质层覆盖于所述沟道层的上表面且位于所述源极与所述漏极之间；所述栅极位于所述电介质层的上方。
在本发明实施例中，分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区域中沟道层材料所占面积的大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
需要说明的是，所述分形图形为将所述指定图形根据指定迭代规则进行N 次迭代后得到，所述指定迭代规则为将图形的至少一条边用对应的生成曲线进行替换，所述生成曲线为具有指定形状的曲线；
其中，迭代图形与所述指定图形之间的周长之比不小于所述迭代图形与所述指定图形的面积之比，所述迭代图形为将所述指定图形根据所述指定迭代规则进行1次迭代后得到；且当所述迭代图形与所述指定图形的周长之比大于所述迭代图形与所述指定图形的面积之比时，所述N为不小于1的自然数；当所述迭代图形与所述指定图形的周长之比等于所述迭代图形与所述指定图形的面积之比时，所述N为不小于2的自然数。
在本发明实施例中，将指定图形根据指定迭代规则进行N次迭代以得到分形图形，在该迭代过程中，实际上是得到了一种具有无限周长和有限面积的分形图形。从而可以在过孔面积有限的前提下，使得过孔周长得以大大增加，也即是在第一区域和第二区域中的沟道层材料所占面积有限减小的前提下，使得接触长度得以大大增加，从而可以保证在接触电阻减小的同时，不会产生其它额外的过大电阻。
需要说明的是，所述沟道层采用石墨烯、二硫化钼、二硫化钨、氮化硼、黑磷或其它二维材料中的一种。
其中，石墨烯可以包括单层石墨烯、双层石墨烯和多层石墨烯。
第二方面，提供了一种场效应晶体管制造方法，所述制造方法包括：
提供一衬底层；
在所述衬底层之上形成沟道层；
在所述沟道层中的第一区域和第二区域中均形成至少一个过孔，各个过孔用于贯穿所述沟道层以暴露出所述衬底层，且所述各个过孔的形状为分形图形，所述分形图形基于指定图形确定得到，且所述分形图形与所述指定图形的周长之比大于所述分形图形与所述指定图形的面积之比；
在所述沟道层中的所述第一区域之上形成源极，所述源极与所述衬底层在所述第一区域的所述至少一个过孔位置处直接相连；
在所述沟道层中的所述第二区域之上形成漏极，所述漏极与所述衬底层在所述第二区域的所述至少一个过孔位置处直接相连；
在所述沟道层之上且在所述源极与所述漏极之间形成电介质层；
在所述电介质层之上形成栅极。
在本发明实施例中，由于分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区域中沟道层材料所占面积大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
需要说明的是，所述分形图形为将所述指定图形根据指定迭代规则进行N次迭代后得到，所述指定迭代规则为将图形的至少一条边用对应的生成曲线进行替换，所述生成曲线为具有指定形状的曲线；
其中，迭代图形与所述指定图形之间的周长之比不小于所述迭代图形与所述指定图形的面积之比，所述迭代图形为将所述指定图形根据所述指定迭代规则进行1次迭代后得到；且当所述迭代图形与所述指定图形的周长之比大于所述迭代图形与所述指定图形的面积之比时，所述N为不小于1的自然数；当所述迭代图形与所述指定图形的周长之比等于所述迭代图形与所述指定图形的面积之比时，所述N为不小于2的自然数。
在本发明实施例中，将指定图形根据指定迭代规则进行N次迭代以得到分形图形，在该迭代过程中，实际上是得到了一种具有无限周长和有限面积的分形图形。从而可以在过孔面积有限的前提下，使得过孔周长得以大大增加，也即是在第一区域和第二区域中的沟道层材料所占面积有限减小的前提下，使得接触长度得以大大增加，从而可以保证在接触电阻减小的同时，不会产生其它额外的过大电阻。
需要说明的是，所述沟道层采用石墨烯、二硫化钼、二硫化钨、氮化硼、黑磷或其它二维材料中的一种。
其中，石墨烯可以包括单层石墨烯、双层石墨烯和多层石墨烯。
本发明提供的技术方案的有益效果是：在本发明实施例提供的场效应晶体管包括衬底层、沟道层、源极、漏极、电介质层和栅极，且沟道层的第一区域和第二区域中的各个过孔的形状均为分形图形，由于分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区 域中沟道层材料所占面积大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是相关技术提供的一种场效应晶体管的结构示意图；
图1B是相关技术提供的一种第一区域和第二区域的示意图；
图2是本发明实施例提供的一种场效应晶体管的结构示意图；
图3(a)是本发明实施例提供的一种科克曲线的示意图；
图3(b)是本发明实施例提供的一种闵可夫斯基曲线的示意图；
图4(a)是本发明实施例提供的一种迭代图形的示意图；
图4(b)是本发明实施例提供的一种迭代过程的示意图；
图5(a)是本发明实施例提供的另一种迭代图形的示意图；
图5(b)是本发明实施例提供的另一种迭代过程的示意图；
图6(a)是本发明实施例提供的又一种迭代图形的示意图；
图6(b)是本发明实施例提供的又一种迭代过程的示意图；
图7是本发明实施例提供的一种场效应晶体管制造方法的流程图；
图8(a)是本发明实施例提供的一种衬底层的示意图；
图8(b)是本发明实施例提供的一种形成沟道层的示意图；
图8(c)是本发明实施例提供的一种形成过孔的示意图；
图8(d)是本发明实施例提供的一种形成源极和漏极的示意图；
图8(e)是本发明实施例提供的一种形成电介质层的示意图；
图8(f)是本发明实施例提供的一种形成栅极的示意图。
附图说明：
1：衬底层；2：沟道层；21：第一区域；22：第二区域；3：源极；4：漏 极；5：电介质层；6：栅极。
通过上述附图，已示出本发明明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本发明构思的范围，而是通过参考特定实施例为本领域技术人员说明本发明的概念。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图2是本发明实施例提供的一种场效应晶体管的结构示意图。参见图2，该场效应晶体管包括衬底层1、沟道层2、源极3、漏极4、电介质层5和栅极6；
沟道层2覆盖于衬底层1的上表面，沟道层2包括第一区域21和第二区域22，第一区域21和第二区域22中均包括至少一个过孔，各个过孔用于贯穿沟道层2以暴露出衬底层1；
源极3位于沟道层2中第一区域21的上方，且源极3与衬底层1在第一区域21的至少一个过孔位置处直接相连；漏极4位于沟道层2中第二区域22的上方，且漏极4与衬底层1在第二区域22的至少一个过孔位置处直接相连；
电介质层5覆盖于沟道层2的上表面且位于源极3与漏极4之间；栅极6位于电介质层5的上方。
需要说明的是，沟道层采用石墨烯、二硫化钼(MoS2)、二硫化钨(WS2)、氮化硼(BN)、黑磷或其它二维材料中的一种，也即是，沟道层材料可以为石墨烯、MoS2、WS2、BN、黑磷或其它二维材料中的一种。其中，石墨烯可以包括单层石墨烯、双层石墨烯和多层石墨烯。
另外，由于源极和漏极一般由金属形成，且金属与沟道层材料边缘接触时的接触电阻会比与沟道层材料顶层接触时的电阻小，因此，在第一区域和第二区域中均设置至少一个过孔，会增加金属与沟道层材料之间的接触长度，从而增加金属与沟道层材料之间的边缘接触，减小金属与沟道层材料之间的接触电阻，也即是，减小源极、漏极与沟道层之间的接触电阻，从而来避免场效应晶体管在栅极长度减小的情况下失去原有的场效应效果。
其中，各个过孔的形状为分形图形，分形图形基于指定图形确定得到，且 分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，指定图形可以预先设置，如指定图形可以为正方形、长方形、三角形、五边形、六边形等。
需要说明的是，相关技术中由于各个过孔的形状为长方形，因此，为了增加接触长度，往往是增加多个长方形过孔，此时，过孔的总周长与过孔的总面积实际上是等比增加的，即，增加了几倍的周长，就同样会增加几倍的面积，从而导致在接触长度增加的同时，会大大减小第一区域和第二区域中沟道层材料所占面积，造成第一区域和第二区域本身的电阻大幅度增加。
而本发明实施例中，分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区域中沟道层材料所占面积的大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
其中，基于指定图形确定分形图形时，可以将指定图形根据指定迭代规则进行N次迭代后得到分形图形，指定迭代规则为将图形的至少一条边用对应的生成曲线进行替换。
需要说明的是，可以将指定图形根据指定迭代规则进行1次迭代后得到的图形称为迭代图形，即迭代图形为将指定图形的至少一条边用对应的生成曲线替换后得到。且迭代图形与指定图形之间的周长之比应不小于迭代图形与指定图形的面积之比，以保证后续得到的分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比。
另外，当迭代图形与指定图形的周长之比大于迭代图形与指定图形的面积之比时，此时最少需要迭代1次就能得到满足要求的分形图形，则此时N可以为不小于1的自然数；而当迭代图形与指定图形的周长之比等于迭代图形与指定图形的面积之比时，此时最少需要迭代2次才能得到满足要求的分形图形，则此时N可以为不小于2的自然数。
再者，某条边对应的生成曲线长度可以为该边长度的指定数值倍，且生成曲线可以为具有指定形状的曲线，指定数值和指定形状均可以预先设置，且指定数值可以根据指定形状来进行设置。
例如，指定形状为科克(Koch)曲线形状时，该生成曲线即为如图3(a)所示的Koch曲线，该Koch曲线是将一条边平分成三截线段后，去掉中间的线段并用两条与该线段等长的线段替代得到。则此时可知该Koch曲线长度为该边长度的
Figure PCTCN2016103695-appb-000001
倍，即指定数值为
Figure PCTCN2016103695-appb-000002
再例如，指定形状为闵可夫斯基(Minkowski)曲线形状，该生成曲线即为如图3(b)所示的Minkowski曲线，该Minkowski曲线是将一条边平分成四截线段后，将中间的两截线段去掉并分别用六条与该线段等长的线段替代得到。则此时可知该Minkowski曲线长度为该边长度的2倍，即指定数值为2。
需要说明的是，本发明实施例中将指定图形根据指定迭代规则进行N次迭代以得到分形图形，在该迭代过程中，实际上是得到了一种具有无限周长和有限面积的分形图形。从而可以在过孔面积有限的前提下，使得过孔周长得以大大增加，也即是在第一区域和第二区域中的沟道层材料所占面积有限减小的前提下，使得接触长度得以大大增加，从而可以保证在接触电阻减小的同时，不会产生其它额外的过大电阻。
例如，指定迭代规则为将图形的每条边用对应的生成曲线进行替换，指定图形为等边三角形，生成曲线为Koch曲线，该Koch曲线可以如图3(a)所示，则此时可以将指定图形根据指定迭代规则进行迭代。图4(a)为将指定图像根据指定迭代规则进行1次迭代后得到的迭代图形，可知，该迭代图形与指定图形的周长之比等于该迭代图形与指定图形的面积之比，因此，需要继续进行迭代以得到满足要求的分形图形，图4(b)为继续将指定图形根据指定规则进行2次迭代、3次迭代……后得到的图形，在该迭代过程中，图形周长以
Figure PCTCN2016103695-appb-000003
的比例在增加，图形面积以
Figure PCTCN2016103695-appb-000004
的比例在增加，可以看出，随着迭代次数的增加，图形周长一直在无限增加，而图形面积却增加的越来越少，趋于有限。
再例如，指定迭代规则为将图形的每条边用对应的生成曲线进行替换，指定图形为正方形，生成曲线为Minkowski曲线，该Minkowski曲线可以如图3 (b)所示，则此时可以将指定图形根据指定迭代规则进行迭代。图5(a)为将指定图像根据指定迭代规则进行1次迭代后得到的迭代图形，可知，该迭代图形与指定图形的周长之比大于该迭代图形与指定图形的面积之比，因此，此时可以直接将该迭代图形确定为分形图形，当然，也可以继续进行迭代以得到更为优质的分形图形，图5(b)为继续将指定图形根据指定规则进行2次迭代……后得到的图形，在该迭代过程中，图形周长以2N的比例在增加，图形面积没有增加，可以看出，随着迭代次数的增加，图形周长一直在无限增加，而图形面积却是一直保持不变的。
又例如，指定迭代规则为将图形的任意两条边用对应的生成曲线进行替换，指定图形为正方形，生成曲线为Minkowski曲线，该Minkowski曲线可以如图3(b)所示，则此时可以将指定图形根据指定迭代规则进行迭代。图6(a)为将指定图像根据指定迭代规则进行1次迭代后得到的迭代图形，可知，该迭代图形与指定图形的周长之比大于该迭代图形与指定图形的面积之比，因此，此时可以直接将该迭代图形确定为分形图形，当然，也可以继续进行迭代以得到更为优质的分形图形，图6(b)为继续将指定图形根据指定规则进行2次迭代、3次迭代……后得到的图形，可以看出，随着迭代次数的增加，图形周长一直在无限增加，而图形面积却是一直保持不变的。
需要说明的是，在实际应用中，指定迭代规则可以灵活进行设置，如1次迭代时可以将图形a条边用对应的生成曲线进行替换，2次迭代时可以将图形的b条边用对应的生成曲线进行替换，3次迭代时可以将图形的c条边用对应的生成曲线进行替换……，其中，a、b、c……可以相同，也可以不同，也即是，每次迭代中替换的边数可以相同，也可以不同。且每次迭代中在选择图形中所要进行替换的边时，可以随机选择，也可以根据实际需求按照一定的策略进行选择，本发明实施例对此不做具体限定。
另外，当指定迭代规则为将图形的每条边用对应的生成曲线进行替换时，如图4(a)、图4(b)、图5(a)、图5(b)所示，最后得到的分形图形将是一个比较规则的图形。而当指定迭代规则为将图形的部分边用对应的生成曲线进行替换时，如图6(a)、图6(b)所示，最后得到的分形图形将是一个不太规则的图形。
再者，由于沟道层材料中处于过孔拐角处的原子比较活跃，更易与金属成键，因此，在实际应用中，可以将生成曲线设计的较为复杂，以便基于生成曲 线得到的分形图形的拐角更多，从而使得沟道层材料中处于过孔拐角处的原子比重增大，沟道层材料中与金属成键的原子增多，从而能够进一步减小接触电阻。
在本发明实施例提供的场效应晶体管包括衬底层、沟道层、源极、漏极、电介质层和栅极，且沟道层的第一区域和第二区域中的各个过孔的形状均为分形图形，由于分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区域中沟道层材料所占面积大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
图7是本发明实施例提供的一种场效应晶体管制造方法的流程图，该制造方法包括如下步骤：
步骤701：提供一衬底层。
如图8(a)所示，提供一衬底层1，在实际应用中，该衬底层材料可以是硅、石英、绝缘衬底上的硅(Silicon-On-Insulator，SOI)、碳化硅(SiC)等材料。
步骤702：在衬底层之上形成沟道层。
如图8(b)所示，可以将沟道层材料转移到衬底层1之上，以形成沟道层2；或者可以通过化学气相沉积(Chemical Vapor Deposition，CVD)等工艺来在衬底层1之上形成沟道层2，本发明实施例对此不作具体限定。
需要说明的是，沟道层采用石墨烯、MoS2、WS2、BN、黑磷或其它二维材料中的一种，也即是，沟道层材料可以为石墨烯、MoS2、WS2、BN、黑磷或其它二维材料中的一种。其中，石墨烯可以包括单层石墨烯、双层石墨烯和多层石墨烯。
步骤703：在沟道层中的第一区域和第二区域中均形成至少一个过孔。
需要说明的是，各个过孔用于贯穿沟道层以暴露出衬底层，且各个过孔的形状为分形图形，分形图形基于指定图形确定得到，且分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比。
另外，基于指定图形确定分形图形的操作已在上述图2提供的实施例中进行说明，本发明实施例在此不再赘述。
如图8(c)所示，在沟道层2中的第一区域21和第二区域22中均形成至少一个过孔时，可以先在沟道层2的两端(即第一区域21和第二区域22)定义过孔的形状和位置，定义好过孔的形状和位置后，将第一区域21和第二区域22中除该过孔位置外的区域通过保护胶进行保护，进而对第一区域21和第二区域22进行刻蚀，得到第一区域21和第二区域22中的各个过孔。
需要说明的是，定义过孔的形状和位置时，可以通过光刻工艺来定义，如可以通过电子束曝光、光学曝光等光刻工艺来定义。
另外，保护胶可以为抗刻蚀的胶、聚甲基丙烯酸甲酯(Poly(methyl methacrylate)，PMMA)等。
再者，对第一区域和第二区域进行刻蚀时，可以通过反应离子刻蚀(Reactive-Ion Etching，RIE)、氧等离子刻蚀等工艺进行刻蚀。
步骤704：在沟道层中的第一区域之上形成源极，在沟道层中的第二区域之上形成漏极。
需要说明的是，源极与衬底层在第一区域的至少一个过孔位置处直接相连，漏极与衬底层在第二区域的至少一个过孔位置处直接相连。
如图8(d)所示，在沟道层2两端(即第一区域21和第二区域22)分别定义源极3和漏极4的位置，漏极3与漏极4相隔一预设距离，定义好源极3和漏极4之后，沉积用于形成源极3的金属得到源极3，沉积用于形成漏极4的金属得到漏极4。
需要说明的是，定义源极和漏极位置时，可以通过光刻工艺来定义，如可以通过电子束曝光、光学曝光等光刻工艺来定义。
另外，形成源极或漏极的金属可以为金属单质、不同金属的层状堆叠、碳化物金属等，其中，金属单质可以为铂(Pt)、铜(Cu)、镍(Ni)、金(Au)等，不同金属的层状堆叠可以为钛/金(Ti/Au)、铬/金(Cr/Au)等，碳化物金属可以为碳化钼(Mo2C)、碳化钽(TaC)、碳化钨(WC)等。
再者，沉积用于形成源极或漏极的金属时可以通过电子束蒸发等工艺来进行沉积。
步骤705：在沟道层之上且在源极与漏极之间形成电介质层。
如图8(e)所示，可以在沟道层2之上且在源极3与漏极4之间沉积高k 电介质材料，以得到电介质层5，其中，k为介电常数。
需要说明的是，沉积高k电介质材料时，可以通过原子层沉积(Atom Layer Deposition，ALD)等工艺来进行沉积。
另外，高k电介质材料可以为二氧化铪(HfO2)、三氧化二铝(Al2O3)、氧化钇(Y2O3)等。
步骤706：在电介质层之上形成栅极。
如图8(f)所示，在电介质层5上定义栅极6的位置，定义好栅极6的位置后，沉积用于形成栅极6的金属得到栅极6。
需要说明的是，定义栅极位置时，可以通过光刻工艺来定义，如可以通过电子束曝光、光学曝光等光刻工艺来定义。
另外，沉积用于形成栅极的金属时可以通过电子束蒸发等工艺来进行沉积。
再者，形成栅极的金属可以为Au、钯(Pd)、钨(W)或者其它金属等。
本发明实施例提供的场效应晶体管制造方法，在场效应晶体管的沟道层中的第一区域和第二区域中均形成至少一个过孔，且将各个过孔的形状设置为分形图形，由于分形图形与指定图形的周长之比大于分形图形与指定图形的面积之比，也即是，在基于指定图形确定分形图形的过程中，图形周长的增加比例大于图形面积的增加比例，从而可以在增加过孔周长的同时，有效控制过孔面积的增加，从而避免第一区域和第二区域中沟道层材料所占面积大幅度减小，避免第一区域和第二区域本身的电阻大幅度增加，使得在有效减小接触电阻的同时，不会产生其它额外的过大电阻，从而可以保证场效应晶体管的场效应效果。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

  1. 一种场效应晶体管，其特征在于，所述场效应晶体管包括衬底层、沟道层、源极、漏极、电介质层和栅极；
    所述沟道层覆盖于所述衬底层的上表面，所述沟道层包括第一区域和第二区域，所述第一区域和所述第二区域中均包括至少一个过孔，各个过孔用于贯穿所述沟道层以暴露出所述衬底层，且所述各个过孔的形状为分形图形，所述分形图形基于指定图形确定得到，且所述分形图形与所述指定图形的周长之比大于所述分形图形与所述指定图形的面积之比；
    所述源极位于所述沟道层中所述第一区域的上方，且所述源极与所述衬底层在所述第一区域的所述至少一个过孔位置处直接相连；所述漏极位于所述沟道层中所述第二区域的上方，且所述漏极与所述衬底层在所述第二区域的所述至少一个过孔位置处直接相连；
    所述电介质层覆盖于所述沟道层的上表面且位于所述源极与所述漏极之间；所述栅极位于所述电介质层的上方。
  2. 如权利要求1所述的场效应晶体管，其特征在于，所述分形图形为将所述指定图形根据指定迭代规则进行N次迭代后得到，所述指定迭代规则为将图形的至少一条边用对应的生成曲线进行替换，所述生成曲线为具有指定形状的曲线；
    其中，迭代图形与所述指定图形之间的周长之比不小于所述迭代图形与所述指定图形的面积之比，所述迭代图形为将所述指定图形根据所述指定迭代规则进行1次迭代后得到；且当所述迭代图形与所述指定图形的周长之比大于所述迭代图形与所述指定图形的面积之比时，所述N为不小于1的自然数；当所述迭代图形与所述指定图形的周长之比等于所述迭代图形与所述指定图形的面积之比时，所述N为不小于2的自然数。
  3. 如权利要求1或2所述的场效应晶体管，其特征在于，所述沟道层采用石墨烯、二硫化钼、二硫化钨、氮化硼、黑磷或其它二维材料中的一种。
  4. 一种场效应晶体管制造方法，其特征在于，所述制造方法包括：
    提供一衬底层；
    在所述衬底层之上形成沟道层；
    在所述沟道层中的第一区域和第二区域中均形成至少一个过孔，各个过孔用于贯穿所述沟道层以暴露出所述衬底层，且所述各个过孔的形状为分形图形，所述分形图形基于指定图形确定得到，且所述分形图形与所述指定图形的周长之比大于所述分形图形与所述指定图形的面积之比；
    在所述沟道层中的所述第一区域之上形成源极，所述源极与所述衬底层在所述第一区域的所述至少一个过孔位置处直接相连；
    在所述沟道层中的所述第二区域之上形成漏极，所述漏极与所述衬底层在所述第二区域的所述至少一个过孔位置处直接相连；
    在所述沟道层之上且在所述源极与所述漏极之间形成电介质层；
    在所述电介质层之上形成栅极。
  5. 如权利要求4所述的制造方法，其特征在于，所述分形图形为将所述指定图形根据指定迭代规则进行N次迭代后得到，所述指定迭代规则为将图形的至少一条边用对应的生成曲线进行替换，所述生成曲线为具有指定形状的曲线；
    其中，迭代图形与所述指定图形之间的周长之比不小于所述迭代图形与所述指定图形的面积之比，所述迭代图形为将所述指定图形根据所述指定迭代规则进行1次迭代后得到；且当所述迭代图形与所述指定图形的周长之比大于所述迭代图形与所述指定图形的面积之比时，所述N为不小于1的自然数；当所述迭代图形与所述指定图形的周长之比等于所述迭代图形与所述指定图形的面积之比时，所述N为不小于2的自然数。
  6. 如权利要求4或5所述的制造方法，其特征在于，所述沟道层采用石墨烯、二硫化钼、二硫化钨、氮化硼、黑磷或其它二维材料中的一种。
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