JP6235426B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6235426B2 JP6235426B2 JP2014141892A JP2014141892A JP6235426B2 JP 6235426 B2 JP6235426 B2 JP 6235426B2 JP 2014141892 A JP2014141892 A JP 2014141892A JP 2014141892 A JP2014141892 A JP 2014141892A JP 6235426 B2 JP6235426 B2 JP 6235426B2
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- oxide semiconductor
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本実施形態の半導体装置は、チャネル領域と、チャネル領域を挟んで設けられチャネル領域よりも膜厚が薄くインジウム(In)濃度の低いソース領域およびドレイン領域とを有し、インジウム(In)、ガリウム(Ga)および亜鉛(Zn)を含有する酸化物半導体層と、チャネル領域上に設けられるゲート絶縁膜と、ゲート絶縁膜上に設けられるゲート電極と、ソース領域下に設けられ、ソース領域に電気的に接続される第1の導電層と、ドレイン領域下に設けられ、ドレイン領域に電気的に接続される第2の導電層と、を備える。
本実施形態の半導体装置は、ゲート電極の両側に、ゲート側壁が設けられること以外は、第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については記述を省略する。
本実施形態の半導体装置は、半導体層と、半導体層上に設けられる第1のゲート絶縁膜と、第1のゲート絶縁膜上に設けられる第1のゲート電極と、を有する第1のトランジスタと、チャネル領域と、チャネル領域を挟んで設けられチャネル領域よりも膜厚が薄くインジウム(In)濃度の低いソース領域およびドレイン領域とを有し、インジウム(In)、ガリウム(Ga)および亜鉛(Zn)を含有する酸化物半導体層と、チャネル領域上に設けられる第2のゲート絶縁膜と、第2のゲート絶縁膜上に設けられる第2のゲート電極と、を有し、第1のトランジスタとの間に層間絶縁膜を挟んで設けられる第2のトランジスタと、ソース領域下に設けられ、ソース領域に電気的に接続される第1の導電層と、ドレイン領域下に設けられ、ドレイン領域に電気的に接続される第2の導電層と、を備える。
10a チャネル領域
10b ソース領域
10c ドレイン領域
12 ゲート絶縁膜(第2のゲート絶縁膜)
14 ゲート電極(第2のゲート電極)
16 第1の導電層
18 第2の導電層
20 層間絶縁膜
36 ゲート側壁
50 半導体基板(半導体層)
52 ゲート絶縁膜(第1のゲート絶縁膜)
54 ゲート電極(第1のゲート電極)
100 半導体装置
110 第1のトランジスタ
120 第2のトランジスタ
200 半導体装置
Claims (7)
- チャネル領域と、前記チャネル領域を挟んで設けられ前記チャネル領域よりも膜厚が薄くインジウム(In)濃度の低いソース領域およびドレイン領域とを有し、インジウム(In)、ガリウム(Ga)および亜鉛(Zn)を含有する酸化物半導体層と、
前記チャネル領域上に設けられるゲート絶縁膜と、
前記ゲート絶縁膜上に設けられるゲート電極と、
前記ソース領域下に設けられ、前記ソース領域に電気的に接続される第1の導電層と、
前記ドレイン領域下に設けられ、前記ドレイン領域に電気的に接続される第2の導電層と、
を備える半導体装置。 - 前記チャネル領域の膜厚が10nm以上であり、前記ソース領域および前記ドレイン領域の膜厚が5nm以下である請求項1記載の半導体装置。
- 前記酸化物半導体層に、ハフニウム(Hf)、スズ(Sn)、アルミニウム(Al)、ジルコニウム(Zr)、リチウム(Li)、スカンジウム(Sc)、窒素(N)の群から選ばれる少なくとも一つの元素が含有される請求項1または請求項2記載の半導体装置。
- 前記ソース領域および前記ドレイン領域のインジウム濃度が、前記チャネル領域のインジウム濃度の80%以下である請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記ゲート電極の両側に、ゲート側壁が設けられる請求項1ないし請求項4いずれか一項記載の半導体装置。
- 第1の導電層および第2の導電層を形成し、
前記第1の導電層および前記第2の導電層上に、インジウム(In)、ガリウム(Ga)および亜鉛(Zn)を含有する酸化物半導体層を形成し、
前記酸化物半導体層の一部が前記第1の導電層および前記第2の導電層上に残存するように前記酸化物半導体層をパターニングし、
前記酸化物半導体層上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極をマスクに、前記ゲート電極両側の前記酸化物半導体層の一部をエッチングし、
プラズマ処理または熱処理により前記ゲート電極両側の前記酸化物半導体層のIn濃度を低下させる半導体装置の製造方法。 - 前記酸化物半導体層の膜厚が10nm以上であり、前記ゲート電極両側の前記酸化物半導体層のエッチング後の膜厚が5nm以下である請求項6記載の半導体装置の製造方法。
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