WO2018058522A1 - 薄膜晶体管制造方法及阵列基板 - Google Patents

薄膜晶体管制造方法及阵列基板 Download PDF

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WO2018058522A1
WO2018058522A1 PCT/CN2016/101072 CN2016101072W WO2018058522A1 WO 2018058522 A1 WO2018058522 A1 WO 2018058522A1 CN 2016101072 W CN2016101072 W CN 2016101072W WO 2018058522 A1 WO2018058522 A1 WO 2018058522A1
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oxide semiconductor
semiconductor layer
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叶江波
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a method for fabricating a thin film transistor and an array substrate.
  • TFT thin-film transistors
  • OLED organic light-emitting diode
  • Embodiments of the present invention provide a method of fabricating a thin film transistor and an array substrate for solving the technical problem of increasing the height difference between the channel region and the oxide semiconductor layer under the source and drain electrodes.
  • the invention provides a method for manufacturing a thin film transistor, the method comprising:
  • Forming a photoresist layer on the oxide semiconductor layer forming the photoresist layer into a first photoresist layer by a halftone mask or a gray masking process, the first photoresist layer having a first thickness a first region and a second region having a second thickness, wherein the second region is located on both sides of the first region;
  • a metal layer is formed on the oxide semiconductor layer and the gate insulating layer and patterned to form a source drain and a channel region.
  • the step of forming a first photoresist layer on the photoresist layer by using a halftone mask comprises: providing a mask, the mask comprises a light shielding area, a semi-transparent area on both sides of the light shielding area, and a semi-transparent area. Full connection of the district Translucent area
  • the second region, the portion opposite to the light shielding region, is the first region.
  • the thickness of the second region is half of the thickness of the first region. It can be understood that the thickness of the second region is half of the thickness of the first region or the film thickness ratio can be made according to actual process requirements.
  • the step of removing the oxide semiconductor layer exposing the first photoresist layer is removed by wet etching.
  • the step of patterning the exposed partial oxide semiconductor layer is to reduce the thickness of the oxide semiconductor layer exposed on both sides of the first region of the first photoresist layer by wet etching.
  • the step of forming a metal layer on the oxide semiconductor layer and the gate insulating layer and patterning the source drain and the channel region includes:
  • the second photoresist layer is removed.
  • the thickness of the second portion is one-half of the first portion.
  • oxide semiconductor layer is projected onto the gate.
  • the gate insulating layer includes any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • the present application provides an array substrate including a substrate, a gate on which the surface of the substrate is stacked, a gate insulating layer covering the gate, and an oxide semiconductor stacked on the gate insulating layer. a layer formed on a source and a drain of the oxide semiconductor layer, wherein the source and the drain form a channel region, wherein a surface height and a channel of the oxide semiconductor layer in contact with the source and the drain The surface of the oxide semiconductor layer in the region has the same height.
  • the thin film transistor of the present invention forms a first photoresist layer to define an oxide half by a halftone mask
  • the conductor layer pattern is etched to ensure that the height difference of the oxide semiconductor layer in which the channel region is connected to the source and drain is the same or the error generated is within the allowable range, and the difference in the step generated at the channel region is reduced, thereby avoiding The effect of thin film transistor electrical and reliability.
  • FIG. 1 is a schematic diagram of a step of manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 to 9 are schematic cross-sectional views showing respective manufacturing flows of the method of manufacturing the thin film transistor shown in Fig. 1.
  • the invention provides a thin film transistor, a TFT array substrate and a flexible display screen, which can be used in a liquid crystal display or an organic display.
  • the flexible display screen according to the embodiment of the present invention is used for, but not limited to, a mobile phone, a tablet computer, a palmtop computer, a personal digital assistant (PDA), or an e-reader.
  • PDA personal digital assistant
  • the invention provides a method for manufacturing a thin film transistor, the method comprising:
  • Forming a photoresist layer on the oxide semiconductor layer forming the photoresist layer into a first photoresist layer by a halftone mask or a gray masking process, the first photoresist layer having a first thickness a first region and a second region having a second thickness, wherein the second region is located on both sides of the first region;
  • a metal layer is formed on the oxide semiconductor layer and the gate insulating layer and patterned to form a source drain and a channel region.
  • step S1 the gate electrode 11, the gate insulating layer 12, and the oxide semiconductor layer 13 are sequentially formed on the substrate 10.
  • the gate insulating layer 123 covers the surfaces of the gate 11 and the substrate 10.
  • the oxide semiconductor layer 13 is laminated on the gate insulating layer 12.
  • the step specifically includes, S11, providing a substrate 10;
  • the material of the first metal layer is selected from the group consisting of copper, tungsten, chromium, aluminum, and One of its combinations
  • the oxide semiconductor layer 13 is one or more of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO), or zinc tin oxide (ZnSnO).
  • the gate insulating layer 13 is formed using one or a mixture of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • step S2 forming a photoresist layer material layer 130 on the oxide semiconductor layer 13, and performing a halftone mask on the photoresist material layer to form the first photoresist layer 14.
  • the first photoresist layer 14 includes a first region 141 and a second region 142 located at two sides of the first region 141, and the thickness of the first region 141 is greater than the thickness of the second region 142. Specifically, the thickness of the second region 142 is half of the thickness of the first region 141.
  • the step specifically includes, in step S21, a mask 143 is provided, which is a (Halftone mask), and the mask 143 includes a light shielding area 1431, a semi-transparent area 1432 located at two sides of the light shielding area 1431, and The full transmissive area 1433 to which the semi-transparent area 1432 is connected.
  • a mask 143 is provided, which is a (Halftone mask)
  • the mask 143 includes a light shielding area 1431, a semi-transparent area 1432 located at two sides of the light shielding area 1431, and The full transmissive area 1433 to which the semi-transparent area 1432 is connected.
  • step S22 the photoresist material layer 130 is patterned by irradiating the photomask 143 with UV light, so that the photoresist material layer opposite to the full transmissive region 1433 is partially removed, and semi-transparent.
  • the portion of the region 1432 opposite to the photoresist layer is reduced in thickness to form the second region 142, and the portion opposite to the light-shielding region 1431 is the first region 141.
  • Forming the first photoresist layer defining the oxide semiconductor layer pattern by the halftone mask and performing etching it is possible to ensure that the height difference of the oxide semiconductor layer in which the channel region is connected to the source and drain is the same or the error generated is within the allowable range, and is lowered. Due to the difference in the step size generated at the channel region, the influence on the electrical and reliability of the thin film transistor is avoided.
  • step S3 removing the oxide semiconductor layer exposing the first photoresist layer 14; referring to the oxide semiconductor layers on both sides of the first photoresist layer 14. This step is mainly removed by wet etching.
  • Step S4 ashing the first photoresist layer 14 to remove the two second regions 142 and expose a portion of the oxide semiconductor layer on both sides of the first region 141.
  • Ashing here mainly means removing the second region 142 by dry etching. A portion of the oxide semiconductor layer at this time is projected onto the gate electrode 11.
  • step S5 patterning the exposed partial oxide semiconductor layer, so that the oxide semiconductor layer 13 forms the first portion 131 covered by the first region 141 and the second portion 132 located on both sides of the first portion 131; Wherein, the thickness of the first portion 131 is greater than the thickness of the second portion 132.
  • the thickness of the oxide semiconductor layer on both sides of the first region 141 exposing the first photoresist layer 14 is reduced by wet etching, thereby forming the first portion 131 and the second portion having a thickness smaller than the first portion 131. 132.
  • the thickness of the second portion 132 is reduced in this step to meet the thin film transistor design requirements, and the thickness of the first portion 131 is large in order to avoid excessive removal of the first portion 131 and prevent the first portion 131 and the second in the step of forming the rear channel.
  • Portion 132 produces a step height difference.
  • the thickness of the second portion 132 is one-half of the first portion 131.
  • Step S6 removing the first region 131 of the first photoresist layer 13.
  • Step S7 The metal layer 20 is formed on the oxide semiconductor layer 14 and the gate insulating layer 12 and patterned to form the source electrode 16, the drain electrode 17, and the channel region 18.
  • the thickness of the first portion 131 of the oxide semiconductor layer 13 is equal to the thickness of the second portion 132 of the oxide semiconductor layer 13.
  • the step specifically includes, in step S71, forming a second photoresist layer 21 on the metal layer 20 to pattern the source 16 and the drain 17.
  • the second photoresist layer 21 includes an opening region 211 that is projected onto the first portion 131 of the oxide semiconductor layer 13.
  • Step S72 forming the source electrode 16 and the drain electrode 17 according to the metal layer 20 exposed by the pattern etching of the second photoresist layer 21, and etching the oxide semiconductor layer 13 opposite to the opening region 211.
  • the first portion 131 has a thickness equal to the thickness of the second portion 132, and the source electrode 16 and the drain electrode 17 respectively cover the two second portions 132 of the oxide semiconductor layer 13.
  • step S73 the second photoresist 20 is removed.
  • the present invention provides an array substrate including a substrate 10 and a surface on which the substrate is stacked. a gate electrode 11, a gate insulating layer 12 covering the gate electrode 11, an oxide semiconductor layer 13 stacked on the gate insulating layer 12, and a source 16 and a drain electrode 17 formed on the oxide semiconductor layer 13.
  • a channel region 18 is formed between the source 16 and the drain 17, wherein a surface height of the oxide semiconductor layer 13 in contact with the source 16 and the drain 17 and an oxide semiconductor layer in the channel region 18 The surface height of 13 is the same.

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  • Thin Film Transistor (AREA)

Abstract

提供了一种薄膜晶体管及其制造方法。方法包括：在基板上依次形成栅极、栅极绝缘层及氧化物半导体层；在氧化物半导体层上形成光阻材料层，通过半色调掩膜或者灰色调掩工艺使光阻材料层形成第一光阻层，第一光阻层具有第一厚度的第一区域和具有第二厚度的第二区域，其中第二区域位于第一区域两侧；去除第二区域，露出位于第二区域下方的氧化物半导体层；去除第二区域下方的部分厚度的氧化物半导体层；其中氧化物半导体层的第一部分的厚度等于氧化物半导体层的第二部分的厚度，在氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域。

Description

薄膜晶体管制造方法及阵列基板 技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种薄膜晶体管制造方法及阵列基板。
背景技术
目前薄膜晶体管(Thin-film transistors，TFT)阵列基板被广泛应用于不同类型的显示装置中，如柔性显示屏、液晶显示屏或OLED显示屏。薄膜晶体管中沟道区域与源漏极下方的氧化物半导体层的高度差对阵列基板的电性有很大的影响，现有技术中采用的光罩形成沟道区域容易导致沟道区域与源漏极下方的氧化物半导体层的高度差增大。
发明内容
本发明实施例提供一种薄膜晶体管制造方法及阵列基板，用以解决沟道区域与源漏极下方的氧化物半导体层的高度差增大的技术问题。
本发明提供一种薄膜晶体管制造方法，所述方法包括：
在基板上依次形成栅极、栅极绝缘层及氧化物半导体层；
在所述氧化物半导体层上形成光阻材料层，通过半色调掩膜或者灰色调掩工艺使所述光阻材料层形成第一光阻层，所述第一光阻层具有第一厚度的第一区域和具有第二厚度的第二区域，其中第二区域位于第一区域两侧；
去除所述第二区域，露出位于第二区域下方的氧化物半导体层；
去除第二区域下方的部分厚度的氧化物半导体层；其中所述氧化物半导体层的第一部分的厚度等于所述氧化物半导体层的第二部分的厚度
在所述氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域。
其中，所述对所述光阻材料层进行半色调光罩形成第一光阻层的步骤包括，提供一光罩，光罩包括遮光区、位于遮光区两侧的半透区及与半透区连接的全 透区；
通过光照射所述光罩对所述光阻材料层进行图案化，使与全透区相对的光阻材料层部分被去除，与半透区相对的光阻材料层部分厚度减小形成所述第二区域，与遮光区相对的部分为所述第一区域。
其中所述第二区域的厚度为所述第一区域厚度的一半。，可以理解，第二区域的厚度为所述第一区域厚度的一半或可依据实际工艺需求进行膜厚比率。
其中所述去除露出所述第一光阻层的氧化物半导体层步骤通过湿蚀刻的方式去除。
其中所述图案化露出的部分氧化物半导体层的步骤是通过湿蚀刻的方式减小露出所述第一光阻层的第一区域两侧氧化物半导体层的厚度。
其中所述在所述氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域的步骤包括：
在所述金属层上形成第二光阻层以对源漏极构图，其中第二光阻层包括正投影于所述氧化物半导体层第一部分的开口区域；
根据所述第二光阻层的图形蚀刻露出的所述金属层形成所述源漏极，同时蚀刻与所述开口区域相对的所述氧化物半导体层第一部分，使所述第一部分的厚度等于第二部分的厚度，所述源漏极分别覆盖所述氧化物半导体层的两个第二部分；
去除第二光阻层。
其中所述第二部分的厚度为第一部分的二分之一。
其中所述氧化物半导体层正投影于所述栅极。
其中，所述栅极绝缘层包括氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的任意一种或多种。
本申请提供一种阵列基板，所述阵列基板包括基板、叠设所述基板表面的栅极、覆盖所述栅极的栅极绝缘层、叠设于所述栅极绝缘层上的氧化物半导体层、形成于氧化物半导体层的源极及漏极，所述源极及漏极之间构成沟道区域，其中，所述氧化物半导体层与源极及漏极接触的表面高度与沟道区域内的氧化物半导体层的表面高度相同。
本发明所述的薄膜晶体管通过半色调光罩形成第一光阻层定义氧化物半 导体层图案并进行蚀刻，可以确保沟道区域与源漏极连接的氧化物半导体层的高度差相同或者产生的误差在允许范围内，降低因沟道区域处产生的段差的差异，从而避免对薄膜晶体管电性及可靠度的影响。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的薄膜晶体管制步骤图。
图2至图9是图1所示的薄膜晶体管制造方法的各个制造流程的截面示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本发明提供了薄膜晶体管、TFT阵列基板及柔性显示屏，所述薄膜晶体管可以用于液晶显示屏或者有机显示屏中。本发明实施例涉及的柔性显示屏用于但不限于手机、平板电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)或电子阅读器等，本发明实施例对此不作具体限定。
本发明提供一种薄膜晶体管制造方法，所述方法包括：
在基板上依次形成栅极、栅极绝缘层及氧化物半导体层；
在所述氧化物半导体层上形成光阻材料层，通过半色调掩膜或者灰色调掩工艺使所述光阻材料层形成第一光阻层，所述第一光阻层具有第一厚度的第一区域和具有第二厚度的第二区域，其中第二区域位于第一区域两侧；
去除所述第二区域，露出位于第二区域下方的氧化物半导体层；
蚀刻去除第二区域下方的部分厚度的氧化物半导体层；其中所述氧化物半导体层的第一部分的厚度等于所述氧化物半导体层的第二部分的厚度
在所述氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域。
具体实施例详细步骤结合参阅图1及图2-9进行说明：
请参阅图2，步骤S1：在基板10上依次形成栅极11、栅极绝缘层12及氧化物半导体层13。所述栅极绝缘层123覆盖所述栅极11及基板10的表面。所述氧化物半导体层13层叠于栅极绝缘层12上。
本步骤具体包括，S11，在提供一基板10；
S12，在所述基板10的一个表面形成第一金属层，通过图案化工艺加工第一金属层形成所述栅极11；所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一
S13，在所述栅极11上以及露出的基板表面上形成栅极绝缘层12及所述氧化物半导体层13。所述氧化物半导体层13为氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)中的一种或多种。所述栅极绝缘层13采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成或者多种混合形成。
参阅图3，步骤S2：在所述氧化物半导体层13上形成光阻层材料层130，并对所述光阻材料层进行半色调光罩形成第一光阻层14。其中，第一光阻层14包括第一区域141及位于所述第一区域141两侧的第二区域142，并且所述第一区域141的厚度大于所述第二区域142的厚度。具体的，所述第二区域142的厚度为所述第一区域141厚度的一半。
参阅图4，本步骤具体包括，步骤S21，提供一光罩143，其为(Halftone mask半色调光罩)，光罩143包括遮光区1431、位于遮光区1431两侧的半透区1432及与半透区1432连接的全透区1433。
参阅图5及图6，步骤S22，通过UV光照射所述光罩143对所述光阻材料层130进行图案化，使与全透区1433相对的光阻材料层部分被去除，与半透区1432相对的光阻材料层部分厚度减小形成所述第二区域142，与遮光区1431相对的部分为所述第一区域141。
通过半色调光罩形成第一光阻层定义氧化物半导体层图案并进行蚀刻，可以确保沟道区域与源漏极连接的氧化物半导体层的高度差相同或者产生的误差在允许范围内，降低因沟道区域处产生的段差的差异，从而避免对薄膜晶体管电性及可靠度的影响。
参阅图7，步骤S3：去除露出所述第一光阻层14的氧化物半导体层；是指第一光阻层14两侧的氧化物半导体层。本步骤主要通过湿蚀刻的方式去除。
步骤S4：对所述第一光阻层14进行灰化，去除所述两个第二区域142，并露出位于第一区域141两侧的部分氧化物半导体层。此处的灰化主要是指通过干法蚀刻方式去除第二区域142。此时的部分氧化物半导体层正投影于所述栅极11。
参阅图8及图9，步骤S5：图案化露出的部分氧化物半导体层，使氧化物半导体层13形成被第一区域141覆盖的第一部分131及位于第一部分131两侧的第二部分132；其中，第一部分131的厚度大于第二部分132的厚度。本步骤中，是通过湿蚀刻的方式减小露出所述第一光阻层14的第一区域141两侧氧化物半导体层的厚度，进而形成第一部分131及厚度小于第一部分131的第二部分132。此步骤中将第二部分132厚度减小以满足薄膜晶体管设计需求，而第一部分131的厚度较大为了避免后面沟道形成的步骤中过多的去除第一部分131并防止第一部分131与第二部分132产生阶梯高度差。本实施例中，所述第二部分132的厚度为第一部分131的二分之一。
步骤S6：去除第一光阻层13的第一区域131。
步骤S7：在所述氧化物半导体层14及栅极绝缘层12上形成金属层20并进行图案化，形成源极16、漏极17及沟道区域18。其中所述氧化物半导体层13的第一部分131的厚度等于所述氧化物半导体层13的第二部分132的厚度。
本步骤具体包括，步骤S71，在所述金属层20上形成第二光阻层21以对源极16、漏极17构图。其中第二光阻层21包括正投影于所述氧化物半导体层13第一部分131的开口区域211。
步骤S72，根据所述第二光阻层21的图形蚀刻露出的所述金属层20形成所述源极16、漏极17，同时蚀刻与所述开口区域211相对的所述氧化物半导体层13的第一部分131，使所述第一部分131的厚度等于第二部分132的厚度，所述源极16、漏极17分别覆盖所述氧化物半导体层13的两个第二部分132。
步骤S73，去除第二光阻20。
如图9，本发明提供一种阵列基板，其包括基板10、叠设所述基板表面的 栅极11、覆盖所述栅极11的栅极绝缘层12、叠设于所述栅极绝缘层12上的氧化物半导体层13、形成于氧化物半导体层13的源极16及漏极17，所述源极16及漏极17之间构成沟道区域18，其中，所述氧化物半导体层13与源极16及漏极17接触的表面高度与沟道区域18内的氧化物半导体层13的表面高度相同。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (13)

  1. 一种薄膜晶体管制造方法，其特征在于，所述方法包括：
    在基板上依次形成栅极、栅极绝缘层及氧化物半导体层；
    在所述氧化物半导体层上形成光阻材料层，通过半色调掩膜或者灰色调掩工艺使所述光阻材料层形成第一光阻层，所述第一光阻层具有第一厚度的第一区域和具有第二厚度的第二区域，其中第二区域位于第一区域两侧；
    去除所述第二区域，露出位于第二区域下方的氧化物半导体层；
    去除第二区域下方的部分厚度的氧化物半导体层；
    在所述氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域。
  2. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，通过半色调掩膜板或者灰色调掩板灰化去除所述第二区域。
  3. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，在去除第二区域步骤之前还包括去除露出所述第一光阻层的氧化物半导体层的步骤。
  4. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，步骤去除第二区域下方的部分厚度的氧化物半导体层后，所述氧化物半导体层包括第一部分及第二部分，所述第一部分的厚度等于所述氧化物半导体层的第二部分的厚度。
  5. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述对所述光阻材料层进行半色调光罩形成第一光阻层的步骤包括，提供一光罩，光罩包括遮光区、位于遮光区两侧的半透区及与半透区连接的全透区；
    通过光照射所述光罩对所述光阻材料层进行图案化，使与全透区相对的光阻材料层部分被去除，与半透区相对的光阻材料层部分厚度减小形成所述第二区域，与遮光区相对的部分为所述第一区域。
  6. 如权利要求3所述的薄膜晶体管制造方法，其特征在于，所述第二区域的厚度为所述第一区域厚度的一半。
  7. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述去除露出所述第一光阻层的氧化物半导体层步骤通过湿蚀刻的方式去除。
  8. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述图案化露出的部分氧化物半导体层的步骤是通过湿蚀刻的方式减小露出所述第一光阻层的第一区域两侧氧化物半导体层的厚度。
  9. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述在所述氧化物半导体层及栅极绝缘层上形成金属层并进行图案化，形成源漏极及沟道区域的步骤包括：
    在所述金属层上形成第二光阻层以对源漏极构图，其中第二光阻层包括正投影于所述氧化物半导体层第一部分的开口区域；
    根据所述第二光阻层的图形蚀刻露出的所述金属层形成所述源漏极，同时蚀刻与所述开口区域相对的所述氧化物半导体层第一部分，使所述第一部分的厚度等于第二部分的厚度，所述源漏极分别覆盖所述氧化物半导体层的两个第二部分；
    去除第二光阻层。
  10. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述第二部分的厚度为第一部分的二分之一。
  11. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述氧化物半导体层正投影于所述栅极。
  12. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述栅极绝缘层包括氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的任意一种或多种。
  13. 一种TFT阵列基板，其特征在于，所述阵列基板包括基板、叠设所述基板表面的栅极、覆盖所述栅极的栅极绝缘层、叠设于所述栅极绝缘层上的氧化物半导体层、形成于氧化物半导体层的源极及漏极，所述源极及漏极之间构成沟道区域，其中，所述氧化物半导体层与源极及漏极接触的表面高度与沟道区域内的氧化物半导体层的表面高度相同。
PCT/CN2016/101072 2016-09-30 2016-09-30 薄膜晶体管制造方法及阵列基板 Ceased WO2018058522A1 (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244186A (zh) * 2018-11-29 2020-06-05 中华映管股份有限公司 薄膜晶体管及其制造方法
CN114530413A (zh) * 2022-02-21 2022-05-24 昆山龙腾光电股份有限公司 阵列基板及其制作方法
CN115084277A (zh) * 2022-06-29 2022-09-20 昆山龙腾光电股份有限公司 金属氧化物薄膜晶体管及其制作方法、阵列基板

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111268641B (zh) * 2020-02-17 2023-07-14 绍兴中芯集成电路制造股份有限公司 晶圆键合方法以及微执行器的制作方法
US12068376B2 (en) * 2021-08-05 2024-08-20 Taiwan Semiconductor Manufacturing Company Limited Metal field plates

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
CN102254860A (zh) * 2011-07-19 2011-11-23 友达光电股份有限公司 一种制造薄膜晶体管的方法
US8586406B1 (en) * 2012-10-18 2013-11-19 Chunghwa Picture Tubes, Ltd. Method for forming an oxide thin film transistor
CN105226015A (zh) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
CN102254860A (zh) * 2011-07-19 2011-11-23 友达光电股份有限公司 一种制造薄膜晶体管的方法
US8586406B1 (en) * 2012-10-18 2013-11-19 Chunghwa Picture Tubes, Ltd. Method for forming an oxide thin film transistor
CN105226015A (zh) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244186A (zh) * 2018-11-29 2020-06-05 中华映管股份有限公司 薄膜晶体管及其制造方法
CN114530413A (zh) * 2022-02-21 2022-05-24 昆山龙腾光电股份有限公司 阵列基板及其制作方法
CN114530413B (zh) * 2022-02-21 2024-04-30 昆山龙腾光电股份有限公司 阵列基板及其制作方法
CN115084277A (zh) * 2022-06-29 2022-09-20 昆山龙腾光电股份有限公司 金属氧化物薄膜晶体管及其制作方法、阵列基板

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