WO2018051412A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2018051412A1
WO2018051412A1 PCT/JP2016/076978 JP2016076978W WO2018051412A1 WO 2018051412 A1 WO2018051412 A1 WO 2018051412A1 JP 2016076978 W JP2016076978 W JP 2016076978W WO 2018051412 A1 WO2018051412 A1 WO 2018051412A1
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Prior art keywords
breakdown voltage
high breakdown
side circuit
circuit region
pchmos
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PCT/JP2016/076978
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English (en)
French (fr)
Inventor
学 吉野
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三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2018538990A priority Critical patent/JP6590076B2/ja
Priority to PCT/JP2016/076978 priority patent/WO2018051412A1/ja
Priority to US16/096,168 priority patent/US11063116B2/en
Priority to CN201680089138.0A priority patent/CN109690770B/zh
Priority to DE112016007213.9T priority patent/DE112016007213B4/de
Publication of WO2018051412A1 publication Critical patent/WO2018051412A1/ja

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Definitions

  • the present invention relates to a semiconductor device including a horizontal high withstand voltage element.
  • An HVIC (High Voltage IC) for driving a power chip forming a half bridge has a low side circuit area, a high side circuit area, and a level shift circuit for transmitting a signal between the two.
  • the low side circuit region is based on the substrate potential, and the high side circuit region is separated from the substrate at a high withstand voltage.
  • the high withstand voltage separation from the substrate voltage in the high side circuit region is realized by the Resurf effect, and the outer periphery of the high side circuit region is surrounded by the Resurf separation structure in plan view (see, for example, Patent Document 1).
  • the level shift circuit has a high breakdown voltage NchMOS transmitting a signal from the low side circuit region to the high side circuit region and a high breakdown voltage Pch MOS transmitting a signal from the high side circuit region to the low side circuit region.
  • the high withstand voltage NchMOS and the high withstand voltage PchMOS have the same withstand voltage as the resurf isolation region surrounding the outer periphery of the high side circuit region (see, for example, Non-Patent Document 1), and have the same Resurf isolation structure surrounding the outer periphery of the high side circuit region. (See, for example, Patent Document 2 and Non-Patent Document 2).
  • the high breakdown voltage NchMOS maintains high breakdown voltage by completely depleting the N-type resurf region.
  • the high breakdown voltage PchMOS maintains the high breakdown voltage by completely depleting the P type diffusion layer on the surface in addition to the N type resurf region. Therefore, a leak current transiently flows in a period from the time when a high voltage is applied to both the high breakdown voltage NchMOS and the high breakdown voltage PchMOS, the depletion layer spreads in the high breakdown voltage isolation region and the complete depletion is achieved. If this transient leak current flows for a long time, the level shift circuit may malfunction.
  • the field plate on the low side is long, depletion is promoted in the high breakdown voltage NchMOS and the period during which the leak current flows transiently becomes short, but in the high breakdown voltage PchMOS, the depletion of the P type diffusion layer is inhibited and the leakage current transiently The period during which the As a result, the high breakdown voltage PchMOS of the level shift circuit is likely to malfunction.
  • the field plate on the low side is shortened, the high breakdown voltage NchMOS of the level shift circuit is likely to malfunction.
  • the field plate structures of the high breakdown voltage NchMOS and the high breakdown voltage PchMOS are the same, the period in which the leak current flows can not be shortened in both the high breakdown voltage NchMOS and the high breakdown voltage PchMOS.
  • the present invention has been made to solve the problems as described above, and its object is to shorten the period in which a leak current transiently flows when a high voltage is applied to both the high breakdown voltage NchMOS and the high breakdown voltage PchMOS. And a semiconductor device capable of improving the malfunction tolerance of the level shift circuit.
  • a semiconductor device comprises a high side circuit area, a low side circuit area, and a resurf isolation structure surrounding the outer periphery of the high side circuit area and separating the high side circuit area and the low side circuit area.
  • the resurf isolation structure includes high breakdown voltage isolation, high breakdown voltage NchMOS and high breakdown voltage PchMOS, and the high breakdown voltage isolation, high breakdown voltage NchMOS and high breakdown voltage PchMOS are formed on a thermal oxide film and the thermal oxide film.
  • the inner end of the field plate closest to the low side circuit region in the high breakdown voltage PchMOS has a plurality of field plates, and the inner end of the field plate closest to the low side circuit region in the high breakdown Nch MOS has the inner end It is characterized in that it is located on the low side circuit area side.
  • the inner end of the field plate closest to the low side circuit region in the high breakdown voltage PchMOS is located closer to the low side circuit region than the inner end of the field plate closest to the low side circuit region in the high breakdown voltage NchMOS.
  • FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a diagram showing a high breakdown voltage NchMOS of the level shift circuit according to the first embodiment of the present invention.
  • FIG. 5 is a diagram showing a high breakdown voltage PchMOS of the level shift circuit according to the first embodiment of the present invention. It is a top view which shows the high side circuit area
  • FIG. 5 is a cross-sectional view of high breakdown voltage separation along I-II in FIG. 4;
  • FIG. 5 is a cross-sectional view of the high breakdown voltage NchMOS along III-IV in FIG. 4;
  • FIG. 5 is a cross sectional view of the high breakdown voltage PchMOS along V-VI in FIG. 4; It is a top view showing the high side circuit field of the semiconductor device concerning a comparative example.
  • FIG. 9 is a cross-sectional view of high breakdown voltage separation along I-II in FIG. 8;
  • FIG. 9 is a cross sectional view of the high breakdown voltage NchMOS along the line III-IV in FIG. 8;
  • FIG. 9 is a cross sectional view of the high breakdown voltage PchMOS along V-VI in FIG. 8;
  • FIG. 16 is a cross-sectional view for illustrating the depletion of the high breakdown voltage NchMOS according to the comparative example.
  • FIG. 16 is a cross-sectional view for illustrating the depletion of the high breakdown voltage NchMOS according to the comparative example.
  • FIG. 16 is a cross sectional view for illustrating the depletion of the high breakdown voltage PchMOS according to the comparative example.
  • FIG. 16 is a cross sectional view for illustrating the depletion of the high breakdown voltage PchMOS according to the comparative example. It is a top view which shows the high side circuit area
  • FIG. 17 is a cross-sectional view of the high breakdown voltage separation along I-II in FIG. 16;
  • FIG. 17 is a cross-sectional view of the high breakdown voltage NchMOS along the line III-IV in FIG. 16; FIG.
  • FIG. 17 is a cross sectional view of the high breakdown voltage PchMOS along V-VI in FIG. 16; It is a top view which shows the high side circuit area
  • FIG. 21 is a cross-sectional view of the high breakdown voltage separation along I-II in FIG. 20.
  • FIG. 21 is a cross-sectional view of the high breakdown voltage NchMOS along III-IV in FIG. 20.
  • FIG. 21 is a cross-sectional view of the high breakdown voltage PchMOS along V-VI in FIG. 20. It is a top view which shows the high side circuit area
  • FIG. 25 is a cross-sectional view of the high breakdown voltage separation along I-II in FIG. 24.
  • FIG. 25 is a cross-sectional view of the high breakdown voltage NchMOS along the line III-IV in FIG. 24.
  • FIG. 25 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG. 24. It is a top view which shows the high side circuit area
  • FIG. 29 is a cross-sectional view of the high voltage separation according to I-II in FIG. 28.
  • FIG. 29 is a cross-sectional view of the high breakdown voltage NchMOS along III-IV in FIG. 28.
  • FIG. 29 is a cross sectional view of the high breakdown voltage PchMOS along V-VI in FIG. 28.
  • FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention.
  • This semiconductor device is a high voltage IC (HVIC) 3 that drives power chips 1 and 2 forming a half bridge.
  • the HVIC 3 includes a high side circuit area 4 for driving the power chip 1, a low side circuit area 5 for driving the power chip 2, and a level shift circuit 6 for transmitting signals between the low side circuit area 5 and the high side circuit area 4.
  • HVIC high voltage IC
  • FIG. 2 is a diagram showing a high breakdown voltage NchMOS of the level shift circuit according to the first embodiment of the present invention. Signal transmission from low side circuit region 5 to high side circuit region 4 is performed by high breakdown voltage Nch MOS 7 of level shift circuit 6.
  • FIG. 3 is a diagram showing a high breakdown voltage PchMOS of the level shift circuit according to the first embodiment of the present invention. Signal transmission from the high side circuit area 4 to the low side circuit area 5 is performed by the high breakdown voltage Pch MOS 8.
  • FIG. 4 is a plan view showing the high side circuit region of the semiconductor device according to the first embodiment of the present invention. Only a part of the configuration is shown for simplicity.
  • the resurf isolation structure surrounds the outer periphery of the high side circuit area in plan view and separates the high side circuit area and the low side circuit area.
  • the resurf isolation structure includes high breakdown voltage isolation, high breakdown voltage NchMOS and high breakdown voltage PchMOS.
  • the low side circuit region is based on the substrate potential, and the high breakdown voltage separation separates the high side circuit region from the substrate potential to a high breakdown voltage.
  • the high breakdown voltage NchMOS and the high breakdown voltage PchMOS have the same breakdown voltage as the high breakdown voltage separation.
  • the spiral polysilicon 9 is a resistor that surrounds the outer periphery of the high side circuit region in the resurf isolation structure.
  • FIG. 5 is a cross-sectional view of high breakdown voltage separation along I-II in FIG.
  • a P type epitaxial layer (not shown) is formed on a P type substrate 10, and an N type diffusion layer 11a which is a resurf region is formed thereon.
  • the P-type diffusion layer 12 reaching the P-type substrate 10 surrounds the high side circuit region and the N-type diffusion layer 11 a.
  • a P-type diffusion layer 13 a is formed inside the end of the P-type diffusion layer 12 so as to partially overlap with the P-type diffusion layer 12.
  • An N + -type buried diffusion layer 14a is formed on the inner side of the end of the P-type diffusion layer 13a so as to be in contact with the lower surface of the P-type epitaxial layer.
  • N + -type diffusion layer 15a is formed on the surface of the N-type diffusion layer 11a at a predetermined distance from the P-type diffusion layer 12.
  • a P + -type diffusion layer 16a is formed on part of the surface of the P-type diffusion layer 13a.
  • a thermal oxide film 17 is formed on the upper surface of the N-type diffusion layer 11 a between the P-type diffusion layer 12 and the N + -type diffusion layer 15 a.
  • Polysilicons 18a and 19a are formed at a predetermined distance apart so as to cover the inner end and the outer end of thermal oxide film 17, respectively.
  • An insulating film 20 is formed to cover these surfaces.
  • Metal interconnection layers 21 and 22 are formed on insulating film 20.
  • Metal interconnection layer 21 is electrically connected to N + type diffusion layer 15a and polysilicon 18a through the contact hole.
  • the metal wiring layer 22 is electrically connected to the P + type diffusion layer 16 a and the polysilicon 19 a through a contact hole penetrating the insulating film 20.
  • polysilicon 9 is formed in the insulating film 20, polysilicon 9 is formed. One end of the polysilicon 9 is electrically connected to the metal wiring layer 22, and the other end is electrically connected to the metal wiring layer 21.
  • the impurity concentration is higher in the order of the N + -type buried diffusion layer 14 a, the P-type diffusion layer 12, the N-type diffusion layer 11 a, and the P-type substrate 10.
  • the N type diffusion layer 11a satisfies the Resurf condition.
  • FIG. 6 is a cross-sectional view of the high breakdown voltage NchMOS taken along line III-IV of FIG.
  • the N-type diffusion layer 11b of the high breakdown voltage NchMOS is electrically separated from the N-type diffusion layer 11a of high breakdown voltage separation (the separation structure is not shown; see, for example, Patent Document 2 and Non-patent Document 2).
  • the N + -type buried diffusion layer 14b is also electrically separated from the N + -type buried diffusion layer 14a.
  • a P + -type diffusion layer 23 is formed on part of the surface of the P-type diffusion layer 12.
  • a P-type diffusion layer 13 b is formed on the surface of the N-type diffusion layer 11 b between the P-type diffusion layer 12 and the thermal oxide film 17.
  • An N + -type diffusion layer 15 b is formed on the surface of the N-type diffusion layer 11 b at a predetermined distance from the P-type diffusion layer 12.
  • the P + -type diffusion layer 16b and the N + -type diffusion layer 24 are formed on part of the surface of the P-type diffusion layer 13b.
  • Polysilicons 18 b and 19 b are formed on the thermal oxide film 17 at a predetermined distance apart so as to cover the inner end and the outer end of the thermal oxide film 17, respectively.
  • the polysilicon 19 b is also formed on the P type diffusion layer 13 b via a gate oxide film.
  • Polysilicon 9 is formed on thermal oxide film 17 between polysilicon 18b and 19b.
  • Metal interconnection layers 25, 26, 27, 28 are formed on insulating film 20.
  • Metal interconnection layer 25 is electrically connected to N + type diffusion layer 15 b and polysilicon 18 b through the contact hole.
  • Metal interconnection layer 26 is electrically connected to polysilicon 19b through the contact hole.
  • Metal interconnection layer 27 is electrically connected to P + type diffusion layer 16 b and N + type diffusion layer 24 through the contact holes.
  • the metal wiring layer 28 is electrically connected to the P + -type diffusion layer 23 through a contact hole penetrating the insulating film 20.
  • the metal wiring layer 28 is also electrically connected to the metal wiring layer 22.
  • FIG. 7 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • the N type diffusion layer 11c of the high breakdown voltage PchMOS is electrically separated from the N type diffusion layer 11a of high breakdown voltage separation.
  • the N + -type buried diffusion layer 14c is also electrically separated from the N + -type buried diffusion layer 14a.
  • a P-type diffusion layer 13 c is formed on the surface of the N-type diffusion layer 11 c between the P-type diffusion layer 12 and the thermal oxide film 17.
  • a P + -type diffusion layer 16c is formed on part of the surface of the P-type diffusion layer 13c.
  • a P-type diffusion layer 29 is formed on the surface of the N-type diffusion layer 11 c so as to be in contact with the lower surface of the thermal oxide film 17.
  • a P + -type diffusion layer 30 is formed on the surface of the N-type diffusion layer 11 c spaced apart from the P-type diffusion layer 29 by a fixed distance.
  • An N + -type diffusion layer 15 c is formed on the opposite side of the P-type diffusion layer 29 to the P-type diffusion layer 30.
  • Polysilicons 18c and 19c are formed at a predetermined distance apart so as to cover the inner end and the outer end of the thermal oxide film 17, respectively.
  • the polysilicon 18 c is formed between the P type diffusion layer 29 and the P type diffusion layer 30 on the N type diffusion layer 11 c via a gate oxide film.
  • Metal interconnection layers 31, 32, and 33 are formed on insulating film 20.
  • the metal wiring layer 31 is electrically connected to the P + -type diffusion layer 30 and the N + -type diffusion layer 15 c through the contact holes.
  • Metal interconnection layer 32 is electrically connected to polysilicon 18c through the contact hole.
  • the metal interconnection layer 33 is electrically connected to the P + -type diffusion layer 16 c and the polysilicon 19 c through a contact hole penetrating the insulating film 20.
  • the high breakdown voltage separated polysilicon 9, 18a, 19a, the high breakdown voltage NchMOS polysilicon 9, 18b, 19b, and the high breakdown voltage PchMOS polysilicon 9, 18c, 19c are respectively field plates.
  • the length Lp of the polysilicon 19c on the thermal oxide film 17 satisfies the relationship of Formula (1).
  • Ln Li> Lp (1) Therefore, the inner end of the polysilicon 19c, which is the field plate closest to the low side circuit region in the high breakdown voltage PchMOS, is lower side than the inner end of the polysilicon 19b which is the field plate closest to the low side circuit region in the high breakdown voltage NchMOS. Located on the circuit area side.
  • the spacing between the plurality of polysilicons 9 in the high breakdown voltage PchMOS is wider than the spacing between the plurality of polysilicons 9 in the high breakdown voltage NchMOS and the high breakdown voltage separation.
  • the spacing between the plurality of polysilicons 9 in the high breakdown voltage PchMOS may not be constant.
  • FIG. 8 is a plan view showing the high side circuit region of the semiconductor device according to the comparative example.
  • FIG. 9 is a cross-sectional view of the high-breakdown-voltage isolation along I-II in FIG.
  • FIG. 10 is a cross-sectional view of the high breakdown voltage NchMOS taken along line III-IV of FIG.
  • FIG. 11 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • the high breakdown voltage NchMOS maintains the high breakdown voltage by completely depleting the N type diffusion layer 11b.
  • the high breakdown voltage PchMOS maintains the high breakdown voltage by completely depleting the P-type diffusion layer 29 on the surface in addition to the N-type diffusion layer 11c. Therefore, a leak current transiently flows in a period from the time when a high voltage is applied to both the high breakdown voltage NchMOS and the high breakdown voltage PchMOS, the depletion layer spreads in the high breakdown voltage isolation region and the complete depletion is achieved. If the transient leak current flows for a long time, the level shift circuit 6 malfunctions.
  • FIG. 12 and 13 are cross-sectional views for illustrating the depletion of the high breakdown voltage NchMOS according to the comparative example.
  • the polysilicon 19b which is the field plate closest to the low side circuit region, is longer than that in FIG. 12, and the low voltage polysilicon 19b extends to the high side circuit region. Therefore, when a high voltage is applied to the metal wiring layer 25 and a low voltage is applied to the metal wiring layers 26, 27, 28, movement of electrons 34 in the N-type diffusion layer 11b to the high side is promoted. As a result, depletion is promoted and the period in which the leak current flows transiently becomes short.
  • FIG. 14 and 15 are cross-sectional views for describing the depletion of the high breakdown voltage PchMOS according to the comparative example.
  • the polysilicon 19c which is the field plate closest to the low side circuit region, is longer than that in FIG. 14, and the polysilicon 19c, which is a low voltage, protrudes to the high side circuit region. Therefore, when a high voltage is applied to the metal interconnection layers 31 and 32 and a low voltage is applied to the metal interconnection layers 28 and 33, the holes 35 in the P type diffusion layer 29 are drawn under the polysilicon 19c. As a result, the depletion of the P-type diffusion layer 29 is inhibited, and the period during which the leak current flows transiently becomes longer.
  • the polysilicon 19b which is the field plate closest to the low side circuit region in the high breakdown voltage NchMOS is long and extended to the high side circuit region side, depletion of the N type diffusion layer 11b Is promoted.
  • the polysilicon 19c which is the field plate closest to the low side circuit region in the high breakdown voltage PchMOS is short and its inner end is located closer to the low side circuit region than in the high breakdown voltage NchMOS, the depletion of the P type diffusion layer 29 Is promoted. Therefore, the period in which the leak current transiently flows when the high voltage is applied can be shortened in both the high breakdown voltage NchMOS and the high breakdown voltage PchMOS, and the malfunction tolerance of the level shift circuit 6 can be improved.
  • FIG. 16 is a plan view showing the high side circuit region of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 17 is a cross-sectional view of the high breakdown voltage separation along I-II in FIG.
  • FIG. 18 is a cross-sectional view of the high breakdown voltage NchMOS taken along line III-IV of FIG.
  • FIG. 19 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • the distance between the plurality of polysilicons 9 in the high breakdown voltage PchMOS and the high breakdown voltage separation is longer than the distance between the plurality of polysilicons 9 in the high breakdown voltage NchMOS.
  • the inner end portion of polysilicon 19c which is the field plate closest to the low side circuit region in high breakdown voltage PchMOS is the inside of polysilicon 19b which is the field plate closest to the low side circuit region in high breakdown voltage NchMOS. It is located closer to the low side circuit area than the end.
  • FIG. 20 is a plan view showing the high side circuit region of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 21 is a cross-sectional view of the high-breakdown-voltage isolation along I-II in FIG.
  • FIG. 22 is a cross-sectional view of the high breakdown voltage NchMOS taken along line III-IV of FIG.
  • FIG. 23 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • the interval of the spiral shaped polysilicon 9 is the same.
  • the plurality of polysilicons 9 in the high breakdown voltage PchMOS are arranged closer to the low side circuit region than the plurality of polysilicons 9 in the high breakdown voltage NchMOS.
  • the inner end portion of polysilicon 19c which is the field plate closest to the low side circuit region in high breakdown voltage PchMOS is the inside of polysilicon 19b which is the field plate closest to the low side circuit region in high breakdown voltage NchMOS. It is located closer to the low side circuit area than the end. Thereby, the same effect as that of the first embodiment can be obtained. In addition, since it is not necessary to widen the intervals of the plurality of polysilicons 9 of the high breakdown voltage PchMOS, it is possible to suppress a drop in the breakdown voltage stability.
  • FIG. 24 is a plan view showing the high side circuit region of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 25 is a cross-sectional view of the high-breakdown-voltage isolation along I-II in FIG.
  • FIG. 26 is a cross-sectional view of the high breakdown voltage NchMOS along the line III-IV in FIG.
  • FIG. 27 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • polysilicon 19c which is the field plate closest to the low side circuit region in high breakdown voltage PchMOS
  • polysilicon 19b which is the field plate closest to the low side circuit region in high breakdown voltage NchMOS. Less than.
  • the polysilicon 19c on the thermal oxide film 17 of the high breakdown voltage PchMOS is moved parallel to the polysilicon 18c side, and the distance between them is made the same as the distance between the polysilicon 18a and 19a and the distance between the polysilicon 18b and 19b.
  • the distance between the field plate closest to the low side circuit region and the field plate closest to the high side circuit region is the same in high breakdown voltage isolation, high breakdown voltage NchMOS and high breakdown voltage PchMOS.
  • the P-type diffusion layer 12, the P + -type diffusion layer 23, the P + -type diffusion layer 16c, the P-type diffusion layer 13c, and the metal wiring layer 33 also move parallel to the polysilicon 18c by the same length as the polysilicon 19c. Further, the lengths of the P type diffusion layer 29 and the thermal oxide film 17 become shorter by the moving length of the polysilicon 19c.
  • the distance between the field plate closest to the low side circuit region and the field plate closest to the high side circuit region is the same, and the position of the polysilicon 9 of spiral shape Can be the same. Therefore, the spiral polysilicon 9 can be formed only by the straight line and the arc pattern, and the layout design becomes easy. Further, the area on the low side of the high breakdown voltage PchMOS can be saved.
  • FIG. 28 is a plan view showing the high side circuit region of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 29 is a cross-sectional view of the high breakdown voltage separation taken along I-II in FIG.
  • FIG. 30 is a cross-sectional view of the high breakdown voltage NchMOS taken along line III-IV of FIG.
  • FIG. 31 is a cross-sectional view of the high breakdown voltage PchMOS taken along V-VI in FIG.
  • polysilicon 36 and metal interconnection layer 37 capacitively coupled to each other are formed on thermal oxide film 17 in place of spiral shaped polysilicon 9 of the first embodiment. Even in this case, the same effect as that of the first embodiment can be obtained.
  • Polysilicon 36 is in the same layer as polysilicon 18a, 18b, 18c, 19a, 19b and 19c, and metal interconnection layer 37 is formed of metal interconnection layers 21, 22, 25, 26, 27, 28, 31, 32, 33. Can be formed simultaneously. Therefore, the step of forming polysilicon 9 can be omitted as compared with the first embodiment.
  • the P-type substrate 10 and the semiconductor layer thereon are not limited to those formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon.
  • the wide band gap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond.
  • a power semiconductor element formed of such a wide band gap semiconductor can be miniaturized because of its high voltage resistance and allowable current density. By using this miniaturized device, it is possible to miniaturize a semiconductor module incorporating this device. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized, and the water cooling portion can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the semiconductor module can be highly efficient.

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Abstract

リサーフ分離構造が、ハイサイド回路領域の外周を囲い、ハイサイド回路領域とローサイド回路領域を分離する。リサーフ分離構造は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳを有する。高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳは、複数のフィールドプレート（９，１９ａ，１９ｂ，１９ｃ）を有する。高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレート（１９ｃ）の内端部は、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレート（１９ｂ）の内端部よりもローサイド回路領域側に位置する。

Description

半導体装置
　本発明は、横型の高耐圧素子を含む半導体装置に関する。
　ハーフブリッジを構成するパワーチップを駆動するＨＶＩＣ（High Voltage IC）は、ローサイド回路領域と、ハイサイド回路領域と、両者の間の信号伝達を行うレベルシフト回路とを有する。ローサイド回路領域は基板電位を基準とし、ハイサイド回路領域は基板から高耐圧に分離されている。ハイサイド回路領域の基板電圧からの高耐圧の分離はリサーフ効果により実現され、平面視でハイサイド回路領域の外周はリサーフ分離構造に囲われている（例えば、特許文献１参照）。
　レベルシフト回路は、ローサイド回路領域からハイサイド回路領域へ信号伝達する高耐圧ＮｃｈＭＯＳと、ハイサイド回路領域からローサイド回路領域へ信号伝達する高耐圧ＰｃｈＭＯＳとを有する。高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳは、ハイサイド回路領域の外周を囲うリサーフ分離領域と同等の耐圧を有し（例えば、非特許文献１参照）、ハイサイド回路領域の外周を囲う同一のリサーフ分離構造内に形成される（例えば、特許文献２及び非特許文献２参照）。
米国特許第４，２９２，６４２号明細書 日本特許第３９１７２１１号公報
T.Terashima, M.Yoshizawa, M.Fukunaga and G. Majumdar, "Structure of 600V IC and A New Voltage Sensing Device", 5th International Symposium on Power Semiconductor Devices & IC’s Kazuhiro Shimizu and Tomohide Terashima, "The 2nd Generation divided RESURF structure for High Voltage ICs", Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC’s May 18-22, 2008 Oralando, FL
　高耐圧ＮｃｈＭＯＳはＮ型のリサーフ領域を完全空乏化することで高耐圧を保持する。一方、高耐圧ＰｃｈＭＯＳはＮ型のリサーフ領域に加え、表面のＰ型拡散層を完全空乏化することで高耐圧を保持する。このため、高耐圧ＮｃｈＭＯＳも高耐圧ＰｃｈＭＯＳも高電圧が印加された時点から、高耐圧分離領域内に空乏層が広がり完全空乏化するまでの期間には過渡的にリーク電流が流れる。この過渡的なリーク電流の流れる期間が長いとレベルシフト回路の誤動作を引き起こす。
　ローサイド側のフィールドプレートが長いと、高耐圧ＮｃｈＭＯＳでは空乏化が促進され過渡的にリーク電流が流れる期間が短くなるが、高耐圧ＰｃｈＭＯＳではＰ型拡散層の空乏化が阻害され過渡的にリーク電流が流れる期間が長くなる。このため、レベルシフト回路の高耐圧ＰｃｈＭＯＳが誤動作を起こしやすくなる。一方、ローサイド側のフィールドプレートを短くすると、レベルシフト回路の高耐圧ＮｃｈＭＯＳが誤動作を起こしやすくなる。従来は、高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳのフィールドプレート構造が同一であるため、高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳの両者においてリーク電流の流れる期間を短くすることはできなかった。
　本発明は、上述のような課題を解決するためになされたもので、その目的は高電圧が印加された際に過渡的にリーク電流が流れる期間を高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳの両者で短くし、レベルシフト回路の誤動作耐量を向上することができる半導体装置を得るものである。
　本発明に係る半導体装置は、ハイサイド回路領域と、ローサイド回路領域と、前記ハイサイド回路領域の外周を囲い、前記ハイサイド回路領域と前記ローサイド回路領域を分離するリサーフ分離構造とを備え、前記リサーフ分離構造は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳを有し、前記高耐圧分離、前記高耐圧ＮｃｈＭＯＳ及び前記高耐圧ＰｃｈＭＯＳは、熱酸化膜と、前記熱酸化膜上に形成された複数のフィールドプレートとを有し、前記高耐圧ＰｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートの内端部は、前記高耐圧ＮｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートの内端部よりも前記ローサイド回路領域側に位置することを特徴とする。
　本発明では、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートの内端部は、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートの内端部よりもローサイド回路領域側に位置する。これにより、高電圧が印加された際に過渡的にリーク電流が流れる期間を高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳの両者で短くし、レベルシフト回路の誤動作耐量を向上することができる。
本発明の実施の形態１に係る半導体装置を示す図である。 本発明の実施の形態１に係るレベルシフト回路の高耐圧ＮｃｈＭＯＳを示す図である。 本発明の実施の形態１に係るレベルシフト回路の高耐圧ＰｃｈＭＯＳを示す図である。 本発明の実施の形態１に係る半導体装置のハイサイド回路領域を示す平面図である。 図４のＩ－ＩＩに沿った高耐圧分離の断面図である。 図４のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図４のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。 比較例に係る半導体装置のハイサイド回路領域を示す平面図である。 図８のＩ－ＩＩに沿った高耐圧分離の断面図である。 図８のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図８のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。 比較例に係る高耐圧ＮｃｈＭＯＳの空乏化を説明するための断面図である。 比較例に係る高耐圧ＮｃｈＭＯＳの空乏化を説明するための断面図である。 比較例に係る高耐圧ＰｃｈＭＯＳの空乏化を説明するための断面図である。 比較例に係る高耐圧ＰｃｈＭＯＳの空乏化を説明するための断面図である。 本発明の実施の形態２に係る半導体装置のハイサイド回路領域を示す平面図である。 図１６のＩ－ＩＩに沿った高耐圧分離の断面図である。 図１６のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図１６のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。 本発明の実施の形態３に係る半導体装置のハイサイド回路領域を示す平面図である。 図２０のＩ－ＩＩに沿った高耐圧分離の断面図である。 図２０のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図２０のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。 本発明の実施の形態４に係る半導体装置のハイサイド回路領域を示す平面図である。 図２４のＩ－ＩＩに沿った高耐圧分離の断面図である。 図２４のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図２４のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。 本発明の実施の形態５に係る半導体装置のハイサイド回路領域を示す平面図である。 図２８のＩ－ＩＩに沿った高耐圧分離の断面図である。 図２８のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。 図２８のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。
　本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、本発明の実施の形態１に係る半導体装置を示す図である。この半導体装置は、ハーフブリッジを構成するパワーチップ１，２を駆動するＨＶＩＣ（High Voltage IC）３である。ＨＶＩＣ３は、パワーチップ１を駆動するハイサイド回路領域４と、パワーチップ２を駆動するローサイド回路領域５と、ローサイド回路領域５とハイサイド回路領域４との間の信号伝達を行うレベルシフト回路６とを有する。
　図２は、本発明の実施の形態１に係るレベルシフト回路の高耐圧ＮｃｈＭＯＳを示す図である。ローサイド回路領域５からハイサイド回路領域４への信号伝達はレベルシフト回路６の高耐圧ＮｃｈＭＯＳ７により行われる。図３は、本発明の実施の形態１に係るレベルシフト回路の高耐圧ＰｃｈＭＯＳを示す図である。ハイサイド回路領域４からローサイド回路領域５への信号伝達は高耐圧ＰｃｈＭＯＳ８により行われる。
　図４は、本発明の実施の形態１に係る半導体装置のハイサイド回路領域を示す平面図である。簡単のため一部の構成のみ図示している。リサーフ分離構造が、平面視でハイサイド回路領域の外周を囲い、ハイサイド回路領域とローサイド回路領域を分離する。リサーフ分離構造は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳを有する。ローサイド回路領域は基板電位を基準とし、高耐圧分離がハイサイド回路領域を基板電位から高耐圧に分離する。高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳは高耐圧分離と同等の耐圧を有する。渦巻き状のポリシリコン９は、リサーフ分離構造においてハイサイド回路領域の外周を囲う抵抗体である。
　図５は、図４のＩ－ＩＩに沿った高耐圧分離の断面図である。Ｐ型基板１０上にＰ型エピタキシャル層（不図示）が形成され、その上にリサーフ領域であるＮ型拡散層１１ａが形成されている。Ｐ型基板１０まで到達するＰ型拡散層１２がハイサイド回路領域及びＮ型拡散層１１ａを囲っている。Ｐ型拡散層１３ａがＰ型拡散層１２の端より内側にＰ型拡散層１２と部分的に重なるように形成されている。Ｐ型拡散層１３ａの端より内側にＰ型エピタキシャル層の下面と接するようにＮ＋型埋め込み拡散層１４ａが形成されている。Ｐ型拡散層１２から一定の距離が離れたＮ型拡散層１１ａの表面にＮ＋型拡散層１５ａが形成されている。Ｐ型拡散層１３ａの表面の一部にＰ＋型拡散層１６ａが形成されている。Ｐ型拡散層１２とＮ＋型拡散層１５ａの間のＮ型拡散層１１ａの上面には熱酸化膜１７が形成されている。ポリシリコン１８ａ，１９ａがそれぞれ熱酸化膜１７の内端部と外端部を覆うように一定の距離を離して形成されている。これらの表面を覆うように絶縁膜２０が形成されている。
　金属配線層２１，２２が絶縁膜２０上に形成されている。金属配線層２１は、コンタクトホールを通じてＮ＋型拡散層１５ａ及びポリシリコン１８ａに電気的に接続されている。金属配線層２２は、絶縁膜２０を貫通するコンタクトホールを通じてＰ＋型拡散層１６ａ及びポリシリコン１９ａに電気的に接続されている。
　絶縁膜２０内にポリシリコン９が形成されている。ポリシリコン９の一端は金属配線層２２に電気的に接続され、他端は金属配線層２１に電気的に接続されている。Ｎ＋型埋め込み拡散層１４ａ、Ｐ型拡散層１２、Ｎ型拡散層１１ａ、Ｐ型基板１０の順に不純物濃度が高くなっている。Ｎ型拡散層１１ａはリサーフ条件を満足している。
　図６は、図４のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。高耐圧ＮｃｈＭＯＳのＮ型拡散層１１ｂは、高耐圧分離のＮ型拡散層１１ａと電気的に分離されている（分離構造は不図示。例えば、特許文献２及び非特許文献２参照）。Ｎ＋型埋め込み拡散層１４ｂもＮ＋型埋め込み拡散層１４ａと電気的に分離されている。Ｐ型拡散層１２の表面の一部にＰ＋型拡散層２３が形成されている。Ｐ型拡散層１２と熱酸化膜１７の間のＮ型拡散層１１ｂの表面にＰ型拡散層１３ｂが形成されている。Ｐ型拡散層１２から一定の距離が離れたＮ型拡散層１１ｂの表面にＮ＋型拡散層１５ｂが形成されている。Ｐ型拡散層１３ｂの表面の一部にＰ＋型拡散層１６ｂ及びＮ＋型拡散層２４が形成されている。
　ポリシリコン１８ｂ，１９ｂがそれぞれ熱酸化膜１７の内端部と外端部を覆うように一定の距離を離して熱酸化膜１７上に形成されている。ポリシリコン１９ｂは、Ｐ型拡散層１３ｂ上にもゲート酸化膜を介して形成されている。ポリシリコン１８ｂ，１９ｂの間において熱酸化膜１７上にポリシリコン９が形成されている。
　絶縁膜２０上に金属配線層２５，２６，２７，２８が形成されている。金属配線層２５は、コンタクトホールを通じてＮ＋型拡散層１５ｂ及びポリシリコン１８ｂと電気的に接続されている。金属配線層２６は、コンタクトホールを通じてポリシリコン１９ｂと電気的に接続されている。金属配線層２７は、コンタクトホールを通じてＰ＋型拡散層１６ｂ及びＮ＋型拡散層２４と電気的に接続されている。金属配線層２８は、絶縁膜２０を貫通するコンタクトホールを通じてＰ＋型拡散層２３と電気的に接続されている。金属配線層２８は金属配線層２２とも電気的に接続されている。
　図７は、図４のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。高耐圧ＰｃｈＭＯＳのＮ型拡散層１１ｃは、高耐圧分離のＮ型拡散層１１ａと電気的に分離されている。Ｎ＋型埋め込み拡散層１４ｃもＮ＋型埋め込み拡散層１４ａと電気的に分離されている。Ｐ型拡散層１２と熱酸化膜１７の間においてＮ型拡散層１１ｃの表面にＰ型拡散層１３ｃが形成されている。Ｐ型拡散層１３ｃの表面の一部にＰ＋型拡散層１６ｃが形成されている。Ｎ型拡散層１１ｃの表面に熱酸化膜１７の下面と接するようにＰ型拡散層２９が形成されている。Ｐ型拡散層２９から一定の距離が離れたＮ型拡散層１１ｃの表面にＰ＋型拡散層３０が形成されている。Ｐ型拡散層３０に対してＰ型拡散層２９と反対側にＮ＋型拡散層１５ｃが形成されている。
　ポリシリコン１８ｃ，１９ｃがそれぞれ熱酸化膜１７の内端部と外端部を覆うように一定の距離を離して形成されている。ポリシリコン１８ｃはＰ型拡散層２９とＰ型拡散層３０の間においてＮ型拡散層１１ｃ上にゲート酸化膜を介して形成されている。絶縁膜２０上に金属配線層３１，３２，３３が形成されている。金属配線層３１は、コンタクトホールを通じてＰ＋型拡散層３０及びＮ＋型拡散層１５ｃと電気的に接続されている。金属配線層３２は、コンタクトホールを通じてポリシリコン１８ｃと電気的に接続されている。金属配線層３３は、絶縁膜２０を貫通するコンタクトホールを通じてＰ＋型拡散層１６ｃ及びポリシリコン１９ｃと電気的に接続されている。
　ここで、高耐圧分離のポリシリコン９，１８ａ，１９ａ、高耐圧ＮｃｈＭＯＳのポリシリコン９，１８ｂ，１９ｂ、高耐圧ＰｃｈＭＯＳのポリシリコン９，１８ｃ，１９ｃがそれぞれフィールドプレートである。
　最もローサイド回路領域側のフィールドプレートである高耐圧ＮｃｈＭＯＳの熱酸化膜１７上のポリシリコン１９ｂの長さＬｎ、高耐圧分離の熱酸化膜１７上のポリシリコン１９ａの長さＬｉ、高耐圧ＰｃｈＭＯＳの熱酸化膜１７上のポリシリコン１９ｃの長さＬｐが数式（１）の関係を満たしている。
Ｌｎ＝Ｌｉ＞Ｌｐ　（１）
このため、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃの内端部が、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂの内端部よりもローサイド回路領域側に位置する。
　また、高耐圧ＰｃｈＭＯＳにおける複数のポリシリコン９の間隔は、高耐圧ＮｃｈＭＯＳ及び高耐圧分離における複数のポリシリコン９の間隔よりも広い。高耐圧ＰｃｈＭＯＳにおける複数のポリシリコン９の間隔は一定でなくてもよい。
　続いて、本実施の形態の効果を比較例と比較して説明する。図８は、比較例に係る半導体装置のハイサイド回路領域を示す平面図である。図９は、図８のＩ－ＩＩに沿った高耐圧分離の断面図である。図１０は、図８のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。図１１は、図８のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。比較例では、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳのフィールドプレート構造は同じになっている（Ｌｎ＝Ｌｉ＝Ｌｐ）。
　高耐圧ＮｃｈＭＯＳはＮ型拡散層１１ｂを完全空乏化することで高耐圧を保持する。一方、高耐圧ＰｃｈＭＯＳはＮ型拡散層１１ｃに加え、表面のＰ型拡散層２９を完全空乏化することで高耐圧を保持する。このため、高耐圧ＮｃｈＭＯＳも高耐圧ＰｃｈＭＯＳも高電圧が印加された時点から、高耐圧分離領域内に空乏層が広がり完全空乏化するまでの期間には過渡的にリーク電流が流れる。この過渡的なリーク電流の流れる期間が長いとレベルシフト回路６の誤動作を引き起こす。
　図１２及び図１３は、比較例に係る高耐圧ＮｃｈＭＯＳの空乏化を説明するための断面図である。図１３は図１２に比べて最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂが長く、低電圧であるポリシリコン１９ｂがハイサイド回路領域側に張出している。このため、金属配線層２５に高電圧、金属配線層２６，２７，２８に低電圧が印加された時に、Ｎ型拡散層１１ｂ内の電子３４のハイサイド側への移動が促進される。この結果、空乏化が促進され過渡的にリーク電流が流れる期間が短くなる。
　図１４及び図１５は、比較例に係る高耐圧ＰｃｈＭＯＳの空乏化を説明するための断面図である。図１５は図１４に比べて最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃが長く、低電圧であるポリシリコン１９ｃがハイサイド回路領域側に張出している。このため、金属配線層３１，３２に高電圧、金属配線層２８，３３に低電圧が印加された時に、Ｐ型拡散層２９内の正孔３５がポリシリコン１９ｃの下に引き寄せられる。この結果、Ｐ型拡散層２９の空乏化が阻害され過渡的にリーク電流が流れる期間が長くなる。
　これに対して、本実施の形態では、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂが長く、ハイサイド回路領域側に張出しているため、Ｎ型拡散層１１ｂの空乏化が促進される。一方、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃが短く、その内端部が高耐圧ＮｃｈＭＯＳの場合よりもローサイド回路領域側に位置するため、Ｐ型拡散層２９の空乏化が促進される。よって、高電圧が印加された際に過渡的にリーク電流が流れる期間を高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳの両者で短くし、レベルシフト回路６の誤動作耐量を向上することができる。
実施の形態２．
　図１６は、本発明の実施の形態２に係る半導体装置のハイサイド回路領域を示す平面図である。図１７は、図１６のＩ－ＩＩに沿った高耐圧分離の断面図である。図１８は、図１６のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。図１９は、図１６のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。
　本実施の形態では、高耐圧ＰｃｈＭＯＳ及び高耐圧分離における複数のポリシリコン９の間隔は、高耐圧ＮｃｈＭＯＳにおける複数のポリシリコン９の間隔よりも長い。高耐圧ＮｃｈＭＯＳの熱酸化膜１７上のポリシリコン１９ｂの長さＬｎ、高耐圧分離の熱酸化膜１７上のポリシリコン１９ａの長さＬｉ、高耐圧ＰｃｈＭＯＳの熱酸化膜１７上のポリシリコン１９ｃの長さＬｐが数式（２）の関係を満たしている。
Ｌｎ＞Ｌｉ＝Ｌｐ　・・・（２）
　本実施の形態の構成でも、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃの内端部は、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂの内端部よりもローサイド回路領域側に位置する。これにより、実施の形態１と同様の効果を得ることができる。
実施の形態３．
　図２０は、本発明の実施の形態３に係る半導体装置のハイサイド回路領域を示す平面図である。図２１は、図２０のＩ－ＩＩに沿った高耐圧分離の断面図である。図２２は、図２０のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。図２３は、図２０のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。
　本実施の形態では、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳにおいて渦巻き形状のポリシリコン９の間隔が同じである。高耐圧ＰｃｈＭＯＳにおける複数のポリシリコン９は高耐圧ＮｃｈＭＯＳにおける複数のポリシリコン９よりもローサイド回路領域側に配置されている。
　本実施の形態の構成でも、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃの内端部は、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂの内端部よりもローサイド回路領域側に位置する。これにより、実施の形態１と同様の効果を得ることができる。また、高耐圧ＰｃｈＭＯＳの複数のポリシリコン９の間隔を広げる必要が無いため、耐圧安定性の低下を抑制することができる。
実施の形態４．
　図２４は、本発明の実施の形態４に係る半導体装置のハイサイド回路領域を示す平面図である。図２５は、図２４のＩ－ＩＩに沿った高耐圧分離の断面図である。図２６は、図２４のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。図２７は、図２４のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。
　本実施の形態では、実施の形態１と同様に、高耐圧ＰｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｃは、高耐圧ＮｃｈＭＯＳにおける最もローサイド回路領域側のフィールドプレートであるポリシリコン１９ｂよりも短い。そして、高耐圧ＰｃｈＭＯＳの熱酸化膜１７上のポリシリコン１９ｃをポリシリコン１８ｃ側へ平行移動して、両者の間隔をポリシリコン１８ａ，１９ａの間隔及びポリシリコン１８ｂ，１９ｂの間隔と同じにしている。即ち、最もローサイド回路領域側のフィールドプレートと最もハイサイド回路領域側のフィールドプレートの間隔は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳにおいて同じである。Ｐ型拡散層１２、Ｐ＋型拡散層２３、Ｐ＋型拡散層１６ｃ、Ｐ型拡散層１３ｃ、金属配線層３３もポリシリコン１９ｃと同じ長さだけポリシリコン１８ｃ側へ平行移動している。また、Ｐ型拡散層２９及び熱酸化膜１７の長さはポリシリコン１９ｃの移動長さ分だけ短くなる。
　これにより、高電圧が印加された際に過渡的にリーク電流が流れる期間を高耐圧ＮｃｈＭＯＳと高耐圧ＰｃｈＭＯＳの両者で短くし、レベルシフト回路６の誤動作耐量を向上することができる。
　また、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳにおいて、最もローサイド回路領域側のフィールドプレートと最もハイサイド回路領域側のフィールドプレートの間隔を同じにすることで、渦巻き形状のポリシリコン９の位置を同じにすることができる。このため、渦巻き形状のポリシリコン９を直線及び円弧パターンのみで形成することができ、レイアウト設計が容易になる。また、高耐圧ＰｃｈＭＯＳのローサイド側の領域を省スペース化することができる。
実施の形態５．
　図２８は、本発明の実施の形態５に係る半導体装置のハイサイド回路領域を示す平面図である。図２９は、図２８のＩ－ＩＩに沿った高耐圧分離の断面図である。図３０は、図２８のＩＩＩ－ＩＶに沿った高耐圧ＮｃｈＭＯＳの断面図である。図３１は、図２８のＶ－ＶＩに沿った高耐圧ＰｃｈＭＯＳの断面図である。
　本実施の形態では、実施の形態１の渦巻き形状のポリシリコン９の代わりに、互いに容量結合したポリシリコン３６と金属配線層３７を熱酸化膜１７上に形成している。この場合でも、実施の形態１と同様の効果を得ることができる。
　また、ポリシリコン３６はポリシリコン１８ａ，１８ｂ，１８ｃ，１９ａ，１９ｂ，１９ｃと同じ層であり、金属配線層３７は金属配線層２１，２２，２５，２６，２７，２８，３１，３２，３３と同じ層であるため、それぞれ同時に形成することができる。従って、実施の形態１に比べてポリシリコン９を形成する工程を省略することができる。
　なお、Ｐ型基板１０及びその上の半導体層は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成されたパワー半導体素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体モジュールも小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
４　ハイサイド回路領域、５　ローサイド回路領域、７　高耐圧ＮｃｈＭＯＳ、８　高耐圧ＰｃｈＭＯＳ、９，１８ａ，１８ｂ，１８ｃ，１９ａ，１９ｂ，１９ｃ，３６　ポリシリコン、１７　熱酸化膜、３７　金属配線層

Claims (5)

  1. 　ハイサイド回路領域と、
    　ローサイド回路領域と、
    　前記ハイサイド回路領域の外周を囲い、前記ハイサイド回路領域と前記ローサイド回路領域を分離するリサーフ分離構造とを備え、
    　前記リサーフ分離構造は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳを有し、
    　前記高耐圧分離、前記高耐圧ＮｃｈＭＯＳ及び前記高耐圧ＰｃｈＭＯＳは、熱酸化膜と、前記熱酸化膜上に形成された複数のフィールドプレートとを有し、
    　前記高耐圧ＰｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートの内端部は、前記高耐圧ＮｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートの内端部よりも前記ローサイド回路領域側に位置することを特徴とする半導体装置。
  2. 　前記複数のフィールドプレートは、前記熱酸化膜上に形成された渦巻き形状のポリシリコンを有し、
    　前記高耐圧ＰｃｈＭＯＳにおける前記渦巻き形状のポリシリコンの間隔は前記高耐圧ＮｃｈＭＯＳにおける前記渦巻き形状のポリシリコンの間隔よりも広いことを特徴とする請求項１に記載の半導体装置。
  3. 　前記複数のフィールドプレートは、前記熱酸化膜上に形成された渦巻き形状のポリシリコンを有し、
    　前記渦巻き形状のポリシリコンの間隔は前記高耐圧ＰｃｈＭＯＳと前記高耐圧ＮｃｈＭＯＳにおいて同じであり、
    　前記高耐圧ＰｃｈＭＯＳにおける前記渦巻き形状のポリシリコンは、前記高耐圧ＮｃｈＭＯＳにおける前記渦巻き形状のポリシリコンよりも前記ローサイド回路領域側に配置されていることを特徴とする請求項１に記載の半導体装置。
  4. 　前記複数のフィールドプレートは、前記熱酸化膜上に形成されて互いに容量結合したポリシリコンと金属配線層を有することを特徴とする請求項１に記載の半導体装置。
  5. 　ハイサイド回路領域と、
    　ローサイド回路領域と、
    　前記ハイサイド回路領域の外周を囲い、前記ハイサイド回路領域と前記ローサイド回路領域を分離するリサーフ分離構造とを備え、
    　前記リサーフ分離構造は、高耐圧分離、高耐圧ＮｃｈＭＯＳ及び高耐圧ＰｃｈＭＯＳを有し、
    　前記高耐圧分離、前記高耐圧ＮｃｈＭＯＳ及び前記高耐圧ＰｃｈＭＯＳは、熱酸化膜と、前記熱酸化膜上に形成された渦巻き形状のポリシリコンを含む複数のフィールドプレートとを有し、
    　前記高耐圧ＰｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートは、前記高耐圧ＮｃｈＭＯＳにおける最も前記ローサイド回路領域側のフィールドプレートよりも短く、
    　最も前記ローサイド回路領域側のフィールドプレートと最も前記ハイサイド回路領域側のフィールドプレートとの間隔は、前記高耐圧分離、前記高耐圧ＮｃｈＭＯＳ及び前記高耐圧ＰｃｈＭＯＳにおいて同じであることを特徴とする半導体装置。
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