CN109690770A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109690770A
CN109690770A CN201680089138.0A CN201680089138A CN109690770A CN 109690770 A CN109690770 A CN 109690770A CN 201680089138 A CN201680089138 A CN 201680089138A CN 109690770 A CN109690770 A CN 109690770A
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high voltage
circuit region
side circuit
nchmos
pchmos
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CN109690770B (zh
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吉野学
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Mitsubishi Electric Corp
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Abstract

RESURF分离构造包围高电位侧电路区域的外周，将高电位侧电路区域与低电位侧电路区域分离。RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS。高耐压分离部、高耐压NchMOS以及高耐压PchMOS具有多个场板(9、19a、19b、19c)。高耐压PchMOS的最靠低电位侧电路区域侧的场板(19c)的内端部与高耐压NchMOS的最靠低电位侧电路区域侧的场板(19b)的内端部相比位于低电位侧电路区域侧。

Description

半导体装置
技术领域
本发明涉及包含横向型高耐压元件的半导体装置。
背景技术
对构成半桥的功率芯片进行驱动的HVIC(High Voltage IC)具有低电位侧电路区域、高电位侧电路区域以及进行两者之间的信号传输的电平移位电路。低电位侧电路区域以衬底电位作为基准，高电位侧电路区域被高耐压地与衬底分离。高电位侧电路区域的相对于衬底电压的高耐压分离通过RESURF(Reduced SURface Field)效应而实现，在俯视观察时高电位侧电路区域的外周被RESURF分离构造包围(例如，参照专利文献1)。
电平移位电路具有高耐压NchMOS和高耐压PchMOS，该高耐压NchMOS从低电位侧电路区域向高电位侧电路区域进行信号传输，该高耐压PchMOS从高电位侧电路区域向低电位侧电路区域进行信号传输。高耐压NchMOS以及高耐压PchMOS具有与将高电位侧电路区域的外周包围的RESURF分离区域同等的耐压(例如，参照非专利文献1)，形成于将高电位侧电路区域的外周包围的同一RESURF分离构造内(例如，参照专利文献2以及非专利文献2)。
专利文献1：美国专利第4,292,642号说明书
专利文献2：日本专利第3917211号公报
非专利文献1：T.Terashima,M.Yoshizawa,M.Fukunaga and G.Majumdar,“Structure of 600V IC and A New Voltage Sensing Device”,5th InternationalSymposium on Power Semiconductor Devices&IC’s
非专利文献2：Kazuhiro Shimizu and Tomohide Terashima,“The 2ndGeneration divided RESURF structure for High Voltage ICs”,Proceedings of the20th International Symposium on Power Semiconductor Devices&IC’s May 18-22,2008Oralando,FL
发明内容
高耐压NchMOS通过将N型的RESURF区域完全耗尽化而保持高耐压。另一方面，高耐压PchMOS除了N型的RESURF区域之外，通过将表面的P型扩散层完全耗尽化而保持高耐压。因此，在从施加了高电压的时刻起至耗尽层在高耐压分离区域内扩展、完全耗尽化为止的期间，高耐压NchMOS和高耐压PchMOS都瞬态地流过泄漏电流。如果流过该瞬态的泄漏电流的期间长，则引起电平移位电路的误动作。
如果低电位侧的场板长，则在高耐压NchMOS的情况下耗尽化得到促进，瞬态地流过泄漏电流的期间变短，但在高耐压PchMOS的情况下P型扩散层的耗尽化受到阻碍，瞬态地流过泄漏电流的期间变长。因此，电平移位电路的高耐压PchMOS变得易于发生误动作。另一方面，如果缩短低电位侧的场板，则电平移位电路的高耐压NchMOS变得易于发生误动作。以往，由于高耐压NchMOS和高耐压PchMOS的场板构造相同，因此无法在高耐压NchMOS和高耐压PchMOS这两者缩短流过泄漏电流的期间。
本发明就是为了解决上述这样的课题而提出的，其目的在于得到如下半导体装置，即，能够使施加了高电压时瞬态地流过泄漏电流的期间在高耐压NchMOS和高耐压PchMOS这两者缩短，提高电平移位电路的误动作耐量。
本发明涉及的半导体装置，其特征在于，具备：高电位侧电路区域；低电位侧电路区域；以及RESURF分离构造，其包围所述高电位侧电路区域的外周，将所述高电位侧电路区域与所述低电位侧电路区域分离，所述RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS，所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS具有热氧化膜和多个场板，该多个场板形成在所述热氧化膜之上，所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板的内端部与所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板的内端部相比位于所述低电位侧电路区域侧。
发明的效果
在本发明中，高耐压PchMOS的最靠低电位侧电路区域侧的场板的内端部与高耐压NchMOS的最靠低电位侧电路区域侧的场板的内端部相比位于低电位侧电路区域侧。由此，能够使施加了高电压时瞬态地流过泄漏电流的期间在高耐压NchMOS和高耐压PchMOS这两者缩短，提高电平移位电路的误动作耐量。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的图。
图2是表示本发明的实施方式1涉及的电平移位电路的高耐压NchMOS的图。
图3是表示本发明的实施方式1涉及的电平移位电路的高耐压PchMOS的图。
图4是表示本发明的实施方式1涉及的半导体装置的高电位侧电路区域的俯视图。
图5是沿图4的I-II的高耐压分离部的剖面图。
图6是沿图4的III-IV的高耐压NchMOS的剖面图。
图7是沿图4的V-VI的高耐压PchMOS的剖面图。
图8是表示对比例涉及的半导体装置的高电位侧电路区域的俯视图。
图9是沿图8的I-II的高耐压分离部的剖面图。
图10是沿图8的III-IV的高耐压NchMOS的剖面图。
图11是沿图8的V-VI的高耐压PchMOS的剖面图。
图12是用于说明对比例涉及的高耐压NchMOS的耗尽化的剖面图。
图13是用于说明对比例涉及的高耐压NchMOS的耗尽化的剖面图。
图14是用于说明对比例涉及的高耐压PchMOS的耗尽化的剖面图。
图15是用于说明对比例涉及的高耐压PchMOS的耗尽化的剖面图。
图16是表示本发明的实施方式2涉及的半导体装置的高电位侧电路区域的俯视图。
图17是沿图16的I-II的高耐压分离部的剖面图。
图18是沿图16的III-IV的高耐压NchMOS的剖面图。
图19是沿图16的V-VI的高耐压PchMOS的剖面图。
图20是表示本发明的实施方式3涉及的半导体装置的高电位侧电路区域的俯视图。
图21是沿图20的I-II的高耐压分离部的剖面图。
图22是沿图20的III-IV的高耐压NchMOS的剖面图。
图23是沿图20的V-VI的高耐压PchMOS的剖面图。
图24是表示本发明的实施方式4涉及的半导体装置的高电位侧电路区域的俯视图。
图25是沿图24的I-II的高耐压分离部的剖面图。
图26是沿图24的III-IV的高耐压NchMOS的剖面图。
图27是沿图24的V-VI的高耐压PchMOS的剖面图。
图28是表示本发明的实施方式5涉及的半导体装置的高电位侧电路区域的俯视图。
图29是沿图28的I-II的高耐压分离部的剖面图。
图30是沿图28的III-IV的高耐压NchMOS的剖面图。
图31是沿图28的V-VI的高耐压PchMOS的剖面图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的图。该半导体装置是对构成半桥的功率芯片1、2进行驱动的HVIC(High VoltageIC)3。HVIC 3具有：高电位侧电路区域4，其驱动功率芯片1；低电位侧电路区域5，其驱动功率芯片2；以及电平移位电路6，其进行低电位侧电路区域5与高电位侧电路区域4之间的信号传输。
图2是表示本发明的实施方式1涉及的电平移位电路的高耐压NchMOS的图。从低电位侧电路区域5向高电位侧电路区域4的信号传输是通过电平移位电路6的高耐压NchMOS 7进行的。图3是表示本发明的实施方式1涉及的电平移位电路的高耐压PchMOS的图。从高电位侧电路区域4向低电位侧电路区域5的信号传输是通过高耐压PchMOS 8进行的。
图4是表示本发明的实施方式1涉及的半导体装置的高电位侧电路区域的俯视图。为了简单仅图示出一部分的结构。RESURF分离构造在俯视观察时包围高电位侧电路区域的外周，将高电位侧电路区域与低电位侧电路区域分离。RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS。低电位侧电路区域以衬底电位作为基准，高耐压分离部将高电位侧电路区域与衬底电位高耐压地分离。高耐压NchMOS以及高耐压PchMOS具有与高耐压分离部同等的耐压。螺旋状的多晶硅9是在RESURF分离构造中将高电位侧电路区域的外周包围的电阻体。
图5是沿图4的I-II的高耐压分离部的剖面图。在P型衬底10之上形成有P型外延层(未图示)，在P型外延层之上形成有作为RESURF区域的N型扩散层11a。到达至P型衬底10的P型扩散层12包围高电位侧电路区域以及N型扩散层11a。P型扩散层13a形成为与P型扩散层12的端部相比在内侧与P型扩散层12局部地重叠。N+型埋入扩散层14a形成为与P型扩散层13a的端部相比在内侧与P型外延层的下表面接触。在与P型扩散层12分离了一定的距离的N型扩散层11a的表面形成有N+型扩散层15a。在P型扩散层13a的表面的一部分形成有P+型扩散层16a。在P型扩散层12与N+型扩散层15a之间的N型扩散层11a的上表面形成有热氧化膜17。多晶硅18a、19a分离一定的距离而形成，以分别覆盖热氧化膜17的内端部和外端部。绝缘膜20形成为覆盖它们的表面。
金属配线层21、22形成在绝缘膜20之上。金属配线层21经过接触孔与N+型扩散层15a以及多晶硅18a电连接。金属配线层22经过贯通绝缘膜20的接触孔与P+型扩散层16a以及多晶硅19a电连接。
在绝缘膜20内形成有多晶硅9。多晶硅9的一端与金属配线层22电连接，另一端与金属配线层21电连接。杂质浓度以N+型埋入扩散层14a、P型扩散层12、N型扩散层11a、P型衬底10的顺序升高。N型扩散层11a满足RESURF条件。
图6是沿图4的III-IV的高耐压NchMOS的剖面图。高耐压NchMOS的N型扩散层11b与高耐压分离部的N型扩散层11a电分离(分离构造未图示。例如，参照专利文献2以及非专利文献2)。N+型埋入扩散层14b也与N+型埋入扩散层14a电分离。在P型扩散层12的表面的一部分形成有P+型扩散层23。在P型扩散层12与热氧化膜17之间的N型扩散层11b的表面形成有P型扩散层13b。在与P型扩散层12分离了一定的距离的N型扩散层11b的表面形成有N+型扩散层15b。在P型扩散层13b的表面的一部分形成有P+型扩散层16b以及N+型扩散层24。
多晶硅18b、19b分离一定的距离而形成在热氧化膜17之上，以分别覆盖热氧化膜17的内端部和外端部。多晶硅19b也隔着栅极氧化膜而形成在P型扩散层13b之上。在多晶硅18b、19b之间，在热氧化膜17之上形成有多晶硅9。
在绝缘膜20之上形成有金属配线层25、26、27、28。金属配线层25经过接触孔与N+型扩散层15b以及多晶硅18b电连接。金属配线层26经过接触孔与多晶硅19b电连接。金属配线层27经过接触孔与P+型扩散层16b以及N+型扩散层24电连接。金属配线层28经过贯通绝缘膜20的接触孔与P+型扩散层23电连接。金属配线层28还与金属配线层22电连接。
图7是沿图4的V-VI的高耐压PchMOS的剖面图。高耐压PchMOS的N型扩散层11c与高耐压分离部的N型扩散层11a电分离。N+型埋入扩散层14c也与N+型埋入扩散层14a电分离。在P型扩散层12与热氧化膜17之间，在N型扩散层11c的表面形成有P型扩散层13c。在P型扩散层13c的表面的一部分形成有P+型扩散层16c。在N型扩散层11c的表面以与热氧化膜17的下表面接触的方式形成有P型扩散层29。在与P型扩散层29分离了一定的距离的N型扩散层11c的表面形成有P+型扩散层30。相对于P型扩散层30在与P型扩散层29相反侧形成有N+型扩散层15c。
多晶硅18c、19c分离一定的距离而形成，以分别覆盖热氧化膜17的内端部和外端部。多晶硅18c在P型扩散层29与P型扩散层30之间隔着栅极氧化膜而形成于N型扩散层11c之上。在绝缘膜20之上形成有金属配线层31、32、33。金属配线层31经过接触孔与P+型扩散层30以及N+型扩散层15c电连接。金属配线层32经过接触孔与多晶硅18c电连接。金属配线层33经过贯通绝缘膜20的接触孔与P+型扩散层16c以及多晶硅19c电连接。
这里，高耐压分离部的多晶硅9、18a、19a、高耐压NchMOS的多晶硅9、18b、19b、高耐压PchMOS的多晶硅9、18c、19c分别是场板。
最靠低电位侧电路区域侧的场板即高耐压NchMOS的热氧化膜17之上的多晶硅19b的长度Ln、高耐压分离部的热氧化膜17之上的多晶硅19a的长度Li、高耐压PchMOS的热氧化膜17之上的多晶硅19c的长度Lp满足式(1)的关系。
Ln＝Li＞Lp(1)
因此，高耐压PchMOS的最靠低电位侧电路区域侧的场板即多晶硅19c的内端部与高耐压NchMOS的最靠低电位侧电路区域侧的场板即多晶硅19b的内端部相比位于低电位侧电路区域侧。
另外，高耐压PchMOS处的多个多晶硅9的间隔比高耐压NchMOS以及高耐压分离部处的多个多晶硅9的间隔宽。高耐压PchMOS处的多个多晶硅9的间隔也可以不固定。
接着，与对比例进行比较而说明本实施方式的效果。图8是表示对比例涉及的半导体装置的高电位侧电路区域的俯视图。图9是沿图8的I-II的高耐压分离部的剖面图。图10是沿图8的III-IV的高耐压NchMOS的剖面图。图11是沿图8的V-VI的高耐压PchMOS的剖面图。在对比例中，高耐压分离部、高耐压NchMOS以及高耐压PchMOS的场板构造相同(Ln＝Li＝Lp)。
高耐压NchMOS通过将N型扩散层11b完全耗尽化而保持高耐压。另一方面，高耐压PchMOS除了N型扩散层11c之外，通过将表面的P型扩散层29完全耗尽化而保持高耐压。因此，在从施加了高电压的时刻起至耗尽层在高耐压分离区域内扩展、完全耗尽化为止的期间，在高耐压NchMOS和高耐压PchMOS都瞬态地流过泄漏电流。如果流过该瞬态的泄漏电流的期间长，则引起电平移位电路6的误动作。
图12以及图13是用于说明对比例涉及的高耐压NchMOS的耗尽化的剖面图。图13与图12相比，最靠低电位侧电路区域侧的场板即多晶硅19b长，呈低电压的多晶硅19b向高电位侧电路区域侧凸出。因此，在对金属配线层25施加了高电压，对金属配线层26、27、28施加了低电压时，N型扩散层11b内的电子34向高电位侧的移动得到促进。其结果，耗尽化得到促进，瞬态地流过泄漏电流的期间变短。
图14以及图15是用于说明对比例涉及的高耐压PchMOS的耗尽化的剖面图。图15与图14相比，最靠低电位侧电路区域侧的场板即多晶硅19c长，呈低电压的多晶硅19c向高电位侧电路区域侧凸出。因此，在对金属配线层31、32施加了高电压，对金属配线层28、33施加了低电压时，P型扩散层29内的空穴35被拉拽到多晶硅19c之下。其结果，P型扩散层29的耗尽化受到阻碍，瞬态地流过泄漏电流的期间变长。
与此相对，在本实施方式中，由于高耐压NchMOS的最靠低电位侧电路区域侧的场板即多晶硅19b长，向高电位侧电路区域侧凸出，因此N型扩散层11b的耗尽化得到促进。另一方面，由于高耐压PchMOS的最靠低电位侧电路区域侧的场板即多晶硅19c短，其内端部与高耐压NchMOS的情况相比位于低电位侧电路区域侧，因此P型扩散层29的耗尽化得到促进。由此，能够使施加了高电压时瞬态地流过泄漏电流的期间在高耐压NchMOS和高耐压PchMOS这两者缩短，提高电平移位电路6的误动作耐量。
实施方式2.
图16是表示本发明的实施方式2涉及的半导体装置的高电位侧电路区域的俯视图。图17是沿图16的I-II的高耐压分离部的剖面图。图18是沿图16的III-IV的高耐压NchMOS的剖面图。图19是沿图16的V-VI的高耐压PchMOS的剖面图。
在本实施方式中，高耐压PchMOS以及高耐压分离部处的多个多晶硅9的间隔比高耐压NchMOS处的多个多晶硅9的间隔长。高耐压NchMOS的热氧化膜17之上的多晶硅19b的长度Ln、高耐压分离部的热氧化膜17之上的多晶硅19a的长度Li、高耐压PchMOS的热氧化膜17之上的多晶硅19c的长度Lp满足式(2)的关系。
Ln＞Li＝Lp···(2)
在本实施方式的结构中，也是高耐压PchMOS的最靠低电位侧电路区域侧的场板即多晶硅19c的内端部与高耐压NchMOS的最靠低电位侧电路区域侧的场板即多晶硅19b的内端部相比位于低电位侧电路区域侧。由此，能够得到与实施方式1同样的效果。
实施方式3.
图20是表示本发明的实施方式3涉及的半导体装置的高电位侧电路区域的俯视图。图21是沿图20的I-II的高耐压分离部的剖面图。图22是沿图20的III-IV的高耐压NchMOS的剖面图。图23是沿图20的V-VI的高耐压PchMOS的剖面图。
在本实施方式中，在高耐压分离部、高耐压NchMOS以及高耐压PchMOS，螺旋形状的多晶硅9的间隔相同。高耐压PchMOS处的多个多晶硅9与高耐压NchMOS处的多个多晶硅9相比配置在低电位侧电路区域侧。
在本实施方式的结构中，也是高耐压PchMOS的最靠低电位侧电路区域侧的场板即多晶硅19c的内端部与高耐压NchMOS的最靠低电位侧电路区域侧的场板即多晶硅19b的内端部相比位于低电位侧电路区域侧。由此，能够得到与实施方式1同样的效果。另外，由于无需将高耐压PchMOS的多个多晶硅9的间隔扩宽，因此能够对耐压稳定性的降低进行抑制。
实施方式4.
图24是表示本发明的实施方式4涉及的半导体装置的高电位侧电路区域的俯视图。图25是沿图24的I-II的高耐压分离部的剖面图。图26是沿图24的III-IV的高耐压NchMOS的剖面图。图27是沿图24的V-VI的高耐压PchMOS的剖面图。
在本实施方式中，与实施方式1同样地，高耐压PchMOS的最靠低电位侧电路区域侧的场板即多晶硅19c比高耐压NchMOS的最靠低电位侧电路区域侧的场板即多晶硅19b短。并且，将高耐压PchMOS的热氧化膜17之上的多晶硅19c向多晶硅18c侧平行移动，使两者的间隔与多晶硅18a、19a的间隔以及多晶硅18b、19b的间隔相同。即，最靠低电位侧电路区域侧的场板与最靠高电位侧电路区域侧的场板的间隔在高耐压分离部、高耐压NchMOS以及高耐压PchMOS处是相同的。将P型扩散层12、P+型扩散层23、P+型扩散层16c、P型扩散层13c、金属配线层33也以与多晶硅19c相同的长度向多晶硅18c侧平行移动。另外，P型扩散层29以及热氧化膜17的长度以多晶硅19c的移动长度的量而变短。
由此，能够使施加了高电压时瞬态地流过泄漏电流的期间在高耐压NchMOS和高耐压PchMOS这两者缩短，提高电平移位电路6的误动作耐量。
另外，通过在高耐压分离部、高耐压NchMOS以及高耐压PchMOS，使最靠低电位侧电路区域侧的场板与最靠高电位侧电路区域侧的场板的间隔相同，从而能够使螺旋形状的多晶硅9的位置相同。因此，能够仅以直线以及圆弧图案来形成螺旋形状的多晶硅9，布局设计变得容易。另外，能够使高耐压PchMOS的低电位侧的区域省空间化。
实施方式5.
图28是表示本发明的实施方式5涉及的半导体装置的高电位侧电路区域的俯视图。图29是沿图28的I-II的高耐压分离部的剖面图。图30是沿图28的III-IV的高耐压NchMOS的剖面图。图31是沿图28的V-VI的高耐压PchMOS的剖面图。
在本实施方式中，取代实施方式1的螺旋形状的多晶硅9，在热氧化膜17之上形成有彼此进行了电容耦合的多晶硅36和金属配线层37。在这种情况下，也能够得到与实施方式1同样的效果。
另外，由于多晶硅36与多晶硅18a、18b、18c、19a、19b、19c为同层，金属配线层37与金属配线层21、22、25、26、27、28、31、32、33为同层，因此能够分别同时地形成。因此，与实施方式1相比能够省略形成多晶硅9的工序。
此外，P型衬底10及其之上的半导体层不限于由硅形成，也可以由与硅相比带隙更大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或者金刚石。由上述这样的宽带隙半导体形成的功率半导体元件，由于耐电压性、容许电流密度高，因此能够小型化。通过使用该实现了小型化的元件，从而能够使组装有该元件的半导体模块也小型化。另外，由于元件的耐热性高，因此能够使散热器的散热鳍片小型化，能够将水冷部空冷化，因而能够进一步将半导体模块小型化。另外，由于元件的电力损耗低且高效，因此能够使半导体模块高效化。
标号的说明
4高电位侧电路区域，5低电位侧电路区域，7高耐压NchMOS，8高耐压PchMOS，9、18a、18b、18c、19a、19b、19c、36多晶硅，17热氧化膜，37金属配线层。
权利要求书(按照条约第19条的修改)
1.一种半导体装置，其特征在于，具备：
高电位侧电路区域；
低电位侧电路区域；以及
RESURF分离构造，其包围所述高电位侧电路区域的外周，将所述高电位侧电路区域与所述低电位侧电路区域分离，
所述RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS，
所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS具有热氧化膜和多个场板，该多个场板形成在所述热氧化膜之上，
所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板的内端部与所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板的内端部相比位于所述低电位侧电路区域侧。
2.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上的螺旋形状的多晶硅，
所述高耐压PchMOS处的所述螺旋形状的多晶硅的间隔比所述高耐压NchMOS处的所述螺旋形状的多晶硅的间隔宽。
3.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上的螺旋形状的多晶硅，
所述螺旋形状的多晶硅的间隔在所述高耐压PchMOS与所述高耐压NchMOS是相同的，
所述高耐压PchMOS处的所述螺旋形状的多晶硅与所述高耐压NchMOS处的所述螺旋形状的多晶硅相比配置在所述低电位侧电路区域侧。
4.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上而相互进行了电容耦合的多晶硅和金属配线层。
5.一种半导体装置，其特征在于，具备：
高电位侧电路区域；
低电位侧电路区域；以及
RESURF分离构造，其包围所述高电位侧电路区域的外周，将所述高电位侧电路区域与所述低电位侧电路区域分离，
所述RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS，
所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS具有热氧化膜和多个场板，该多个场板形成在所述热氧化膜之上，包含螺旋形状的多晶硅，
所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板的外端部与所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板的外端部相比位于所述高电位侧电路区域侧，
最靠所述低电位侧电路区域侧的场板与最靠所述高电位侧电路区域侧的场板之间的间隔在所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS是相同的。
说明或声明(按照条约第19条的修改)
对权利要求第5项进行修改，明确了以下内容，即，所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板的外端部与所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板的外端部相比位于所述高电位侧电路区域侧。本修改的根据是日文说明书的38～41段以及图24～27。

Claims (5)

1.一种半导体装置，其特征在于，具备：
高电位侧电路区域；
低电位侧电路区域；以及
RESURF分离构造，其包围所述高电位侧电路区域的外周，将所述高电位侧电路区域与所述低电位侧电路区域分离，
所述RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS，
所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS具有热氧化膜和多个场板，该多个场板形成在所述热氧化膜之上，
所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板的内端部与所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板的内端部相比位于所述低电位侧电路区域侧。
2.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上的螺旋形状的多晶硅，
所述高耐压PchMOS处的所述螺旋形状的多晶硅的间隔比所述高耐压NchMOS处的所述螺旋形状的多晶硅的间隔宽。
3.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上的螺旋形状的多晶硅，
所述螺旋形状的多晶硅的间隔在所述高耐压PchMOS与所述高耐压NchMOS是相同的，
所述高耐压PchMOS处的所述螺旋形状的多晶硅与所述高耐压NchMOS处的所述螺旋形状的多晶硅相比配置在所述低电位侧电路区域侧。
4.根据权利要求1所述的半导体装置，其特征在于，
所述多个场板具有形成在所述热氧化膜之上而相互进行了电容耦合的多晶硅和金属配线层。
5.一种半导体装置，其特征在于，具备：
高电位侧电路区域；
低电位侧电路区域；以及
RESURF分离构造，其包围所述高电位侧电路区域的外周，将所述高电位侧电路区域与所述低电位侧电路区域分离，
所述RESURF分离构造具有高耐压分离部、高耐压NchMOS以及高耐压PchMOS，
所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS具有热氧化膜和多个场板，该多个场板形成在所述热氧化膜之上，包含螺旋形状的多晶硅，
所述高耐压PchMOS的最靠所述低电位侧电路区域侧的场板比所述高耐压NchMOS的最靠所述低电位侧电路区域侧的场板短，
最靠所述低电位侧电路区域侧的场板与最靠所述高电位侧电路区域侧的场板之间的间隔在所述高耐压分离部、所述高耐压NchMOS以及所述高耐压PchMOS是相同的。
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