WO2018049640A1 - 一种具有体内场板的折叠型终端 - Google Patents

一种具有体内场板的折叠型终端 Download PDF

Info

Publication number
WO2018049640A1
WO2018049640A1 PCT/CN2016/099163 CN2016099163W WO2018049640A1 WO 2018049640 A1 WO2018049640 A1 WO 2018049640A1 CN 2016099163 W CN2016099163 W CN 2016099163W WO 2018049640 A1 WO2018049640 A1 WO 2018049640A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
type semiconductor
semiconductor
field
field plate
Prior art date
Application number
PCT/CN2016/099163
Other languages
English (en)
French (fr)
Inventor
任敏
张玉蒙
底聪
熊景枝
李泽宏
张金平
高巍
张波
Original Assignee
电子科技大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 电子科技大学 filed Critical 电子科技大学
Priority to CN201680057871.4A priority Critical patent/CN108292677B/zh
Priority to US15/774,286 priority patent/US10340332B2/en
Priority to PCT/CN2016/099163 priority patent/WO2018049640A1/zh
Publication of WO2018049640A1 publication Critical patent/WO2018049640A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure

Definitions

  • the invention belongs to the technical field of semiconductors and relates to a folding terminal structure having an in-field field plate.
  • the ability of a power device to block high voltage is primarily dependent on the reverse bias breakdown voltage of a particular PN junction in the device structure. All semiconductor devices are limited in size, and the wafer is diced into chips for packaging. The crystal lattice of the wafer is greatly damaged during the cutting process. For power devices, if the cut passes through a device structure that is subjected to high voltages, lattice damage can cause large leakage currents, which can reduce the breakdown voltage and long-term stability of the device. In power devices, due to the non-ideal factors of the PN junction bend or the termination of the PN junction, the reverse bias PN junction breakdown voltage is limited by the occurrence of a local region near the surface or the junction bend, which occurs earlier than the parallel plane junction in the body.
  • the breakdown phenomenon is a special structure specially designed to reduce the local electric field, increase the surface breakdown voltage and reliability, and make the actual breakdown voltage of the device closer to the ideal value of the parallel plane junction.
  • the longitudinal conducting device it is typically distributed around the active area of the device and is an adjunct structure of the PN junction in the active region for withstanding external high voltages.
  • a power semiconductor device fabricated by a planar process has a junction termination structure mainly provided with extension structures at the edge of the main junction (often curved), and these extension structures actually extend the main junction depletion region outward. Effect, thereby reducing the electric field strength within it and ultimately increasing the breakdown voltage, such as field plate (FP), field limiting ring (FLR), junction termination (JTE), laterally doped (VLD), resistive field plate (eg Oxygen-doped polysilicon (SIPOS), RESURF, and the like.
  • FP field plate
  • FLR field limiting ring
  • JTE junction termination
  • VLD laterally doped
  • resistive field plate eg Oxygen-doped polysilicon (SIPOS), RESURF, and the like.
  • the extension structure must be long enough to ensure adequate diffusion of the depletion zone. Therefore, in the high-voltage device, the area occupied by the existing extended terminal structure is too large, resulting in an increase in device cost.
  • the present invention has been made in view of the above problems, and proposes a terminal structure having an in-field field plate which has a smaller area than a conventional structure under the same withstand voltage.
  • the technical solution of the present invention is: a folded type terminal structure having an in-field field plate, comprising a first conductive type semiconductor heavily doped substrate 2, and a first conductive layer on the upper surface of the first conductive type semiconductor heavily doped substrate 2 a type semiconductor lightly doped drift region 3 and a metal drain electrode 1 located on a lower surface of the first conductive type semiconductor heavily doped substrate 2; wherein the first conductive type semiconductor lightly doped drift region 3 has a trench 4, the trench 4 is located in the middle of the first conductive type semiconductor lightly doped drift region 3, and extends vertically downward along the upper surface of the first conductive type semiconductor lightly doped drift region 3 into the first conductive type semiconductor lightly doped drift In the region 3, the trench 4 is filled with an insulating medium; the first conductive type is semiconductive The upper surface of the bulk lightly doped drift region 3 has a field oxide layer 10; the side of the trench 4 adjacent to the active region of the device has a first semiconductor implant region 6, and the first semiconductor implant region 6 is respectively associated with the active region
  • the polysilicon field plate 8 has an inverted trapezoidal shape in the cross-sectional view of the device, and the depth of the lower bottom side of the polysilicon field plate 8 is greater than the junction depth of the second semiconductor implantation region 5, and the angle between the side of the polysilicon field plate 8 and the horizontal line.
  • the value of ⁇ is between 60° and 70°.
  • the trench 4 has a second conductive type semiconductor buried layer 14 directly under the trench 4.
  • the lower surface of the trench 4 extends into the first conductive type semiconductor heavily doped substrate 2.
  • a sidewall of the trench 4 is disposed under the second semiconductor implant region 5 with a plurality of semiconductor doped regions whose doping concentration is sequentially lowered.
  • the upper layer of the first conductive type semiconductor lightly doped drift region 3 has a main junction 7 of a second conductive type semiconductor in contact with the first semiconductor implant region 6, the second conductive type An end of the upper surface of the main junction 7 of the semiconductor remote from the termination region has a source metal 11 which is in contact with the field oxide layer 10.
  • the main junction 7 of the second conductivity type semiconductor is connected to the polysilicon layer 9 through a contact hole.
  • the source metal 11 extends along the upper surface of the field oxide layer 10 to be connected to the polysilicon layer 9, and the potential of the source is connected to the polysilicon field plate 8.
  • the trench 4 has a second conductive type semiconductor buried layer 14 directly under the trench 4.
  • the invention has the beneficial effects that, compared with the conventional structure, the present invention folds the field plate structure and the junction terminal extension region into the device interior, and can fully utilize the thickness of the drift region in the body, thereby reducing the lateral area of the terminal and alleviating the electric field at the termination end of the PN junction. Concentration, the position of the breakdown point is transferred from the terminating end of the original PN junction to the body, and the withstand voltage of the terminal can reach the breakdown voltage of the parallel plane junction; therefore, the terminal of the folding terminal structure with the in-field field plate proposed by the present invention is provided. The efficiency is much higher than the conventional junction terminal extension structure.
  • Embodiment 1 is a schematic structural view of Embodiment 1;
  • FIG. 2 is a schematic diagram of a depletion line of a conventional planar junction termination structure when a drain terminal is applied with a high voltage
  • FIG. 3 is a cross-sectional view showing formation of a light-doped region 5 of a second conductive type semiconductor material after high energy ion implantation in the manufacturing process of Embodiment 1;
  • FIG. 4 is a cross-sectional view showing formation of a lightly doped region 6 of a second conductive type semiconductor material after ion implantation in the manufacturing process of Embodiment 1;
  • FIG. 5 is a cross-sectional view showing ion implantation in an active region in the manufacturing process of Embodiment 1 to form a doped region 7 of a second conductivity type semiconductor material;
  • FIG. 6 is a cross-sectional view showing the formation of a heavily doped region 13 of a first conductivity type semiconductor material after ion implantation in a termination region in the manufacturing process of Embodiment 1;
  • Figure 7 is a cross-sectional view showing the growth of a field oxide layer on the surface of the device in the manufacturing process of Example 1;
  • FIG. 8 is a cross-sectional view showing a trench etched in a termination region in a manufacturing process of Embodiment 1 and filled with an insulating medium in the trench;
  • 9 is a trench in which the inverted trapezoid is etched in the termination region in the manufacturing process of the first embodiment, and the oxide layer on the upper surface of the doped region 7 of the second conductive type semiconductor material in the active region is etched away, and in the trench and the device. a cross-sectional view of the surface after depositing polysilicon;
  • Figure 10 is a schematic structural view of Embodiment 2.
  • Figure 11 is a schematic structural view of Embodiment 3.
  • Figure 12 is a schematic structural view of Embodiment 4.
  • Figure 13 is a schematic structural view of Embodiment 5.
  • Figure 14 is a schematic structural view of Embodiment 6;
  • Figure 15 is a schematic view showing the structure of Embodiment 7.
  • the terminal structure of the present embodiment has an in-field field plate, including a first conductive type semiconductor heavily doped substrate 2. a first conductive type semiconductor lightly doped drift region 3 located on an upper surface of the first conductive type semiconductor heavily doped substrate 2 and a metal drain electrode 1 located on a lower surface of the first conductive type semiconductor heavily doped substrate 2;
  • the first conductive type semiconductor lightly doped drift region 3 has a trench 4 therein, the trench 4 is located in the middle of the first conductive type semiconductor lightly doped drift region 3, and is lightly doped and drifted along the first conductive type semiconductor
  • the upper surface of the region 3 extends vertically downward into the first conductive type semiconductor lightly doped drift region 3, the trench 4 is filled with an insulating medium; the upper surface of the first conductive type semiconductor lightly doped drift region 3 has a field The oxide layer 10;
  • the trench 4 has a first semiconductor implant region 6 on a side close to the active region of the device, and the first semiconductor implant region 6 and the second conductive type semiconductor device main junction 7 and the trench
  • the inverted trapezoid is formed, and the junction depth of the lower bottom side of the polysilicon field plate 8 is greater than the junction depth of the second semiconductor implantation region 5.
  • the angle ⁇ between the side of the polysilicon field plate 8 and the horizontal line is between 60° and 70°.
  • the doped region 3 is directed to the main junction 5 of the second conductivity type semiconductor material, the second conductivity type semiconductor material lightly doped region 6 and the second conductivity type semiconductor material lighter doped region 7.
  • This structure can greatly improve the electric field concentration at the edge of the main junction 5 and increase the breakdown voltage.
  • the light-doped region 6 of the second conductive type semiconductor material and the lightly doped region 7 of the second conductive type semiconductor material are all spread on the surface of the semiconductor, a large area is required.
  • a trench is formed on the side of the main junction 5 of the second conductive type semiconductor material, and a second conductivity type implant region 6 and a second conductivity type implant are sequentially formed on the side of the trench to reduce the doping concentration.
  • the junction terminal extension region is led from the surface to the body, and the terminal electric field is expanded by using the thickness of the first conductivity type semiconductor lightly doped drift region 3, thereby effectively saving the surface area.
  • the second conductivity type implant region 6 and the second conductivity type implant region 5 constitute a junction termination extension (JTE) region.
  • JTE region charge must be precisely controlled to maximize the breakdown voltage. If the charge amount is too small, the effect on the electric field is limited. If the charge amount in the JTE region is too large, the radius of curvature of the edge of the depletion region is too small, and the breakdown voltage is also lowered. Therefore, the charge in the JTE region should be completely depleted by the reverse bias.
  • the trench region 4 is trenched and filled with polysilicon as a field plate, and the lower edge of the field plate exceeds the lower surface of the lighter doped region 5 of the second conductive type semiconductor material, the field plate and the second conductive type semiconductor.
  • the main junction 7 of the material is connected by polysilicon. Therefore, the field plate is equipotential to the main junction 7, and the depletion region boundary can be further extended toward the body of the first conductivity type semiconductor lightly doped region 3.
  • Another advantage of the field plate is that it can shield the effect of charge on the terminal electric field in the oxide layer. The additional charge is easily introduced in the trench etching and field oxygen growth processes, and the reliability of the terminal structure proposed by the present invention is also improved due to the presence of the field plate.
  • an electric field exhibits a large value at the end of the field plate because the potential difference across the oxide layer at the end of the field plate is maximized when the field oxygen thickness is constant.
  • the trench is engraved into an inverted trapezoid when etching the polysilicon field plate 8, which makes the thickness of the silicon dioxide layer in the longitudinal direction from the lightly doped drift region of the first conductive type semiconductor.
  • the surface of 3 is gradually increased in the body, ensuring that the device does not break down prematurely because of the excessive electric field at the end of the field plate.
  • the angle ⁇ between the side wall of the polysilicon field plate 8 and the horizontal direction is a key parameter.
  • the excessively large angle makes the thickness of the silicon dioxide layer less obvious, that is, the effect of slowing down the electric field at the end of the field plate is not obvious.
  • too small an angle will make the area of the terminal too large, which may cause unnecessary waste.
  • the value of ⁇ is more suitable between 60° and 70°.
  • the process manufacturing process of this example is:
  • the impurity atoms are bonded to the silicon atoms in the crystal lattice, as shown in FIG. 4;
  • Photolithographically active regions are formed and ion implantation is performed to form a doped region 7 of a second conductivity type semiconductor material. And through the thermal propulsion process, the p-type semiconductor material doped region 7 reaches a certain junction depth, and is activated at a high temperature, as shown in FIG. 5;
  • the structure of the present example is such that, on the basis of Embodiment 1, the buried layer 14 of the second conductive type semiconductor material is added directly under the trench 4, which can slow down the electric field concentration at the corner of the trench and further improve Pressure resistance.
  • the structure of the present embodiment is such that, on the basis of Embodiment 1, a second conductive type lightly doped region having a lower doping concentration is formed along the sidewall directly under the second conductivity type implant region 5. 14, can enhance the effect of JTE.
  • the structure of the present embodiment is such that, on the basis of Embodiment 1, the trench 4 is dug into the body of the first conductive type semiconductor heavily doped region 2, and the withstand voltage is increased by increasing the thickness of the insulating dielectric layer. .
  • the structure of this example is such that, on the basis of Embodiment 1, the connection of the polysilicon field plate and the main junction 7, that is, polysilicon is used as the floating field plate.
  • the structure of this example is based on Embodiment 1, the source metal 11 is connected to the polysilicon interconnection 9 through a contact hole, and the potential of the source is connected to the polysilicon field plate.
  • the structure of this example is such that, on the basis of Embodiment 1, an oxide layer is deposited on the polysilicon field plate 8, and the polysilicon field plate is floated.
  • the semiconductor material may be replaced by a semiconductor material such as silicon carbide, gallium arsenide, indium phosphide or germanium silicon in the fabrication of the device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种具有体内场板的折叠型终端，将场板结构和结终端扩展区向器件内部折叠，充分利用体内漂移区厚度，从而缩小终端的横向面积，缓解了PN结终止端的电场集中，击穿点的位置从原来的PN结的终止端转移到了体内，终端的耐压能达到平行平面结的击穿电压。采用该结构能够在相同耐压的情况下获得比常规结构更小的面积。

Description

一种具有体内场板的折叠型终端 技术领域
本发明属于半导体技术领域，涉及一种具有体内场板的折叠型终端结构。
背景技术
功率器件阻断高压的能力主要取决于器件结构中特定PN结的反偏击穿电压。所有半导体器件的尺寸都是有限的，将晶圆切割成芯片进行封装制成器件。切割过程中会对硅片的晶格造成很大的损伤。对于功率器件而言，如果切割穿过了承受高压的器件结构区，晶格损伤会引起很大的漏电流，这会降低器件的击穿电压和长期稳定性。在功率器件中,受PN结弯曲或PN结终止处表面非理想因素的影响,反偏PN结击穿电压又受限于发生在表面附近或结弯曲处局部区域相对于体内平行平面结提前出现的击穿现象。结终端就是为了减小局部电场、提高表面击穿电压及可靠性、使器件实际击穿电压更接近平行平面结理想值而专门设计的特殊结构。在纵向导电器件中它通常分布在器件有源区的周边,是有源区内用于承受外高压的PN结的附属结构。
目前，采用平面工艺制作的功率半导体器件，其结终端结构主要是在主结边缘处(常是弯曲的)设置一些延伸结构,这些延伸结构实际上起到将主结耗尽区向外展宽的作用,从而降低其内的电场强度最终提高击穿电压,如场板(FP)、场限环(FLR)、结终端扩展(JTE)、横向变掺杂(VLD)、阻性场板(如掺氧多晶硅(SIPOS))、RESURF等。要实现高的耐压，延伸结构必须足够长，以保证耗尽区充分扩散。因此，在高压器件中，现有的延伸型终端结构所占用面积都太大，造成器件成本的上升。
发明内容
本发明所要解决的，就是针对上述问题，提出一种在相同耐压的情况下获得比常规结构更小的面积的具有体内场板的终端结构。
本发明的技术方案是：一种具有体内场板的折叠型终端结构，包括第一导电类型半导体重掺杂衬底2、位于第一导电类型半导体重掺杂衬底2上表面的第一导电类型半导体轻掺杂漂移区3和位于第一导电类型半导体重掺杂衬底2下表面的金属漏电极1；其特征在于，所述第一导电类型半导体轻掺杂漂移区3中具有沟槽4，所述沟槽4位于第一导电类型半导体轻掺杂漂移区3中部，并沿第一导电类型半导体轻掺杂漂移区3上表面垂直向下延伸入第一导电类型半导体轻掺杂漂移区3中，所述沟槽4中填充有绝缘介质；所述第一导电类型半导 体轻掺杂漂移区3上表面具有场氧化层10；所述沟槽4靠近器件有源区的一侧具有第一半导体注入区6，所述第一半导体注入区6分别与有源区的第二导电类型半导体主结7和沟槽4接触，第一半导体注入区6的上表面与场氧化层10接触；所述第一半导体注入区6的下表面连接有第二半导体注入区5，所述第二半导体注入区5的侧面与沟槽4接触；所述第一半导体注入区6与第二半导体注入区5为第二导电类型半导体，且第一半导体注入区6的掺杂浓度大于第二半导体注入区5；所述第一导电类型半导体轻掺杂漂移区3上层远离器件有源区的一端具有第一导电类型半导体的重掺杂区13，所述第一导电类型半导体的重掺杂区13的上表面与场氧化层10接触；所述场氧化层10的上表面具有多晶硅层9；所述沟槽4中具有多晶硅场板8，所述多晶硅场板8的上表面与多晶硅层9接触。
进一步的，多晶硅场板8在器件的剖面图中呈倒梯形，且多晶硅场板8下底边的深度大于第二半导体注入区5的结深，多晶硅场板8的侧边与水平线的夹角θ的取值在60°到70°之间。
进一步的，所述沟槽4的正下方具有第二导电类型半导体埋层14。
进一步的，所述沟槽4的下表面延伸至第一导电类型半导体重掺杂衬底2中。
进一步的，所述第二半导体注入区5下方沿沟槽4的侧壁还设置有多个掺杂浓度依次降低的半导体掺杂区。
进一步的，所述器件有源区中，在第一导电类型半导体轻掺杂漂移区3上层具有与第一半导体注入区6接触的第二导电类型半导体的主结7，所述第二导电类型半导体的主结7上表面远离终端区的一端具有源极金属11，所述源极金属11与场氧化层10接触。
进一步的，所述第二导电类型半导体的主结7通过接触孔与多晶硅层9连接。
进一步的，所述源极金属11沿场氧化层10上表面延伸至与多晶硅层9连接，将源极的电位接到多晶硅场板8上。
进一步的，所述沟槽4的正下方具有第二导电类型半导体埋层14。
本发明的有益效果为，相对于传统结构，本发明将场板结构和结终端扩展区向器件内部折叠，可以充分利用体内漂移区厚度，从而缩小终端的横向面积，缓解了PN结终止端的电场集中，击穿点的位置从原来的PN结的终止端转移到了体内，终端的耐压能达到平行平面结的击穿电压；因此，本发明提出的具有体内场板的折叠式终端结构的终端效率要远高于常规的结终端扩展结构。
附图说明
图1为实施例1的结构示意图；
图2为常规平面型结终端扩展结构在漏端加高电压时，耗尽线示意图；
图3为实施例1制造流程中高能离子注入后形成第二导电类型半导体材料轻掺杂区5的剖视图；
图4为实施例1制造流程中离子注入后形成第二导电类型半导体材料轻掺杂区6的剖视图；
图5为实施例1制造流程中在有源区进行离子注入形成第二导电类型半导体材料掺杂区7的剖视图；
图6为实施例1制造流程中终端区经过离子注入后形成第一导电类型半导体材料重掺杂区13的剖视图；
图7为实施例1制造流程中在器件表面生长一层场氧化层后的剖视图；
图8为实施例1制造流程中在终端区刻蚀出沟槽，并在槽中填充绝缘介质后的剖视图；
图9为实施例1制造流程中在终端区刻蚀出倒梯形的槽，同时将有源区第二导电类型半导体材料掺杂区7上表面的氧化层刻蚀掉，并在槽中及器件表面淀积多晶硅后的剖视图；
图10是实施例2的结构示意图；
图11是实施例3的结构示意图；
图12是实施例4的结构示意图；
图13是实施例5的结构示意图；
图14是实施例6的结构示意图；
图15是实施例7的结构示意图。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图1所示，本例的具有体内场板的终端结构，包括第一导电类型半导体重掺杂衬底2、 位于第一导电类型半导体重掺杂衬底2上表面的第一导电类型半导体轻掺杂漂移区3和位于第一导电类型半导体重掺杂衬底2下表面的金属漏电极1；其特征在于，所述第一导电类型半导体轻掺杂漂移区3中具有沟槽4，所述沟槽4位于第一导电类型半导体轻掺杂漂移区3中部，并沿第一导电类型半导体轻掺杂漂移区3上表面垂直向下延伸入第一导电类型半导体轻掺杂漂移区3中，所述沟槽4中填充有绝缘介质；所述第一导电类型半导体轻掺杂漂移区3上表面具有场氧化层10；所述沟槽4靠近器件有源区的一侧具有第一半导体注入区6，所述第一半导体注入区6分别与有源区的第二导电类型半导体器件主结7和沟槽4接触，第一半导体注入区6的上表面与场氧化层10接触；所述第一半导体注入区6的下表面连接有第二半导体注入区5，所述第二半导体注入区5的侧面与沟槽4接触；所述第一半导体注入区6与第二半导体注入区5为第二导电类型半导体，且第一半导体注入区6的掺杂浓度大于第二半导体注入区5；所述第一导电类型半导体轻掺杂漂移区3上层远离器件有源区的一端具有第一导电类型半导体的重掺杂区13，所述第一导电类型半导体的重掺杂区13的上表面与场氧化层10接触；所述场氧化层10的上表面具有多晶硅层9；所述沟槽4中具有多晶硅场板8，所述多晶硅场板8的上表面与多晶硅层9接触；多晶硅场板8在器件的剖面图中呈倒梯形，且多晶硅场板8下底边的结深大于第二半导体注入区5的结深，多晶硅场板8的侧边与水平线的夹角θ的取值在60°到70°之间。
以第一导电类型半导体为P型半导体为例，说明本例的工作原理和制造方法。
图2为常规平面型结终端扩展结构，当功率器件处于反向阻断状态时，在漏极金属1上接正偏压，源极金属8上接零电位，电场由第一导电类型半导体轻掺杂区3指向第二导电类型半导体材料的主结5、第二导电类型半导体材料轻掺杂区6以及第二导电类型半导体材料更轻掺杂区7。该结构能极大的改善主结5边缘处的电场集中，提高击穿电压。但是，由于第二导电类型半导体材料轻掺杂区6以及第二导电类型半导体材料更轻掺杂区7均在半导体表面展开，需要较大的面积。
本例相比与传统结构，在第二导电类型半导体材料的主结5的侧面挖一沟槽，在沟槽侧面形成掺杂浓度依次降低的第二导电类型注入区6和第二导电类型注入区5，将结终端扩展区从表面引向体内，利用第一导电类型半导体轻掺杂漂移区3的厚度来扩展终端电场，有效节省了表面积。第二导电类型注入区6和第二导电类型注入区5构成结终端扩展(JTE)区。必须精确控制JTE区电荷来最大化击穿电压，如果电荷量过小，对电场的影响有限，如果JTE区的电荷量过大，耗尽区边缘曲率半径过小，击穿电压也会降低。因此，JTE区的电荷应正好被反向偏压完全耗尽。
同时，本例在沟槽区4的内部挖槽并填充多晶硅作为场板，场板的下边缘超过第二导电类型半导体材料更轻掺杂区5的下表面，场板与第二导电类型半导体材料的主结7通过多晶硅相连。因此，场板与主结7等电位，可以进一步将耗尽区边界向第一导电类型半导体轻掺杂区3的体内延伸。场板的另一个优点是可以屏蔽氧化层中电荷对终端电场的影响。沟槽刻蚀和场氧生长工艺中极易带来附加电荷，由于有场板的存在，本发明提出的终端结构的可靠性也得到了提高。
常规的场板结构中电场在场板的末端会出现一个较大的值，这是由于在场氧厚度一定的情况下场板末端的氧化层两端的电势差是最大的。为了减小该处的电场，本例中在刻蚀多晶硅场板8的时候将槽刻成倒梯形，这就使得在纵向上二氧化硅层的厚度从第一导电类型半导体轻掺杂漂移区3的表面向体内是逐渐增加的，保证了不会因为场板的末端电场过大而导致器件提前击穿。多晶硅场板8的侧壁与水平方向的夹角角度θ是一个关键参数。一方面，过大的角度使得二氧化硅层厚度增加得不明显，即减缓场板末端电场的作用不明显。另一方面，过小的角度会使终端的面积过大，容易造成不必要的浪费。综上，θ的取值在60°到70°之间较为合适。
本例的工艺制造流程为：
(1)在N+衬底上外延生长N—掺杂浓度的漂移区，然后在硅片表面生长一层薄的预氧化层；
(2)通过高能离子注入在终端区内部形成第二导电类型半导体轻掺杂区5，如图3所示；
(3)在终端区进行光刻，并进行离子注入，在终端区形成第二导电类型半导体材料轻掺杂区6，之后通过高温推进过程使得轻掺杂区6与轻掺杂区5刚好接触。紧接着进行高温激活，使得杂质原子与晶格中的硅原子键合，如图4所示；
(4)光刻有源区，并进行离子注入，形成第二导电类型半导体材料掺杂区7。并通过热推进过程使得p型半导体材料掺杂区7达到一定的结深，并进行高温激活，如图5所示；
(5)在终端区进行光刻，并进行离子注入，形成第一导电类型半导体材料重掺杂区8，如图6所示；
(6)在硅片表面生长场氧化层10，如图7所示；
(7)在终端区刻蚀出一个的矩形槽4，并在槽中填充绝缘介质，如图8所示；
(8)在终端区刻蚀出倒梯形的槽，同时将有源区第二导电类型半导体材料掺杂区7表面 的氧化层刻蚀掉，并在槽中及器件表面淀积多晶硅，如图9所示；
(9)刻蚀形成接触孔，进行低能量高剂量的硼离子注入，在接触孔内形成P+接触区；淀积金属，并反刻金属，形成源电极。对硅片背面减薄，金属化形成漏极金属，如图1所示。
实施例2
如图10所示，本例的结构为在实施例1的基础上，在沟槽4的正下方增加第二导电类型半导体材料的埋层14，可以减缓沟槽拐角处的电场集中，进一步提升耐压能力。
实施例3
如图11所示，本例的结构为在实施例1的基础上，在第二导电类型注入区5正下方沿着侧壁再形成一个掺杂浓度更低的第二导电类型轻掺杂区14，可以增强JTE的效果。
实施例4
如图12所示，本例的结构为在实施例1的基础上，将沟槽4一直挖到第一导电类型半导体重掺杂区2的体内，通过增加绝缘介质层的厚度来提高耐压。
实施例5
如图13所示，本例的结构为在实施例1的基础上，取消多晶硅场板和主结7的连接，即多晶硅作为浮空场板。
实施例6
如图14所示，本例的结构为在实施例1的基础上，源极金属11通过接触孔和多晶硅互连9相连，将源极的电位接到多晶硅场板上。
实施例7
如图15所示，本例的结构为在实施例1的基础上，在多晶硅场板8上面淀积一层氧化层，多晶硅场板浮空。
以上实施例中，制作器件时还可用碳化硅、砷化镓、磷化铟或锗硅等半导体材料代替体硅。

Claims (9)

  1. 一种具有体内场板的折叠型终端，包括第一导电类型半导体重掺杂衬底(2)、位于第一导电类型半导体重掺杂衬底(2)上表面的第一导电类型半导体轻掺杂漂移区(3)和位于第一导电类型半导体重掺杂衬底(2)下表面的金属漏电极(1)；其特征在于，所述第一导电类型半导体轻掺杂漂移区(3)中具有沟槽(4)，所述沟槽(4)位于第一导电类型半导体轻掺杂漂移区(3)中部，并沿第一导电类型半导体轻掺杂漂移区(3)上表面垂直向下延伸入第一导电类型半导体轻掺杂漂移区(3)中，所述沟槽(4)中填充有绝缘介质；所述第一导电类型半导体轻掺杂漂移区(3)上表面具有场氧化层(10)；所述沟槽(4)靠近器件有源区的一侧具有第一半导体注入区(6)，所述第一半导体注入区(6)分别与有源区的第二导电类型半导体主结(7)和沟槽(4)接触，第一半导体注入区(6)的上表面与场氧化层(10)接触；所述第一半导体注入区(6)的下表面连接有第二半导体注入区(5)，所述第二半导体注入区(5)的侧面与沟槽(4)接触；所述第一半导体注入区(6)与第二半导体注入区(5)为第二导电类型半导体，且第一半导体注入区(6)的掺杂浓度大于第二半导体注入区(5)；所述第一导电类型半导体轻掺杂漂移区(3)上层远离器件有源区的一端具有第一导电类型半导体的重掺杂区(13)，所述第一导电类型半导体的重掺杂区(13)的上表面与场氧化层(10)接触；所述场氧化层(10)的上表面具有多晶硅层(9)；所述沟槽(4)中具有多晶硅场板(8)，所述多晶硅场板(8)的上表面与多晶硅层(9)接触。
  2. 根据权利要求1所述的一种具有体内场板的折叠型终端，其特征在于，多晶硅场板(8)在器件的剖面图中呈倒梯形，且多晶硅场板(8)下底边的结深大于第二半导体注入区(5)的结深，多晶硅场板(8)的侧边与水平线的夹角θ的取值在60°到70°之间。
  3. 根据权利要求2所述的一种具有体内场板的折叠型终端，其特征在于，所述沟槽(4)的正下方具有第二导电类型半导体埋层(14)。
  4. 根据权利要求2所述的一种具有体内场板的折叠型终端，其特征在于，所述沟槽(4)的下表面延伸至第一导电类型半导体重掺杂衬底(2)中。
  5. 根据权利要求4所述的一种具有体内场板的折叠型终端，其特征在于，所述第二半导体注入区(5)下方沿沟槽(4)的侧壁还设置有多个掺杂浓度依次降低的半导体掺杂区。
  6. 根据权利要求2-5任意一项所述的一种具有体内场板的折叠型终端，其特征在于，所述器件有源区中，在第一导电类型半导体轻掺杂漂移区(3)上层具有与第一半导体注入区(6)接触的第二导电类型半导体的主结(7)，所述第二导电类型半导体的主结(7)上表面远离终端区的一端具有源极金属(11)，所述源极金属(11)与场氧化层(10)接触。
  7. 根据权利要求6所述的一种具有体内场板的折叠型终端，其特征在于，所述第二导电类型半导体的主结(7)通过接触孔与多晶硅层(9)连接。
  8. 根据权利要求7所述的一种具有体内场板的折叠型终端，其特征在于，所述源极金属(11)沿场氧化层(10)上表面延伸至与多晶硅层(9)连接，将源极的电位接到多晶硅场板(8)上。
  9. 根据权利要求5-7任意一项所述的一种具有体内场板的折叠型终端，其特征在于，所述沟槽(4)的正下方具有第二导电类型半导体埋层(14)。
PCT/CN2016/099163 2016-09-17 2016-09-17 一种具有体内场板的折叠型终端 WO2018049640A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201680057871.4A CN108292677B (zh) 2016-09-17 2016-09-17 一种具有体内场板的折叠型终端
US15/774,286 US10340332B2 (en) 2016-09-17 2016-09-17 Folded termination with internal field plate
PCT/CN2016/099163 WO2018049640A1 (zh) 2016-09-17 2016-09-17 一种具有体内场板的折叠型终端

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/099163 WO2018049640A1 (zh) 2016-09-17 2016-09-17 一种具有体内场板的折叠型终端

Publications (1)

Publication Number Publication Date
WO2018049640A1 true WO2018049640A1 (zh) 2018-03-22

Family

ID=61618613

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/099163 WO2018049640A1 (zh) 2016-09-17 2016-09-17 一种具有体内场板的折叠型终端

Country Status (3)

Country Link
US (1) US10340332B2 (zh)
CN (1) CN108292677B (zh)
WO (1) WO2018049640A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598151A (zh) * 2018-05-28 2018-09-28 江苏捷捷微电子股份有限公司 能提高耐压能力的半导体器件终端结构及其制造方法
CN109103248A (zh) * 2018-08-23 2018-12-28 深圳市南硕明泰科技有限公司 一种功率器件终端结构及其制备方法
CN110931548A (zh) * 2019-12-16 2020-03-27 安建科技(深圳)有限公司 一种半导体器件结构及其制造方法
CN113823679A (zh) * 2021-11-23 2021-12-21 成都蓉矽半导体有限公司 栅控二极管整流器
WO2023133925A1 (zh) * 2022-01-17 2023-07-20 中国电子科技集团公司第二十四研究所 功率半导体器件及其制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109103260A (zh) * 2018-08-23 2018-12-28 深圳市南硕明泰科技有限公司 功率器件
US11158703B2 (en) * 2019-06-05 2021-10-26 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating same
CN111755504B (zh) * 2020-07-13 2024-02-23 电子科技大学 一种横向变掺杂终端结构及设计方法和制备方法
CN112382653B (zh) * 2020-07-13 2024-02-23 电子科技大学 横向变掺杂终端结构及设计方法和制备方法
CN113299745B (zh) * 2021-06-10 2022-04-15 珠海市浩辰半导体有限公司 一种终端结构、半导体器件及制作方法
CN113299744B (zh) * 2021-06-10 2022-04-15 珠海市浩辰半导体有限公司 一种终端结构、半导体器件及制作方法
CN114496802B (zh) * 2022-04-14 2022-06-24 北京智芯微电子科技有限公司 Ldmosfet器件的制作方法及ldmosfet器件
CN117116974A (zh) * 2023-08-31 2023-11-24 海信家电集团股份有限公司 半导体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101894865A (zh) * 2009-05-21 2010-11-24 中芯国际集成电路制造(北京)有限公司 碰撞电离金属氧化物半导体晶体管及制造方法
CN102254931A (zh) * 2011-07-14 2011-11-23 西安理工大学 一种浅槽负斜角终端结构及其制备方法
CN103094324A (zh) * 2011-11-08 2013-05-08 无锡华润上华半导体有限公司 沟槽型绝缘栅双极型晶体管及其制备方法
CN104992976A (zh) * 2015-05-21 2015-10-21 电子科技大学 一种vdmos器件及其制造方法
CN105047721A (zh) * 2015-08-26 2015-11-11 国网智能电网研究院 一种碳化硅沟槽栅功率MOSFETs器件及其制备方法
WO2016042330A1 (en) * 2014-09-17 2016-03-24 Anvil Semiconductors Limited High voltage semiconductor devices
CN105932051A (zh) * 2016-07-04 2016-09-07 电子科技大学 一种槽栅mosfet器件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4097417B2 (ja) * 2001-10-26 2008-06-11 株式会社ルネサステクノロジ 半導体装置
DE102007061191B4 (de) * 2007-12-17 2012-04-05 Infineon Technologies Austria Ag Halbleiterbauelement mit einem Halbleiterkörper
WO2010008617A1 (en) * 2008-07-15 2010-01-21 Maxpower Semiconductor Inc. Mosfet switch with embedded electrostatic charge
CN102969358B (zh) * 2012-12-06 2015-08-19 电子科技大学 一种横向高压功率半导体器件
CN103022134B (zh) * 2012-12-06 2015-09-09 电子科技大学 一种超低比导通电阻的soi横向高压功率器件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101894865A (zh) * 2009-05-21 2010-11-24 中芯国际集成电路制造(北京)有限公司 碰撞电离金属氧化物半导体晶体管及制造方法
CN102254931A (zh) * 2011-07-14 2011-11-23 西安理工大学 一种浅槽负斜角终端结构及其制备方法
CN103094324A (zh) * 2011-11-08 2013-05-08 无锡华润上华半导体有限公司 沟槽型绝缘栅双极型晶体管及其制备方法
WO2016042330A1 (en) * 2014-09-17 2016-03-24 Anvil Semiconductors Limited High voltage semiconductor devices
CN104992976A (zh) * 2015-05-21 2015-10-21 电子科技大学 一种vdmos器件及其制造方法
CN105047721A (zh) * 2015-08-26 2015-11-11 国网智能电网研究院 一种碳化硅沟槽栅功率MOSFETs器件及其制备方法
CN105932051A (zh) * 2016-07-04 2016-09-07 电子科技大学 一种槽栅mosfet器件

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598151A (zh) * 2018-05-28 2018-09-28 江苏捷捷微电子股份有限公司 能提高耐压能力的半导体器件终端结构及其制造方法
CN108598151B (zh) * 2018-05-28 2024-02-02 江苏捷捷微电子股份有限公司 能提高耐压能力的半导体器件终端结构及其制造方法
CN109103248A (zh) * 2018-08-23 2018-12-28 深圳市南硕明泰科技有限公司 一种功率器件终端结构及其制备方法
CN110931548A (zh) * 2019-12-16 2020-03-27 安建科技(深圳)有限公司 一种半导体器件结构及其制造方法
CN113823679A (zh) * 2021-11-23 2021-12-21 成都蓉矽半导体有限公司 栅控二极管整流器
WO2023133925A1 (zh) * 2022-01-17 2023-07-20 中国电子科技集团公司第二十四研究所 功率半导体器件及其制造方法

Also Published As

Publication number Publication date
CN108292677B (zh) 2020-09-29
US20190067415A1 (en) 2019-02-28
US10340332B2 (en) 2019-07-02
CN108292677A (zh) 2018-07-17

Similar Documents

Publication Publication Date Title
WO2018049640A1 (zh) 一种具有体内场板的折叠型终端
TWI520337B (zh) 階梯溝渠式金氧半場效電晶體及其製造方法
US8264033B2 (en) Semiconductor device having a floating semiconductor zone
US10886396B2 (en) Transistor structures having a deep recessed P+ junction and methods for making same
TWI512844B (zh) 利用耗盡ｐ－屏蔽的低輸出電容的高頻開關ｍｏｓｆｅｔ
US8610210B2 (en) Power semiconductor device and method for manufacturing same
EP2710635B1 (en) Sic devices with high blocking voltage terminated by a negative bevel
WO2016047438A1 (ja) 半導体装置
US20140159053A1 (en) Sic trench gate transistor with segmented field shielding region and method of fabricating the same
CN106024866B (zh) 一种功率半导体器件的沟槽型终端结构
US9293524B2 (en) Semiconductor device with a field ring edge termination structure and a separation trench arranged between different field rings
CN109166922B (zh) 一种沟槽型超结功率终端结构及其制备方法
CN103563087A (zh) 凹陷终端结构和带有凹陷终端结构的电子器件的制备方法
CN103413822A (zh) 降低浮空埋层半导体器件漏电流的方法
CN106098751B (zh) 一种功率半导体器件终端结构
CN106024863A (zh) 一种高压功率器件终端结构
TWI470802B (zh) 溝槽式金氧半導體電晶體元件及其製造方法
CN114744049B (zh) 碳化硅mosfet半导体器件及制作方法
JP3998454B2 (ja) 電力用半導体装置
CN105810754A (zh) 一种具有积累层的金属氧化物半导体二极管
WO2017152443A1 (zh) 一种半导体元胞结构和功率半导体器件
JP6981585B1 (ja) 半導体装置、電力変換装置、および半導体装置の製造方法
KR101949511B1 (ko) 전력 반도체 소자 및 그 제조방법
KR101572196B1 (ko) 트렌치 게이트형 전력 모스 소자 및 그 제조방법
CN113299750A (zh) 半导体功率器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16916020

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16916020

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16916020

Country of ref document: EP

Kind code of ref document: A1