WO2018036200A1 - 膜层测试结构及阵列基板 - Google Patents

膜层测试结构及阵列基板 Download PDF

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Publication number
WO2018036200A1
WO2018036200A1 PCT/CN2017/083195 CN2017083195W WO2018036200A1 WO 2018036200 A1 WO2018036200 A1 WO 2018036200A1 CN 2017083195 W CN2017083195 W CN 2017083195W WO 2018036200 A1 WO2018036200 A1 WO 2018036200A1
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Prior art keywords
film layer
test
tested
conductive film
test structure
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English (en)
French (fr)
Inventor
张淼
孙静
傅武霞
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/573,067 priority Critical patent/US10332811B2/en
Publication of WO2018036200A1 publication Critical patent/WO2018036200A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
    • G01N27/041—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0416—Connectors, terminals

Definitions

  • the present disclosure relates to a film layer test structure and an array substrate.
  • a thin film transistor is a basic device in an array substrate.
  • the characteristics of each film layer in the thin film transistor affect the electrical characteristics of the thin film transistor, thereby affecting the final display effect of the display device.
  • the sheet resistance is an important means of evaluating the properties of the film layer.
  • the sheet resistance value is usually measured by a four-probe method.
  • the test is performed using four probes that are equally spaced and aligned, and the probe is in direct contact with the film layer.
  • FIG. 1 is a schematic diagram of the test piece resistance.
  • the probe is blocked by four probes that require equal distances between the four probe heads.
  • the resistance meter can be used to display the sheet resistance of the material.
  • the principle is that the two probes at the outer end generate a current field, and the two probes at the inner end test the current field at the two probe points. The potential formed on it.
  • the larger the sheet resistance the larger the potential generated, so that the sheet resistance of the film layer can be measured.
  • At least one embodiment of the present disclosure provides a film layer test structure including: a conductive film layer to be tested; a plurality of test lead wires, which are located in different layers from the conductive film layer to be tested and respectively associated with the conductive film layer to be tested Electrical connection; a plurality of test terminals, wherein the plurality of test terminals are electrically connected to the plurality of test lead wires respectively.
  • one end of the test lead wire is connected to the conductive film layer to be tested, and the other end is connected to the test terminal.
  • the test lead wire is integrally formed with the test terminal.
  • the test lead wire is disposed above or below the conductive film layer to be tested.
  • a film layer test structure further includes an insulating layer disposed on a side of the conductive film layer to be tested, the insulating layer having a plurality of first via holes, and the plurality of tests
  • the lead wires are electrically connected to the conductive film layer to be tested through the corresponding plurality of first via holes.
  • the first via hole is disposed in an intermediate region of the conductive film layer to be tested.
  • the distance between any two adjacent first via holes is substantially equal.
  • a plurality of the first via holes are arranged in a line.
  • the number of the first via holes is four, and the four first via holes are arranged in an equilateral quadrangle.
  • the plurality of test terminals are located in the same layer as the conductive film layer to be tested but are isolated from each other or in the same layer as the plurality of test leads. Electrically connected to each other.
  • the insulating layer further includes a plurality of second via holes.
  • the plurality of test terminals and the plurality of test lead wires are electrically connected through the second via holes.
  • At least one embodiment of the present disclosure further provides an array substrate comprising the film layer test structure described above, wherein the conductive film layer to be tested is located in a gate film layer, a source/drain electrode film layer or a pixel electrode film layer.
  • the plurality of test lead lines are located in the source/drain electrode film layer
  • a plurality of test terminals are located in the gate film layer or the source/drain electrode film layer.
  • the conductive film layer to be tested is the source/drain electrode film layer
  • the plurality of test lead lines are located in the gate film layer
  • a plurality of test terminals are located in the gate film layer or the source/drain electrode film layer.
  • the plurality of test lead lines are located in the source/drain electrode film layer, A plurality of test terminals are located on the source/drain electrode film layer or the pixel electrode film layer.
  • Figure 1 is a schematic diagram of a test block resistance
  • Figure 2 is a schematic view of the probe of Figure 1 after deformation
  • FIG. 3 is a schematic diagram of a film layer testing structure according to an embodiment of the present disclosure.
  • FIG. 4a is a schematic cross-sectional view of the film test structure of FIG. 3 taken along A-B;
  • 4b is a schematic cross-sectional view of the film test structure of FIG. 3 taken along C-D;
  • FIG. 5 is a schematic diagram of a film layer testing structure according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a film layer testing structure according to another embodiment of the present disclosure.
  • the sheet resistance value is usually measured by a four-probe method, and is tested using four probes that are equally spaced and aligned.
  • the sheet resistance value is only related to the thickness of the conductive film layer to be tested.
  • the test requirements for the sheet resistance are: the distance from each probe to the boundary of the conductive film layer to be tested is much larger than the distance between any adjacent two probes, for example, the distance from each probe to the boundary of the conductive film layer to be tested is at least Greater than 10 times the spacing of adjacent probes; probes need to be placed at equal intervals.
  • the sheet resistance value can be calculated by the following formula:
  • the probe 1, the probe 2, the probe 3 and the probe 4 are sequentially disposed on the conductive test film layer
  • the Sprobe is the probe pitch
  • the U23 is between the probe 2 and the probe 3.
  • the voltage difference, I14 is the current between probe 1 and probe 4.
  • a metal film layer or a transparent conductive film layer to form circuit structures such as gate lines, data lines, and pixel electrodes.
  • the sheet resistance of these conductive film layers can usually be measured. The sheet resistance is a test performed after the formation of the conductive film layer to be tested and before the etching operation, and the probe is placed in the area to be etched for testing to avoid damage to the film layer.
  • Figure 2 is a schematic view of the probe after deformation. As shown in Fig. 2, the probe is bent and deformed, causing a change in the spacing between the probes. When the square resistance value is calculated using the square resistance formula (1), an error occurs. Moreover, the inventors have also found that it is possible to perform a unified test after forming the sheet resistance test pattern after completion of each film layer, which is more convenient to operate.
  • a film test structure comprising: a conductive film layer to be tested; a plurality of test lead wires which are located at different layers from the conductive film layer to be tested and electrically connected to the conductive film layer to be tested respectively; and a plurality of test terminals The plurality of test terminals are electrically connected to the plurality of test lead wires respectively.
  • FIG. 3 is a schematic diagram of a film layer test structure according to an embodiment of the present disclosure.
  • the film layer test structure 100 includes a conductive film layer to be tested. 101, a plurality of test lead wires 102 and a plurality of test terminals 103, and a plurality of test lead wires 102 are located at different layers from the conductive film layer 101 to be tested, and are respectively electrically connected to the conductive film layer 101 to be tested, and the plurality of test terminals 103 respectively It is electrically connected to a plurality of test leads 102.
  • the plurality of test lead wires 102 are different from the conductive film layer 101 to be tested.
  • the layer means that the plurality of test lead wires 102 are not formed in the same film forming process as the film layer 101 to be tested, and the plurality of test lead wires 102 are not part of the film layer 101 to be tested.
  • test points on the conductive film layer 101 to be tested are taken out to the outside of the conductive film layer 101 to be tested through a plurality of test lead lines 102, and the conductive film layer 101 to be tested is replaced by a plurality of test terminals 103.
  • the test points are such that as long as the probe moves within the corresponding test terminal 103, substantially the resistance at each test point that is electrically connected to each test terminal 103 is measured.
  • the film layer test structure in the embodiment of the present disclosure when the probe changes in the pitch between the bending deformation probes due to long-term use, as long as the probe moves within the corresponding test terminal 103, the measured The resistance value of the square is still accurate. That is, the test of the film layer in the embodiment can conveniently complete the test of the square resistance, which can ensure the accuracy of the test and avoid frequent replacement of the probe, thereby reducing the production cost.
  • a plurality of test lead wires 102 in the film test structure 100 may be disposed above or below the conductive film layer 101 to be tested.
  • the film test structure 100 can be formed in a blank area of the substrate.
  • a pixel area for at least one display panel may be formed on the substrate, and the blank area is distributed around or between the pixel areas. This blank area is removed after the substrate is cut.
  • the conductive film layer 101 to be tested may be a gate film layer, a source/drain electrode film layer, a pixel electrode film layer made of a transparent conductive oxide, a common electrode film layer, or the like.
  • the manufacturing process of the film to be tested includes: depositing a conductive film layer on the substrate by magnetron sputtering, vapor deposition (for example, chemical vapor deposition), and then coating a photoresist on the conductive film layer, and then applying a photoresist.
  • the test lead line 102 can be formed when the source/drain electrode layer or the pixel electrode film layer is formed, so that the process step can be omitted.
  • the process of forming the test lead line 102 includes: depositing a source/drain metal film layer by magnetron sputtering, etc., then applying a photoresist on the film layer, and performing exposure, development, etching, and stripping of the photoresist, etc. The process forms a test lead line 102 on the substrate.
  • the test lead wires may be formed in the same layer as the gate metal film layer or the pixel electrode film layer.
  • a plurality of test terminals 103 are located in the same manner as the conductive film layer 101 to be tested.
  • One layer but isolated from each other or a plurality of test terminals 103 are in the same layer as the plurality of test leads 102 and are electrically connected to each other. This saves the process of making test terminals separately. Taking the test terminals in the same layer as the conductive film layer to be tested but isolated from each other as an example, the formation process of the test terminals is formed simultaneously with the conductive film layer to be tested.
  • the width of the test terminal 103 is larger than the width of the corresponding test lead line 102, and the size of the test terminal 103 should be such that the probe is preferably measured, and the shape of the test terminal 103 is not limited, so that It is preferred to perform measurements on the probe.
  • the test terminal 103 is square.
  • the shape of the test terminal 103 may also be a circle, a rectangle, a polygon, or the like.
  • the test terminal can be placed at any position around the conductive film layer to be tested.
  • the test terminals should be placed on the same straight line as much as possible.
  • the width of the test lead line is fixed, the length of the test lead line is set to the shortest to reduce the influence of the resistance of the test lead line itself on the accuracy of the test. And to ensure that the test leads can lead the test points out of the film to be tested.
  • FIG. 4a is a schematic cross-sectional view of the film test structure of FIG. 3 after being cut along the AB.
  • the film test structure further includes an insulating layer 105 disposed on a side of the conductive film layer 101 to be tested.
  • the insulating layer 105 has a plurality of first via holes 106, and the plurality of test lead wires are electrically connected to the conductive film layer 101 to be tested through the corresponding plurality of first via holes 106.
  • the first via 106 is disposed in an intermediate region of the conductive film layer 101 to be tested.
  • the plurality of first vias 106 define a geometry that passes or encompasses the center of the conductive film layer 101 to be tested.
  • the plurality of first via holes 106 are in the same straight line, it is meant that the center of the conductive film layer 101 to be tested is located in a line in which the plurality of first via holes 106 are arranged;
  • a polygon it is meant that the center of the conductive film layer 101 to be tested is located in a polygon in which the plurality of first via holes 106 are arranged.
  • the distance between any two adjacent first vias 106 is substantially equal.
  • the number of the first via holes is four, and the four first via holes are arranged in a straight line.
  • the four first via holes may also be arranged in a square or a diamond shape as long as the pitch between the adjacent two first via holes is substantially equal.
  • the first vias are arranged in a square or a diamond shape, it is necessary to multiply the corresponding coefficients by calculating the resistance using the formula.
  • FIG. 4b is a schematic cross-sectional view of the film test structure of FIG. 3 cut along C-D.
  • the insulating layer 105 further includes a plurality of second via holes 107, a plurality of test terminals 103 and a plurality of strips.
  • the test lead wires 102 are electrically connected through the second via holes 107.
  • the plurality of test terminals 103 are in the same layer as the conductive film layer 101 to be tested, that is, the plurality of test terminals 103 are formed in the same film forming process as the conductive film layer 101 to be tested.
  • the four probe sets are used to contact the four terminals, and the current is input and output on the two probes on both sides, and the voltages on the middle two terminals are simultaneously measured. Poor, the square resistance value can be calculated according to the square resistance formula.
  • the contact position of the probe is on the test terminal, and even if the probe is deformed for a long time, the test result is not detected due to the large area of the test terminal. There is an error in the test value of the sheet resistance when the needle pitch is changed.
  • the arrangement shape of the plurality of via holes is not limited to being arranged in a straight line and arranged in an equilateral quadrilateral shape, and may be other arrangement manners as long as the calculation formula of the corresponding sheet resistance can be Matching is optional and will not be described here.
  • FIG. 6 is a schematic diagram of a film layer testing structure provided by an embodiment of the present disclosure, in which the ends of the plurality of test lead wires 102 extend respectively Corresponding test terminals 103 are formed integrally.
  • the plurality of test terminals 103 are respectively formed by extending the ends of the plurality of test lead wires 102, and the width of the test terminals 103 is greater than the width of the corresponding test lead wires 102.
  • the plurality of test lead wires 102 and the plurality of test terminals 103 Located on the same floor.
  • the test terminals 103 are respectively formed by extending the ends of the plurality of test lead wires 102.
  • the planar shape of the test terminal 103 may be square and its side length is greater than the width of the test lead line 102.
  • the arrangement shape of the plurality of via holes is not limited to being arranged in a straight line and arranged in an equilateral quadrilateral shape, and may be other arrangement manners as long as the calculation formula of the corresponding sheet resistance can be Matching is optional and will not be described here.
  • Embodiments of the present disclosure also provide an array substrate including any of the above-described film layer test structures.
  • the conductive film layer to be tested is located at the gate film layer, the source/drain electrode film layer, or the pixel electrode film layer.
  • the conductive film layer to be tested is a gate film layer
  • a plurality of test lead wires are located in the source/drain electrode film layer
  • a plurality of test terminals are located in the gate film layer or the source/drain electrode film layer. If the film test structure shown in FIG. 6 is employed, the plurality of test terminals are located on the same film layer as the plurality of test lead wires.
  • the conductive film layer to be tested is a source/drain electrode film layer
  • a plurality of test lead lines are located in the gate film layer
  • a plurality of test terminals are located in the gate film layer or the source/drain electrode film layer. If the film test structure shown in FIG. 6 is employed, the plurality of test terminals are located on the same film layer as the plurality of test lead wires.
  • the conductive film layer to be tested is a pixel electrode film layer
  • a plurality of test lead lines are located in the source/drain electrode film layer
  • a plurality of test terminals are located in the source/drain electrode film layer or the pixel electrode film layer. If the film test structure shown in FIG. 6 is employed, the plurality of test terminals are located on the same film layer as the plurality of test lead wires.

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Abstract

一种膜层测试结构及阵列基板，该膜层测试结构（100）包括待测试导电膜层（101）、与待测试导电膜层（101）位于不同层且分别与待测试导电膜层（101）电连接的多条测试引出线（102）以及多个分别与多条测试引出线（102）电连接的测试端子（103）。将该膜层测试结构应用于阵列基板中，可以方便地完成方块电阻的测试，并且能够保证测试的精度，同时能够避免测试探针的频繁更换，减小测试探针的消耗，从而降低生产成本。

Description

膜层测试结构及阵列基板 技术领域
本公开涉及一种膜层测试结构及阵列基板。
背景技术
在显示技术领域中，例如，在液晶显示器或有机电致发光显示器件中，薄膜晶体管是阵列基板中的基本器件。薄膜晶体管中各膜层的特性影响着薄膜晶体管的电学特性，从而影响显示器件最终的显示效果。
方块电阻是评价膜层特性的一个重要手段。目前，方块电阻值通常用四探针法实现测量，测试时使用等间距且排成直线的四个探针进行测试，且探针直接接触膜层，例如，图1为测试方块电阻的示意图。探头由四根探针阻成，其要求四根探针头部的距离相等。当探头压在导电薄膜材料上面时，电阻计可用于显示出材料的方块电阻值，其原理是外端的两根探针产生电流场，内端的两根探针测试电流场在这两个探点上形成的电势。方块电阻越大，产生的电势也越大，这样就可以测出膜层的方块电阻值。
发明内容
本公开的至少一实施例提供一种膜层测试结构，包括：待测试导电膜层；多条测试引出线，与所述待测试导电膜层位于不同层且分别与所述待测试导电膜层电连接；多个测试端子，多个所述测试端子分别与所述多条测试引出线电连接。
例如，在本公开一实施例提供的膜层测试结构中，所述测试引出线的一端连接所述待测试导电膜层，另一端连接所述测试端子。
例如，在本公开一实施例提供的膜层测试结构中，所述测试引出线与所述测试端子一体成形。
例如，在本公开一实施例提供的膜层测试结构中，所述测试引出线设置在所述待测试导电膜层的上方或下方。
例如，本公开一实施例提供的膜层测试结构，还包括设置在所述待测试导电膜层一侧的绝缘层，所述绝缘层具有多个第一过孔，所述多条测试 引出线通过相应的所述多个第一过孔与所述待测试导电膜层电连接。
例如，在本公开一实施例提供的膜层测试结构中，所述第一过孔设置在所述待测试导电膜层的中间区域。
例如，在本公开一实施例提供的膜层测试结构中，任意相邻两个所述第一过孔之间的距离大致相等。
例如，在本公开一实施例提供的膜层测试结构中，多个所述第一过孔呈直线排列。
例如，在本公开一实施例提供的膜层测试结构中，所述第一过孔的个数为4个，且4个所述第一过孔排列成等边四边形。
例如，在本公开一实施例提供的膜层测试结构中，所述多个测试端子与所述待测试导电膜层位于同一层但彼此隔离，或者与所述多条测试引出线位于同一层并彼此电连接。
例如，在本公开一实施例提供的膜层测试结构中，所述多个测试端子与所述待测试导电膜层位于同一层的情况下，所述绝缘层还包括多个第二过孔，所述多个测试端子与所述多条测试引出线通过所述第二过孔电连接。
本公开的至少一实施例还提供一种阵列基板，包括上述中所述的膜层测试结构，所述待测试导电膜层位于栅极膜层、源漏电极膜层或像素电极膜层。
例如，本公开一实施例提供的阵列基板中，在所述待测试导电膜层为所述栅极膜层的情况下，所述多条测试引出线位于所述源漏电极膜层，所述多个测试端子位于所述栅极膜层或者所述源漏电极膜层。
例如，本公开一实施例提供的阵列基板中，在所述待测试导电膜层为所述源漏电极膜层的情况下，所述多条测试引出线位于所述栅极膜层，所述多个测试端子位于所述栅极膜层或者所述源漏电极膜层。
例如，本公开一实施例提供的阵列基板中，在所述待测试导电膜层为所述像素电极膜层的情况下，所述多条测试引出线位于所述源漏电极膜层，所述多个测试端子位于所述源漏电极膜层或像素电极膜层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实 施例，而非对本公开的限制。
图1为一种测试方块电阻的示意图；
图2为图1中的探针变形后的示意图；
图3为本公开一实施例提供的一种膜层测试结构的示意图；
图4a为图3中的膜层测试结构沿A-B切割后的截面结构示意图；
图4b为图3中的膜层测试结构沿C-D切割后的截面结构示意图；
图5为本公开另一实施例提供的膜层测试结构的示意图；
图6为本公开另一实施例提供的膜层测试结构的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
方块电阻值通常用四探针法实现测量，使用等间距且排成直线的四个探针进行测试，对于导电膜层而言，方块电阻值仅与待测试导电膜层厚度相关。方块电阻定义为：R□＝ρ/t，其中，ρ为金属电阻率，t为所测薄膜的厚度。
方块电阻的测试要求为：每个探针到待测试导电膜层边界的距离要远大于任意相邻两探针之间的间距，例如，每个探针到待测试导电膜层边界的距离至少大于相邻探针间距的10倍；探针需要等间距放置。
采用等间距且成直线放置的四探针测试方块电阻时，方块电阻值可用以下公式计算：
Figure PCTCN2017083195-appb-000001
其中，如图1所示，探针1、探针2、探针3和探针4依次设置在导电测试膜层上，Sprobe为探针间距，U23为探针2与探针3之间的电压差，I14为探针1与探针4之间的电流。
在常规的阵列基板工艺中，需要形成例如金属膜层或透明导电膜层，以形成栅线、数据线、像素电极等电路结构。为了检测这些导电膜层的成膜质量，通常可以测量这些导电膜层的方块电阻。方块电阻是在待测试导电膜层形成之后且在刻蚀作业之前进行的测试，探针放置于待刻蚀区域进行测试以避免对膜层带来损坏。本公开的发明人注意到，当探针长时间使用后，探针会发生诸如弯曲、偏移等磨损，从而导致探针的间距发生变化，进而导致测量误差，使得使用上述公式(1)计算电阻时不准确，测试精度下降，因而可能需要频繁地更换探针。例如，图2为探针变形后的示意图。如图2所示，探针发生了弯曲变形，导致探针之间的间距发生了变化，当使用方块电阻公式(1)计算方块电阻值时会发生误差。并且，发明人还发现，可以在各膜层完成之后，形成方块电阻测试图案之后再进行统一测试，这样操作起来更方便。
为解决上述在方块电阻的测试中，由于探针长时间使用易发生弯曲变形而导致探针之间的间距发生变化，最终导致方块电阻值的测量不准确的问题，本公开一实施例提供了一种膜层测试结构，该膜层测试结构包括：待测试导电膜层；与待测试导电膜层位于不同层且分别与待测试导电膜层电连接的多条测试引出线；多个测试端子，该多个测试端子分别与多条测试引出线电连接。
本公开的实施例提供一种膜层测试结构，图3为本公开一实施例提供的一种膜层测试结构的示意图，如图3所示，该膜层测试结构100包括待测试导电膜层101、多条测试引出线102和多个测试端子103，并且多条测试引出线102与待测试导电膜层101位于不同层且分别与待测试导电膜层101电连接，多个测试端子103分别与多条测试引出线102电连接。
需要说明的是，多条测试引出线102与待测试导电膜层101位于不同 层是指多条测试引出线102不与待测试膜层101在同一成膜工艺中形成，且多条测试引出线102不是待测试膜层101的一部分。
如图3所示，通过多条测试引出线102把待测试导电膜层101上的测试点引出到待测试导电膜层101外，且通过多个测试端子103代替了待测试导电膜层101上的测试点，这样，只要探针在相应的测试端子103内移动，实质上所测的是与各个测试端子103电连接的各个测试点处的电阻。
当采用本公开的实施例中的膜层测试结构时，当探针由于长时间使用发生弯曲变形探针之间的间距发生变化时，只要探针在相应的测试端子103内移动，所测出的方块电阻值仍然是准确的，即采用本实施例中的膜层测试结构能够方便地完成方块电阻的测试，可以保证测试的精度，避免探针的频繁更换，从而降低了生产成本。
例如，如图3所示，该膜层测试结构100中的多条测试引出线102可以设置在待测试导电膜层101的上方或下方。
例如，该膜层测试结构100可以形成在基板的空白区域。基板上通常可以形成用于至少一个显示面板的像素区域，空白区域分布在像素区域周边或之间。该空白区域在对基板进行切割后被除去。
例如，该待测试导电膜层101可以为栅极膜层、源漏电极膜层和透明导电氧化物制作的像素电极膜层、公共电极膜层等。
例如，该待测试膜层的制作过程包括：通过磁控溅射、气相沉积(例如化学气相沉积)等方式在基板上沉积导电膜层，然后在该导电膜层上涂覆光刻胶，再进行曝光、显影、刻蚀和剥离光刻胶等工序在基板上形成待测试导电膜层101，以及相应地形成在像素区中的电路结构(例如栅线、栅极、数据线、源漏极、像素电极、公共电极等)。
下面以形成的膜层为栅极金属膜层为例加以说明，测试引出线102可以在形成源漏电极层或者像素电极膜层时形成，这样可以不用增加工艺步骤。例如，形成测试引出线102的过程包括：通过磁控溅射等方式沉积源漏金属膜层，然后在膜层上涂覆光刻胶，再进行曝光、显影、刻蚀和剥离光刻胶等工序在基板上形成测试引出线102。同样地，如果待测试膜层为源漏金属膜层时，测试引出线可以与栅极金属膜层或者像素电极膜层同层形成。
例如，如图3所示，多个测试端子103与待测试导电膜层101位于同 一层但彼此隔离或者多个测试端子103与多条测试引出线102位于同一层并且彼此电连接。这样可以节省单独做测试端子的工序。以测试端子与待测试导电膜层位于同一层但彼此隔离为例加以说明，测试端子的形成过程与待测试导电膜层同时形成。
例如，如图3所示，测试端子103的宽度大于相应测试引出线102的宽度，测试端子103的大小应以便于探针进行测量为宜，且测试端子103的形状也不受限制，仍以便于探针进行测量为宜。如图3所示，测试端子103为正方形，在本公开的其他实施例中，测试端子103的形状还可以为圆形、矩形、多边形等。
例如，在保证测试端子与待测试导电膜层绝缘的前提下，可以将测试端子设置在待测试导电膜层周围的任意位置，为了保证测试的方便，尽量将测试端子设置在同一条直线上。在测试引出线的宽度固定的情况下，将测试引出线的长度设置到最短，以减少测试引出线自身的电阻给测试的精确度造成的影响。且保证测试引出线能将测试点引出到待测试膜层外。
例如，图4a为图3中的膜层测试结构沿A-B切割后的截面结构示意图，如图4a所示，该膜层测试结构还包括设置在待测试导电膜层101一侧的绝缘层105，绝缘层105上具有多个第一过孔106，多条测试引出线通过相应的多个第一过孔106与待测试导电膜层101电连接。
例如，如图4a所示，第一过孔106设置在待测试导电膜层101的中间区域。例如，多个第一过孔106限定成的几何形状经过或涵盖待测试导电膜层101的中心。例如，对于多个第一过孔106位于同一直线的情形，指的是待测试导电膜层101的中心位于多个第一过孔106排列的直线中；对于多个第一过孔106排列成多边形的情形，指的是待测试导电膜层101的中心位于多个第一过孔106排列成的多边形内。
例如，如图4a所示，任意相邻两个第一过孔106之间的距离大致相等。
例如，如图4a所示，第一过孔的个数为4个，且4个第一过孔呈直线排列。
例如，如图5所示，4个第一过孔还可以排列成正方形或者菱形，只要满足相邻的两个第一过孔之间的间距大致相等即可。但当第一过孔排列成正方形或者菱形时，利用公式计算电阻时需要乘以相应的系数。
例如，图4b为图3中的膜层测试结构沿C-D切割后的截面结构示意 图，如图3和图4b所示，在多个测试端子与待测试导电膜层位于同一层的情况下，绝缘层105还包括多个第二过孔107，多个测试端子103与多条测试引出线102通过第二过孔107电连接。
需要说明的是，多个测试端子103与待测试导电膜层101位于同一层是指多个测试端子103与待测试导电膜层101在同一成膜工艺中形成。
当本公开的实施例中的膜层测试结构制作完成以后，采用四探针组接触四个端子，在两侧的两个探针上分别输入和输出电流，同时测量中间两个端子上的电压差，根据方块电阻公式即可计算得到方块电阻值。当对本实施例中的膜层测试结构进行方块电阻测试时，探针的接触位置在测试端子上，即使探针长时间使用发生变形，由于测试端子的面积较大，测试结果也不会因为探针间距的变化而出现方块电阻的测试值出现误差。
例如，在本公开的实施例中，多个过孔的排列形状也并不仅限于呈直线排列和呈等边四边形排列，还可以为其他的排列方式，只要能与相应的方块电阻的计算公式相匹配即可，在此不再赘述。
本公开的实施例还提供一种膜层测试结构，图6为本公开的实施例提供的膜层测试结构的示意图，在该膜层测试结构中，多个测试引出线102的末端延伸出各自对应的测试端子103且二者一体成形。
例如，多个测试端子103分别由多个测试引出线102的末端延伸构成，且测试端子103的宽度大于相应的测试引出线102的宽度，此时多个测试引出线102与多个测试端子103位于同一层。如图6所示，测试端子103分别由多个测试引出线102的末端延伸构成。例如，测试端子103的平面形状可以为正方形，且其边长大于测试引出线102的宽度。
在本公开的实施例中，除了多个测试端子103分别由多个测试引出线102的末端延伸构成外，其他的结构特征均可参考上述中的相关描述，在此不再赘述。
例如，在本公开的实施例中，多个过孔的排列形状也并不仅限于呈直线排列和呈等边四边形排列，还可以为其他的排列方式，只要能与相应的方块电阻的计算公式相匹配即可，在此不再赘述。
本公开的实施例还提供一种阵列基板，包括上述任一膜层测试结构。
例如，该待测试导电膜层位于栅极膜层、源漏电极膜层或像素电极膜层。
例如，在待测试导电膜层为栅极膜层的情况下，多条测试引出线位于源漏电极膜层，多个测试端子位于栅极膜层或者源漏电极膜层。如果采用图6所示的的膜层测试结构，则多个测试端子与多条测试引出线位于同一膜层。
例如，在待测试导电膜层为源漏电极膜层的情况下，多条测试引出线位于栅极膜层，多个测试端子位于栅极膜层或者源漏电极膜层。如果采用图6所示的膜层测试结构，则多个测试端子与多条测试引出线位于同一膜层。
例如，在待测试导电膜层为像素电极膜层的情况下，多条测试引出线位于源漏电极膜层，多个测试端子位于源漏电极膜层或像素电极膜层。如果采用图6所示的膜层测试结构，则多个测试端子与多条测试引出线位于同一膜层。
本公开的实施例提供的一种膜层测试结构及阵列基板至少具有以下一项有益效果：
(1)将该膜层测试结构应用于阵列基板中，可以方便地完成方块电阻的测试，并且能够保证测试的精度，同时能够避免测试探针的频繁更换，减小测试探针的消耗，从而降低生产成本；
(2)可以在各膜层完成之后，形成方块电阻测试图案之后再进行统一测试，这样操作起来更方便。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年8月26日递交的中国专利申请第 201620956579.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种膜层测试结构，包括：
    待测试导电膜层；
    多条测试引出线，与所述待测试导电膜层位于不同层且分别与所述待测试导电膜层电连接；
    多个测试端子，多个所述测试端子分别与所述多条测试引出线电连接。
  2. 根据权利要求1所述的膜层测试结构，其中，所述测试引出线的一端连接所述待测试导电膜层，另一端连接所述测试端子。
  3. 根据权利要求2所述的膜层测试结构，其中，所述测试引出线与所述测试端子一体成形。
  4. 根据权利要求2或3所述的膜层测试结构，其中，所述测试引出线设置在所述待测试导电膜层的上方或下方。
  5. 根据权利要求4所述的膜层测试结构，其中，还包括设置在所述待测试导电膜层与所述测试端子之间的绝缘层，所述绝缘层具有多个第一过孔，所述多条测试引出线通过相应的所述多个第一过孔与所述待测试导电膜层电连接。
  6. 根据权利要求5所述的膜层测试结构，其中，所述第一过孔设置在所述待测试导电膜层的中间区域。
  7. 根据权利要求6所述的膜层测试结构，其中，任意相邻两个所述第一过孔之间的距离大致相等。
  8. 根据权利要求5-7中任一项所述的膜层测试结构，其中，多个所述第一过孔呈直线排列。
  9. 根据权利要求5-7中任一项所述的膜层测试结构，其中，所述第一过孔的个数为4个，且4个所述第一过孔排列成等边四边形。
  10. 根据权利要求5-9中任一项所述的膜层测试结构，其中，所述多个测试端子与所述待测试导电膜层位于同一层但彼此隔离，或者与所述多条测试引出线位于同一层并彼此电连接。
  11. 根据权利要求10所述的膜层测试结构，其中，所述多个测试端子与所述待测试导电膜层位于同一层的情况下，所述绝缘层还包括多个第二 过孔，所述多个测试端子与所述多条测试引出线通过所述第二过孔电连接。
  12. 一种阵列基板，其中，包括权利要求1-11中任一项所述的膜层测试结构，所述待测试导电膜层位于栅极膜层、源漏电极膜层或像素电极膜层。
  13. 根据权利要求12所述的阵列基板，其中，在所述待测试导电膜层为所述栅极膜层的情况下，所述多条测试引出线位于所述源漏电极膜层，所述多个测试端子位于所述栅极膜层或者所述源漏电极膜层。
  14. 根据权利要求12所述的阵列基板，其中，在所述待测试导电膜层为所述源漏电极膜层的情况下，所述多条测试引出线位于所述栅极膜层，所述多个测试端子位于所述栅极膜层或者所述源漏电极膜层。
  15. 根据权利要求12所述的阵列基板，其中，在所述待测试导电膜层为所述像素电极膜层的情况下，所述多条测试引出线位于所述源漏电极膜层，所述多个测试端子位于所述源漏电极膜层或像素电极膜层。
PCT/CN2017/083195 2016-08-26 2017-05-05 膜层测试结构及阵列基板 Ceased WO2018036200A1 (zh)

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