WO2018034067A1 - Dispositif à semi-conducteur avec condensateur - Google Patents

Dispositif à semi-conducteur avec condensateur Download PDF

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Publication number
WO2018034067A1
WO2018034067A1 PCT/JP2017/024085 JP2017024085W WO2018034067A1 WO 2018034067 A1 WO2018034067 A1 WO 2018034067A1 JP 2017024085 W JP2017024085 W JP 2017024085W WO 2018034067 A1 WO2018034067 A1 WO 2018034067A1
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Prior art keywords
capacitor
semiconductor element
semiconductor device
layer
resin layer
Prior art date
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PCT/JP2017/024085
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English (en)
Japanese (ja)
Inventor
尚之 小林
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株式会社村田製作所
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Publication of WO2018034067A1 publication Critical patent/WO2018034067A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Definitions

  • the present invention relates to a semiconductor device with a capacitor, and more particularly, to a semiconductor device with a capacitor in which, even if a temperature change occurs, warpage, damage to a semiconductor element, and occurrence of poor connection are suppressed.
  • a power supply wiring that supplies power to the semiconductor element and a ground wiring are interposed.
  • a capacitor decoupling capacitor
  • Japanese Laid-Open Patent Publication No. 2001-223299 discloses a package substrate in which a capacitor is connected between a power supply wiring and a ground wiring.
  • FIG. 7 shows a package substrate 1000 disclosed in Patent Document 1.
  • a semiconductor element (IC chip) 101 is mounted on the package substrate 1000.
  • a power supply wiring (power supply line) 102 is connected from the power supply to the power supply terminal 101 ⁇ / b> P of the semiconductor element 101.
  • a ground wiring (earth wire) 103 is connected from the ground terminal 101E of the semiconductor element 101 to the power source.
  • capacitors (chip capacitors) 104 and 105 are mounted on the package substrate 1000.
  • the capacitors 104 and 105 are connected between the power supply wiring 102 and the ground wiring 103, respectively.
  • the loop inductance that becomes a transmission loss is proportional to the wiring length from the power supply terminal 101P of the semiconductor element 101 to the power supply via the power supply wiring 102 and the wiring length from the power supply to the ground terminal 101E via the ground wiring 103.
  • the loop length for determining the loop inductance is shortened to the wiring length via the capacitors 104 and 105 indicated by solid lines in the drawing.
  • the capacitors 104 and 105 are preferably connected as close to the semiconductor element 101 as possible.
  • the package substrate 1000 reduces the power impedance by reducing the loop inductance and suppresses voltage fluctuation.
  • the capacitors 104 and 105 have a function of removing noise entering and exiting the semiconductor element 101.
  • capacitors 104 and 105 are connected in the package substrate 1000.
  • different types of capacitors for example, aluminum
  • Many electrolytic capacitors and multilayer ceramic capacitors may be connected.
  • a sealing resin layer may be provided so as to cover the semiconductor element 101 and the capacitors 104 and 105.
  • FO-WLP fan-out-wafer-level package
  • This FO-WLP cuts out a semiconductor element from a wafer, attaches the functional surface (terminal surface) side of the semiconductor element to a film, and then molds a resin on the surface opposite to the film of the semiconductor element.
  • a packaging method for removing a film The semiconductor element is embedded in the resin layer (holding resin layer) with the functional surface (terminal surface) side exposed to the outside.
  • a rewiring layer is formed on the surface of the resin layer where the semiconductor element is exposed.
  • the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the interposer may be brought close to each other.
  • the difference between the thermal expansion coefficient of the Si interposer and the thermal expansion coefficient of the capacitor is too large.
  • the Si interposer may be warped, the capacitor may be peeled off from the Si interposer, or a connection failure may occur.
  • the semiconductor device with a capacitor according to the present invention is formed of at least one Si semiconductor element formed of Si and Si.
  • the Si semiconductor element and the Si capacitor are mounted on the Si interposer, respectively, and a sealing resin layer is formed on the main surface of the Si interposer so as to cover the mounted Si semiconductor element and the Si capacitor. can do.
  • the Si interposer and the mounted Si semiconductor element and the Si capacitor have close thermal expansion coefficients, the Si interposer is warped even if a temperature change occurs, or the Si semiconductor element and the Si capacitor are It does not peel off from the interposer or cause poor connection. Further, the Si semiconductor element and the Si capacitor are protected from the outside by the sealing resin layer.
  • each of the Si semiconductor element and the Si capacitor is embedded in the holding resin layer with one main surface exposed, and on the main surface of the holding resin layer where the Si semiconductor element and the Si capacitor are exposed, A rewiring layer may be formed.
  • the holding resin layer, the embedded Si semiconductor element, and the Si capacitor have similar coefficients of thermal expansion. Therefore, even if a temperature change occurs, the holding resin layer warps, the Si semiconductor element or the Si capacitor. The capacitor does not peel from the holding resin layer.
  • the Si capacitor for example, a trench capacitor in which a hole is formed in a Si base made of Si and formed in the hole can be used.
  • the Si capacitor is not limited to a trench capacitor, and may have another structure.
  • a thin film high-capacitance capacitor in which a conductive porous layer, a dielectric layer, and a conductor layer are sequentially laminated on the Si capacitor is formed, and the Si capacitor and the thin-film high-capacity capacitor are connected in parallel.
  • the required large capacitance can be formed between the power supply wiring and the ground wiring by using the Si capacitor and the thin film high-capacity capacitor.
  • the Si capacitor mainly reduces the power impedance in the high frequency range
  • the thin film high-capacitance capacitor mainly reduces the power impedance in the low frequency range, reducing the power impedance over a wide frequency range, and suppressing voltage fluctuations. Can do. Furthermore, noises of various frequencies can be removed.
  • a multilayer ceramic capacitor may be mounted on the Si capacitor, and the Si capacitor and the multilayer ceramic capacitor may be connected in parallel.
  • the required large capacitance can be formed between the power supply wiring and the ground wiring by the Si capacitor and the multilayer ceramic capacitor.
  • the Si capacitor mainly reduces the power supply impedance in the high frequency range
  • the multilayer ceramic capacitor mainly reduces the power supply impedance in the low frequency range, thereby reducing the power supply impedance over a wide frequency range and suppressing voltage fluctuations. it can. Furthermore, noises of various frequencies can be removed.
  • the multilayer ceramic capacitor is directly mounted on the Si interposer or embedded in the holding resin layer, the above-mentioned trouble may occur due to a temperature change, but if the multilayer ceramic capacitor is mounted on the Si capacitor, Since the Si capacitor functions as a buffer material, it is possible to avoid such troubles.
  • a thin film resistor may be formed on the surface of the Si capacitor, and the Si capacitor and the thin film resistor may be connected in series. If the ESR (Equivalent Series Resistance) of the Si capacitor is too small relative to the inductance component of the power supply wiring, anti-resonance with a large peak may occur, but as described above, the thin film resistor in series with the Si capacitor Can be connected to suppress the peak of antiresonance.
  • ESR Equivalent Series Resistance
  • the semiconductor device with a capacitor uses a Si semiconductor element as a semiconductor element, uses a Si capacitor as a capacitor, and arranges or holds the Si semiconductor element and the Si capacitor in a planar direction in a Si interposer. Since one main surface is embedded in the resin layer for use, even if the temperature changes, warping, damage to the semiconductor element, peeling of the semiconductor element or Si capacitor, or connection failure may occur. Is suppressed.
  • FIG. 1A is a front view showing the capacitor-equipped semiconductor device 100 according to the first embodiment.
  • FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor. It is explanatory drawing (front view which looked through and showed the inside of the resin layer 12 for sealing) which shows the semiconductor device 200 with a capacitor concerning 2nd Embodiment.
  • FIG. 3A is a front view showing a semiconductor device 300 with a capacitor according to the third embodiment.
  • FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor.
  • FIG. 4A is a front view showing a semiconductor device with a capacitor 400 according to the fourth embodiment.
  • FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400.
  • FIG. 5A is a front view showing a semiconductor device 500 with a capacitor according to the fifth embodiment.
  • FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500.
  • 6 (A) to 6 (E) are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 according to the sixth embodiment (see through the inside of the holding resin layer 20). It is a front view shown).
  • 10 is an explanatory view showing a package substrate 1000 disclosed in Patent Document 1.
  • FIG. 1 is an explanatory view showing a package substrate 1000 disclosed in Patent Document 1.
  • each embodiment shows an embodiment of the present invention by way of example, and the present invention is not limited to the content of the embodiment. Moreover, it is also possible to implement combining the content described in different embodiment, and the implementation content in that case is also included in this invention. Further, the drawings are for helping understanding of the embodiment, and may not be drawn strictly. For example, a drawn component or a dimensional ratio between the components may not match the dimensional ratio described in the specification. In addition, the constituent elements described in the specification may be omitted in the drawings or may be drawn with the number omitted.
  • FIG. 1A and 1B show a semiconductor device 100 with a capacitor according to the first embodiment.
  • FIG. 1A is a front view showing the semiconductor device 100 with a capacitor.
  • FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor.
  • the capacitor-equipped semiconductor device 100 includes a Si interposer 1 made of Si. Although not shown, a plurality of electrodes are formed on both main surfaces of the Si interposer 1, and predetermined wiring is made by surface wiring, interlayer wiring, via conductors, and the like.
  • the Si interposer 1 can be manufactured by an existing interposer manufacturing method that is generally implemented.
  • a semiconductor element (LSI element or the like) 3 is mounted on the electrode formed on the upper main surface of the Si interposer 1 by a bump 2 made of Sn-3.5Ag, Cu, Sn-Pb or the like.
  • the Si capacitor 4 is mounted by the bump 2 on another electrode formed on the upper main surface of the Si interposer.
  • FIG. 1B shows the details of the Si capacitor 4.
  • a trench capacitor is used as the Si capacitor 4.
  • the Si capacitor 4 includes a Si base 5 made of Si.
  • a plurality of holes 6 are formed in one main surface (lower main surface) of the Si substrate 5.
  • An insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the hole 6.
  • the insulating layer 7 is formed of SiO 2
  • the first electrode layer 8 is formed of Si
  • the dielectric layer 9 is formed of Ti 2 O 3
  • the second electrode layer 10 is formed of TiN. .
  • the first electrode layer 8 and the second electrode layer 10 are each drawn out to the surface of the Si substrate 5, and the bumps 2 are formed in the drawn portions.
  • the Si capacitor 4 can be manufactured by an existing trench capacitor manufacturing method that is generally performed.
  • a bump 11 made of Sn-3.5Ag, Cu, Sn-Pb or the like is formed on the electrode formed on the lower main surface of the Si interposer.
  • the Si capacitor 4 is connected between a power supply wiring (not shown) for supplying power to the Si semiconductor element 3 and a ground wiring (not shown).
  • the Si capacitor 4 is connected between the power supply wiring and the ground wiring, so that the power supply impedance is small and voltage fluctuation is suppressed. Further, noise can be removed by the Si capacitor 4.
  • the semiconductor device with a capacitor 100 since the semiconductor device with a capacitor 100 has the Si semiconductor element 3 and the Si capacitor 4 mounted on the Si interposer 1 having a coefficient of thermal expansion close to each other, even if a temperature change occurs, The semiconductor element 3 is not damaged, and the Si semiconductor element 3 and the Si capacitor 4 are not peeled off from the Si interposer 1 to cause connection failure.
  • the capacitor-equipped semiconductor device 100 has a low profile because the Si capacitor 4 has a smaller height than an aluminum electrolytic capacitor or a multilayer ceramic capacitor.
  • FIG. 2 shows a semiconductor device 200 with a capacitor according to the second embodiment.
  • FIG. 2 is an explanatory view showing the semiconductor device with a capacitor 200 (a front view seen through the inside of the sealing resin layer 12).
  • the sealing resin layer 12 is added to the semiconductor device with a capacitor 100 according to the first embodiment. Specifically, in the semiconductor device with a capacitor 200, the sealing resin layer 12 is formed on the upper main surface of the Si interposer 1 so as to cover the Si semiconductor element 3 and the Si capacitor 4.
  • the sealing resin layer 12 is for protecting the Si semiconductor element 3 and the Si capacitor 4 and has characteristics such as a linear expansion coefficient relatively close to Si and low hygroscopicity. preferable.
  • an epoxy resin, a silicon resin, or the like can be used for the sealing resin layer 12.
  • the sealing resin layer 12 is formed by, for example, dropping a liquid resin on the upper main surface of the Si interposer 1 and heating it to cure after mounting the Si semiconductor element 3 and the Si capacitor 4. Can do.
  • FIG. 3A and 3B show a capacitor-equipped semiconductor device 300 according to the third embodiment.
  • FIG. 3A is a front view showing the semiconductor device 300 with a capacitor.
  • FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor.
  • the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with a Si capacitor 14 having a thin film resistor 15 formed on the surface thereof. Then, the Si semiconductor element 3 and the Si capacitor 14 were mounted on the Si interposer 1.
  • FIG. 3B shows the details of the Si capacitor 14.
  • the Si capacitor 14 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • the thin film resistor 15 is further formed on the lower main surface of the Si base 5 in the Si capacitor 14.
  • the thin film resistor 15 is made of NiCr, for example.
  • the thin film resistor 15 is connected in series with the trench capacitor (the first electrode layer 8, the dielectric layer 9, and the second electrode layer 10).
  • the ESR of the capacitor connected between the power supply wiring and the ground is too small with respect to the inductance component of the power supply wiring, anti-resonance with a large peak in the power supply impedance may occur.
  • the semiconductor device with a capacitor 300 according to the third embodiment since the thin film resistor 15 is connected in series with the trench capacitor, the anti-resonance peak can be suppressed to a small value.
  • the thin film resistor 15 can be formed by thin film technology, for example.
  • FIG. 4A and 4B show a semiconductor device 400 with a capacitor according to the fourth embodiment.
  • FIG. 4A is a front view showing the semiconductor device 400 with a capacitor.
  • FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400.
  • the Si capacitor 4 of the semiconductor device with capacitor 100 according to the first embodiment is replaced with the Si capacitor 24 in which the thin film high-capacitance capacitor 16 is formed on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 24 were mounted on the Si interposer 1.
  • FIG. 4B shows details of the Si capacitor 24.
  • the Si capacitor 24 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • a thin film high-capacity capacitor 16 is further formed on the upper main surface of the Si base 5.
  • the thin film high-capacitance capacitor 16 has a structure in which a conductive porous layer 16a, a dielectric layer 16b, and a conductive layer 16c are sequentially stacked.
  • the thin film high capacity capacitor 16 has a very large capacity because the dielectric layer 16b is formed on the conductive porous layer 16a.
  • the thin film high capacity capacitor 16 can be formed by the following method, for example.
  • an insulating layer 17 made of, for example, SiO 2 is formed in a region of the Si base 5 where the thin film high capacity capacitor 16 is to be formed.
  • the insulating layer 17 made of SiO 2 can be formed by a CVD (Chemical Vapor Deposition) method or the like.
  • a conductor layer (not shown) made of, for example, Al is formed on the insulating layer 17 by, for example, photolithography.
  • the material of the conductor layer is not limited to Al and may be other metals.
  • an extremely large number of fine holes are formed in the conductor layer by, for example, etching after anodic oxidation to form the conductor porous body layer 16a.
  • the formation of fine holes is not limited to the anodic oxidation method, and may be formed by a method such as a method of depositing metal fine particles by printing, ink jetting, spraying, spraying, or the like.
  • a dielectric layer 16b made of, for example, AlOX (X is 1.2 or more) is formed on the conductive porous layer 16a by an atomic deposition method (ALD method; Atomic Layer Deposition).
  • a diffusion preventing layer made of, for example, TiON may be formed in advance between the conductive porous body layer 16a and the dielectric layer 16b. The formation of the diffusion preventing layer can also be performed by the ALD method.
  • a conductor layer 16c made of, for example, Al is formed on the dielectric layer 16b by, for example, the ALD method.
  • the material of the conductor layer 16c is not limited to Al, and may be Cu, Ni, or the like.
  • a diffusion prevention layer made of TiON or the like may be formed in advance between the dielectric layer 16b and the conductor layer 16c. This diffusion prevention layer can also be formed by the ALD method.
  • the conductive porous body layer 16a, the dielectric layer 16b, and the conductive layer 16c are patterned by using a photolithography technique to complete the thin film high-capacitance capacitor 16.
  • the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the thin film high-capacitance capacitor 16 are formed in the Si substrate 5 and via conductors are formed. By connecting in parallel.
  • the capacitor-equipped semiconductor device 400 can form a desired large capacitance between the power supply wiring and the ground wiring by the trench capacitor and the thin film high-capacitance capacitor 16.
  • the capacitor-equipped semiconductor device 400 since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
  • the thin film resistor 15 is formed on the surface of the Si substrate 5, and the trench capacitor (first electrode layer) of the Si capacitor 24 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
  • FIG. 5A and 5B show a semiconductor device 500 with a capacitor according to the fifth embodiment.
  • FIG. 5A is a front view showing the semiconductor device 500 with a capacitor.
  • FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500.
  • the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with the Si capacitor 34 on which the multilayer ceramic capacitor 18 is mounted on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 34 were mounted on the Si interposer 1.
  • FIG. 5B shows details of the Si capacitor 34.
  • the Si capacitor 34 includes a Si base 5, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • a multilayer ceramic capacitor 18 is mounted on the upper main surface of the Si base 5 using a bonding material 19.
  • the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the multilayer ceramic capacitor 18 are formed in the Si substrate 5 and via conductors are formed. Are connected in parallel.
  • the trench capacitor and the multilayer ceramic capacitor 18 provide a desired large capacity between the power supply wiring and the ground wiring. Can be formed.
  • the capacitor-equipped semiconductor device 400 since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
  • the semiconductor device with a capacitor 400 uses a multilayer ceramic capacitor 18 having a coefficient of thermal expansion that is significantly different from that of the Si interposer 1 and the Si semiconductor element 3.
  • Si Since it is mounted on the interposer 1 and the Si base 5 functions as a kind of buffer material, even if a temperature change occurs, it does not warp and the multilayer ceramic capacitor 18 does not peel off.
  • the thin film resistor 15 is formed on the surface of the Si base 5, and the trench capacitor (first electrode layer) of the Si capacitor 34 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
  • FIGS. 6A to 6E show a semiconductor device 600 with a capacitor according to a sixth embodiment.
  • FIGS. 6A to 6E are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 (front views showing through the inside of the holding resin layer 20). 6E shows the completed semiconductor device 600 with a capacitor.
  • the capacitor-equipped semiconductor device 600 holds the Si semiconductor element 13 and the Si capacitor 44 in the holding resin layer 20 by FO-WLP (fan out-Wafer Level Package).
  • FO-WLP fan out-Wafer Level Package
  • the Si semiconductor element 13 and the Si capacitor 44 are prepared.
  • the Si semiconductor element 13 the same one as the Si semiconductor element 3 used in the first embodiment was prepared.
  • the Si capacitor 44 the same one as the Si capacitor 4 used in the first embodiment was prepared.
  • the bumps are not formed on the lower main surface of the Si semiconductor element 13 and the Si capacitor 44, respectively.
  • the Si semiconductor element 13 and the Si capacitor 44 are attached to the film 21 with the surfaces on which the terminals are formed facing the film 21, respectively.
  • the surface of the film 21 is previously given adhesiveness.
  • a liquid resin is dropped on the film 21 so as to cover the Si semiconductor element 13 and the Si capacitor 44, and then heated to cure the resin and retain the resin.
  • Layer 20 is formed.
  • a material having characteristics (such as a linear expansion coefficient) that the holding resin layer 20 is not warped or the Si semiconductor element 13 is not peeled off from the holding resin layer 20 must be selected.
  • the film 21 is removed from the holding resin layer 20 in which the Si semiconductor element 13 and the Si capacitor 44 are embedded.
  • 6C to 6E show the holding resin layer 20 upside down with respect to FIGS. 6A and 6B.
  • the surface on which the terminals of the Si semiconductor element 13 are formed and the surface on which the terminals of the Si capacitor 44 are formed are exposed.
  • the rewiring layer 22 is formed on the surface of the holding resin layer 20 where the Si semiconductor element 13 and the Si capacitor 44 are exposed.
  • the redistribution layer 22 is formed by laminating a plurality of insulating layers (not shown), and a via conductor formed through the insulating layer or a wiring electrode formed between the layers, between the two main surfaces. Wiring is made.
  • the rewiring layer 22 connects the Si semiconductor element 13 and the Si capacitor 44.
  • the rewiring layer 22 can be formed using a general insulating material or a conductive material by using a photolithography technique.
  • bumps 23 are formed on the rewiring layer 22 to complete the semiconductor device 600 with a capacitor.
  • the resin constituting the holding resin layer takes into account the thermal expansion coefficient, size, and shape of the semiconductor element, and even if the temperature changes, the holding resin layer warps.
  • the element is selected so that the element is not damaged or the semiconductor element does not peel from the holding resin layer.
  • the Si capacitor 44 having a thermal expansion coefficient close to that of the Si semiconductor element 13 is used as the capacitor embedded in the holding resin layer 20 together with the Si semiconductor element 13.
  • the holding resin layer 20 is prevented from warping, the Si semiconductor element 13 is damaged, and the Si semiconductor element 13 and the Si capacitor 44 are prevented from peeling from the holding resin layer.
  • capacitor semiconductor devices 100 to 600 according to the first to sixth embodiments have been described above.
  • the present invention is not limited to the contents described above, and various modifications can be made in accordance with the spirit of the invention.
  • trench capacitors are used for the Si capacitors 4, 14, 24, 34, and 44.
  • the Si capacitor only needs to use Si for the substrate, Is not limited and may be of other types.
  • the Si capacitor 44 having only the trench capacitor is embedded in the holding resin layer 20 as the Si capacitor.
  • the Si capacitor 14 including the trench capacitor and the thin film resistor 15, the Si capacitor 24 including the trench capacitor and the thin film high-capacitance capacitor 16, the trench capacitor and the multilayer ceramic capacitor 18 used in the other embodiments are used.
  • a Si capacitor 34 or the like provided with may be embedded in the holding resin layer 20.
  • the number of Si capacitors mounted on the Si interposer 1 and the number of Si capacitors embedded in the holding resin layer 20 are arbitrary, and are not limited to the number drawn in the drawing.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

L'invention concerne un dispositif à semi-conducteur avec un condensateur pour lequel même lorsqu'un changement de température se produit, un gauchissement, un endommagement d'un élément semi-conducteur, et l'apparition d'une défaillance de connexion sont empêchés. L'invention concerne au moins un élément semi-conducteur de Si 3 formé à l'aide de Si, et au moins un condensateur de Si 4 formé à l'aide de Si, l'élément semi-conducteur de Si 3 et le condensateur de Si 4 étant respectivement disposés alignés dans la direction plane en étant montés sur un interposeur de Si 1 formé à l'aide de Si.
PCT/JP2017/024085 2016-08-19 2017-06-30 Dispositif à semi-conducteur avec condensateur WO2018034067A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016161029 2016-08-19
JP2016-161029 2016-08-19

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WO2018034067A1 true WO2018034067A1 (fr) 2018-02-22

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TW (1) TWI651741B (fr)
WO (1) WO2018034067A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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