WO2018034067A1 - Semiconductor device with capacitor - Google Patents

Semiconductor device with capacitor Download PDF

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Publication number
WO2018034067A1
WO2018034067A1 PCT/JP2017/024085 JP2017024085W WO2018034067A1 WO 2018034067 A1 WO2018034067 A1 WO 2018034067A1 JP 2017024085 W JP2017024085 W JP 2017024085W WO 2018034067 A1 WO2018034067 A1 WO 2018034067A1
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WIPO (PCT)
Prior art keywords
capacitor
semiconductor element
semiconductor device
layer
resin layer
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PCT/JP2017/024085
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French (fr)
Japanese (ja)
Inventor
尚之 小林
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株式会社村田製作所
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Publication of WO2018034067A1 publication Critical patent/WO2018034067A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Definitions

  • the present invention relates to a semiconductor device with a capacitor, and more particularly, to a semiconductor device with a capacitor in which, even if a temperature change occurs, warpage, damage to a semiconductor element, and occurrence of poor connection are suppressed.
  • a power supply wiring that supplies power to the semiconductor element and a ground wiring are interposed.
  • a capacitor decoupling capacitor
  • Japanese Laid-Open Patent Publication No. 2001-223299 discloses a package substrate in which a capacitor is connected between a power supply wiring and a ground wiring.
  • FIG. 7 shows a package substrate 1000 disclosed in Patent Document 1.
  • a semiconductor element (IC chip) 101 is mounted on the package substrate 1000.
  • a power supply wiring (power supply line) 102 is connected from the power supply to the power supply terminal 101 ⁇ / b> P of the semiconductor element 101.
  • a ground wiring (earth wire) 103 is connected from the ground terminal 101E of the semiconductor element 101 to the power source.
  • capacitors (chip capacitors) 104 and 105 are mounted on the package substrate 1000.
  • the capacitors 104 and 105 are connected between the power supply wiring 102 and the ground wiring 103, respectively.
  • the loop inductance that becomes a transmission loss is proportional to the wiring length from the power supply terminal 101P of the semiconductor element 101 to the power supply via the power supply wiring 102 and the wiring length from the power supply to the ground terminal 101E via the ground wiring 103.
  • the loop length for determining the loop inductance is shortened to the wiring length via the capacitors 104 and 105 indicated by solid lines in the drawing.
  • the capacitors 104 and 105 are preferably connected as close to the semiconductor element 101 as possible.
  • the package substrate 1000 reduces the power impedance by reducing the loop inductance and suppresses voltage fluctuation.
  • the capacitors 104 and 105 have a function of removing noise entering and exiting the semiconductor element 101.
  • capacitors 104 and 105 are connected in the package substrate 1000.
  • different types of capacitors for example, aluminum
  • Many electrolytic capacitors and multilayer ceramic capacitors may be connected.
  • a sealing resin layer may be provided so as to cover the semiconductor element 101 and the capacitors 104 and 105.
  • FO-WLP fan-out-wafer-level package
  • This FO-WLP cuts out a semiconductor element from a wafer, attaches the functional surface (terminal surface) side of the semiconductor element to a film, and then molds a resin on the surface opposite to the film of the semiconductor element.
  • a packaging method for removing a film The semiconductor element is embedded in the resin layer (holding resin layer) with the functional surface (terminal surface) side exposed to the outside.
  • a rewiring layer is formed on the surface of the resin layer where the semiconductor element is exposed.
  • the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the interposer may be brought close to each other.
  • the difference between the thermal expansion coefficient of the Si interposer and the thermal expansion coefficient of the capacitor is too large.
  • the Si interposer may be warped, the capacitor may be peeled off from the Si interposer, or a connection failure may occur.
  • the semiconductor device with a capacitor according to the present invention is formed of at least one Si semiconductor element formed of Si and Si.
  • the Si semiconductor element and the Si capacitor are mounted on the Si interposer, respectively, and a sealing resin layer is formed on the main surface of the Si interposer so as to cover the mounted Si semiconductor element and the Si capacitor. can do.
  • the Si interposer and the mounted Si semiconductor element and the Si capacitor have close thermal expansion coefficients, the Si interposer is warped even if a temperature change occurs, or the Si semiconductor element and the Si capacitor are It does not peel off from the interposer or cause poor connection. Further, the Si semiconductor element and the Si capacitor are protected from the outside by the sealing resin layer.
  • each of the Si semiconductor element and the Si capacitor is embedded in the holding resin layer with one main surface exposed, and on the main surface of the holding resin layer where the Si semiconductor element and the Si capacitor are exposed, A rewiring layer may be formed.
  • the holding resin layer, the embedded Si semiconductor element, and the Si capacitor have similar coefficients of thermal expansion. Therefore, even if a temperature change occurs, the holding resin layer warps, the Si semiconductor element or the Si capacitor. The capacitor does not peel from the holding resin layer.
  • the Si capacitor for example, a trench capacitor in which a hole is formed in a Si base made of Si and formed in the hole can be used.
  • the Si capacitor is not limited to a trench capacitor, and may have another structure.
  • a thin film high-capacitance capacitor in which a conductive porous layer, a dielectric layer, and a conductor layer are sequentially laminated on the Si capacitor is formed, and the Si capacitor and the thin-film high-capacity capacitor are connected in parallel.
  • the required large capacitance can be formed between the power supply wiring and the ground wiring by using the Si capacitor and the thin film high-capacity capacitor.
  • the Si capacitor mainly reduces the power impedance in the high frequency range
  • the thin film high-capacitance capacitor mainly reduces the power impedance in the low frequency range, reducing the power impedance over a wide frequency range, and suppressing voltage fluctuations. Can do. Furthermore, noises of various frequencies can be removed.
  • a multilayer ceramic capacitor may be mounted on the Si capacitor, and the Si capacitor and the multilayer ceramic capacitor may be connected in parallel.
  • the required large capacitance can be formed between the power supply wiring and the ground wiring by the Si capacitor and the multilayer ceramic capacitor.
  • the Si capacitor mainly reduces the power supply impedance in the high frequency range
  • the multilayer ceramic capacitor mainly reduces the power supply impedance in the low frequency range, thereby reducing the power supply impedance over a wide frequency range and suppressing voltage fluctuations. it can. Furthermore, noises of various frequencies can be removed.
  • the multilayer ceramic capacitor is directly mounted on the Si interposer or embedded in the holding resin layer, the above-mentioned trouble may occur due to a temperature change, but if the multilayer ceramic capacitor is mounted on the Si capacitor, Since the Si capacitor functions as a buffer material, it is possible to avoid such troubles.
  • a thin film resistor may be formed on the surface of the Si capacitor, and the Si capacitor and the thin film resistor may be connected in series. If the ESR (Equivalent Series Resistance) of the Si capacitor is too small relative to the inductance component of the power supply wiring, anti-resonance with a large peak may occur, but as described above, the thin film resistor in series with the Si capacitor Can be connected to suppress the peak of antiresonance.
  • ESR Equivalent Series Resistance
  • the semiconductor device with a capacitor uses a Si semiconductor element as a semiconductor element, uses a Si capacitor as a capacitor, and arranges or holds the Si semiconductor element and the Si capacitor in a planar direction in a Si interposer. Since one main surface is embedded in the resin layer for use, even if the temperature changes, warping, damage to the semiconductor element, peeling of the semiconductor element or Si capacitor, or connection failure may occur. Is suppressed.
  • FIG. 1A is a front view showing the capacitor-equipped semiconductor device 100 according to the first embodiment.
  • FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor. It is explanatory drawing (front view which looked through and showed the inside of the resin layer 12 for sealing) which shows the semiconductor device 200 with a capacitor concerning 2nd Embodiment.
  • FIG. 3A is a front view showing a semiconductor device 300 with a capacitor according to the third embodiment.
  • FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor.
  • FIG. 4A is a front view showing a semiconductor device with a capacitor 400 according to the fourth embodiment.
  • FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400.
  • FIG. 5A is a front view showing a semiconductor device 500 with a capacitor according to the fifth embodiment.
  • FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500.
  • 6 (A) to 6 (E) are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 according to the sixth embodiment (see through the inside of the holding resin layer 20). It is a front view shown).
  • 10 is an explanatory view showing a package substrate 1000 disclosed in Patent Document 1.
  • FIG. 1 is an explanatory view showing a package substrate 1000 disclosed in Patent Document 1.
  • each embodiment shows an embodiment of the present invention by way of example, and the present invention is not limited to the content of the embodiment. Moreover, it is also possible to implement combining the content described in different embodiment, and the implementation content in that case is also included in this invention. Further, the drawings are for helping understanding of the embodiment, and may not be drawn strictly. For example, a drawn component or a dimensional ratio between the components may not match the dimensional ratio described in the specification. In addition, the constituent elements described in the specification may be omitted in the drawings or may be drawn with the number omitted.
  • FIG. 1A and 1B show a semiconductor device 100 with a capacitor according to the first embodiment.
  • FIG. 1A is a front view showing the semiconductor device 100 with a capacitor.
  • FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor.
  • the capacitor-equipped semiconductor device 100 includes a Si interposer 1 made of Si. Although not shown, a plurality of electrodes are formed on both main surfaces of the Si interposer 1, and predetermined wiring is made by surface wiring, interlayer wiring, via conductors, and the like.
  • the Si interposer 1 can be manufactured by an existing interposer manufacturing method that is generally implemented.
  • a semiconductor element (LSI element or the like) 3 is mounted on the electrode formed on the upper main surface of the Si interposer 1 by a bump 2 made of Sn-3.5Ag, Cu, Sn-Pb or the like.
  • the Si capacitor 4 is mounted by the bump 2 on another electrode formed on the upper main surface of the Si interposer.
  • FIG. 1B shows the details of the Si capacitor 4.
  • a trench capacitor is used as the Si capacitor 4.
  • the Si capacitor 4 includes a Si base 5 made of Si.
  • a plurality of holes 6 are formed in one main surface (lower main surface) of the Si substrate 5.
  • An insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the hole 6.
  • the insulating layer 7 is formed of SiO 2
  • the first electrode layer 8 is formed of Si
  • the dielectric layer 9 is formed of Ti 2 O 3
  • the second electrode layer 10 is formed of TiN. .
  • the first electrode layer 8 and the second electrode layer 10 are each drawn out to the surface of the Si substrate 5, and the bumps 2 are formed in the drawn portions.
  • the Si capacitor 4 can be manufactured by an existing trench capacitor manufacturing method that is generally performed.
  • a bump 11 made of Sn-3.5Ag, Cu, Sn-Pb or the like is formed on the electrode formed on the lower main surface of the Si interposer.
  • the Si capacitor 4 is connected between a power supply wiring (not shown) for supplying power to the Si semiconductor element 3 and a ground wiring (not shown).
  • the Si capacitor 4 is connected between the power supply wiring and the ground wiring, so that the power supply impedance is small and voltage fluctuation is suppressed. Further, noise can be removed by the Si capacitor 4.
  • the semiconductor device with a capacitor 100 since the semiconductor device with a capacitor 100 has the Si semiconductor element 3 and the Si capacitor 4 mounted on the Si interposer 1 having a coefficient of thermal expansion close to each other, even if a temperature change occurs, The semiconductor element 3 is not damaged, and the Si semiconductor element 3 and the Si capacitor 4 are not peeled off from the Si interposer 1 to cause connection failure.
  • the capacitor-equipped semiconductor device 100 has a low profile because the Si capacitor 4 has a smaller height than an aluminum electrolytic capacitor or a multilayer ceramic capacitor.
  • FIG. 2 shows a semiconductor device 200 with a capacitor according to the second embodiment.
  • FIG. 2 is an explanatory view showing the semiconductor device with a capacitor 200 (a front view seen through the inside of the sealing resin layer 12).
  • the sealing resin layer 12 is added to the semiconductor device with a capacitor 100 according to the first embodiment. Specifically, in the semiconductor device with a capacitor 200, the sealing resin layer 12 is formed on the upper main surface of the Si interposer 1 so as to cover the Si semiconductor element 3 and the Si capacitor 4.
  • the sealing resin layer 12 is for protecting the Si semiconductor element 3 and the Si capacitor 4 and has characteristics such as a linear expansion coefficient relatively close to Si and low hygroscopicity. preferable.
  • an epoxy resin, a silicon resin, or the like can be used for the sealing resin layer 12.
  • the sealing resin layer 12 is formed by, for example, dropping a liquid resin on the upper main surface of the Si interposer 1 and heating it to cure after mounting the Si semiconductor element 3 and the Si capacitor 4. Can do.
  • FIG. 3A and 3B show a capacitor-equipped semiconductor device 300 according to the third embodiment.
  • FIG. 3A is a front view showing the semiconductor device 300 with a capacitor.
  • FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor.
  • the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with a Si capacitor 14 having a thin film resistor 15 formed on the surface thereof. Then, the Si semiconductor element 3 and the Si capacitor 14 were mounted on the Si interposer 1.
  • FIG. 3B shows the details of the Si capacitor 14.
  • the Si capacitor 14 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • the thin film resistor 15 is further formed on the lower main surface of the Si base 5 in the Si capacitor 14.
  • the thin film resistor 15 is made of NiCr, for example.
  • the thin film resistor 15 is connected in series with the trench capacitor (the first electrode layer 8, the dielectric layer 9, and the second electrode layer 10).
  • the ESR of the capacitor connected between the power supply wiring and the ground is too small with respect to the inductance component of the power supply wiring, anti-resonance with a large peak in the power supply impedance may occur.
  • the semiconductor device with a capacitor 300 according to the third embodiment since the thin film resistor 15 is connected in series with the trench capacitor, the anti-resonance peak can be suppressed to a small value.
  • the thin film resistor 15 can be formed by thin film technology, for example.
  • FIG. 4A and 4B show a semiconductor device 400 with a capacitor according to the fourth embodiment.
  • FIG. 4A is a front view showing the semiconductor device 400 with a capacitor.
  • FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400.
  • the Si capacitor 4 of the semiconductor device with capacitor 100 according to the first embodiment is replaced with the Si capacitor 24 in which the thin film high-capacitance capacitor 16 is formed on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 24 were mounted on the Si interposer 1.
  • FIG. 4B shows details of the Si capacitor 24.
  • the Si capacitor 24 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • a thin film high-capacity capacitor 16 is further formed on the upper main surface of the Si base 5.
  • the thin film high-capacitance capacitor 16 has a structure in which a conductive porous layer 16a, a dielectric layer 16b, and a conductive layer 16c are sequentially stacked.
  • the thin film high capacity capacitor 16 has a very large capacity because the dielectric layer 16b is formed on the conductive porous layer 16a.
  • the thin film high capacity capacitor 16 can be formed by the following method, for example.
  • an insulating layer 17 made of, for example, SiO 2 is formed in a region of the Si base 5 where the thin film high capacity capacitor 16 is to be formed.
  • the insulating layer 17 made of SiO 2 can be formed by a CVD (Chemical Vapor Deposition) method or the like.
  • a conductor layer (not shown) made of, for example, Al is formed on the insulating layer 17 by, for example, photolithography.
  • the material of the conductor layer is not limited to Al and may be other metals.
  • an extremely large number of fine holes are formed in the conductor layer by, for example, etching after anodic oxidation to form the conductor porous body layer 16a.
  • the formation of fine holes is not limited to the anodic oxidation method, and may be formed by a method such as a method of depositing metal fine particles by printing, ink jetting, spraying, spraying, or the like.
  • a dielectric layer 16b made of, for example, AlOX (X is 1.2 or more) is formed on the conductive porous layer 16a by an atomic deposition method (ALD method; Atomic Layer Deposition).
  • a diffusion preventing layer made of, for example, TiON may be formed in advance between the conductive porous body layer 16a and the dielectric layer 16b. The formation of the diffusion preventing layer can also be performed by the ALD method.
  • a conductor layer 16c made of, for example, Al is formed on the dielectric layer 16b by, for example, the ALD method.
  • the material of the conductor layer 16c is not limited to Al, and may be Cu, Ni, or the like.
  • a diffusion prevention layer made of TiON or the like may be formed in advance between the dielectric layer 16b and the conductor layer 16c. This diffusion prevention layer can also be formed by the ALD method.
  • the conductive porous body layer 16a, the dielectric layer 16b, and the conductive layer 16c are patterned by using a photolithography technique to complete the thin film high-capacitance capacitor 16.
  • the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the thin film high-capacitance capacitor 16 are formed in the Si substrate 5 and via conductors are formed. By connecting in parallel.
  • the capacitor-equipped semiconductor device 400 can form a desired large capacitance between the power supply wiring and the ground wiring by the trench capacitor and the thin film high-capacitance capacitor 16.
  • the capacitor-equipped semiconductor device 400 since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
  • the thin film resistor 15 is formed on the surface of the Si substrate 5, and the trench capacitor (first electrode layer) of the Si capacitor 24 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
  • FIG. 5A and 5B show a semiconductor device 500 with a capacitor according to the fifth embodiment.
  • FIG. 5A is a front view showing the semiconductor device 500 with a capacitor.
  • FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500.
  • the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with the Si capacitor 34 on which the multilayer ceramic capacitor 18 is mounted on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 34 were mounted on the Si interposer 1.
  • FIG. 5B shows details of the Si capacitor 34.
  • the Si capacitor 34 includes a Si base 5, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
  • a multilayer ceramic capacitor 18 is mounted on the upper main surface of the Si base 5 using a bonding material 19.
  • the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the multilayer ceramic capacitor 18 are formed in the Si substrate 5 and via conductors are formed. Are connected in parallel.
  • the trench capacitor and the multilayer ceramic capacitor 18 provide a desired large capacity between the power supply wiring and the ground wiring. Can be formed.
  • the capacitor-equipped semiconductor device 400 since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
  • the semiconductor device with a capacitor 400 uses a multilayer ceramic capacitor 18 having a coefficient of thermal expansion that is significantly different from that of the Si interposer 1 and the Si semiconductor element 3.
  • Si Since it is mounted on the interposer 1 and the Si base 5 functions as a kind of buffer material, even if a temperature change occurs, it does not warp and the multilayer ceramic capacitor 18 does not peel off.
  • the thin film resistor 15 is formed on the surface of the Si base 5, and the trench capacitor (first electrode layer) of the Si capacitor 34 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
  • FIGS. 6A to 6E show a semiconductor device 600 with a capacitor according to a sixth embodiment.
  • FIGS. 6A to 6E are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 (front views showing through the inside of the holding resin layer 20). 6E shows the completed semiconductor device 600 with a capacitor.
  • the capacitor-equipped semiconductor device 600 holds the Si semiconductor element 13 and the Si capacitor 44 in the holding resin layer 20 by FO-WLP (fan out-Wafer Level Package).
  • FO-WLP fan out-Wafer Level Package
  • the Si semiconductor element 13 and the Si capacitor 44 are prepared.
  • the Si semiconductor element 13 the same one as the Si semiconductor element 3 used in the first embodiment was prepared.
  • the Si capacitor 44 the same one as the Si capacitor 4 used in the first embodiment was prepared.
  • the bumps are not formed on the lower main surface of the Si semiconductor element 13 and the Si capacitor 44, respectively.
  • the Si semiconductor element 13 and the Si capacitor 44 are attached to the film 21 with the surfaces on which the terminals are formed facing the film 21, respectively.
  • the surface of the film 21 is previously given adhesiveness.
  • a liquid resin is dropped on the film 21 so as to cover the Si semiconductor element 13 and the Si capacitor 44, and then heated to cure the resin and retain the resin.
  • Layer 20 is formed.
  • a material having characteristics (such as a linear expansion coefficient) that the holding resin layer 20 is not warped or the Si semiconductor element 13 is not peeled off from the holding resin layer 20 must be selected.
  • the film 21 is removed from the holding resin layer 20 in which the Si semiconductor element 13 and the Si capacitor 44 are embedded.
  • 6C to 6E show the holding resin layer 20 upside down with respect to FIGS. 6A and 6B.
  • the surface on which the terminals of the Si semiconductor element 13 are formed and the surface on which the terminals of the Si capacitor 44 are formed are exposed.
  • the rewiring layer 22 is formed on the surface of the holding resin layer 20 where the Si semiconductor element 13 and the Si capacitor 44 are exposed.
  • the redistribution layer 22 is formed by laminating a plurality of insulating layers (not shown), and a via conductor formed through the insulating layer or a wiring electrode formed between the layers, between the two main surfaces. Wiring is made.
  • the rewiring layer 22 connects the Si semiconductor element 13 and the Si capacitor 44.
  • the rewiring layer 22 can be formed using a general insulating material or a conductive material by using a photolithography technique.
  • bumps 23 are formed on the rewiring layer 22 to complete the semiconductor device 600 with a capacitor.
  • the resin constituting the holding resin layer takes into account the thermal expansion coefficient, size, and shape of the semiconductor element, and even if the temperature changes, the holding resin layer warps.
  • the element is selected so that the element is not damaged or the semiconductor element does not peel from the holding resin layer.
  • the Si capacitor 44 having a thermal expansion coefficient close to that of the Si semiconductor element 13 is used as the capacitor embedded in the holding resin layer 20 together with the Si semiconductor element 13.
  • the holding resin layer 20 is prevented from warping, the Si semiconductor element 13 is damaged, and the Si semiconductor element 13 and the Si capacitor 44 are prevented from peeling from the holding resin layer.
  • capacitor semiconductor devices 100 to 600 according to the first to sixth embodiments have been described above.
  • the present invention is not limited to the contents described above, and various modifications can be made in accordance with the spirit of the invention.
  • trench capacitors are used for the Si capacitors 4, 14, 24, 34, and 44.
  • the Si capacitor only needs to use Si for the substrate, Is not limited and may be of other types.
  • the Si capacitor 44 having only the trench capacitor is embedded in the holding resin layer 20 as the Si capacitor.
  • the Si capacitor 14 including the trench capacitor and the thin film resistor 15, the Si capacitor 24 including the trench capacitor and the thin film high-capacitance capacitor 16, the trench capacitor and the multilayer ceramic capacitor 18 used in the other embodiments are used.
  • a Si capacitor 34 or the like provided with may be embedded in the holding resin layer 20.
  • the number of Si capacitors mounted on the Si interposer 1 and the number of Si capacitors embedded in the holding resin layer 20 are arbitrary, and are not limited to the number drawn in the drawing.

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Abstract

Provided is a semiconductor device with capacitor for which even when a temperature change occurs, warping, damage to a semiconductor element, and the occurrence of connection failure are suppressed. Provided are at least one Si semiconductor element 3 formed using Si, and at least one Si capacitor 4 formed using Si, wherein the Si semiconductor element 3 and the Si capacitor 4 are respectively placed aligned in the planar direction by being mounted on one Si interposer 1 formed using Si.

Description

キャパシタ付半導体装置Semiconductor device with capacitor
　本発明は、キャパシタ付半導体装置に関し、さらに詳しくは、温度変化が起こっても、反ったり、半導体素子が破損したり、接続不良が発生したりすることが抑制されたキャパシタ付半導体装置に関する。 The present invention relates to a semiconductor device with a capacitor, and more particularly, to a semiconductor device with a capacitor in which, even if a temperature change occurs, warpage, damage to a semiconductor element, and occurrence of poor connection are suppressed.
　半導体素子を使用した電子回路においては、ノイズを除去するために、また、電源インピーダンスを小さくして電圧変動を抑制するために、半導体素子へ電力を供給する電源配線と、グランド配線との間に、キャパシタ（デカップリングコンデンサ）を接続する場合が多い。 In an electronic circuit using a semiconductor element, in order to eliminate noise and to reduce voltage fluctuation by reducing power supply impedance, a power supply wiring that supplies power to the semiconductor element and a ground wiring are interposed. In many cases, a capacitor (decoupling capacitor) is connected.
　特許文献１（特開２００１-２２３２９９号公報）に、電源配線とグランド配線との間にキャパシタを接続したパッケージ基板が開示されている。 Japanese Laid-Open Patent Publication No. 2001-223299 discloses a package substrate in which a capacitor is connected between a power supply wiring and a ground wiring.
　図７に、特許記文献１に開示されたパッケージ基板１０００を示す。 FIG. 7 shows a package substrate 1000 disclosed in Patent Document 1.
　パッケージ基板１０００には、半導体素子（ＩＣチップ）１０１が実装されている。そして、電源から半導体素子１０１の電源端子１０１Ｐに、電源配線（電源線）１０２が接続されている。また、半導体素子１０１のグランド端子１０１Ｅから電源に、グランド配線（アース線）１０３が接続されている。 A semiconductor element (IC chip) 101 is mounted on the package substrate 1000. A power supply wiring (power supply line) 102 is connected from the power supply to the power supply terminal 101 </ b> P of the semiconductor element 101. A ground wiring (earth wire) 103 is connected from the ground terminal 101E of the semiconductor element 101 to the power source.
　パッケージ基板１０００には、さらに、キャパシタ（チップコンデンサ）１０４、１０５が実装されている。キャパシタ１０４、１０５は、それぞれ、電源配線１０２とグランド配線１０３との間に接続されている。 Further, capacitors (chip capacitors) 104 and 105 are mounted on the package substrate 1000. The capacitors 104 and 105 are connected between the power supply wiring 102 and the ground wiring 103, respectively.
　伝送損失となるループインダクタンスは、半導体素子１０１の電源端子１０１Ｐから電源配線１０２を介して電源までの配線長、および、電源からグランド配線１０３を介してグランド端子１０１Ｅまでの配線長に比例するが、パッケージ基板１０００では、キャパシタ１０４、１０５を接続することにより、ループインダクタンスを決定するループ長を、図中に実線で示すキャパシタ１０４、１０５を経由する配線長に短縮している。なお、ループ長を短くするためには、キャパシタ１０４、１０５は、できる限り半導体素子１０１の近くに接続することが好ましい。 The loop inductance that becomes a transmission loss is proportional to the wiring length from the power supply terminal 101P of the semiconductor element 101 to the power supply via the power supply wiring 102 and the wiring length from the power supply to the ground terminal 101E via the ground wiring 103. In the package substrate 1000, by connecting the capacitors 104 and 105, the loop length for determining the loop inductance is shortened to the wiring length via the capacitors 104 and 105 indicated by solid lines in the drawing. In order to shorten the loop length, the capacitors 104 and 105 are preferably connected as close to the semiconductor element 101 as possible.
　パッケージ基板１０００は、ループインダクタンスを小さくすることによって、電源インピーダンスを小さくし、電圧変動を抑制している。また、キャパシタ１０４、１０５は、半導体素子１０１に出入りするノイズを除去する機能も有している。 The package substrate 1000 reduces the power impedance by reducing the loop inductance and suppresses voltage fluctuation. In addition, the capacitors 104 and 105 have a function of removing noise entering and exiting the semiconductor element 101.
　なお、パッケージ基板１０００では、２個のキャパシタ１０４、１０５を接続しているが、広い周波数範囲で電源インピーダンスを小さくするために、電源配線とグランド配線との間に、種類の異なるキャパシタ（たとえばアルミ電解キャパシタと積層セラミックキャパシタなど）を、多数個、接続する場合もある。 In the package substrate 1000, two capacitors 104 and 105 are connected. In order to reduce the power supply impedance in a wide frequency range, different types of capacitors (for example, aluminum) are provided between the power supply wiring and the ground wiring. Many electrolytic capacitors and multilayer ceramic capacitors may be connected.
　また、パッケージ基板１０００では示されていないが、半導体素子１０１やキャパシタ１０４、１０５を覆うように、封止用樹脂層を設ける場合もある。 Although not shown in the package substrate 1000, a sealing resin layer may be provided so as to cover the semiconductor element 101 and the capacitors 104 and 105.
特開２００１-２２３２９９号公報JP 2001-223299 A
　今日、半導体素子（ＬＳＩ素子など）の小型化が進み、平面方向にも、厚み方向にも、寸法が極めて小さくなってきている。それにともない、半導体素子を直接に基板に実装するのではなく、間にインターポーザを介して、基板に実装する場合がある。 Today, the miniaturization of semiconductor elements (LSI elements, etc.) has progressed, and the dimensions have become extremely small both in the planar direction and in the thickness direction. Along with this, there is a case where the semiconductor element is not directly mounted on the substrate, but is mounted on the substrate via an interposer.
　また、新しい半導体パッケージ技術として、ＦＯ-ＷＬＰ（fan out - Wafer Level Package）と呼ばれる手法が実用化されつつある。このＦＯ-ＷＬＰは、ウエハから半導体素子を切り出し、半導体素子の機能面（端子面）側をフィルムに貼着させたうえで、半導体素子のフィルムと反対側の面に樹脂を成型し、成型後にフィルムを除去するパッケージング方法である。半導体素子は、機能面（端子面）側を外部に露出させて、樹脂層（保持用樹脂層）に埋設される。そして、樹脂層の半導体素子が露出した面に、再配線層が形成される。 Also, as a new semiconductor package technology, a technique called FO-WLP (fan-out-wafer-level package) is being put into practical use. This FO-WLP cuts out a semiconductor element from a wafer, attaches the functional surface (terminal surface) side of the semiconductor element to a film, and then molds a resin on the surface opposite to the film of the semiconductor element. A packaging method for removing a film. The semiconductor element is embedded in the resin layer (holding resin layer) with the functional surface (terminal surface) side exposed to the outside. A rewiring layer is formed on the surface of the resin layer where the semiconductor element is exposed.
　小型化された脆弱な半導体素子を、インターポーザに実装する場合や、ＦＯ-ＷＬＰによって保持用樹脂層に埋設させる場合には、半導体素子の熱膨張係数とインターポーザの熱膨張係数をできるだけ近づけること、また、半導体素子の熱膨張係数と保持用樹脂層の熱膨張係数とをできるだけ近づけることが重要である。熱膨張係数に差があると、僅かな温度変化で、半導体素子が破損したり、インターポーザや保持用樹脂層が反ったり、半導体素子がインターポーザや保持用樹脂層から剥離したりする虞があるからである。 When mounting a miniaturized fragile semiconductor element in an interposer or embedding it in a holding resin layer with FO-WLP, make the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the interposer as close as possible. It is important to make the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the holding resin layer as close as possible. If there is a difference in the coefficient of thermal expansion, a slight temperature change may damage the semiconductor element, warp the interposer or holding resin layer, or peel the semiconductor element from the interposer or holding resin layer. It is.
　そこで、たとえば、Ｓｉにより形成されたＳｉ半導体素子を、Ｓｉにより形成されたＳｉインターポーザに実装することで、半導体素子の熱膨張係数とインターポーザの熱膨張係数とを近づける場合がある。 Therefore, for example, by mounting a Si semiconductor element formed of Si on a Si interposer formed of Si, the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the interposer may be brought close to each other.
　また、ＦＯ-ＷＬＰにおいては、埋設される半導体素子の熱膨張係数や大きさや形状を十分に考慮したうえで、慎重に保持用樹脂層の材質を選定し、温度変化があっても、保持用樹脂層が反ったり、半導体素子が破損したり、半導体素子が保持用樹脂層から剥離したりしないようにしている。 In FO-WLP, after carefully considering the thermal expansion coefficient, size, and shape of the embedded semiconductor element, carefully select the material of the holding resin layer, even if there is a change in temperature. The resin layer is not warped, the semiconductor element is damaged, or the semiconductor element is not separated from the holding resin layer.
　一方、上述したように、半導体素子を使用した電子回路において、ノイズの出入りや電圧変動を抑制するために、電源配線とグランド配線との間にキャパシタを接続する場合、できるだけ半導体素子の近くに接続することが好ましい。したがって、たとえば、インターポーザを使用する場合には、インターポーザにキャパシタが実装されることが好ましい。また、ＦＯ-ＷＬＰによる場合には、保持用樹脂層に、キャパシタを埋設することが好
ましい。 On the other hand, as described above, in an electronic circuit using a semiconductor element, when connecting a capacitor between the power supply wiring and the ground wiring in order to suppress noise in / out and voltage fluctuation, connect as close to the semiconductor element as possible. It is preferable to do. Therefore, for example, when an interposer is used, it is preferable that a capacitor is mounted on the interposer. In the case of FO-WLP, it is preferable to embed a capacitor in the holding resin layer.
　しかしながら、Ｓｉにより形成されたＳｉインターポーザに、アルミ電解キャパシタや、積層セラミックキャパシタを実装した場合、Ｓｉインターポーザの熱膨張係数とキャパシタの熱膨張係数との差が大き過ぎるために、僅かな温度変化で、Ｓｉインターポーザが反ったり、キャパシタがＳｉインターポーザから剥離したり、接続不良を起こしたりする虞があった。 However, when an aluminum electrolytic capacitor or a multilayer ceramic capacitor is mounted on a Si interposer formed of Si, the difference between the thermal expansion coefficient of the Si interposer and the thermal expansion coefficient of the capacitor is too large. The Si interposer may be warped, the capacitor may be peeled off from the Si interposer, or a connection failure may occur.
　また、Ｓｉ半導体素子の熱膨張係数などを考慮して選定された、ＦＯ-ＷＬＰの保持用樹脂層に、アルミ電解キャパシタや、積層セラミックキャパシタを埋設した場合、保持用樹脂層の熱膨張係数とキャパシタの熱膨張係数との差が大き過ぎるために、僅かな温度変化で、保持用樹脂層が反ったり、キャパシタが保持用樹脂層から剥離したりする虞があった。 In addition, when an aluminum electrolytic capacitor or a multilayer ceramic capacitor is embedded in the holding resin layer of FO-WLP selected in consideration of the thermal expansion coefficient of the Si semiconductor element, the thermal expansion coefficient of the holding resin layer Since the difference from the thermal expansion coefficient of the capacitor is too large, there is a possibility that the holding resin layer is warped or the capacitor is peeled off from the holding resin layer by a slight temperature change.
　本発明は、上述した従来の課題を解決するためになされたものであり、その手段として本発明のキャパシタ付半導体装置は、Ｓｉにより形成された少なくとも１つのＳｉ半導体素子と、Ｓｉにより形成された少なくとも１つのＳｉキャパシタと、を備え、Ｓｉ半導体素子とＳｉキャパシタとが、それぞれ、Ｓｉにより形成された１つのＳｉインターポーザに実装されることにより、または、１つの保持用樹脂層に一方の主面を露出させて埋設されることにより、平面方向に並べて配置されたものとした。 The present invention has been made in order to solve the above-described conventional problems, and as a means therefor, the semiconductor device with a capacitor according to the present invention is formed of at least one Si semiconductor element formed of Si and Si. At least one Si capacitor, wherein the Si semiconductor element and the Si capacitor are each mounted on one Si interposer formed of Si, or one main surface on one holding resin layer It was assumed that they were arranged side by side in the plane direction by being exposed and embedded.
　Ｓｉ半導体素子とＳｉキャパシタとが、それぞれ、Ｓｉインターポーザに実装され、実装されたＳｉ半導体素子とＳｉキャパシタとを覆うように、Ｓｉインターポーザの主面上に封止用樹脂層が形成されたものとすることができる。この場合には、Ｓｉインターポーザと、実装されたＳｉ半導体素子およびＳｉキャパシタとは、熱膨張係数が近いため、温度変化が起こっても、Ｓｉインターポーザが反ったり、Ｓｉ半導体素子やＳｉキャパシタが、Ｓｉインターポーザから剥離したり、接続不良を起こしたりすることがない。また、封止用樹脂層により、Ｓｉ半導体素子とＳｉキャパシタとが外部から保護される。 The Si semiconductor element and the Si capacitor are mounted on the Si interposer, respectively, and a sealing resin layer is formed on the main surface of the Si interposer so as to cover the mounted Si semiconductor element and the Si capacitor. can do. In this case, since the Si interposer and the mounted Si semiconductor element and the Si capacitor have close thermal expansion coefficients, the Si interposer is warped even if a temperature change occurs, or the Si semiconductor element and the Si capacitor are It does not peel off from the interposer or cause poor connection. Further, the Si semiconductor element and the Si capacitor are protected from the outside by the sealing resin layer.
　また、Ｓｉ半導体素子とＳｉキャパシタとが、それぞれ、保持用樹脂層に一方の主面を露出させて埋設され、Ｓｉ半導体素子とＳｉキャパシタとが露出された保持用樹脂層の主面上に、再配線層が形成されたものとすることができる。この場合には、保持用樹脂層と、埋設されたＳｉ半導体素子とＳｉキャパシタとは、熱膨張係数が近いため、温度変化が起こっても、保持用樹脂層が反ったり、Ｓｉ半導体素子やＳｉキャパシタが保持用樹脂層から剥離したりすることがない。 Further, each of the Si semiconductor element and the Si capacitor is embedded in the holding resin layer with one main surface exposed, and on the main surface of the holding resin layer where the Si semiconductor element and the Si capacitor are exposed, A rewiring layer may be formed. In this case, the holding resin layer, the embedded Si semiconductor element, and the Si capacitor have similar coefficients of thermal expansion. Therefore, even if a temperature change occurs, the holding resin layer warps, the Si semiconductor element or the Si capacitor. The capacitor does not peel from the holding resin layer.
　Ｓｉキャパシタとしては、たとえば、Ｓｉにより形成されたＳｉ基体に孔が形成され、孔に形成されたトレンチキャパシタを使用することができる。ただし、Ｓｉキャパシタはトレンチキャパシタには限定されず、他の構造のものであっても良い。 As the Si capacitor, for example, a trench capacitor in which a hole is formed in a Si base made of Si and formed in the hole can be used. However, the Si capacitor is not limited to a trench capacitor, and may have another structure.
　また、Ｓｉキャパシタ上に、導体多孔体層と、誘電体層と、導体層とが順に積層された薄膜高容量キャパシタを形成し、Ｓｉキャパシタと薄膜高容量性キャパシタとを並列に接続しても良い。この場合には、Ｓｉキャパシタと薄膜高容量キャパシタとで、電源配線とグランド配線との間に、必要とする所望の大きな容量を形成することができる。また、Ｓｉキャパシタで主に高周波域の電源インピーダンスを小さくし、薄膜高容量キャパシタで主に低周波域の電源インピーダンスを小さくし、広い周波数範囲にわたって、電源インピーダンスを小さくし、電圧変動を抑制することができる。さらに、種々の周波数のノイズを除去することができる。 Alternatively, a thin film high-capacitance capacitor in which a conductive porous layer, a dielectric layer, and a conductor layer are sequentially laminated on the Si capacitor is formed, and the Si capacitor and the thin-film high-capacity capacitor are connected in parallel. good. In this case, the required large capacitance can be formed between the power supply wiring and the ground wiring by using the Si capacitor and the thin film high-capacity capacitor. In addition, the Si capacitor mainly reduces the power impedance in the high frequency range, and the thin film high-capacitance capacitor mainly reduces the power impedance in the low frequency range, reducing the power impedance over a wide frequency range, and suppressing voltage fluctuations. Can do. Furthermore, noises of various frequencies can be removed.
　また、Ｓｉキャパシタに、積層セラミックキャパシタを実装し、Ｓｉキャパシタと積層セラミックキャパシタとを並列に接続しても良い。この場合には、Ｓｉキャパシタと積層セラミックキャパシタとで、電源配線とグランド配線との間に、必要とする所望の大きな容量を形成することができる。また、Ｓｉキャパシタで主に高周波域の電源インピーダンスを小さくし、積層セラミックキャパシタで主に低周波域の電源インピーダンスを小さくし、広い周波数範囲にわたって、電源インピーダンスを小さくし、電圧変動を抑制することができる。さらに、種々の周波数のノイズを除去することができる。なお、積層セラミックキャパシタを、直接にＳｉインターポーザに実装したり保持用樹脂層に埋設したりすると、温度変化により上述したような支障が生じる虞があるが、Ｓｉキャパシタに積層セラミックキャパシタを実装すれば、Ｓｉキャパシタが緩衝材として機能するため、それらの支障を回避することができる。 Alternatively, a multilayer ceramic capacitor may be mounted on the Si capacitor, and the Si capacitor and the multilayer ceramic capacitor may be connected in parallel. In this case, the required large capacitance can be formed between the power supply wiring and the ground wiring by the Si capacitor and the multilayer ceramic capacitor. In addition, the Si capacitor mainly reduces the power supply impedance in the high frequency range, and the multilayer ceramic capacitor mainly reduces the power supply impedance in the low frequency range, thereby reducing the power supply impedance over a wide frequency range and suppressing voltage fluctuations. it can. Furthermore, noises of various frequencies can be removed. If the multilayer ceramic capacitor is directly mounted on the Si interposer or embedded in the holding resin layer, the above-mentioned trouble may occur due to a temperature change, but if the multilayer ceramic capacitor is mounted on the Si capacitor, Since the Si capacitor functions as a buffer material, it is possible to avoid such troubles.
　また、Ｓｉキャパシタの表面に薄膜抵抗体を形成し、Ｓｉキャパシタと薄膜抵抗体とを直列に接続しても良い。ＳｉキャパシタのＥＳＲ（Equivalent Series Resistance）が、電源配線のインダクタンス成分に対して小さすぎる場合、大きなピークをもった反共振が発生する場合があるが、上記のようにＳｉキャパシタと直列に薄膜抵抗体を接続すれば、反共振のピークを小さく抑制することができる。 Alternatively, a thin film resistor may be formed on the surface of the Si capacitor, and the Si capacitor and the thin film resistor may be connected in series. If the ESR (Equivalent Series Resistance) of the Si capacitor is too small relative to the inductance component of the power supply wiring, anti-resonance with a large peak may occur, but as described above, the thin film resistor in series with the Si capacitor Can be connected to suppress the peak of antiresonance.
　本発明のキャパシタ付半導体装置は、半導体素子にＳｉ半導体素子を用いるとともに、キャパシタにＳｉキャパシタを用い、Ｓｉ半導体素子とＳｉキャパシタとを、平面方向に並べて、Ｓｉインターポーザに実装するか、または、保持用樹脂層に一方の主面を露出させて埋設しているため、温度変化が起こっても、反ったり、半導体素子が破損したり、半導体素子やＳｉキャパシタが剥離したり、接続不良が発生したりすることが抑制されている。 The semiconductor device with a capacitor according to the present invention uses a Si semiconductor element as a semiconductor element, uses a Si capacitor as a capacitor, and arranges or holds the Si semiconductor element and the Si capacitor in a planar direction in a Si interposer. Since one main surface is embedded in the resin layer for use, even if the temperature changes, warping, damage to the semiconductor element, peeling of the semiconductor element or Si capacitor, or connection failure may occur. Is suppressed.
図１（Ａ）は、第１実施形態にかかるキャパシタ付半導体装置１００を示す正面図である。図１（Ｂ）は、キャパシタ付半導体装置１００のＳｉキャパシタ４を示す断面図である。FIG. 1A is a front view showing the capacitor-equipped semiconductor device 100 according to the first embodiment. FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor. 第２実施形態にかかるキャパシタ付半導体装置２００を示す説明図（封止用樹脂層１２の内部を透視して示した正面図）である。It is explanatory drawing (front view which looked through and showed the inside of the resin layer 12 for sealing) which shows the semiconductor device 200 with a capacitor concerning 2nd Embodiment. 図３（Ａ）は、第３実施形態にかかるキャパシタ付半導体装置３００を示す正面図である。図３（Ｂ）は、キャパシタ付半導体装置３００のＳｉキャパシタ１４を示す断面図である。FIG. 3A is a front view showing a semiconductor device 300 with a capacitor according to the third embodiment. FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor. 図４（Ａ）は、第４実施形態にかかるキャパシタ付半導体装置４００を示す正面図である。図４（Ｂ）は、キャパシタ付半導体装置４００のＳｉキャパシタ２４を示す断面図である。FIG. 4A is a front view showing a semiconductor device with a capacitor 400 according to the fourth embodiment. FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400. 図５（Ａ）は、第５実施形態にかかるキャパシタ付半導体装置５００を示す正面図である。図５（Ｂ）は、キャパシタ付半導体装置５００のＳｉキャパシタ３４を示す説明図（一部分を断面で示した正面図）である。FIG. 5A is a front view showing a semiconductor device 500 with a capacitor according to the fifth embodiment. FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500. 図６（Ａ）～（Ｅ）は、それぞれ、第６実施形態にかかるキャパシタ付半導体装置６００の製造方法の一例において実施される工程を示す説明図（保持用樹脂層２０の内部を透視して示した正面図）である。6 (A) to 6 (E) are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 according to the sixth embodiment (see through the inside of the holding resin layer 20). It is a front view shown). 特許文献１に開示されたパッケージ基板１０００を示す説明図である。10 is an explanatory view showing a package substrate 1000 disclosed in Patent Document 1. FIG.
　以下、図面とともに、本発明を実施するための形態について説明する。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
　なお、各実施形態は、本発明の実施の形態を例示的に示したものであり、本発明が実施形態の内容に限定されることはない。また、異なる実施形態に記載された内容を組合せて実施することも可能であり、その場合の実施内容も本発明に含まれる。また、図面は、実施形態の理解を助けるためのものであり、必ずしも厳密に描画されていない場合がある。たとえば、描画された構成要素ないし構成要素間の寸法の比率が、明細書に記載されたそれらの寸法の比率と一致していない場合がある。また、明細書に記載されている構成要素が、図面において省略されている場合や、個数を省略して描画されている場合などがある。 Each embodiment shows an embodiment of the present invention by way of example, and the present invention is not limited to the content of the embodiment. Moreover, it is also possible to implement combining the content described in different embodiment, and the implementation content in that case is also included in this invention. Further, the drawings are for helping understanding of the embodiment, and may not be drawn strictly. For example, a drawn component or a dimensional ratio between the components may not match the dimensional ratio described in the specification. In addition, the constituent elements described in the specification may be omitted in the drawings or may be drawn with the number omitted.
　［第１実施形態］
　図１（Ａ）、（Ｂ）に、第１実施形態にかかるキャパシタ付半導体装置１００を示す。ただし、図１（Ａ）は、キャパシタ付半導体装置１００を示す正面図である。図１（Ｂ）は、キャパシタ付半導体装置１００のＳｉキャパシタ４を示す断面図である。 [First Embodiment]
1A and 1B show a semiconductor device 100 with a capacitor according to the first embodiment. However, FIG. 1A is a front view showing the semiconductor device 100 with a capacitor. FIG. 1B is a cross-sectional view showing the Si capacitor 4 of the semiconductor device 100 with a capacitor.
　キャパシタ付半導体装置１００は、Ｓｉにより形成されたＳｉインターポーザ１を備える。図示しないが、Ｓｉインターポーザ１の両主面には、それぞれ複数の電極が形成され、表面配線、層間配線、ビア導体などによって、所定の配線がなされている。Ｓｉインターポーザ１は、一般に実施されている、既存のインターポーザの製造方法によって製造することができる。 The capacitor-equipped semiconductor device 100 includes a Si interposer 1 made of Si. Although not shown, a plurality of electrodes are formed on both main surfaces of the Si interposer 1, and predetermined wiring is made by surface wiring, interlayer wiring, via conductors, and the like. The Si interposer 1 can be manufactured by an existing interposer manufacturing method that is generally implemented.
　Ｓｉインターポーザ１の上側主面に形成された電極に、Ｓｎ‐３．５Ａｇ、Ｃｕ、Ｓｎ‐Ｐｂなどからなるバンプ２によって、半導体素子（ＬＳＩ素子など）３が実装されている。 A semiconductor element (LSI element or the like) 3 is mounted on the electrode formed on the upper main surface of the Si interposer 1 by a bump 2 made of Sn-3.5Ag, Cu, Sn-Pb or the like.
　また、Ｓｉインターポーザの上側主面に形成された別の電極に、バンプ２によって、Ｓｉキャパシタ４が実装されている。 Further, the Si capacitor 4 is mounted by the bump 2 on another electrode formed on the upper main surface of the Si interposer.
　図１（Ｂ）に、Ｓｉキャパシタ４の詳細を示す。本実施形態においては、Ｓｉキャパシタ４として、トレンチキャパシタを使用している。 FIG. 1B shows the details of the Si capacitor 4. In the present embodiment, a trench capacitor is used as the Si capacitor 4.
　Ｓｉキャパシタ４は、Ｓｉにより形成されたＳｉ基体５を備える。Ｓｉ基体５の一方主面（下側主面）に、複数の孔６が形成されている。 The Si capacitor 4 includes a Si base 5 made of Si. A plurality of holes 6 are formed in one main surface (lower main surface) of the Si substrate 5.
　孔６の内部に、絶縁層７、第１電極層８、誘電体層９、第２電極層１０、が形成されている。本実施形態においては、絶縁層７をＳｉＯ２によって形成し、第１電極層８をＳｉによって形成し、誘電体層９をＴｉ２Ｏ３によって形成し、第２電極層１０をＴｉＮによって形成した。 An insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the hole 6. In this embodiment, the insulating layer 7 is formed of SiO 2 , the first electrode layer 8 is formed of Si, the dielectric layer 9 is formed of Ti 2 O 3 , and the second electrode layer 10 is formed of TiN. .
　第１電極層８、第２電極層１０は、それぞれ、Ｓｉ基体５の表面に引き出され、引き出された部分にバンプ２が形成されている。 The first electrode layer 8 and the second electrode layer 10 are each drawn out to the surface of the Si substrate 5, and the bumps 2 are formed in the drawn portions.
　Ｓｉキャパシタ４は、一般に実施されている、既存のトレンチキャパシタの製造方法によって製造することができる。 The Si capacitor 4 can be manufactured by an existing trench capacitor manufacturing method that is generally performed.
　Ｓｉインターポーザの下側主面に形成された電極に、Ｓｎ‐３．５Ａｇ、Ｃｕ、Ｓｎ‐Ｐｂなどからなるバンプ１１が形成されている。 A bump 11 made of Sn-3.5Ag, Cu, Sn-Pb or the like is formed on the electrode formed on the lower main surface of the Si interposer.
　キャパシタ付半導体装置１００においては、Ｓｉキャパシタ４が、Ｓｉ半導体素子３へ電力を供給する電源配線（図示せず）と、グランド配線（図示せず）との間に接続されている。 In the capacitor-equipped semiconductor device 100, the Si capacitor 4 is connected between a power supply wiring (not shown) for supplying power to the Si semiconductor element 3 and a ground wiring (not shown).
　以上の構造からなるキャパシタ付半導体装置１００は、Ｓｉキャパシタ４を電源配線とグランド配線との間に接続しているため、電源インピーダンスが小さく、電圧変動が抑制されている。また、Ｓｉキャパシタ４によって、ノイズを除去することができる。 In the semiconductor device with a capacitor 100 having the above structure, the Si capacitor 4 is connected between the power supply wiring and the ground wiring, so that the power supply impedance is small and voltage fluctuation is suppressed. Further, noise can be removed by the Si capacitor 4.
　また、キャパシタ付半導体装置１００は、相互に熱膨張係数が近い、Ｓｉインターポーザ１に、Ｓｉ半導体素子３と、Ｓｉキャパシタ４とを実装しているため、温度変化が起こっても、反ったり、Ｓｉ半導体素子３が破損したり、Ｓｉ半導体素子３やＳｉキャパシタ４がＳｉインターポーザ１から剥離して接続不良が発生したりすることがない。 In addition, since the semiconductor device with a capacitor 100 has the Si semiconductor element 3 and the Si capacitor 4 mounted on the Si interposer 1 having a coefficient of thermal expansion close to each other, even if a temperature change occurs, The semiconductor element 3 is not damaged, and the Si semiconductor element 3 and the Si capacitor 4 are not peeled off from the Si interposer 1 to cause connection failure.
　さらに、キャパシタ付半導体装置１００は、Ｓｉキャパシタ４が、アルミ電解キャパシタや積層セラミックキャパシタなどに比べて高さ寸法が小さいため、低背化されている。 Further, the capacitor-equipped semiconductor device 100 has a low profile because the Si capacitor 4 has a smaller height than an aluminum electrolytic capacitor or a multilayer ceramic capacitor.
　［第２実施形態］
　図２に、第２実施形態にかかるキャパシタ付半導体装置２００を示す。ただし、図２は、キャパシタ付半導体装置２００を示す説明図（封止用樹脂層１２の内部を透視して示した正面図）である。 [Second Embodiment]
FIG. 2 shows a semiconductor device 200 with a capacitor according to the second embodiment. However, FIG. 2 is an explanatory view showing the semiconductor device with a capacitor 200 (a front view seen through the inside of the sealing resin layer 12).
　キャパシタ付半導体装置２００は、第１実施形態にかかるキャパシタ付半導体装置１００に、封止用樹脂層１２を追加した。具体的には、キャパシタ付半導体装置２００は、Ｓｉインターポーザの１の上側主面に、Ｓｉ半導体素子３とＳｉキャパシタ４とを覆うように、封止用樹脂層１２が形成されている。 In the semiconductor device with a capacitor 200, the sealing resin layer 12 is added to the semiconductor device with a capacitor 100 according to the first embodiment. Specifically, in the semiconductor device with a capacitor 200, the sealing resin layer 12 is formed on the upper main surface of the Si interposer 1 so as to cover the Si semiconductor element 3 and the Si capacitor 4.
　封止用樹脂層１２は、Ｓｉ半導体素子３やＳｉキャパシタ４を保護するためのものであり、線膨張係数がＳｉに比較的近い、吸湿性が低いなどの特性を備えたものであることが好ましい。封止用樹脂層１２には、たとえば、エポキシ樹脂、シリコン樹脂などを使用することができる。 The sealing resin layer 12 is for protecting the Si semiconductor element 3 and the Si capacitor 4 and has characteristics such as a linear expansion coefficient relatively close to Si and low hygroscopicity. preferable. For the sealing resin layer 12, for example, an epoxy resin, a silicon resin, or the like can be used.
　封止用樹脂層１２は、たとえば、Ｓｉ半導体素子３とＳｉキャパシタ４とを実装した後に、Ｓｉインターポーザの１の上側主面に液状の樹脂を滴下し、加熱して硬化させることにより形成することができる。 The sealing resin layer 12 is formed by, for example, dropping a liquid resin on the upper main surface of the Si interposer 1 and heating it to cure after mounting the Si semiconductor element 3 and the Si capacitor 4. Can do.
　［第３実施形態］
　図３（Ａ）、（Ｂ）に、第３実施形態にかかるキャパシタ付半導体装置３００を示す。ただし、図３（Ａ）は、キャパシタ付半導体装置３００を示す正面図である。図３（Ｂ）は、キャパシタ付半導体装置３００のＳｉキャパシタ１４を示す断面図である。 [Third Embodiment]
3A and 3B show a capacitor-equipped semiconductor device 300 according to the third embodiment. However, FIG. 3A is a front view showing the semiconductor device 300 with a capacitor. FIG. 3B is a cross-sectional view showing the Si capacitor 14 of the semiconductor device 300 with a capacitor.
　キャパシタ付半導体装置３００は、第１実施形態にかかるキャパシタ付半導体装置１００のＳｉキャパシタ４を、表面に薄膜抵抗体１５が形成されたＳｉキャパシタ１４に置換えた。そして、Ｓｉインターポーザ１に、Ｓｉ半導体素子３と、Ｓｉキャパシタ１４とを実装した。 In the semiconductor device with a capacitor 300, the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with a Si capacitor 14 having a thin film resistor 15 formed on the surface thereof. Then, the Si semiconductor element 3 and the Si capacitor 14 were mounted on the Si interposer 1.
　図３（Ｂ）に、Ｓｉキャパシタ１４の詳細を示す。 FIG. 3B shows the details of the Si capacitor 14.
　Ｓｉキャパシタ１４は、Ｓｉキャパシタ４と同様に、Ｓｉ基体５を備え、Ｓｉ基体５にトレンチキャパシタが形成されている。すなわち、Ｓｉ基体５に複数の孔６が形成され、孔６の内部に、絶縁層７、第１電極層８、誘電体層９、第２電極層１０が形成されている。 The Si capacitor 14 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
　Ｓｉキャパシタ１４には、さらに、Ｓｉ基体５の下側主面に、薄膜抵抗体１５が形成されている。薄膜抵抗体１５は、たとえば、ＮｉＣｒからなる。薄膜抵抗体１５は、トレンチキャパシタ（第１電極層８、誘電体層９、第２電極層１０）と直列に接続されている。 The thin film resistor 15 is further formed on the lower main surface of the Si base 5 in the Si capacitor 14. The thin film resistor 15 is made of NiCr, for example. The thin film resistor 15 is connected in series with the trench capacitor (the first electrode layer 8, the dielectric layer 9, and the second electrode layer 10).
　上述したとおり、電源配線とグランドとの間に接続するキャパシタのＥＳＲが、電源配線のインダクタンス成分に対して小さすぎる場合、電源インピーダンスに大きなピークをもった反共振が発生する場合がある。しかしながら、第３実施形態にかかるキャパシタ付半導体装置３００では、トレンチキャパシタと直列に薄膜抵抗体１５を接続しているため、反共振のピークを小さく抑えることができる。 As described above, if the ESR of the capacitor connected between the power supply wiring and the ground is too small with respect to the inductance component of the power supply wiring, anti-resonance with a large peak in the power supply impedance may occur. However, in the semiconductor device with a capacitor 300 according to the third embodiment, since the thin film resistor 15 is connected in series with the trench capacitor, the anti-resonance peak can be suppressed to a small value.
　薄膜抵抗体１５は、たとえば、薄膜技術により形成することができる。 The thin film resistor 15 can be formed by thin film technology, for example.
　［第４実施形態］
　図４（Ａ）、（Ｂ）に、第４実施形態にかかるキャパシタ付半導体装置４００を示す。ただし、図４（Ａ）は、キャパシタ付半導体装置４００を示す正面図である。図４（Ｂ）は、キャパシタ付半導体装置４００のＳｉキャパシタ２４を示す断面図である。 [Fourth Embodiment]
4A and 4B show a semiconductor device 400 with a capacitor according to the fourth embodiment. However, FIG. 4A is a front view showing the semiconductor device 400 with a capacitor. FIG. 4B is a cross-sectional view showing the Si capacitor 24 of the semiconductor device with a capacitor 400.
　キャパシタ付半導体装置４００は、第１実施形態にかかるキャパシタ付半導体装置１００のＳｉキャパシタ４を、上側主面に薄膜高容量キャパシタ１６が形成されたＳｉキャパシタ２４に置換えた。そして、Ｓｉインターポーザ１に、Ｓｉ半導体素子３と、Ｓｉキャパシタ２４とを実装した。 In the semiconductor device with capacitor 400, the Si capacitor 4 of the semiconductor device with capacitor 100 according to the first embodiment is replaced with the Si capacitor 24 in which the thin film high-capacitance capacitor 16 is formed on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 24 were mounted on the Si interposer 1.
　図４（Ｂ）に、Ｓｉキャパシタ２４の詳細を示す。 FIG. 4B shows details of the Si capacitor 24.
　Ｓｉキャパシタ２４は、Ｓｉキャパシタ４と同様に、Ｓｉ基体５を備え、Ｓｉ基体５にトレンチキャパシタが形成されている。すなわち、Ｓｉ基体５に複数の孔６が形成され、孔６の内部に、絶縁層７、第１電極層８、誘電体層９、第２電極層１０が形成されている。 The Si capacitor 24 includes the Si base 5 similarly to the Si capacitor 4, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
　Ｓｉキャパシタ２４には、さらに、Ｓｉ基体５の上側主面に、薄膜高容量キャパシタ１６が形成されている。薄膜高容量キャパシタ１６は、導体多孔体層１６ａと、誘電体層１６ｂと、導体層１６ｃとが順に積層されたが形成された構造を備えている。薄膜高容量キャパシタ１６は、導体多孔体層１６ａ上に誘電体層１６ｂを形成しているため、非常に大きな容量を備えている。 In the Si capacitor 24, a thin film high-capacity capacitor 16 is further formed on the upper main surface of the Si base 5. The thin film high-capacitance capacitor 16 has a structure in which a conductive porous layer 16a, a dielectric layer 16b, and a conductive layer 16c are sequentially stacked. The thin film high capacity capacitor 16 has a very large capacity because the dielectric layer 16b is formed on the conductive porous layer 16a.
　薄膜高容量キャパシタ１６は、たとえば、次の方法で形成することができる。 The thin film high capacity capacitor 16 can be formed by the following method, for example.
　まず、Ｓｉ基体５の薄膜高容量キャパシタ１６を形成する領域に、たとえばＳｉＯ２からなる絶縁層１７を形成する。ＳｉＯ２からなる絶縁層１７は、ＣＶＤ（Chemical Vapor Deposition；化学気相蒸着）工法などにより形成することができる。 First, an insulating layer 17 made of, for example, SiO 2 is formed in a region of the Si base 5 where the thin film high capacity capacitor 16 is to be formed. The insulating layer 17 made of SiO 2 can be formed by a CVD (Chemical Vapor Deposition) method or the like.
　次に、絶縁層１７上に、たとえばフォトリソグラフィ技術により、たとえばＡｌからなる導体層（図示せず）を形成する。ただし、導体層の材質はＡｌには限定されず、他の金属であっても良い。 Next, a conductor layer (not shown) made of, for example, Al is formed on the insulating layer 17 by, for example, photolithography. However, the material of the conductor layer is not limited to Al and may be other metals.
　次に、たとえば陽極酸化後にエッチングする手法によって、導体層に極めて多数の微細な孔を形成し、導体多孔体層１６ａを形成する。なお、微細な孔の形成は、陽極酸化法には限定されず、印刷、インクジェットや吹付け、溶射などで金属微粒子を堆積する手法などの方法によって形成しても良い。 Next, an extremely large number of fine holes are formed in the conductor layer by, for example, etching after anodic oxidation to form the conductor porous body layer 16a. The formation of fine holes is not limited to the anodic oxidation method, and may be formed by a method such as a method of depositing metal fine particles by printing, ink jetting, spraying, spraying, or the like.
　次に、導体多孔体層１６ａ上に、原子堆積法（ＡＬＤ法；Atomic Layer Deposition）により、たとえばＡｌＯＸ（Ｘは１．２以上）からなる誘電体層１６ｂを形成する。なお、導体多孔体層１６ａと誘電体層１６ｂとの間に、予め、たとえばＴｉＯＮなどからなる拡散防止層を形成しておいても良い。拡散防止層の形成も、ＡＬＤ法によりおこなうことができる。 Next, a dielectric layer 16b made of, for example, AlOX (X is 1.2 or more) is formed on the conductive porous layer 16a by an atomic deposition method (ALD method; Atomic Layer Deposition). A diffusion preventing layer made of, for example, TiON may be formed in advance between the conductive porous body layer 16a and the dielectric layer 16b. The formation of the diffusion preventing layer can also be performed by the ALD method.
　次に、誘電体層１６ｂ上に、たとえばＡＬＤ法により、たとえばＡｌからなる導体層１６ｃを形成する。なお、導体層１６ｃの材質はＡｌには限定されず、Ｃｕ、Ｎｉなどであっても良い。また、誘電体層１６ｂと導体層１６ｃとの間に、予め、たとえばＴｉＯＮなどからなる拡散防止層を形成しておいても良い。この拡散防止層の形成も、ＡＬＤ法によりおこなうことができる。 Next, a conductor layer 16c made of, for example, Al is formed on the dielectric layer 16b by, for example, the ALD method. The material of the conductor layer 16c is not limited to Al, and may be Cu, Ni, or the like. Further, a diffusion prevention layer made of TiON or the like may be formed in advance between the dielectric layer 16b and the conductor layer 16c. This diffusion prevention layer can also be formed by the ALD method.
　最後に、導体多孔体層１６ａ、誘電体層１６ｂ、導体層１６ｃを、フォトソグラフィー技術を用いてパターニングし、薄膜高容量キャパシタ１６を完成させる。 Finally, the conductive porous body layer 16a, the dielectric layer 16b, and the conductive layer 16c are patterned by using a photolithography technique to complete the thin film high-capacitance capacitor 16.
キャパシタ付半導体装置４００では、Ｓｉキャパシタ２４のトレンチキャパシタ（第１電極層８、誘電体層９、第２電極層１０）と、薄膜高容量キャパシタ１６とを、Ｓｉ基体５にビア導体を形成することによって、並列に接続している。 In the semiconductor device with a capacitor 400, the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the thin film high-capacitance capacitor 16 are formed in the Si substrate 5 and via conductors are formed. By connecting in parallel.
　キャパシタ付半導体装置４００は、トレンチキャパシタと薄膜高容量キャパシタ１６とで、電源配線とグランド配線との間に、必要とする所望の大きな容量を形成することができる。また、キャパシタ付半導体装置４００は、種類の異なるキャパシタを並列に接続しているため、広い周波数範囲にわたって、電源インピーダンスを小さくし、電圧変動を抑制することができる。さらに、種々の周波数のノイズを除去することができる。 The capacitor-equipped semiconductor device 400 can form a desired large capacitance between the power supply wiring and the ground wiring by the trench capacitor and the thin film high-capacitance capacitor 16. In addition, since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
　なお、キャパシタ付半導体装置４００においても、第３実施形態にかかるキャパシタ付半導体装置３００と同様に、Ｓｉ基体５の表面に薄膜抵抗体１５を形成し、Ｓｉキャパシタ２４のトレンチキャパシタ（第１電極層８、誘電体層９、第２電極層１０）と薄膜抵抗体１５とを直列に接続させても良い。 In the semiconductor device with a capacitor 400, as in the semiconductor device with a capacitor 300 according to the third embodiment, the thin film resistor 15 is formed on the surface of the Si substrate 5, and the trench capacitor (first electrode layer) of the Si capacitor 24 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
　［第５実施形態］
　図５（Ａ）、（Ｂ）に、第５実施形態にかかるキャパシタ付半導体装置５００を示す。ただし、図５（Ａ）は、キャパシタ付半導体装置５００を示す正面図である。図５（Ｂ）は、キャパシタ付半導体装置５００のＳｉキャパシタ３４を示す説明図（一部分を断面で示した正面図）である。 [Fifth Embodiment]
5A and 5B show a semiconductor device 500 with a capacitor according to the fifth embodiment. However, FIG. 5A is a front view showing the semiconductor device 500 with a capacitor. FIG. 5B is an explanatory diagram (a front view partially showing a cross section) showing the Si capacitor 34 of the semiconductor device with a capacitor 500.
　キャパシタ付半導体装置５００は、第１実施形態にかかるキャパシタ付半導体装置１００のＳｉキャパシタ４を、上側主面に積層セラミックキャパシタ１８が実装されたＳｉキャパシタ３４に置換えた。そして、Ｓｉインターポーザ１に、Ｓｉ半導体素子３と、Ｓｉキャパシタ３４とを実装した。 In the semiconductor device with a capacitor 500, the Si capacitor 4 of the semiconductor device with a capacitor 100 according to the first embodiment is replaced with the Si capacitor 34 on which the multilayer ceramic capacitor 18 is mounted on the upper main surface. Then, the Si semiconductor element 3 and the Si capacitor 34 were mounted on the Si interposer 1.
　図５（Ｂ）に、Ｓｉキャパシタ３４の詳細を示す。 FIG. 5B shows details of the Si capacitor 34.
　Ｓｉキャパシタ３４は、Ｓｉキャパシタ４と同様に、Ｓｉ基体５を備え、Ｓｉ基体５にトレンチキャパシタが形成されている。すなわち、Ｓｉ基体５に複数の孔６が形成され、孔６の内部に、絶縁層７、第１電極層８、誘電体層９、第２電極層１０が形成されている。 Similar to the Si capacitor 4, the Si capacitor 34 includes a Si base 5, and a trench capacitor is formed in the Si base 5. That is, a plurality of holes 6 are formed in the Si substrate 5, and an insulating layer 7, a first electrode layer 8, a dielectric layer 9, and a second electrode layer 10 are formed inside the holes 6.
　Ｓｉキャパシタ２４には、さらに、Ｓｉ基体５の上側主面に、接合材１９を使って、積層セラミックキャパシタ１８が実装されている。 In the Si capacitor 24, a multilayer ceramic capacitor 18 is mounted on the upper main surface of the Si base 5 using a bonding material 19.
　キャパシタ付半導体装置４００では、Ｓｉキャパシタ２４のトレンチキャパシタ（第１電極層８、誘電体層９、第２電極層１０）と、積層セラミックキャパシタ１８とを、Ｓｉ基体５にビア導体を形成することによって、並列に接続している。 In the semiconductor device with a capacitor 400, the trench capacitor (first electrode layer 8, dielectric layer 9, second electrode layer 10) of the Si capacitor 24 and the multilayer ceramic capacitor 18 are formed in the Si substrate 5 and via conductors are formed. Are connected in parallel.
　キャパシタ付半導体装置４００は、積層セラミックキャパシタ１８に容量の大きなものを選択することによって、トレンチキャパシタと積層セラミックキャパシタ１８とで、電源配線とグランド配線との間に、必要とする所望の大きな容量を形成することができる。また、キャパシタ付半導体装置４００は、種類の異なるキャパシタを並列に接続しているため、広い周波数範囲にわたって、電源インピーダンスを小さくし、電圧変動を抑制することができる。さらに、種々の周波数のノイズを除去することができる。 In the semiconductor device with a capacitor 400, by selecting a multilayer ceramic capacitor 18 having a large capacity, the trench capacitor and the multilayer ceramic capacitor 18 provide a desired large capacity between the power supply wiring and the ground wiring. Can be formed. In addition, since the capacitor-equipped semiconductor device 400 has different types of capacitors connected in parallel, the power source impedance can be reduced and voltage fluctuation can be suppressed over a wide frequency range. Furthermore, noises of various frequencies can be removed.
　なお、キャパシタ付半導体装置４００は、Ｓｉインターポーザ１やＳｉ半導体素子３と熱膨張係数が大きく異なる積層セラミックキャパシタ１８を使用しているが、積層セラミックキャパシタ１８をＳｉ基体５に実装したうえで、Ｓｉインターポーザ１に実装しており、Ｓｉ基体５が一種の緩衝材として機能するため、温度変化が発生しても、反ったり、積層セラミックキャパシタ１８が剥離したりすることがない。 The semiconductor device with a capacitor 400 uses a multilayer ceramic capacitor 18 having a coefficient of thermal expansion that is significantly different from that of the Si interposer 1 and the Si semiconductor element 3. However, after mounting the multilayer ceramic capacitor 18 on the Si substrate 5, Si Since it is mounted on the interposer 1 and the Si base 5 functions as a kind of buffer material, even if a temperature change occurs, it does not warp and the multilayer ceramic capacitor 18 does not peel off.
　なお、キャパシタ付半導体装置５００においても、第３実施形態にかかるキャパシタ付半導体装置３００と同様に、Ｓｉ基体５の表面に薄膜抵抗体１５を形成し、Ｓｉキャパシタ３４のトレンチキャパシタ（第１電極層８、誘電体層９、第２電極層１０）と薄膜抵抗体１５とを直列に接続させても良い。 Also in the semiconductor device with a capacitor 500, as in the semiconductor device with a capacitor 300 according to the third embodiment, the thin film resistor 15 is formed on the surface of the Si base 5, and the trench capacitor (first electrode layer) of the Si capacitor 34 is formed. 8, the dielectric layer 9, the second electrode layer 10) and the thin film resistor 15 may be connected in series.
　［第６実施形態］
　図６（Ａ）～（Ｅ）に、第６実施形態にかかるキャパシタ付半導体装置６００を示す。ただし、図６（Ａ）～（Ｅ）は、それぞれ、キャパシタ付半導体装置６００の製造方法の一例において実施される工程を示す説明図（保持用樹脂層２０の内部を透視して示した正面図）であり、図６（Ｅ）が完成したキャパシタ付半導体装置６００を示している。 [Sixth Embodiment]
6A to 6E show a semiconductor device 600 with a capacitor according to a sixth embodiment. However, FIGS. 6A to 6E are explanatory views showing steps performed in an example of the method of manufacturing the capacitor-equipped semiconductor device 600 (front views showing through the inside of the holding resin layer 20). 6E shows the completed semiconductor device 600 with a capacitor.
　キャパシタ付半導体装置６００は、ＦＯ-ＷＬＰ（fan out - Wafer Level Package）により、Ｓｉ半導体素子１３とＳｉキャパシタ４４とを、保持用樹脂層２０に保持させている。 The capacitor-equipped semiconductor device 600 holds the Si semiconductor element 13 and the Si capacitor 44 in the holding resin layer 20 by FO-WLP (fan out-Wafer Level Package).
　以下、製造方法の一例を説明することを通して、キャパシタ付半導体装置６００の詳細を説明する。 Hereinafter, the details of the semiconductor device with a capacitor 600 will be described by explaining an example of the manufacturing method.
　まず、Ｓｉ半導体素子１３とＳｉキャパシタ４４とを用意する。Ｓｉ半導体素子１３として、第１実施形態で使用したＳｉ半導体素子３と同じものを用意した。また、Ｓｉキャパシタ４４として、第１実施形態で使用したＳｉキャパシタ４と同じものを用意した。ただし、Ｓｉ半導体素子１３とＳｉキャパシタ４４とは、それぞれ、下側主面にバンプは形成されていない。 First, the Si semiconductor element 13 and the Si capacitor 44 are prepared. As the Si semiconductor element 13, the same one as the Si semiconductor element 3 used in the first embodiment was prepared. Further, as the Si capacitor 44, the same one as the Si capacitor 4 used in the first embodiment was prepared. However, the bumps are not formed on the lower main surface of the Si semiconductor element 13 and the Si capacitor 44, respectively.
　次に、図６（Ａ）に示すように、Ｓｉ半導体素子１３とＳｉキャパシタ４４とを、それぞれ、端子が形成された面をフィルム２１に対向させて、フィルム２１に貼着する。なお、フィルム２１の表面には、予め、粘着性がもたせてある。 Next, as shown in FIG. 6A, the Si semiconductor element 13 and the Si capacitor 44 are attached to the film 21 with the surfaces on which the terminals are formed facing the film 21, respectively. In addition, the surface of the film 21 is previously given adhesiveness.
　次に、図６（Ｂ）に示すように、Ｓｉ半導体素子１３とＳｉキャパシタ４４とを覆うようにフィルム２１上に液状の樹脂を滴下させ、続いて加熱し、樹脂を硬化させて保持用樹脂層２０を形成する。ただし、保持用樹脂層２０を構成する樹脂には、Ｓｉ半導体素子１３の熱膨張係数や大きさや形状を十分に考慮したうえで、温度変化があっても、Ｓｉ半導体素子１３が破損したり、保持用樹脂層２０が反ったり、Ｓｉ半導体素子１３が保持用樹脂層２０から剥離したりしない特性（線膨張係数など）を備えたものを選定しなければならない。 Next, as shown in FIG. 6B, a liquid resin is dropped on the film 21 so as to cover the Si semiconductor element 13 and the Si capacitor 44, and then heated to cure the resin and retain the resin. Layer 20 is formed. However, in the resin constituting the holding resin layer 20, after considering the thermal expansion coefficient, size, and shape of the Si semiconductor element 13 sufficiently, even if there is a temperature change, the Si semiconductor element 13 is damaged, A material having characteristics (such as a linear expansion coefficient) that the holding resin layer 20 is not warped or the Si semiconductor element 13 is not peeled off from the holding resin layer 20 must be selected.
　次に、図６（Ｃ）に示すように、Ｓｉ半導体素子１３とＳｉキャパシタ４４とが埋設された保持用樹脂層２０から、フィルム２１を除去する。なお、図６（Ｃ）～（Ｅ）は、図６（Ａ）、（Ｂ）と保持用樹脂層２０の上下方向を反転させて示している。フィルム２１を除去した保持用樹脂層２０の表面には、Ｓｉ半導体素子１３の端子が形成された面と、Ｓｉキャパシタ４４の端子が形成された面とが、それぞれ、露出している。 Next, as shown in FIG. 6C, the film 21 is removed from the holding resin layer 20 in which the Si semiconductor element 13 and the Si capacitor 44 are embedded. 6C to 6E show the holding resin layer 20 upside down with respect to FIGS. 6A and 6B. On the surface of the holding resin layer 20 from which the film 21 has been removed, the surface on which the terminals of the Si semiconductor element 13 are formed and the surface on which the terminals of the Si capacitor 44 are formed are exposed.
　次に、図６（Ｄ）に示すように、保持用樹脂層２０のＳｉ半導体素子１３とＳｉキャパシタ４４とが露出した面に、再配線層２２を形成する。再配線層２２は、複数の絶縁層（図示せず）が積層されたものからなり、絶縁層を貫通して形成されたビア導体や、層間に形成された配線電極によって、両主面間に配線がなされている。また、再配線層２２は、Ｓｉ半導体素子１３とＳｉキャパシタ４４とを接続している。再配線層２２は、たとえば、一般的な絶縁材料、導電材料を使用して、フォトリソグラフィ技術を使用して形成することができる。 Next, as shown in FIG. 6D, the rewiring layer 22 is formed on the surface of the holding resin layer 20 where the Si semiconductor element 13 and the Si capacitor 44 are exposed. The redistribution layer 22 is formed by laminating a plurality of insulating layers (not shown), and a via conductor formed through the insulating layer or a wiring electrode formed between the layers, between the two main surfaces. Wiring is made. The rewiring layer 22 connects the Si semiconductor element 13 and the Si capacitor 44. For example, the rewiring layer 22 can be formed using a general insulating material or a conductive material by using a photolithography technique.
　最後に、図６（Ｅ）に示すように、再配線層２２上にバンプ２３を形成して、キャパシタ付半導体装置６００を完成させる。 Finally, as shown in FIG. 6E, bumps 23 are formed on the rewiring layer 22 to complete the semiconductor device 600 with a capacitor.
　ＦＯ-ＷＬＰにおいては、保持用樹脂層を構成する樹脂に、半導体素子の熱膨張係数や大きさや形状を十分に考慮したうえで、温度変化があっても、保持用樹脂層が反ったり、半導体素子が破損したり、半導体素子が保持用樹脂層から剥離したりしないものが選定される。キャパシタ付半導体装置６００では、Ｓｉ半導体素子１３とともに保持用樹脂層２０に埋設されるキャパシタに、Ｓｉ半導体素子１３と熱膨張係数の近いＳｉキャパシタ４４を使用しているため、温度変化があっても、保持用樹脂層２０が反ったり、Ｓｉ半導体素子１３が破損したり、Ｓｉ半導体素子１３やＳｉキャパシタ４４が保持用樹脂層から剥離したりすることが抑制されている。 In FO-WLP, the resin constituting the holding resin layer takes into account the thermal expansion coefficient, size, and shape of the semiconductor element, and even if the temperature changes, the holding resin layer warps. The element is selected so that the element is not damaged or the semiconductor element does not peel from the holding resin layer. In the semiconductor device with a capacitor 600, the Si capacitor 44 having a thermal expansion coefficient close to that of the Si semiconductor element 13 is used as the capacitor embedded in the holding resin layer 20 together with the Si semiconductor element 13. The holding resin layer 20 is prevented from warping, the Si semiconductor element 13 is damaged, and the Si semiconductor element 13 and the Si capacitor 44 are prevented from peeling from the holding resin layer.
　以上、第１実施形態～第６実施形態にかかるキャパシタ付半導体装置１００～６００について説明した。しかしながら、本発明が上述した内容に限定されることはなく、発明の趣旨に沿って、種々の変更をなすことができる。 The capacitor semiconductor devices 100 to 600 according to the first to sixth embodiments have been described above. However, the present invention is not limited to the contents described above, and various modifications can be made in accordance with the spirit of the invention.
　たとえば、キャパシタ付半導体装置１００～６００では、Ｓｉキャパシタ４、１４、２４、３４、４４にトレンチキャパシタを使用しているが、Ｓｉキャパシタは、基体にＳｉを使用していれば良く、トレンチキャパシタには限定されず、他の種類のものであっても良い。 For example, in the semiconductor devices with capacitors 100 to 600, trench capacitors are used for the Si capacitors 4, 14, 24, 34, and 44. However, the Si capacitor only needs to use Si for the substrate, Is not limited and may be of other types.
　また、ＦＯ-ＷＬＰを使用した第６実施形態にかかるキャパシタ付半導体装置６００においては、Ｓｉキャパタとして、トレンチキャパシタのみを備えたＳｉキャパシタ４４を保持用樹脂層２０に埋設しているが、これに代えて、他の実施形態で使用した、トレンチキャパシタと薄膜抵抗体１５とを備えたＳｉキャパシタ１４、トレンチキャパシタと薄膜高容量キャパシタ１６とを備えたＳｉキャパシタ２４、トレンチキャパシタと積層セラミックキャパシタ１８とを備えたＳｉキャパシタ３４などを保持用樹脂層２０に埋設しても良い。 In the semiconductor device with a capacitor 600 according to the sixth embodiment using FO-WLP, the Si capacitor 44 having only the trench capacitor is embedded in the holding resin layer 20 as the Si capacitor. Instead, the Si capacitor 14 including the trench capacitor and the thin film resistor 15, the Si capacitor 24 including the trench capacitor and the thin film high-capacitance capacitor 16, the trench capacitor and the multilayer ceramic capacitor 18 used in the other embodiments are used. A Si capacitor 34 or the like provided with may be embedded in the holding resin layer 20.
　また、Ｓｉインターポーザ１に実装されるＳｉキャパシタの個数や、保持用樹脂層２０に埋設されるＳｉキャパシタの個数は任意であり、図面に描画された個数には限定されない。 Further, the number of Si capacitors mounted on the Si interposer 1 and the number of Si capacitors embedded in the holding resin layer 20 are arbitrary, and are not limited to the number drawn in the drawing.
１・・・Ｓｉインターポーザ
２、１１、２３・・・バンプ
３、１３・・・Ｓｉ半導体素子（ＬＳＩ素子など）
４、１４、２４、３４、４４・・・Ｓｉキャパシタ
５・・・Ｓｉ基体
６・・・孔
７、１７・・・絶縁層
８・・・第１電極層
９・・・誘電体層
１０・・・第２電極層
１２・・・封止用樹脂層
１５・・・薄膜抵抗体
１６・・・薄膜高容量キャパシタ
１６ａ・・・導体多孔体層
１６ｂ・・・誘電体層
１６ｃ・・・導体層
１８・・・積層セラミックキャパシタ
２０・・・保持用樹脂層
２１・・・フィルム
２２・・・再配線層 DESCRIPTION OF SYMBOLS 1 ... Si interposer 2, 11, 23 ... Bump 3, 13 ... Si semiconductor element (LSI element etc.)
4, 14, 24, 34, 44 ... Si capacitor 5 ... Si substrate 6 ... hole 7, 17 ... insulating layer 8 ... first electrode layer 9 ... dielectric layer 10 .... Second electrode layer 12 ... Sealing resin layer 15 ... Thin film resistor 16 ... Thin film high capacity capacitor 16a ... Conductor porous body layer 16b ... Dielectric layer 16c ... Conductor Layer 18 ... multilayer ceramic capacitor 20 ... holding resin layer 21 ... film 22 ... rewiring layer

Claims (7)

  1. 　Ｓｉにより形成された少なくとも１つのＳｉ半導体素子と、
    　Ｓｉにより形成された少なくとも１つのＳｉキャパシタと、を備え、
    　前記Ｓｉ半導体素子と前記Ｓｉキャパシタとが、それぞれ、Ｓｉにより形成された１つのＳｉインターポーザに実装されることにより、または、１つの保持用樹脂層に一方の主面を露出させて埋設されることにより、平面方向に並べて配置された、キャパシタ付半導体装置。     At least one Si semiconductor element formed of Si;
    And at least one Si capacitor formed of Si,
    The Si semiconductor element and the Si capacitor are each mounted on one Si interposer formed of Si, or embedded in one holding resin layer with one main surface exposed. Thus, the semiconductor device with a capacitor arranged side by side in the plane direction.
  2. 　前記Ｓｉ半導体素子と前記Ｓｉキャパシタとが、それぞれ、前記Ｓｉインターポーザに実装され、
    　実装された前記Ｓｉ半導体素子と前記Ｓｉキャパシタとを覆うように、前記Ｓｉインターポーザの主面上に封止用樹脂層が形成された、請求項１に記載されたキャパシタ付半導体装置。     The Si semiconductor element and the Si capacitor are each mounted on the Si interposer,
    The semiconductor device with a capacitor according to claim 1, wherein a sealing resin layer is formed on a main surface of the Si interposer so as to cover the mounted Si semiconductor element and the Si capacitor.
  3. 　前記Ｓｉ半導体素子と前記Ｓｉキャパシタとが、それぞれ、前記保持用樹脂層に一方の主面を露出させて埋設され、
    　前記Ｓｉ半導体素子と前記Ｓｉキャパシタとが露出された前記保持用樹脂層の主面上に、再配線層が形成された、請求項１に記載されたキャパシタ付半導体装置。     The Si semiconductor element and the Si capacitor are each embedded in the holding resin layer with one main surface exposed,
    The semiconductor device with a capacitor according to claim 1, wherein a rewiring layer is formed on a main surface of the holding resin layer from which the Si semiconductor element and the Si capacitor are exposed.
  4. 　前記Ｓｉキャパシタが、Ｓｉにより形成されたＳｉ基体に孔が形成され、前記孔に形成されたトレンチキャパシタである、請求項１ないし３のいずれか１項に記載されたキャパシタ付半導体装置。 The semiconductor device with a capacitor according to any one of claims 1 to 3, wherein the Si capacitor is a trench capacitor formed in the hole by forming a hole in a Si base made of Si.
  5. 　前記Ｓｉキャパシタ上に、導体多孔体層と、誘電体層と、導体層とが順に積層された薄膜高容量キャパシタが形成され、
    　前記Ｓｉキャパシタと、前記薄膜高容量キャパシタとが、並列に接続された、請求項１ないし４のいずれか１項に記載されたキャパシタ付半導体装置。     On the Si capacitor, a thin film high-capacity capacitor in which a conductive porous layer, a dielectric layer, and a conductive layer are sequentially laminated is formed.
    5. The semiconductor device with a capacitor according to claim 1, wherein the Si capacitor and the thin film high-capacitance capacitor are connected in parallel. 6.
  6. 　前記Ｓｉキャパシタに、積層セラミックキャパシタが実装され、
    　前記Ｓｉキャパシタと、前記積層セラミックキャパシタとが、並列に接続された、請求項１ないし５のいずれか１項に記載されたキャパシタ付半導体装置。     A multilayer ceramic capacitor is mounted on the Si capacitor,
    The semiconductor device with a capacitor according to claim 1, wherein the Si capacitor and the multilayer ceramic capacitor are connected in parallel.
  7. 　前記Ｓｉキャパシタの表面に薄膜抵抗体が形成され、
    　前記Ｓｉキャパシタと、前記薄膜抵抗体とが、直列に接続された、請求項４ないし６のいずれか１項に記載されたキャパシタ付半導体装置。     A thin film resistor is formed on the surface of the Si capacitor,
    The semiconductor device with a capacitor according to claim 4, wherein the Si capacitor and the thin film resistor are connected in series.
PCT/JP2017/024085 2016-08-19 2017-06-30 Semiconductor device with capacitor WO2018034067A1 (en)

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JP2020009602A (en) * 2018-07-06 2020-01-16 東芝ライテック株式会社 Power supply circuit and luminaire
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