JPWO2009028596A1 - Passive element embedded substrate, manufacturing method, and semiconductor device - Google Patents

Passive element embedded substrate, manufacturing method, and semiconductor device Download PDF

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JPWO2009028596A1
JPWO2009028596A1 JP2009530174A JP2009530174A JPWO2009028596A1 JP WO2009028596 A1 JPWO2009028596 A1 JP WO2009028596A1 JP 2009530174 A JP2009530174 A JP 2009530174A JP 2009530174 A JP2009530174 A JP 2009530174A JP WO2009028596 A1 JPWO2009028596 A1 JP WO2009028596A1
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passive element
substrate
resin
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built
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渋谷　明信
明信 渋谷
明 大内
明 大内
康博 石井
康博 石井
森　透
透 森
浩一 竹村
浩一 竹村
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Abstract

破壊が起こりにくく、低コストで容易に製造可能な受動素子内蔵基板およびその製造方法を提供する。接続パッド２が形成された実装基板１と、基板７に薄膜受動素子４が形成されるとともに、接続パッド２に対向する薄膜受動素子４側の面に接続パッド２に対応した端子電極３が形成され、かつ、端子電極３が接続パッド２に接合され、基板７の厚さが１５μｍ以下である受動素子チップと、受動素子チップと実装基板１の間に充填されるとともに、受動素子チップの外周部に配された部分の上面が基板７の上面と一致するように形成された樹脂６と、基板７の上面に半導体素子又は半導体パッケージの端子に対応して形成されたＬＳＩ接続パッド９と、受動素子チップ内にて対応するＬＳＩ接続パッド９と端子電極３とを電気的に接続するように形成された貫通ビア８と、を備える。Provided are a passive element-embedded substrate that is unlikely to break down and can be easily manufactured at low cost, and a method for manufacturing the same. The thin film passive element 4 is formed on the mounting substrate 1 on which the connection pad 2 is formed, and the substrate 7, and the terminal electrode 3 corresponding to the connection pad 2 is formed on the surface on the thin film passive element 4 side facing the connection pad 2. In addition, the terminal electrode 3 is bonded to the connection pad 2 and the substrate 7 is filled between the passive element chip having a thickness of 15 μm or less and the passive element chip and the mounting substrate 1, and the outer periphery of the passive element chip A resin 6 formed so that the upper surface of the portion arranged in the portion coincides with the upper surface of the substrate 7, an LSI connection pad 9 formed on the upper surface of the substrate 7 corresponding to the terminals of the semiconductor element or the semiconductor package, A through via 8 formed so as to electrically connect the corresponding LSI connection pad 9 and the terminal electrode 3 in the passive element chip is provided.

Description

（関連出願についての記載）
本願は、先の日本特許出願２００７−２２４２６１号（２００７年８月３０日出願）の優先権を主張するものであり、前記先の出願の全記載内容は、本書に引用をもって繰込み記載されているものとみなされる。
本発明は、インターポーザ型の受動素子内蔵基板、製造方法、及び半導体装置に関する。(Description of related applications)
This application claims the priority of the previous Japanese Patent Application No. 2007-224261 (filed on August 30, 2007), and the entire description of the previous application is incorporated herein by reference. Is considered to be.
The present invention relates to an interposer-type passive element built-in substrate, a manufacturing method, and a semiconductor device.

近年、ＬＳＩ（Large Scale Integration）のスイッチングノイズ対策として、半導体チップ直下にデカップリングキャパシタとしてのインターポーザ型キャパシタを接続した構造の半導体パッケージあるいは、半導体チップの実装構造が研究開発されている。ＬＳＩにクロック動作による急激な負荷ｉが加わると電源とＬＳＩ間の配線に存在する抵抗ＲとインダクタンスＬによって、数式１で示される電圧降下ΔＶが生じる。   In recent years, as a countermeasure for switching noise in LSI (Large Scale Integration), a semiconductor package having a structure in which an interposer type capacitor as a decoupling capacitor is connected directly under a semiconductor chip or a mounting structure of a semiconductor chip has been researched and developed. When an abrupt load i due to clock operation is applied to the LSI, a voltage drop ΔV represented by Equation 1 is generated by the resistance R and inductance L existing in the wiring between the power supply and the LSI.

Figure 2009028596
Figure 2009028596

ΔＶを小さくするためにはＬＳＩに接続される電源ライン−接地ライン間に並列にデカップリングキャパシタが接続されるが、キャパシタの等価直列抵抗（ＥＳＲ：Equivalent Series Resistance）、等価直列インダクタンス（ＥＳＬ：Equivalent Series Inductance）、及びキャパシタからＬＳＩまでの配線抵抗Ｒl，配線インダクタンスＬlの影響により数式１の△Ｖが生じていた。   In order to reduce ΔV, a decoupling capacitor is connected in parallel between the power supply line and the ground line connected to the LSI, but the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the capacitor Series Δ Inductance, and ΔV in Formula 1 occurred due to the influence of the wiring resistance Rl and the wiring inductance Ll from the capacitor to the LSI.

近年、クロック周波数がＧＨｚのオーダーに達し、デカップリングキャパシタとＬＳＩ間の配線による配線インダクタンスＬlが無視できなくなってきた。そのため、Ｌlを限りなく小さくできるインターポーザ型キャパシタが開発されている。インターポーザ型キャパシタの開発例としては、特許文献１〜４が挙げられる。例として、特許文献３のインターポーザ型キャパシタの構造を図１４に示す。   In recent years, the clock frequency has reached the order of GHz, and the wiring inductance Ll due to the wiring between the decoupling capacitor and the LSI cannot be ignored. Therefore, an interposer type capacitor that can make Ll as small as possible has been developed. Examples of development of an interposer type capacitor include Patent Documents 1 to 4. As an example, FIG. 14 shows a structure of an interposer type capacitor disclosed in Patent Document 3.

従来のチップキャリア型キャパシタは、スルーホール１１２ａ、１１２ｂが形成された基板１１０上にキャパシタが形成された構造となっている。したがって、上記構造を実現するためには、スルーホール１１２ａ、１１２ｂが形成された基板１１０にキャパシタを形成するか、基板１１０にキャパシタを形成した後にスルーホール１１２ａ、１１２ｂを形成していた。   A conventional chip carrier type capacitor has a structure in which a capacitor is formed on a substrate 110 on which through holes 112a and 112b are formed. Therefore, in order to realize the above structure, capacitors are formed on the substrate 110 in which the through holes 112a and 112b are formed, or the through holes 112a and 112b are formed after the capacitors are formed on the substrate 110.

特開２００５−３３１９５号公報JP 2005-33195 A 特開２００１−３３８８３６号公報JP 2001-338836 A 特開２００２−８９４２号公報JP 2002-8942 A 特許第３４６５４６４号公報Japanese Patent No. 3465464 特開２００４−３２００４３号公報JP 2004-320043 A

特許文献１〜５の開示事項は、本書に引用をもって繰り込み記載されているものとする。以下の分析は、本発明によって与えられたものである。
しかし、スルーホール１１２ａ、１１２ｂが形成された基板１１０にキャパシタを形成する場合、キャパシタ形成時の基板加熱時に基板材料とビア導体の熱膨張係数差によりスルーホール１１２ａ、１１２ｂが伸縮し、キャパシタ不良を招くおそれがあった。The disclosure items of Patent Documents 1 to 5 are incorporated herein by reference. The following analysis is given by the present invention.
However, when a capacitor is formed on the substrate 110 in which the through holes 112a and 112b are formed, the through holes 112a and 112b expand and contract due to a difference in thermal expansion coefficient between the substrate material and the via conductor when the substrate is heated at the time of forming the capacitor. There was a risk of inviting.

また、キャパシタ形成後にスルーホール１１２ａ、１１２ｂを形成する場合には、キャパシタが存在することでスルーホール形成プロセスが制限されてしまうおそれがあった。例えば、スルーホール形成時に基板１１０にクラックが発生し、キャパシタ部にクラックが進展し不良になる問題や、キャパシタがエッチングされないプロセスに制限される問題があった。   In addition, when the through holes 112a and 112b are formed after the capacitor is formed, there is a possibility that the through hole forming process is limited due to the presence of the capacitor. For example, there is a problem that a crack is generated in the substrate 110 when the through hole is formed, the crack progresses in the capacitor portion and becomes defective, and the process is limited to a process in which the capacitor is not etched.

さらに、いずれの場合においても、スルーホール導体の充填は、基板厚みが小さい方が容易であるが、基板厚みを小さくすると、ハンドリングが困難になるおそれがあり、実装プロセスで基板を破壊してしまう問題があった。   Furthermore, in any case, filling the through-hole conductor is easier when the substrate thickness is smaller, but if the substrate thickness is reduced, handling may be difficult, and the substrate may be destroyed in the mounting process. There was a problem.

一方、キャパシタのような受動素子を実装基板内部に形成することは、受動素子部品の実装コストを低下することや受動素子部品を実装基板に内蔵することによるパッケージやモジュールの小型化が可能となることから開発が盛んに行われている。しかし、インターポーザ型キャパシタについては、前述したようにインターポーザ型キャパシタそのものの製造が困難である。また、特許文献５には、実装基板内部に実装可能な上下面に接続パッドを有する積層セラミックコンデンサが開示されているが、積層セラミックコンデンサでは形成できるビアサイズを小さくできないため、狭ピッチの接続パッドを形成できないおそれがある。さらに、積層セラミックコンデンサでは数百μｍオーダー以上の厚みを有するため、受動素子内蔵基板の薄化に限界がある。   On the other hand, forming a passive element such as a capacitor inside the mounting substrate reduces the mounting cost of the passive element component, and enables the miniaturization of the package or module by incorporating the passive element component in the mounting substrate. Therefore, development is actively done. However, as for the interposer type capacitor, as described above, it is difficult to manufacture the interposer type capacitor itself. Further, Patent Document 5 discloses a multilayer ceramic capacitor having connection pads on the upper and lower surfaces that can be mounted inside the mounting substrate. However, since the via size that can be formed with the multilayer ceramic capacitor cannot be reduced, connection pads with a narrow pitch are provided. There is a possibility that it cannot be formed. Furthermore, since the multilayer ceramic capacitor has a thickness of the order of several hundred μm or more, there is a limit to the thinning of the passive element built-in substrate.

以上説明したように、従来のインターポーザ型キャパシタでは製造が困難な問題と製造しやすくするために基板厚みを小さくすると実装プロセスのハンドリング時に破壊しやすくなってしまう問題があった。一方、インターポーザ型キャパシタを内蔵した受動素子内蔵基板は、製造が困難であり、ビア狭ピッチ化と基板薄化が困難であった。   As described above, the conventional interposer type capacitor has a problem that it is difficult to manufacture, and there is a problem that if the substrate thickness is reduced in order to make it easy to manufacture, it is easily broken during the handling of the mounting process. On the other hand, a substrate with a built-in passive element incorporating an interposer type capacitor is difficult to manufacture, and it is difficult to narrow the via pitch and thin the substrate.

本発明の主な課題は、破壊が起こりにくく、低コストで容易に製造可能な受動素子内蔵基板およびその製造方法を提供することである。   A main object of the present invention is to provide a passive element-embedded substrate that is unlikely to break down and can be easily manufactured at low cost, and a method for manufacturing the same.

本発明の第１の視点においては、受動素子内蔵基板において、複数の第１接続パッドが形成された実装基板と、基板に受動素子が形成されるとともに、前記第１接続パッドに対向する前記受動素子側の面に前記第１接続パッドに対応した端子電極が形成され、かつ、前記端子電極が前記第１接続パッドに接合された受動素子チップと、前記受動素子チップと前記実装基板の間に充填されるとともに、前記受動素子チップの外周部に配された部分の上面が前記基板の上面と一致するように形成された樹脂と、前記基板の上面に半導体素子又は半導体パッケージの端子に対応して形成された第２接続パッドと、前記受動素子チップ内にて対応する前記第２接続パッドと前記端子電極とを電気的に接続するように形成された貫通ビアと、を備えることを特徴とする。   According to a first aspect of the present invention, in a passive element-embedded substrate, a mounting substrate on which a plurality of first connection pads are formed, a passive element is formed on the substrate, and the passive element that faces the first connection pad is formed. A terminal electrode corresponding to the first connection pad is formed on a surface on the element side, and the passive element chip is bonded to the first connection pad. Between the passive element chip and the mounting substrate Resin formed so that the upper surface of the portion disposed on the outer peripheral portion of the passive element chip coincides with the upper surface of the substrate, and the upper surface of the substrate corresponds to the terminals of the semiconductor element or the semiconductor package. And a through via formed to electrically connect the corresponding second connection pad and the terminal electrode in the passive element chip. The features.

本発明の第２の視点においては、半導体装置において、前記受動素子内蔵基板と、前記受動素子内蔵基板上に搭載された半導体素子又は半導体パッケージと、を備えることを特徴とする。   According to a second aspect of the present invention, a semiconductor device includes the passive element built-in substrate and a semiconductor element or a semiconductor package mounted on the passive element built-in substrate.

本発明の第３の視点においては、受動素子内蔵基板の製造方法において、基板上に受動素子を形成し前記受動素子上に端子電極を形成する工程と、前記基板を切断し受動素子チップを形成する工程と、前記受動素子チップの前記端子電極と実装基板上の接続パッドとを接合する工程と、前記実装基板上に前記受動素子チップの前記基板と前記受動素子の界面よりも高くなるように樹脂で封止する工程と、前記基板の厚さが１５μｍ以下になるまで前記基板及び前記樹脂を研削する工程と、前記受動素子チップ内に前記端子電極に通ずる下穴を形成する工程と、を含むことを特徴とする。   In a third aspect of the present invention, in a method for manufacturing a substrate with a built-in passive element, a step of forming a passive element on the substrate and forming a terminal electrode on the passive element, and cutting the substrate to form a passive element chip A step of bonding the terminal electrode of the passive element chip to a connection pad on the mounting substrate, and a height of the interface between the substrate of the passive element chip and the passive element on the mounting substrate. A step of sealing with resin, a step of grinding the substrate and the resin until the thickness of the substrate is 15 μm or less, and a step of forming a pilot hole communicating with the terminal electrode in the passive element chip. It is characterized by including.

本発明によれば、以下の効果を奏する。   The present invention has the following effects.

本発明に係る受動素子内蔵基板の第１の効果は、受動素子チップの厚さを小さくできるため、受動素子チップ内に形成された貫通ビアを介して受動素子と半導体素子又は半導体パッケージ間の距離が小さい状態で接続可能になり、低インダクタンスで受動素子と半導体素子又は半導体パッケージが接続される点にある。特に、高速で動作するＬＳＩのデカップリングに対して効果がある。   The first effect of the substrate with built-in passive element according to the present invention is that the thickness of the passive element chip can be reduced, so that the distance between the passive element and the semiconductor element or semiconductor package through the through via formed in the passive element chip. Can be connected in a small state, and a passive element and a semiconductor element or a semiconductor package are connected with low inductance. In particular, this is effective for decoupling LSIs that operate at high speed.

本発明に係る受動素子内蔵基板の第２の効果は、受動素子内蔵基板内の受動素子チップに形成される貫通ビアの長さが１５μｍ以下とすることができるため、容易に製造可能な構造を有しており、低コスト化が可能な点にある。   The second effect of the passive element built-in substrate according to the present invention is that a through via formed in the passive element chip in the passive element built-in substrate can have a length of 15 μm or less. The cost is reduced.

本発明に係る受動素子内蔵基板の第３の効果は、受動素子形成基板にＬＳＩまたは半導体パッケージと熱膨張係数が近い材料を使用することにより、半導体素子又は半導体パッケージ実装後の信頼性が高いパッケージあるいはインターポーザが得られる点にある。   A third effect of the substrate with built-in passive element according to the present invention is that the passive element forming substrate uses a material having a thermal expansion coefficient close to that of the LSI or the semiconductor package, so that the package having high reliability after mounting the semiconductor element or the semiconductor package. Alternatively, an interposer can be obtained.

本発明に係る受動素子内蔵基板の第４の効果は、受動素子チップの厚みが小さいことから非内蔵の基板とほとんど変わらない厚みとなる点である。   The fourth effect of the substrate with built-in passive element according to the present invention is that the thickness of the passive element chip is small, so that the thickness is almost the same as that of the non-built-in substrate.

本発明の実施例１に係る受動素子内蔵基板の構成を模式的に示した断面図である。It is sectional drawing which showed typically the structure of the board | substrate with a built-in passive element which concerns on Example 1 of this invention. 本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの第１の構成を模式的に示した部分断面図である。It is the fragmentary sectional view which showed typically the 1st structure of the thin film passive element chip | tip in the board | substrate with a built-in passive element which concerns on Example 1 of this invention. 図３は、本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの第２の構成を模式的に示した部分断面図である。FIG. 3 is a partial cross-sectional view schematically showing a second configuration of the thin film passive element chip in the passive element built-in substrate according to the first embodiment of the present invention. 本発明の実施例１に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the board | substrate with a built-in passive element which concerns on Example 1 of this invention. 本発明の実施例１に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した第１の断面図である。It is the 1st sectional view showing typically the modification of the composition after the resin formation process in the manufacturing method of the substrate with a built-in passive element concerning Example 1 of the present invention. 本発明の実施例１に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した第２の断面図である。It is the 2nd sectional view showing typically the modification of the composition after the resin formation process in the manufacturing method of the substrate with a built-in passive element concerning Example 1 of the present invention. 本発明の実施例１に係る受動素子内蔵基板の製造方法における中間品の一例の構成を模式的に示した部分断面図である。It is the fragmentary sectional view which showed typically the structure of an example of the intermediate product in the manufacturing method of the board | substrate with a built-in passive element which concerns on Example 1 of this invention. 本発明の実施例２に係る受動素子内蔵基板の構成を模式的に示した断面図である。It is sectional drawing which showed typically the structure of the board | substrate with a built-in passive element which concerns on Example 2 of this invention. 本発明の実施例２に係る受動素子内蔵基板におけるスティフナーの構成を模式的に示した平面図である。It is the top view which showed typically the structure of the stiffener in the passive element built-in board | substrate which concerns on Example 2 of this invention. 本発明の実施例２に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the board | substrate with a built-in passive element which concerns on Example 2 of this invention. 本発明の実施例３に係る受動素子内蔵基板の構成を模式的に示した断面図である。It is sectional drawing which showed typically the structure of the board | substrate with a built-in passive element which concerns on Example 3 of this invention. 本発明の実施例３に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the board | substrate with a built-in passive element which concerns on Example 3 of this invention. 本発明の実施例３に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した断面図である。It is sectional drawing which showed typically the modification of the structure after the resin formation process in the manufacturing method of the passive element built-in board | substrate which concerns on Example 3 of this invention. 従来例に係るインターポーザ型キャパシタの構成を模式的に示した断面図である。It is sectional drawing which showed typically the structure of the interposer type capacitor which concerns on a prior art example.

符号の説明Explanation of symbols

１ 実装基板
２ 接続パッド
３ 端子電極
４ 薄膜受動素子
５ 接合材
６ 樹脂
７ 基板
８ 貫通ビア
９ ＬＳＩ接続パッド
９ａ ＬＳＩ接続パッド（電源用）
９ｂ ＬＳＩ接続パッド（接地用）
９ｃ ＬＳＩ接続パッド（信号用）
１０ 下部電極
１１ 薄膜誘電体
１２ 上部電極
１３ 絶縁膜
１４ カバー膜
１５ 上部電極接続ビア
１６ 下部電極接続ビア
１７ スティフナー
１８ キャビティー
１９ アンダーフィル樹脂
２０ モールド樹脂
２１ ガラス基板
１１０ 基板
１１１ 支持体
１１２ａ 第１のスルーホール
１１２ｂ 第２のスルーホール
１１４ 下部電極
１１６ 高誘電体膜
１１８ 上部電極
１２０、１２２ 保護膜
１２１ａ、１２１ｂ 電極パッド
１２４ａ、１２４ｂ 電極パッド
１２８ａ、１２８ｂ バンプ電極DESCRIPTION OF SYMBOLS 1 Mounting board 2 Connection pad 3 Terminal electrode 4 Thin film passive element 5 Bonding material 6 Resin 7 Substrate 8 Through-via 9 LSI connection pad 9a LSI connection pad (for power supply)
9b LSI connection pad (for grounding)
9c LSI connection pad (for signal)
DESCRIPTION OF SYMBOLS 10 Lower electrode 11 Thin film dielectric 12 Upper electrode 13 Insulating film 14 Cover film 15 Upper electrode connection via 16 Lower electrode connection via 17 Stiffener 18 Cavity 19 Underfill resin 20 Mold resin 21 Glass substrate 110 Substrate 111 Support 112a 1st Through hole 112b Second through hole 114 Lower electrode 116 High dielectric film 118 Upper electrode 120, 122 Protective film 121a, 121b Electrode pad 124a, 124b Electrode pad 128a, 128b Bump electrode

本発明の実施形態に係る受動素子内蔵基板では、複数の接続パッド（図１の２）が形成された実装基板（図１の１）と、基板（図１の７）に受動素子（図１の４）が形成されるとともに、接続パッド（図１の２）に対向する受動素子（図１の４）側の面に接続パッド（図１の２）に対応した端子電極（図１の３）が形成され、かつ、端子電極（図１の３）が接続パッド（図１の２）に接合された受動素子チップと、受動素子チップと実装基板（図１の１）の間に充填されるとともに、受動素子チップの外周部に配された部分の上面が基板（図１の７）の上面と一致するように形成された樹脂（図１の６）と、基板（図１の７）の上面に半導体素子又は半導体パッケージの端子に対応して形成された接続パッド（図１の９）と、受動素子チップ内にて対応する接続パッド（図１の９）と端子電極（図１の３）とを電気的に接続するように形成された貫通ビア（図１の８）と、を備える。   In the substrate with a built-in passive element according to the embodiment of the present invention, a mounting board (1 in FIG. 1) on which a plurality of connection pads (2 in FIG. 1) are formed, and a passive element (7 in FIG. 1) on the board (7 in FIG. 1). 4) and a terminal electrode (3 in FIG. 1) corresponding to the connection pad (2 in FIG. 1) on the surface of the passive element (4 in FIG. 1) facing the connection pad (2 in FIG. 1). ) And the terminal element (3 in FIG. 1) is bonded to the connection pad (2 in FIG. 1), and the space is filled between the passive element chip and the mounting substrate (1 in FIG. 1). In addition, the resin (6 in FIG. 1) formed so that the upper surface of the portion arranged on the outer peripheral portion of the passive element chip coincides with the upper surface of the substrate (7 in FIG. 1), and the substrate (7 in FIG. 1). And a passive element chip (9 in FIG. 1) formed on the upper surface of the semiconductor chip corresponding to the terminals of the semiconductor element or semiconductor package. Provided with corresponding connection pads (3 in FIG. 1) (Fig. 1 9) and the terminal electrode electrically connected to so-formed through vias (8 in FIG. 1), the at.

本発明の実施形態に係る受動素子内蔵基板の製造方法では、基板（図４の７）上に受動素子（図４の４）を形成し受動素子（図４の４）上に端子電極（図４の３）を形成する工程と、基板（図４の７）を切断し受動素子チップを形成する工程と、受動素子チップの端子電極（図４の３）と実装基板（図４の１）上の接続パッド（図４の２）とを接合する工程と、実装基板（図４の１）上に受動素子チップの基板（図４の７）と受動素子（図４の４）の界面よりも高くなるように樹脂（図４の６）で封止する工程と、基板（図４の７）の厚さが１５μｍ以下になるまで基板（図４の７）及び樹脂（図４の６）を研削する工程と、受動素子チップ内に端子電極（図４の３）に通ずる下穴（図４の貫通ビア８用の下穴）を形成する工程と、を含む。   In the method for manufacturing a substrate with built-in passive element according to the embodiment of the present invention, a passive element (4 in FIG. 4) is formed on the substrate (7 in FIG. 4), and a terminal electrode (FIG. 4) is formed on the passive element (4 in FIG. 4). 4-3), a step of cutting the substrate (7 in FIG. 4) to form a passive element chip, a terminal electrode of the passive element chip (3 in FIG. 4), and a mounting substrate (1 in FIG. 4). The step of bonding the upper connection pad (2 in FIG. 4) and the interface between the passive element chip substrate (7 in FIG. 4) and the passive element (4 in FIG. 4) on the mounting substrate (1 in FIG. 4) And sealing with resin (6 in FIG. 4) so that the thickness of the substrate (7 in FIG. 4) is 15 μm or less and the resin (6 in FIG. 4) and the resin (6 in FIG. 4). And a step of forming a pilot hole (a pilot hole for the through via 8 in FIG. 4) communicating with the terminal electrode (3 in FIG. 4) in the passive element chip.

本発明の実施例１に係る受動素子内蔵基板について図面を用いて説明する。図１は、本発明の実施例１に係る受動素子内蔵基板の構成を模式的に示した断面図である。   A passive element built-in substrate according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a passive element built-in substrate according to Embodiment 1 of the present invention.

図１を参照すると、実施例１に係る受動素子内蔵基板は、薄膜受動素子４を内蔵した基板である。受動素子内蔵基板は、実装基板１と、接続パッド２と、端子電極３と、薄膜受動素子４と、接合材５と、樹脂６と、基板７と、貫通ビア８と、ＬＳＩ接続パッド９と、を有する。   Referring to FIG. 1, the passive element built-in substrate according to the first embodiment is a substrate in which the thin film passive element 4 is built. The substrate with a built-in passive element includes a mounting substrate 1, a connection pad 2, a terminal electrode 3, a thin film passive element 4, a bonding material 5, a resin 6, a substrate 7, a through via 8, and an LSI connection pad 9. Have.

実装基板１は、半導体チップを搭載するための基板である。実装基板１の薄膜受動素子４側の面には、複数の接続パッド２が配設されている。実装基板１の表面や内部には、配線（図示せず）が形成されている。実装基板１には、例えば、ガラスとエポキシ樹脂を基材にしたプリント基板を用いることができ、セラミック基板やその他の絶縁材料を基材にした基板を用いることができる。実装基板１は、インターポーザ基板として使用することができる。   The mounting substrate 1 is a substrate for mounting a semiconductor chip. A plurality of connection pads 2 are provided on the surface of the mounting substrate 1 on the thin film passive element 4 side. Wiring (not shown) is formed on the surface and inside of the mounting substrate 1. For the mounting substrate 1, for example, a printed board based on glass and epoxy resin can be used, and a board based on a ceramic substrate or other insulating material can be used. The mounting substrate 1 can be used as an interposer substrate.

接続パッド２は、実装基板１の薄膜受動素子４側の面に配設され、対応する端子電極３と接合材５を介して接合され、当該端子電極３と電気的に接続されている。   The connection pad 2 is disposed on the surface of the mounting substrate 1 on the thin film passive element 4 side, is bonded to the corresponding terminal electrode 3 via the bonding material 5, and is electrically connected to the terminal electrode 3.

端子電極３は、薄膜受動素子４の実装基板１側の面に配設されている。端子電極３は、対応する接続パッド２と接合材５を介して接合され、当該接続パッド２と電気的に接続されている。端子電極３は、対応するＬＳＩ接続パッド９と貫通ビア８を介して電気的に接続されている。   The terminal electrode 3 is disposed on the surface of the thin film passive element 4 on the mounting substrate 1 side. The terminal electrode 3 is bonded to the corresponding connection pad 2 via the bonding material 5 and is electrically connected to the connection pad 2. The terminal electrode 3 is electrically connected to the corresponding LSI connection pad 9 through the through via 8.

薄膜受動素子４は、受動素子を有する部分であり、基板７と組み合わされて薄膜受動素子チップを構成する。薄膜受動素子４は、基板７の実装基板１側の面に配されている。薄膜受動素子４は、実装基板１側の面に接続パッド２に対応した端子電極３が配設されている。薄膜受動素子４内の受動素子は、キャパシタ、抵抗、インダクタ等とすることができ、それらを組み合わせた素子でもよい。薄膜受動素子４には、互いに対応する端子電極３及びＬＳＩ接続パッド９の間の所定の位置に下穴が形成されており、当該下穴に貫通ビア８が埋め込まれている。薄膜受動素子４と基板７から構成される薄膜受動素子チップの厚さは、１５μｍ以下である。   The thin film passive element 4 is a part having a passive element, and is combined with the substrate 7 to constitute a thin film passive element chip. The thin film passive element 4 is disposed on the surface of the substrate 7 on the mounting substrate 1 side. The thin-film passive element 4 is provided with a terminal electrode 3 corresponding to the connection pad 2 on the surface on the mounting substrate 1 side. The passive element in the thin film passive element 4 can be a capacitor, a resistor, an inductor, or the like, or may be an element that combines them. In the thin film passive element 4, a pilot hole is formed at a predetermined position between the corresponding terminal electrode 3 and the LSI connection pad 9, and a through via 8 is embedded in the pilot hole. The thickness of the thin film passive element chip composed of the thin film passive element 4 and the substrate 7 is 15 μm or less.

接合材５は、薄膜受動素子４の端子電極３と、実装基板１の接続パッド２とを接合し、互いに対応する端子電極３と接続パッド２を電気的に接続する。接合材５には、例えば、半田を用いることができる。   The bonding material 5 bonds the terminal electrode 3 of the thin film passive element 4 and the connection pad 2 of the mounting substrate 1, and electrically connects the corresponding terminal electrode 3 and connection pad 2. For the bonding material 5, for example, solder can be used.

樹脂６は、少なくとも実装基板１と薄膜受動素子４の間における接合部（接続パッド２、端子電極３、接合材５）以外の空間を封止する絶縁樹脂である。樹脂６は、実装基板１上の薄膜受動素子４を実装する領域の外周において、基板７のＬＳＩ接続パッド９側の面まで満たされ、薄膜受動素子４を埋め込んでいる。樹脂には、例えば、フィラーを含む低熱膨張樹脂を用いることができ、アンダーフィルやモールドに使用される樹脂を用いることができる。   The resin 6 is an insulating resin that seals at least a space between the mounting substrate 1 and the thin-film passive element 4 other than the bonding portion (the connection pad 2, the terminal electrode 3, and the bonding material 5). The resin 6 is filled up to the surface on the LSI connection pad 9 side of the substrate 7 in the outer periphery of the region where the thin film passive device 4 is mounted on the mounting substrate 1 and embeds the thin film passive device 4. As the resin, for example, a low thermal expansion resin containing a filler can be used, and a resin used for underfill or mold can be used.

基板７は、薄膜受動素子４を支持する基板であり、薄膜受動素子４と組み合わされて薄膜受動素子チップを構成する。基板７には、互いに対応する端子電極３及びＬＳＩ接続パッド９の間の所定の位置に下穴が形成されており、当該下穴に貫通ビア８が埋め込まれている。   The substrate 7 is a substrate that supports the thin film passive element 4 and is combined with the thin film passive element 4 to constitute a thin film passive element chip. In the substrate 7, pilot holes are formed at predetermined positions between the corresponding terminal electrodes 3 and LSI connection pads 9, and through vias 8 are embedded in the pilot holes.

基板７には、例えば、ビア形成前の絶縁処理が不要な点、表面が平滑な点、及び、微細な薄膜素子を形成に有利な点からガラスを用いることが好ましい。また、基板７には、絶縁性のセラミックを用いることができ、薄膜素子形成に適しているシリコンを用い下穴の側壁面に絶縁性の膜を形成したものを用いてもよい。また、基板７には、基板７自身の反りを考慮すると、低熱膨張係数を有する材料からなることが好ましい。また、基板７は、搭載されるＬＳＩや半導体パッケージと熱膨張係数が近い材料を用いることにより、半導体素子実装後の信頼性が向上する。   For the substrate 7, for example, glass is preferably used because it does not require an insulating treatment before via formation, has a smooth surface, and is advantageous for forming a fine thin film element. The substrate 7 may be made of an insulating ceramic, and may be made of silicon suitable for forming a thin film element and having an insulating film formed on the side wall surface of the pilot hole. The substrate 7 is preferably made of a material having a low thermal expansion coefficient in consideration of the warpage of the substrate 7 itself. Further, the substrate 7 is made of a material having a thermal expansion coefficient close to that of the mounted LSI or semiconductor package, thereby improving the reliability after mounting the semiconductor element.

貫通ビア８は、互いに対応する端子電極３及びＬＳＩ接続パッド９を電気的に接続する。貫通ビア８は、薄膜受動素子４と基板７から構成される薄膜受動素子チップの所定の位置に形成された下穴に埋め込まれている。貫通ビア８は、薄膜受動素子４と基板７から構成される薄膜受動素子チップの厚さが１５μｍ以下と小さいために、微小サイズかつ低コストで形成することが可能である。   The through via 8 electrically connects the terminal electrode 3 and the LSI connection pad 9 corresponding to each other. The through via 8 is embedded in a pilot hole formed at a predetermined position of the thin film passive element chip constituted by the thin film passive element 4 and the substrate 7. The through via 8 can be formed in a small size and at a low cost because the thickness of the thin film passive element chip composed of the thin film passive element 4 and the substrate 7 is as small as 15 μm or less.

ＬＳＩ接続パッド９は、基板７の表面側に配設された接続パッドであり、ＬＳＩ（図示せず）と電気的に接続するためのものである。ＬＳＩ接続パッド９は、対応する端子電極３と貫通ビア８を介して電気的に接続されている。   The LSI connection pad 9 is a connection pad disposed on the surface side of the substrate 7 and is used for electrical connection with an LSI (not shown). The LSI connection pad 9 is electrically connected to the corresponding terminal electrode 3 through the through via 8.

次に、本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの受動素子がキャパシタの場合の例について図面を用いて説明する。図２は、本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの第１の構成を模式的に示した部分断面図である。図３は、本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの第２の構成を模式的に示した部分断面図である。   Next, an example in which the passive element of the thin film passive element chip in the passive element-embedded substrate according to the first embodiment of the present invention is a capacitor will be described with reference to the drawings. FIG. 2 is a partial cross-sectional view schematically showing a first configuration of the thin film passive element chip in the passive element built-in substrate according to the first embodiment of the present invention. FIG. 3 is a partial cross-sectional view schematically showing a second configuration of the thin film passive element chip in the passive element built-in substrate according to the first embodiment of the present invention.

図２を参照すると、薄膜受動素子チップは、端子電極３と、薄膜受動素子４と、基板７と、貫通ビア８と、ＬＳＩ接続パッド９ａ、９ｂ、９ｃと、カバー膜１４と、を有する。   Referring to FIG. 2, the thin film passive element chip includes a terminal electrode 3, a thin film passive element 4, a substrate 7, a through via 8, LSI connection pads 9 a, 9 b, 9 c, and a cover film 14.

端子電極３は、対応する実装基板（図１の１）の接続パッド（図１の２）と電気的に接続するための電極である。薄膜受動素子４（絶縁膜１３）の実装基板側の面（図２の下側）に配設されている。端子電極３は、対応するＬＳＩ接続パッド９ａ、９ｂ、９ｃと貫通ビア８を介して電気的に接続されている。接地用のＬＳＩ接続パッド９ｂに対応する端子電極３については、下部電極接続ビア１６、下部電極１０、及び貫通ビア８を介して接地用のＬＳＩ接続パッド９ｂと電気的に接続されている。電源用のＬＳＩ接続パッド９ａに対応する端子電極３については、貫通ビア８を介して電源用のＬＳＩ接続パッド９ａと電気的に接続されるとともに、上部電極接続ビア１５を介して上部電極１２と電気的に接続されている。端子電極３の材質は、限定されないが、めっき法で形成することができ、Ｃｕ等が適しており、Ｃｕの下地にＴｉ等の密着層があってもよい。Ｃｕめっきを用いる場合の厚さは、限定されないが、１〜２０μｍ程度とすることができる。   The terminal electrode 3 is an electrode for electrically connecting to a connection pad (2 in FIG. 1) of a corresponding mounting substrate (1 in FIG. 1). The thin film passive element 4 (insulating film 13) is disposed on the mounting substrate side surface (lower side in FIG. 2). The terminal electrode 3 is electrically connected to the corresponding LSI connection pads 9 a, 9 b, 9 c through the through via 8. The terminal electrode 3 corresponding to the grounding LSI connection pad 9 b is electrically connected to the grounding LSI connection pad 9 b through the lower electrode connection via 16, the lower electrode 10, and the through via 8. The terminal electrode 3 corresponding to the power supply LSI connection pad 9 a is electrically connected to the power supply LSI connection pad 9 a through the through via 8 and is connected to the upper electrode 12 through the upper electrode connection via 15. Electrically connected. Although the material of the terminal electrode 3 is not limited, it can be formed by a plating method, Cu or the like is suitable, and an adhesion layer such as Ti or the like may be provided on the base of Cu. Although the thickness in the case of using Cu plating is not limited, it can be set to about 1 to 20 μm.

薄膜受動素子４は、受動素子を有する部分であり、下部電極１０と、薄膜誘電体１１と、上部電極１２と、絶縁膜１３と、上部電極接続ビア１５と、下部電極接続ビア１６と、を有する。   The thin film passive element 4 is a part having a passive element, and includes a lower electrode 10, a thin film dielectric 11, an upper electrode 12, an insulating film 13, an upper electrode connection via 15, and a lower electrode connection via 16. Have.

下部電極１０は、基板７上に形成された電極であり、基板７側の反対面の所定の領域に薄膜誘電体１１が形成されている。下部電極１０は、薄膜誘電体１１と上部電極１２とともにＭＩＭ（Metal Insulation Metal）キャパシタを構成する。下部電極１０は、基板７側で貫通ビア８を介して接地用のＬＳＩ接続パッド９ｂと電気的に接続され、基板７側の反対側で下部電極接続ビア１６を介して端子電極３と電気的に接続されている。下部電極１０の材質は、限定されるものではないが、ベースとなる基板７との密着性に優れ、薄膜誘電体１１への拡散が少ない金属または合金が望ましく、例えば、絶縁基板側からＴｉ，Ｃｒ，Ｔａ，Ｍｏ等の活性金属、Ｐｔ，Ｒｕ，ＴｉＮ，Ａｕ等の高バリア性金属の順で成膜することが望ましい。下部電極１０の形成方法は、限定されないが、スパッタ法、ＣＶＤ法、蒸着法あるいはめっき法を用いることができる。   The lower electrode 10 is an electrode formed on the substrate 7, and a thin film dielectric 11 is formed in a predetermined region on the opposite surface on the substrate 7 side. The lower electrode 10 and the thin film dielectric 11 and the upper electrode 12 constitute an MIM (Metal Insulation Metal) capacitor. The lower electrode 10 is electrically connected to the grounding LSI connection pad 9b via the through via 8 on the substrate 7 side, and electrically connected to the terminal electrode 3 via the lower electrode connection via 16 on the opposite side of the substrate 7 side. It is connected to the. The material of the lower electrode 10 is not limited, but a metal or an alloy that is excellent in adhesion to the base substrate 7 and has little diffusion to the thin film dielectric 11 is desirable. For example, Ti, It is desirable to form a film in the order of an active metal such as Cr, Ta and Mo and a high barrier metal such as Pt, Ru, TiN and Au. Although the formation method of the lower electrode 10 is not limited, a sputtering method, a CVD method, a vapor deposition method, or a plating method can be used.

薄膜誘電体１１は、下部電極１０上に形成された誘電体であり、下部電極１０側の反対面の所定の領域に上部電極１２が形成されている。薄膜誘電体１１は、下部電極１０と上部電極１２とともにＭＩＭキャパシタを構成する。薄膜誘電体１１の材料は、特に限定されず、酸化タンタル、酸化アルミニウム、酸化シリコン等の高絶縁性の材料を用いることができ、高誘電率を有するペロブスカイト構造を有する化合物を用いることが望ましい。ペロブスカイト構造を有する化合物としては、ＳｒＴｉＯ３、ＳｒＴｉＯ３のＳｒの一部をＢａに置換した（Ｓｒ，Ｂａ）ＴｉＯ３またはＰｂＴｉＯ３やＢａＴｉＯ３を骨格としてＰｂ，Ｂａサイト（Ａサイト）の一部をＳｒ，Ｃａ，Ｌａ等で置換することによってＡサイトの平均原子価を２価にした、ないしＴｉ（Ｂサイト）の一部をＭｇ，Ｗ，Ｎｂ，Ｚｒ，Ｎｉ，Ｚｎ等で置換してＢサイトの平均原子価を４価にした複合ペロブスカイト化合物が望ましい。薄膜誘電体１１の形成方法は限定されないが、スパッタ法，ＣＶＤ法またはゾルゲル法を用いることができる。The thin film dielectric 11 is a dielectric formed on the lower electrode 10, and the upper electrode 12 is formed in a predetermined region on the opposite surface on the lower electrode 10 side. The thin film dielectric 11 forms an MIM capacitor together with the lower electrode 10 and the upper electrode 12. The material of the thin film dielectric 11 is not particularly limited, and a highly insulating material such as tantalum oxide, aluminum oxide, or silicon oxide can be used, and it is desirable to use a compound having a perovskite structure having a high dielectric constant. As a compound having a perovskite structure, a part of SrTiO 3 , SrTiO 3 Sr is replaced with Ba (Sr, Ba) TiO 3 or PbTiO 3 or BaTiO 3 as a skeleton and a part of Pb, Ba site (A site) Is replaced with Sr, Ca, La, etc., so that the average valence of the A site is divalent, or a part of Ti (B site) is replaced with Mg, W, Nb, Zr, Ni, Zn, etc. A composite perovskite compound having a B-site average valence of 4 is desirable. The method for forming the thin film dielectric 11 is not limited, but a sputtering method, a CVD method, or a sol-gel method can be used.

上部電極１２は、薄膜誘電体１１上に形成された電極であり、薄膜誘電体１１側の反対面の所定の領域にて上部電極接続ビア１５と接続されている。上部電極１２は、下部電極１０と薄膜誘電体１１とともにＭＩＭキャパシタを構成する。上部電極１２は、貫通ビア８、端子電極３、及び上部電極接続ビア１５を介して電源用のＬＳＩ接続パッド９ａと電気的に接続されている。上部電極１２の材質は、下部電極１０と同様に限定はされないが、薄膜誘電体１１への拡散の少ないものが望ましく、例えば、Ｐｔ，Ｒｕ，ＴｉＮ，Ａｕが望ましい。上部電極１２の形成方法は、限定されないが、スパッタ法、ＣＶＤ法、蒸着法あるいはめっき法を用いることができる。   The upper electrode 12 is an electrode formed on the thin film dielectric 11 and is connected to the upper electrode connection via 15 in a predetermined region on the opposite surface on the thin film dielectric 11 side. The upper electrode 12 forms an MIM capacitor together with the lower electrode 10 and the thin film dielectric 11. The upper electrode 12 is electrically connected to the power supply LSI connection pad 9 a through the through via 8, the terminal electrode 3, and the upper electrode connection via 15. The material of the upper electrode 12 is not limited as in the case of the lower electrode 10, but a material with little diffusion into the thin film dielectric 11 is desirable, for example, Pt, Ru, TiN, and Au are desirable. Although the formation method of the upper electrode 12 is not limited, a sputtering method, a CVD method, a vapor deposition method, or a plating method can be used.

絶縁膜１３は、薄膜受動素子４において下部電極１０、薄膜誘電体１１、上部電極１２、上部電極接続ビア１５、及び下部電極接続ビア１６が配されていない空間に充填された絶縁体であり、ＭＩＭキャパシタとビアの間は電気的に絶縁されている。絶縁膜１３には、互いに対応する端子電極３及びＬＳＩ接続パッド９ａ、９ｃの間の所定の位置に下穴が形成されており、当該下穴に貫通ビア８が埋め込まれている。絶縁膜１３には、互いに対応する端子電極３及び下部電極１０の間の所定の位置に下穴が形成されており、当該下穴に下部電極接続ビア１６が埋め込まれている。絶縁膜１３には、互いに対応する端子電極３及び上部電極１２の間の所定の位置に下穴が形成されており、当該下穴に上部電極接続ビア１５が埋め込まれている。絶縁膜の材質や厚みは、限定されないが、ＳｉＯ２やＳｉ３Ｎ４からなる無機絶縁膜やポリイミドやエポキシ樹脂を用いることができる。The insulating film 13 is an insulator filled in a space where the lower electrode 10, the thin film dielectric 11, the upper electrode 12, the upper electrode connection via 15, and the lower electrode connection via 16 are not provided in the thin film passive element 4. The MIM capacitor and the via are electrically insulated. In the insulating film 13, a pilot hole is formed at a predetermined position between the terminal electrode 3 and the LSI connection pads 9 a and 9 c corresponding to each other, and the through via 8 is embedded in the pilot hole. In the insulating film 13, a pilot hole is formed at a predetermined position between the terminal electrode 3 and the lower electrode 10 corresponding to each other, and a lower electrode connection via 16 is embedded in the pilot hole. In the insulating film 13, a pilot hole is formed at a predetermined position between the terminal electrode 3 and the upper electrode 12 corresponding to each other, and an upper electrode connection via 15 is embedded in the pilot hole. The material and thickness of the insulating film are not limited, but an inorganic insulating film made of SiO 2 or Si 3 N 4 , polyimide, or epoxy resin can be used.

上部電極接続ビア１５は、互いに対応する端子電極３と上部電極１２を電気的に接続するビアである。上部電極接続ビア１５は、互いに対応する端子電極３及び上部電極１２の間の絶縁膜１３に形成された下穴に埋め込まれている。上部電極接続ビア１５の材質は、限定されず、金属あるいは合金を用いることができる。   The upper electrode connection via 15 is a via that electrically connects the terminal electrode 3 and the upper electrode 12 corresponding to each other. The upper electrode connection via 15 is embedded in a pilot hole formed in the insulating film 13 between the terminal electrode 3 and the upper electrode 12 corresponding to each other. The material of the upper electrode connection via 15 is not limited, and a metal or an alloy can be used.

下部電極接続ビア１６は、互いに対応する端子電極３と下部電極１０を電気的に接続するビアである。下部電極接続ビア１６は、互いに対応する端子電極３及び下部電極１０の間の絶縁膜１３に形成された下穴に埋め込まれている。上部電極接続ビア１５の材質は、限定されず、金属あるいは合金を用いることができる。   The lower electrode connection via 16 is a via that electrically connects the terminal electrode 3 and the lower electrode 10 corresponding to each other. The lower electrode connection via 16 is embedded in a prepared hole formed in the insulating film 13 between the terminal electrode 3 and the lower electrode 10 corresponding to each other. The material of the upper electrode connection via 15 is not limited, and a metal or an alloy can be used.

基板７は、薄膜受動素子４を支持する基板である。基板７には、互いに対応する端子電極３及びＬＳＩ接続パッド９ａ、９ｃの間の所定の位置に下穴が形成されており、当該下穴に貫通ビア８が埋め込まれている。基板７には、互いに対応する接地用のＬＳＩ接続パッド９ｂ及び下部電極１０の間の所定の位置に下穴が形成されており、当該下穴に貫通ビア８が埋め込まれている。   The substrate 7 is a substrate that supports the thin film passive element 4. In the substrate 7, a pilot hole is formed at a predetermined position between the terminal electrode 3 and the LSI connection pads 9 a and 9 c corresponding to each other, and a through via 8 is embedded in the pilot hole. In the substrate 7, a pilot hole is formed at a predetermined position between the corresponding LSI connection pads 9 b for grounding and the lower electrode 10, and a through via 8 is embedded in the pilot hole.

貫通ビア８は、少なくとも基板７を貫通するビアである。ＬＳＩ接続パッド９ａ、９ｃが配された領域の貫通ビア８は、基板７及び薄膜受動素子４（絶縁膜１３）を貫通する。電源用のＬＳＩ接続パッド９ａに対応する貫通ビア８は、電源用のＬＳＩ接続パッド９ａと端子電極３を電気的に接続する。接地用のＬＳＩ接続パッド９ｂに対応する貫通ビア８は、接地用のＬＳＩ接続パッド９ｂと下部電極１０を電気的に接続する。信号用のＬＳＩ接続パッド９ｃに対応する貫通ビア８は、信号用のＬＳＩ接続パッド９ｃと端子電極３を電気的に接続する。貫通ビア８の材質は、限定されず、金属あるいは合金を用いることができる。   The through via 8 is a via that penetrates at least the substrate 7. The through via 8 in the region where the LSI connection pads 9a and 9c are disposed penetrates the substrate 7 and the thin-film passive element 4 (insulating film 13). The through via 8 corresponding to the power supply LSI connection pad 9 a electrically connects the power supply LSI connection pad 9 a and the terminal electrode 3. The through via 8 corresponding to the ground LSI connection pad 9 b electrically connects the ground LSI connection pad 9 b and the lower electrode 10. The through via 8 corresponding to the signal LSI connection pad 9 c electrically connects the signal LSI connection pad 9 c and the terminal electrode 3. The material of the through via 8 is not limited, and a metal or an alloy can be used.

ＬＳＩ接続パッド９ａは、ＬＳＩ（図示せず）の電源パッド（図示せず）と電気的に接続するための接続パッドである。ＬＳＩ接続パッド９ａは、基板７のＬＳＩ（図示せず）側の面に配設されている。ＬＳＩ接続パッド９ａは、貫通ビア８を介して端子電極３と電気的に接続され、貫通ビア８、端子電極３、上部電極接続ビア１５を介して上部電極１２と電気的に接続されている。   The LSI connection pad 9a is a connection pad for electrical connection with a power supply pad (not shown) of an LSI (not shown). The LSI connection pad 9a is disposed on the surface of the substrate 7 on the LSI (not shown) side. The LSI connection pad 9 a is electrically connected to the terminal electrode 3 through the through via 8, and is electrically connected to the upper electrode 12 through the through via 8, the terminal electrode 3, and the upper electrode connection via 15.

ＬＳＩ接続パッド９ｂは、ＬＳＩ（図示せず）の接地パッド（図示せず）と電気的に接続するための接続パッドである。ＬＳＩ接続パッド９ｂは、基板７のＬＳＩ（図示せず）側の面に配設されている。ＬＳＩ接続パッド９ｂは、貫通ビア８を介して下部電極１０と電気的に接続され、貫通ビア８、下部電極１０、下部電極接続ビア１６を介して端子電極３と電気的に接続されている。   The LSI connection pad 9b is a connection pad for electrically connecting to a ground pad (not shown) of an LSI (not shown). The LSI connection pad 9b is disposed on the surface of the substrate 7 on the LSI (not shown) side. The LSI connection pad 9 b is electrically connected to the lower electrode 10 through the through via 8, and is electrically connected to the terminal electrode 3 through the through via 8, the lower electrode 10, and the lower electrode connection via 16.

ＬＳＩ接続パッド９ｃは、ＬＳＩ（図示せず）の信号パッド（図示せず）と電気的に接続するための接続パッドである。ＬＳＩ接続パッド９ｃは、基板７のＬＳＩ（図示せず）側の面に配設されている。ＬＳＩ接続パッド９ｃは、貫通ビア８を介して端子電極３と電気的に接続されている。なお、ＬＳＩ接続パッド９ｃは、ＭＩＭキャパシタには接続されていない。   The LSI connection pad 9c is a connection pad for electrically connecting to a signal pad (not shown) of an LSI (not shown). The LSI connection pad 9c is disposed on the surface of the substrate 7 on the LSI (not shown) side. The LSI connection pad 9 c is electrically connected to the terminal electrode 3 through the through via 8. The LSI connection pad 9c is not connected to the MIM capacitor.

なお、図２では、電源用のＬＳＩ接続パッド９ａが上部電極１２に電気的に接続され、かつ、接地用のＬＳＩ接続パッド９ｂが下部電極１０に電気的に接続された構成となっているが、これらの関係が逆の構成、すなわち、電源用のＬＳＩ接続パッド９ａが下部電極１０に電気的に接続され、かつ、接地用のＬＳＩ接続パッド９ｂが上部電極１２に電気的に接続された構成としてもよい。   In FIG. 2, the power supply LSI connection pad 9a is electrically connected to the upper electrode 12, and the grounding LSI connection pad 9b is electrically connected to the lower electrode 10. These configurations are reversed, that is, a power supply LSI connection pad 9a is electrically connected to the lower electrode 10 and a grounding LSI connection pad 9b is electrically connected to the upper electrode 12. It is good.

ＬＳＩ接続パッド９ａ、９ｂ、９ｃの材質は、限定されないが、めっき法で形成することができ、Ｃｕ等が適しており、Ｃｕの下地にＴｉ等の密着層があってもよい。Ｃｕめっきを用いる場合の厚さは、限定されないが、１〜２０μｍ程度とすることができる。また、ＬＳＩ接続パッド９ａ、９ｂ、９ｃは、ＬＳＩ（半導体素子）に接合する際には表面側からＡｕ／ＮｉやＳｎ等の表面処理が施されていることが望ましい。   The material of the LSI connection pads 9a, 9b, and 9c is not limited, but can be formed by a plating method, Cu or the like is suitable, and an adhesion layer such as Ti or the like may be provided on the base of Cu. Although the thickness in the case of using Cu plating is not limited, it can be set to about 1 to 20 μm. Further, it is desirable that the LSI connection pads 9a, 9b, and 9c are subjected to surface treatment such as Au / Ni or Sn from the surface side when bonded to the LSI (semiconductor element).

カバー膜１４は、絶縁膜１３上の端子電極３間と、基板７上のＬＳＩ接続パッド９ａ、９ｂ、９ｃ間と、をカバーする絶縁体である。カバー膜１４は、各端子電極３及び各ＬＳＩ接続パッド９ａ、９ｂ、９ｃのそれぞれの周縁部を覆い、各端子電極３及び各ＬＳＩ接続パッド９ａ、９ｂ、９ｃのそれぞれの中心の必要な部分は開口している。カバー膜１４の材質や構造は、限定されないが、カバー膜１４を形成することにより半田接続する場合のソルダーレジストの役目をなすものであればよい。   The cover film 14 is an insulator that covers between the terminal electrodes 3 on the insulating film 13 and between the LSI connection pads 9a, 9b, and 9c on the substrate 7. The cover film 14 covers the peripheral portions of the terminal electrodes 3 and the LSI connection pads 9a, 9b, and 9c, and the necessary portions at the centers of the terminal electrodes 3 and the LSI connection pads 9a, 9b, and 9c are It is open. Although the material and structure of the cover film 14 are not limited, any material may be used as long as it serves as a solder resist when soldered by forming the cover film 14.

図２の薄膜受動素子チップのキャパシタは、ＬＳＩ接続パッド９ｂ、端子電極３がビア８、１５、１６により基板７に垂直方向に接続されているが、この構造とすることによりＬＳＩからの信号の劣化を防ぐことができる。   In the capacitor of the thin film passive element chip of FIG. 2, the LSI connection pad 9b and the terminal electrode 3 are connected to the substrate 7 through the vias 8, 15 and 16 in the vertical direction. Deterioration can be prevented.

なお、図２では端子電極３のピッチはＬＳＩ接続パッド９ａ、９ｂ、９ｃのピッチと対応した構成となっているが、図３のように端子電極３のピッチをＬＳＩ接続パッド９ａ、９ｂ、９ｃのピッチよりも大きくしても構わない。図３では端子電極３で貫通ビア８からの配線を引き回し、カバー膜１４で端子電極３の開口ピッチを広げている。図３の構造ではキャパシタ（１０、１１、１２）とＬＳＩの間の配線距離は、図２と同様に十分に小さいため、デカップリングキャパシタとして使用する場合にはＬＳＩとキャパシタの間のインダクタンスが小さい接続構造となる。また、端子電極３のピッチを大きくすることで、信号については図２よりも大きいが、低コストなプリント基板を使用できる利点がある。   In FIG. 2, the pitch of the terminal electrodes 3 corresponds to the pitch of the LSI connection pads 9a, 9b, 9c, but the pitch of the terminal electrodes 3 is changed to the LSI connection pads 9a, 9b, 9c as shown in FIG. It may be larger than the pitch. In FIG. 3, the wiring from the through via 8 is routed by the terminal electrode 3, and the opening pitch of the terminal electrode 3 is widened by the cover film 14. In the structure of FIG. 3, the wiring distance between the capacitors (10, 11, 12) and the LSI is sufficiently small as in FIG. 2, so that when used as a decoupling capacitor, the inductance between the LSI and the capacitor is small. It becomes a connection structure. Further, by increasing the pitch of the terminal electrodes 3, the signal is larger than that in FIG. 2, but there is an advantage that a low-cost printed circuit board can be used.

また、図１から図３では薄膜受動素子チップの受動素子非形成面にＬＳＩ接続パッドを形成した構造について説明したが、ＬＳＩ接続パッド９（９ａ、９ｂ、９ｃ）に代えて半導体パッケージの入出力端子に対応したパッケージ接続パッドであってもよい。   1 to 3, the structure in which the LSI connection pad is formed on the passive element non-forming surface of the thin film passive element chip has been described. However, instead of the LSI connection pad 9 (9a, 9b, 9c), input / output of the semiconductor package is performed. It may be a package connection pad corresponding to the terminal.

次に、本発明の実施例１に係る受動素子内蔵基板の製造方法について図面を用いて説明する。図４は、本発明の実施例１に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。図５は、本発明の実施例１に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した第１の断面図である。図６は、本発明の実施例１に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した第２の断面図である。   Next, a method for manufacturing a substrate with a built-in passive element according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 4 is a process cross-sectional view schematically showing the method for manufacturing the substrate with built-in passive element according to the first embodiment of the present invention. FIG. 5 is a first cross-sectional view schematically showing a modified example of the configuration after the resin forming step in the method for manufacturing the substrate with built-in passive element according to the first embodiment of the present invention. FIG. 6 is a second cross-sectional view schematically showing a modified example of the configuration after the resin forming step in the method for manufacturing the substrate with built-in passive element according to the first embodiment of the present invention.

まず、基板７上に複数の端子電極３を有する薄膜受動素子４を形成する（ステップＡ１；図４（Ａ）参照）。なお、基板７上に受動素子をキャパシタとする薄膜受動素子４が形成された薄膜受動素子チップの製造方法の詳細は後述する。また、基板７は、限定されないが、ガラス基板、セラミック基板、シリコン基板等を用いることができる。   First, a thin film passive element 4 having a plurality of terminal electrodes 3 is formed on a substrate 7 (step A1; see FIG. 4A). The details of the method of manufacturing the thin film passive element chip in which the thin film passive element 4 having the passive element as a capacitor is formed on the substrate 7 will be described later. The substrate 7 is not limited, but a glass substrate, a ceramic substrate, a silicon substrate, or the like can be used.

次に、基板７をチップ状に切断して受動素子チップを製造した後、該受動素子チップを反転させ、該チップを接合材５を用いて、あらかじめ薄膜受動素子４の端子電極３に対応した接続パッド２が形成された実装基板１に接合する（ステップＡ２；図４（Ｂ）参照）。ここで、接合材５は、限定されないが、Ｓｎ−Ａｇ−Ｃｕ半田を用いることができる。   Next, after manufacturing the passive element chip by cutting the substrate 7 into a chip shape, the passive element chip is inverted, and the chip is used in advance with the bonding material 5 to correspond to the terminal electrode 3 of the thin film passive element 4. Bonding is made to the mounting substrate 1 on which the connection pads 2 are formed (step A2; see FIG. 4B). Here, the bonding material 5 is not limited, but Sn—Ag—Cu solder can be used.

次に、薄膜受動素子４と実装基板１の間および実装基板１の表面を覆うように、樹脂６で封止する（ステップＡ３；図４（Ｃ）参照）。なお、樹脂６の種類や厚みは、限定されないが、薄膜受動素子チップの薄膜受動素子４の実装基板１側の面から基板７の周囲を１５μｍ以上の高さとなるように覆う事が望ましい。   Next, sealing is performed with resin 6 so as to cover the thin film passive element 4 and the mounting substrate 1 and the surface of the mounting substrate 1 (step A3; see FIG. 4C). The type and thickness of the resin 6 are not limited, but it is desirable to cover the periphery of the substrate 7 so as to have a height of 15 μm or more from the surface on the mounting substrate 1 side of the thin film passive element 4 of the thin film passive element chip.

ここで、図４（Ｃ）では樹脂６が薄膜受動素子チップ（基板７乃至薄膜受動素子４）の側壁を全部覆っていないが、図５のようにアンダーフィル工程および図６に示すモールド工程を経て薄膜受動素子チップ（基板７乃至薄膜受動素子４）全体を覆ってもよい。図６の後、モールド樹脂２０上部から研削加工することにより、図４（Ｄ）と同様の構造を得ることができる。図６のように薄膜受動素子チップ（基板７乃至薄膜受動素子４）全体をモールドした方が研削加工時に薄膜受動素子チップにクラック等の不良発生頻度が減る利点がある。   Here, in FIG. 4C, the resin 6 does not cover all the side walls of the thin film passive element chip (substrate 7 to thin film passive element 4), but the underfill process as shown in FIG. 5 and the molding process shown in FIG. Then, the entire thin film passive element chip (substrate 7 to thin film passive element 4) may be covered. After FIG. 6, by grinding from the upper part of the mold resin 20, the same structure as FIG. 4D can be obtained. As shown in FIG. 6, molding the entire thin film passive element chip (substrate 7 to thin film passive element 4) has an advantage of reducing the frequency of occurrence of defects such as cracks in the thin film passive element chip during grinding.

次に、基板７の受動素子非形成面側から研削加工を行い、基板７の厚さが１５μｍ以下となるまで、基板７および樹脂６を研削する（ステップＡ４；図４（Ｄ）参照）。   Next, grinding is performed from the passive element non-formation surface side of the substrate 7, and the substrate 7 and the resin 6 are ground until the thickness of the substrate 7 becomes 15 μm or less (step A4; see FIG. 4D).

次に、基板７乃至薄膜受動素子４に下穴を形成し、下穴内に導体を充填し、貫通ビア８を形成する（ステップＡ５）。なお、基板７にＳｉ等の非絶縁性基板を使用した場合には、下穴形成後、下穴側壁に絶縁処理を施し、その後、ビア導体を充填する必要がある。   Next, a pilot hole is formed in the substrate 7 to the thin film passive element 4, a conductor is filled in the pilot hole, and a through via 8 is formed (step A5). When a non-insulating substrate such as Si is used for the substrate 7, it is necessary to insulate the side wall of the prepared hole after forming the prepared hole, and then fill the via conductor.

ここで、下穴の形成方法は、限定されないが、基板７の厚みが１５μｍ以下と小さいため、容易に下穴を形成することができ、低コストなウエットエッチングでもビア形成が可能である。例えば、レジストでマスクを形成した後、弗酸によりガラス基板（基板７）をエッチングして直径５０μｍの下穴を形成し、続いて、Ｏ２プラズマにより薄膜受動素子４（図２の絶縁膜１３）にも下穴を形成し、その後、上記レジストを除去する。Here, the method for forming the pilot hole is not limited, but since the thickness of the substrate 7 is as small as 15 μm or less, the pilot hole can be easily formed, and via formation is possible even with low-cost wet etching. For example, after forming a mask with a resist, the glass substrate (substrate 7) is etched with hydrofluoric acid to form a pilot hole with a diameter of 50 μm, and then the thin film passive element 4 (insulating film 13 in FIG. 2) is formed with O 2 plasma. ) Is also formed, and then the resist is removed.

また、受動素子チップ単体では厚みを５０μｍ以下にするとハンドリングが困難となるが、実施例１では樹脂６で封止した後に基板７を薄化しているため、１５μｍ以下の厚みが可能となっている。また、厚みが１５μｍ以下としてから貫通ビア８を形成しているため、下穴形成とともにビア充填も容易に行うことができる。   In addition, when the thickness of the passive element chip alone is 50 μm or less, handling becomes difficult, but in Example 1, since the substrate 7 is thinned after sealing with the resin 6, a thickness of 15 μm or less is possible. . Further, since the through via 8 is formed after the thickness is 15 μm or less, the via filling can be easily performed together with the formation of the prepared hole.

また、ビアの材質、充填の方法も限定はされないが、Ｃｕめっきによるビア充填を用いることができる。また、この後に形成するＬＳＩ接続パッド９に適合した形状をレジストでパターニングした後、電解Ｃｕめっきにより貫通ビア８とＬＳＩ接続パッド９を同時に形成することもできる。ビアの深さが小さいため、めっきによるビア充填を行った場合にも短時間でビア充填を行うことができ、低コスト化に有利となっている。また、ビア径も限定されないが、導電性ペーストによりビア充填を行う場合にもビア深さが小さいためアスペクト比が小さく容易に充填が可能である。   The via material and filling method are not limited, but via filling by Cu plating can be used. In addition, after a shape suitable for the LSI connection pad 9 to be formed later is patterned with a resist, the through via 8 and the LSI connection pad 9 can be simultaneously formed by electrolytic Cu plating. Since the via depth is small, via filling can be performed in a short time even when via filling by plating is performed, which is advantageous for cost reduction. Also, the via diameter is not limited, but even when filling vias with a conductive paste, the via depth is small, so the aspect ratio is small and can be filled easily.

次に、貫通ビア８と対応する位置にＬＳＩ接続パッド９を形成する（ステップＡ６；図４（Ｅ）参照）。   Next, an LSI connection pad 9 is formed at a position corresponding to the through via 8 (step A6; see FIG. 4E).

次に、絶縁樹脂として感光性エポキシーフェノール樹脂を使用し、露光・現像によりＬＳＩ接続パッド９の裏面を露出するようにパターニング、キュアして、カバー膜（図２の１４に対応）を形成する（ステップＡ７）。   Next, a photosensitive epoxy-phenol resin is used as an insulating resin, and patterning and curing are performed so as to expose the back surface of the LSI connection pad 9 by exposure and development, thereby forming a cover film (corresponding to 14 in FIG. 2) ( Step A7).

以上により、図１と同様な受動素子内蔵基板が完成する。なお、ＬＳＩ接続パッド９に代えて半導体パッケージ接続パッドを形成してもよい。また、図４（Ｅ）では、実装基板１上に設けた接続パッド２の位置と貫通ビア８の形成位置が一致しているが、貫通ビア８と接続パッド２が電気的に接続していれば位置が同じでなくても構わない。   Thus, a passive element built-in substrate similar to that shown in FIG. 1 is completed. Instead of the LSI connection pad 9, a semiconductor package connection pad may be formed. In FIG. 4E, the position of the connection pad 2 provided on the mounting substrate 1 and the formation position of the through via 8 match, but the through via 8 and the connection pad 2 are electrically connected. If the position is not the same.

この後、図１の受動素子内蔵基板のＬＳＩ接続パッド９上に電極として無電解めっきでパッド側からＮｉおよびＡｕをそれぞれ３μｍ、０．０５μｍの厚みで成膜し、その後、Ｓｎ−Ａｇ−Ｃｕ半田を用いてＬＳＩ接続パッド９上の電極にＬＳＩを接続することになる。   Thereafter, Ni and Au are formed in thickness of 3 μm and 0.05 μm from the pad side by electroless plating as an electrode on the LSI connection pad 9 of the passive element built-in substrate of FIG. 1, and then Sn—Ag—Cu. The LSI is connected to the electrode on the LSI connection pad 9 using solder.

図１の受動素子内蔵基板に電源電圧１Ｖ、クロック周波数２ＧＨｚ、最大負荷電流１００ＡのＬＳＩを接続した場合、このＬＳＩを動作評価したところ、電源ノイズがほとんど無く十分なデカップリング特性を確認することができる。   When an LSI with a power supply voltage of 1 V, a clock frequency of 2 GHz, and a maximum load current of 100 A is connected to the passive element built-in substrate of FIG. 1, when this LSI is evaluated for operation, there is almost no power supply noise and sufficient decoupling characteristics are confirmed. it can.

次に、本発明の実施例１に係る受動素子内蔵基板における薄膜受動素子チップの受動素子がキャパシタの場合の例の製造方法について図面を用いて説明する。図７は、本発明の実施例１に係る受動素子内蔵基板の製造方法における中間品の一例の構成を模式的に示した部分断面図である。ここでの薄膜受動素子チップの受動素子がキャパシタの場合の例の製造方法は、ステップＡ１に相当するものである。   Next, a manufacturing method of an example in which the passive element of the thin film passive element chip in the substrate with built-in passive element according to the first embodiment of the present invention is a capacitor will be described with reference to the drawings. FIG. 7 is a partial cross-sectional view schematically showing the configuration of an example of an intermediate product in the method for manufacturing a substrate with a built-in passive element according to Example 1 of the present invention. The example manufacturing method in the case where the passive element of the thin film passive element chip is a capacitor corresponds to step A1.

まず、ガラス基板２１（図１の基板７に対応）となる５００μｍ厚の無アルカリガラスウエハ上に下部電極１０としてウエハ側からＴａ，Ｒｕの順でＤＣマグネトロンスパッタにより成膜する（ステップＢ１）。なお、Ｔａ，Ｒｕの膜厚は、共に５０ｎｍとすることができる。   First, a lower electrode 10 is deposited on a 500 μm-thick alkali-free glass wafer to be a glass substrate 21 (corresponding to the substrate 7 in FIG. 1) by DC magnetron sputtering in the order of Ta and Ru from the wafer side (step B1). The film thicknesses of Ta and Ru can both be 50 nm.

次に、薄膜誘電体１１としてＭｎを５％添加したＳｒＴｉＯ３（ＳＴＯ）をＲＦスパッタにより、４００℃で５０ｎｍの厚みに成膜する（ステップＢ２）。Next, SrTiO 3 (STO) to which 5% of Mn is added as the thin film dielectric 11 is formed to a thickness of 50 nm at 400 ° C. by RF sputtering (step B2).

次に、上部電極１２としてＴｉＮをターゲットとしてプロセスガスに窒素を利用したＤＣマグネトロンスパッタにより室温で１００ｎｍの厚みで成膜する（ステップＢ３）。これにより、ＭＩＭキャパシタ構造を得ることができる。   Next, the upper electrode 12 is formed with a thickness of 100 nm at room temperature by DC magnetron sputtering using TiN as a target and nitrogen as a process gas (step B3). Thereby, an MIM capacitor structure can be obtained.

次に、フォトリソグラフィーによりパターニングしたレジストをマスクとして、アンモニア、過酸化水素水および水の混合水溶液を用いて、上部電極１２となるＴｉＮをエッチングし、その後、レジストをメチルエチルケトン洗浄および酸素プラズマ洗浄で除去する（ステップＢ４）。   Next, using a resist patterned by photolithography as a mask, TiN to be the upper electrode 12 is etched using a mixed aqueous solution of ammonia, hydrogen peroxide and water, and then the resist is removed by cleaning with methyl ethyl ketone and oxygen plasma. (Step B4).

次に、パターニングしたフォトレジストをマスクとして、薄膜誘電体１１を弗酸と硝酸の混合水溶液によるエッチングでパターニングし、その後、フォトレジストを除去する（ステップＢ５）。   Next, using the patterned photoresist as a mask, the thin film dielectric 11 is patterned by etching with a mixed aqueous solution of hydrofluoric acid and nitric acid, and then the photoresist is removed (step B5).

次に、パターニングしたレジストをマスクとして、Ａｒイオンミリングにより下部電極１０をパターニングし、その後、レジストを除去する（ステップＢ６）。   Next, using the patterned resist as a mask, the lower electrode 10 is patterned by Ar ion milling, and then the resist is removed (step B6).

次に、絶縁膜１３として、感光性ポリイミドをスピンコートによる塗布および露光・現像によるパターニングを行った後、窒素気流中３２０℃で２時間キュアする（ステップＢ７）。ここで、絶縁膜１３の膜厚は、キュア後１．５μｍとして、この後に形成する端子電極３が上部電極１２および下部電極１０に接続あるいは非接続となるようにパターン形成する。   Next, as the insulating film 13, photosensitive polyimide is applied by spin coating and patterned by exposure / development, and then cured at 320 ° C. for 2 hours in a nitrogen stream (step B7). Here, the film thickness of the insulating film 13 is 1.5 μm after curing, and the pattern is formed so that the terminal electrode 3 to be formed thereafter is connected to or disconnected from the upper electrode 12 and the lower electrode 10.

次に、電解めっきのシード層としてウエハ側からＴｉを５０ｎｍ、Ｃｕを３００ｎｍの厚みで成膜した後、レジストをマスクとして電解めっきによりＣｕで端子電極３の下地を形成し、レジストを除去する（ステップＢ８）。   Next, after forming a 50 nm thick Ti and 300 nm thick Cu from the wafer side as a seed layer for electrolytic plating, the base of the terminal electrode 3 is formed by Cu by electrolytic plating using the resist as a mask, and the resist is removed ( Step B8).

次に、絶縁樹脂として感光性エポキシフェノール樹脂を使用し、露光・現像により端子電極３の裏面を露出するようにパターニング、キュアして、カバー膜１４を形成する（ステップＢ９）。   Next, a photosensitive epoxy phenol resin is used as the insulating resin, and the cover film 14 is formed by patterning and curing so as to expose the back surface of the terminal electrode 3 by exposure and development (step B9).

次に、端子電極３として無電解めっきで端子電極側からＮｉ、Ａｕをそれぞれ３μｍ、０．０５μｍの厚みで成膜する（ステップＢ１０）。   Next, Ni and Au are formed in a thickness of 3 μm and 0.05 μm from the terminal electrode side by electroless plating as the terminal electrode 3 (step B10).

ステップＢ１０で得られた複数のキャパシタを形成した薄膜受動素子ウエハを切断する（ステップＢ１１）。これにより、図７の薄膜受動素子チップを得ることができる。   The thin film passive element wafer formed with the plurality of capacitors obtained in step B10 is cut (step B11). Thereby, the thin film passive element chip of FIG. 7 can be obtained.

図７では、３種類の端子電極３、すなわち、絶縁膜１３に上部電極接続ビア１５が形成されて上部電極１２に接続されている端子電極３と、下部電極１０に接続されている端子電極３と、キャパシタの電極に接続されていない端子電極３と、が存在することがわかる。   In FIG. 7, there are three types of terminal electrodes 3, that is, a terminal electrode 3 in which an upper electrode connection via 15 is formed in the insulating film 13 and connected to the upper electrode 12, and a terminal electrode 3 connected to the lower electrode 10. And a terminal electrode 3 not connected to the electrode of the capacitor.

ステップＢ１１の後、図４（Ｂ）のステップＡ２に続くことになる。   Step B11 is followed by step A2 in FIG.

ステップＢ１〜ステップＢ１１により製造した薄膜キャパシタチップを用いて、ステップＡ２〜Ａ７により薄膜受動素子内蔵基板を製造すると、一辺が２０ｍｍのサイズの薄膜受動素子内蔵基板で端子電極３は９０００個あり、７．２μＦの容量が得られる。   When a thin film passive element built-in substrate is manufactured in steps A2 to A7 using the thin film capacitor chip manufactured in steps B1 to B11, the thin film passive element built-in substrate with a side of 20 mm is 9000 terminal electrodes 3. A capacitance of 2 μF is obtained.

実施例１によれば、以下のような効果を奏する。   According to the first embodiment, the following effects can be obtained.

実施例１に係る受動素子内蔵基板の第１の効果は、受動素子チップ（薄膜受動素子４乃至基板７）の厚さを小さくできるため、受動素子チップ内に形成された貫通ビア８を介して受動素子とＬＳＩまたは半導体パッケージ間の距離が小さい状態で接続可能になり、低インダクタンスで受動素子と半導体素子又は半導体パッケージが接続される点にある。特に、高速で動作するＬＳＩのデカップリングに対して効果がある。   The first effect of the substrate with built-in passive element according to the first embodiment is that the thickness of the passive element chip (thin film passive element 4 to substrate 7) can be reduced, and therefore through the through via 8 formed in the passive element chip. Connection is possible with a small distance between the passive element and the LSI or semiconductor package, and the passive element and the semiconductor element or semiconductor package are connected with low inductance. In particular, this is effective for decoupling LSIs that operate at high speed.

実施例１に係る受動素子内蔵基板の第２の効果は、受動素子内蔵基板内の受動素子チップに形成される貫通ビア８の長さが１５μｍ以下となるため、容易に製造可能な構造を有しており、低コスト化が可能な点にある。   The second effect of the passive element built-in substrate according to the first embodiment is that the through via 8 formed in the passive element chip in the passive element built-in substrate has a length of 15 μm or less. Therefore, the cost can be reduced.

実施例１に係る受動素子内蔵基板の第３の効果は、受動素子形成基板にＬＳＩまたは半導体パッケージと熱膨張係数が近い材料を使用することにより、半導体素子又は半導体パッケージ実装後の信頼性が高いパッケージあるいはインターポーザが得られる点にある。   The third effect of the passive element built-in substrate according to the first embodiment is that the passive element forming substrate is made of a material having a thermal expansion coefficient close to that of the LSI or the semiconductor package, so that the reliability after mounting the semiconductor element or the semiconductor package is high. The package or interposer is obtained.

実施例１に係る受動素子内蔵基板の第４の効果は、薄膜受動素子チップの厚みが小さいことから非内蔵の基板とほとんど変わらない厚みとなる点である。   A fourth effect of the passive element built-in substrate according to the first embodiment is that the thickness of the thin film passive element chip is almost the same as that of the non-built-in substrate because the thickness of the thin film passive element chip is small.

実施例１に係る受動素子内蔵基板の製造方法の第１の効果は、実装基板１の接合材５および樹脂６による固定後に受動素子チップ（薄膜受動素子４乃至基板７）を薄化することが可能なため、受動素子内蔵基板の薄化が可能な点にある。   The first effect of the method for manufacturing the substrate with built-in passive elements according to the first embodiment is that the passive element chip (thin film passive elements 4 to 7) is thinned after the mounting substrate 1 is fixed with the bonding material 5 and the resin 6. Since this is possible, the passive element built-in substrate can be thinned.

実施例１に係る受動素子内蔵基板の製造方法の第２の効果は、単体ではハンドリング困難な厚みに薄化された受動素子チップ（薄膜受動素子４乃至基板７）を実装基板１に接続した後に貫通ビア８を形成するため、貫通ビア８を容易に低コストで形成できる点にある。   The second effect of the method for manufacturing the substrate with built-in passive element according to the first embodiment is that after the passive element chip (thin film passive elements 4 to 7) thinned to a thickness that is difficult to handle by itself is connected to the mounting substrate 1. Since the through via 8 is formed, the through via 8 can be easily formed at low cost.

実施例１に係る受動素子内蔵基板の製造方法の第３の効果は、薄膜受動素子４も一般的な積層セラミック部品と比較して低インダクタンス構造を製造できる点にある。また、これらの構造は受動素子チップの厚みが１５μｍ以下と小さいため、容易にビア形成が可能であり低コスト化に有利である。   A third effect of the method for manufacturing the substrate with built-in passive element according to the first embodiment is that the thin-film passive element 4 can also manufacture a low inductance structure as compared with a general multilayer ceramic component. Moreover, since the passive element chip has a small thickness of 15 μm or less in these structures, a via can be easily formed, which is advantageous for cost reduction.

本発明の実施例２に係る受動素子内蔵基板について図面を用いて説明する。図８は、本発明の実施例２に係る受動素子内蔵基板の構成を模式的に示した断面図である。図９は、本発明の実施例２に係る受動素子内蔵基板におけるスティフナーの構成を模式的に示した平面図である。   A passive element built-in substrate according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 8 is a cross-sectional view schematically showing the configuration of the passive element built-in substrate according to the second embodiment of the present invention. FIG. 9 is a plan view schematically showing the configuration of the stiffener in the substrate with built-in passive element according to the second embodiment of the present invention.

実施例２に係る受動素子内蔵基板には、実装基板１上の薄膜受動素子チップ（薄膜受動素子４乃至基板７）周辺部にスティフナー１７を接着した構造を示す。スティフナー１７の材質については限定されないが、低熱膨張かつ高弾性の金属あるいは合金を用いることができる。スティフナー１７の上面は、薄膜受動素子チップの受動素子非形成面（基板７の表面）および樹脂６の表面と一致している。その他の構成は、実施例１と同様である。スティフナー１７を設けることにより樹脂６による封止時の実装基板１の反りを低減することができる。   The passive element built-in substrate according to the second embodiment has a structure in which a stiffener 17 is bonded to the periphery of the thin film passive element chip (the thin film passive elements 4 to 7) on the mounting substrate 1. The material of the stiffener 17 is not limited, but a metal or alloy having low thermal expansion and high elasticity can be used. The upper surface of the stiffener 17 coincides with the passive element non-formation surface (surface of the substrate 7) of the thin film passive element chip and the surface of the resin 6. Other configurations are the same as those of the first embodiment. By providing the stiffener 17, it is possible to reduce the warpage of the mounting substrate 1 during sealing with the resin 6.

次に、本発明の実施例２に係る受動素子内蔵基板の製造方法について図面を用いて説明する。図１０は、本発明の実施例２に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。   Next, a method for manufacturing a substrate with a built-in passive element according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 10 is a process cross-sectional view schematically showing a method for manufacturing a substrate with a built-in passive element according to Embodiment 2 of the present invention.

まず、実施例１のステップＡ１（例えば、ステップＢ１〜Ｂ１１）と同様に、基板７上に複数の端子電極３を有する薄膜受動素子４を形成する（ステップＣ１；図１０（Ａ）参照）。   First, the thin-film passive element 4 having a plurality of terminal electrodes 3 is formed on the substrate 7 in the same manner as in Step A1 (for example, Steps B1 to B11) of Example 1 (Step C1; see FIG. 10A).

次に、基板７をチップ状に切断して受動素子チップを製造し、一方で、実装基板１に図９に示す厚さ１ｍｍのスティフナー１７を接着剤（図示せず；例えばエポキシ接着剤）で接着した後、受動素子チップを実装基板１に接合材５（例えばＳｎ−Ａｇ−Ｃｕ半田）で接続する（ステップＣ２；図１０（Ｂ）参照）。   Next, the substrate 7 is cut into chips to produce a passive element chip. On the other hand, a 1 mm thick stiffener 17 shown in FIG. 9 is attached to the mounting substrate 1 with an adhesive (not shown; for example, epoxy adhesive). After bonding, the passive element chip is connected to the mounting substrate 1 with a bonding material 5 (for example, Sn—Ag—Cu solder) (step C2; see FIG. 10B).

次に、薄膜受動素子４と実装基板１の間、及び、実装基板１の表面を全て覆うように樹脂６を充填した後、キュアする（ステップＣ３；図１０（Ｃ）参照）。   Next, the resin 6 is filled between the thin film passive element 4 and the mounting substrate 1 and so as to cover the entire surface of the mounting substrate 1, and then cured (step C3; see FIG. 10C).

次に、基板７の受動素子非形成面側から研削加工を行い、基板７の厚さが１０μｍ程度になるまで、スティフナー１７、基板７および樹脂６を研削する（ステップＣ４；図１０（Ｄ）参照）。   Next, grinding is performed from the passive element non-formation surface side of the substrate 7, and the stiffener 17, the substrate 7 and the resin 6 are ground until the thickness of the substrate 7 becomes about 10 μm (step C4; FIG. 10D). reference).

次に、基板７乃至薄膜受動素子４に下穴を形成し、下穴内に導体を充填し、貫通ビア８を形成する（ステップＣ５）。なお、下穴の形成では、例えば、レジストマスクを形成して、ＩＣＰエッチング装置で、反応性ガスとしてＳＦ６、ＣＨＦ３、Ｏ２の混合ガスを用いてφ５０μｍの下穴を形成することができる。Next, a pilot hole is formed in the substrate 7 to the thin film passive element 4, a conductor is filled in the pilot hole, and a through via 8 is formed (step C5). In forming the pilot hole, for example, a resist mask can be formed, and an ICP etching apparatus can form a pilot hole of φ50 μm using a mixed gas of SF 6 , CHF 3 , and O 2 as a reactive gas. .

次に、実施例１のステップＡ６と同様に、貫通ビア８と対応する位置にＬＳＩ接続パッド９を形成する（ステップＣ６；図１０（Ｅ）参照）。   Next, as in step A6 of the first embodiment, an LSI connection pad 9 is formed at a position corresponding to the through via 8 (step C6; see FIG. 10E).

以上により、図８と同様な受動素子内蔵基板が完成する。実施例２においても、この後、図１の受動素子内蔵基板のＬＳＩ接続パッド９上に電極として無電解めっきでパッド側からＮｉおよびＡｕをそれぞれ３μｍ、０．０５μｍの厚みで成膜し、その後、Ｓｎ−Ａｇ−Ｃｕ半田を用いてＬＳＩ接続パッド９上の電極にＬＳＩを接続することになる。これにより、図２と同様な受動素子チップを内蔵した場合、キャパシタが正常に動作していることを確認した。   Thus, a passive element built-in substrate similar to that shown in FIG. 8 is completed. Also in Example 2, thereafter, Ni and Au were formed in thickness of 3 μm and 0.05 μm from the pad side by electroless plating as an electrode on the LSI connection pad 9 of the passive element built-in substrate of FIG. Then, the LSI is connected to the electrode on the LSI connection pad 9 using Sn—Ag—Cu solder. As a result, it was confirmed that the capacitor was operating normally when a passive element chip similar to that shown in FIG. 2 was incorporated.

なお、スティフナー１７の実装基板１に接着する工程は、薄膜受動素子４を実装基板１に接合する工程の前後いずれでもよい。   The step of adhering the stiffener 17 to the mounting substrate 1 may be either before or after the step of bonding the thin film passive element 4 to the mounting substrate 1.

実施例２によれば、実施例１と同様な効果を奏するとともに、以下の効果を奏する。
実施例２に係る受動素子内蔵基板の第１の効果は、スティフナー１７を設けることにより、実装基板１の変形を抑制することが可能となり、ＬＳＩ実装時の歩留向上や信頼性が向上する利点がある。According to the second embodiment, the same effects as in the first embodiment and the following effects can be obtained.
The first effect of the substrate with built-in passive elements according to the second embodiment is that by providing the stiffener 17, it is possible to suppress the deformation of the mounting substrate 1, and the advantage that the yield is improved and the reliability is improved when the LSI is mounted. There is.

実施例２に係る受動素子内蔵基板の第２の効果は、スティフナー１７により補強されるので、実施例１よりも受動素子内蔵基板の厚さを小さくすることができ、薄膜受動素子４とＬＳＩあるいは半導体パッケージとの距離をさらに小さくできるため、より低インダクタンスで薄膜受動素子４とＬＳＩあるいは半導体パッケージ間を接続できる点にある。   Since the second effect of the substrate with built-in passive element according to the second embodiment is reinforced by the stiffener 17, the thickness of the substrate with built-in passive element can be made smaller than that of the first embodiment, and the thin film passive element 4 and the LSI or Since the distance from the semiconductor package can be further reduced, the thin film passive element 4 and the LSI or the semiconductor package can be connected with lower inductance.

本発明の実施例３に係る受動素子内蔵基板について図面を用いて説明する。図１１は、本発明の実施例３に係る受動素子内蔵基板の構成を模式的に示した断面図である。   A passive element built-in substrate according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 11 is a cross-sectional view schematically showing a configuration of a passive element built-in substrate according to Embodiment 3 of the present invention.

実施例３に係る受動素子内蔵基板では、実装基板１にあらかじめキャビティー１８を形成し、キャビティー１８内に薄膜受動素子チップ（薄膜受動素子４乃至基板７）の端子電極３に対応した接続パッド２を設け、薄膜受動素子チップを接続し、キャビティー１８内を樹脂６で封止している。その他の構成は、実施例１と同様である。この構造では樹脂６の量を少なくすることができるため、実装基板１の反りを低減することできる。また、キャビティー１８が存在することで、ワニスを流し込み、硬化させることにより樹脂６を形成できるので、樹脂形成工程が容易になる利点がある。また、受動素子内蔵基板の薄型化がより有利となる。   In the passive element built-in substrate according to the third embodiment, the cavity 18 is formed in the mounting substrate 1 in advance, and the connection pad corresponding to the terminal electrode 3 of the thin film passive element chip (the thin film passive element 4 to the substrate 7) is formed in the cavity 18. 2, a thin film passive element chip is connected, and the inside of the cavity 18 is sealed with resin 6. Other configurations are the same as those of the first embodiment. In this structure, since the amount of the resin 6 can be reduced, the warpage of the mounting substrate 1 can be reduced. Further, since the cavity 18 is present, the resin 6 can be formed by pouring and curing the varnish, so that there is an advantage that the resin forming process is facilitated. Further, it is more advantageous to reduce the thickness of the passive element built-in substrate.

次に、本発明の実施例３に係る受動素子内蔵基板の製造方法について図面を用いて説明する。図１２は、本発明の実施例３に係る受動素子内蔵基板の製造方法を模式的に示した工程断面図である。図１３は、本発明の実施例３に係る受動素子内蔵基板の製造方法における樹脂形成工程後の構成の変形例を模式的に示した断面図である。   Next, a method for manufacturing a passive element-embedded substrate according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 12 is a process cross-sectional view schematically showing a method for manufacturing a substrate with a built-in passive element according to Embodiment 3 of the present invention. FIG. 13: is sectional drawing which showed typically the modification of the structure after the resin formation process in the manufacturing method of the board | substrate with a built-in passive element based on Example 3 of this invention.

まず、実施例１のステップＡ１（例えば、ステップＢ１〜Ｂ１１）と同様に、基板７上に複数の端子電極３を有する薄膜受動素子４を形成する（ステップＤ１；図１２（Ａ）参照）。   First, the thin-film passive element 4 having a plurality of terminal electrodes 3 is formed on the substrate 7 in the same manner as in Step A1 (for example, Steps B1 to B11) of Example 1 (Step D1; see FIG. 12A).

次に、基板７をチップ状に切断して受動素子チップを製造し、一方で、深さ１００μｍ程度のキャビティー１８と該キャビティー１８の底面に接続パッド２を形成した実装基板１を製造した後、キャビティー１８内にて受動素子チップを実装基板１に接合材５（例えばＳｎ−Ａｇ−Ｃｕ半田）で接続する（ステップＤ２；図１２（Ｂ）参照）。   Next, the substrate 7 was cut into chips to produce a passive element chip, while the mounting substrate 1 having a cavity 18 with a depth of about 100 μm and a connection pad 2 formed on the bottom surface of the cavity 18 was produced. Thereafter, the passive element chip is connected to the mounting substrate 1 with the bonding material 5 (for example, Sn—Ag—Cu solder) in the cavity 18 (step D2; see FIG. 12B).

次に、少なくともキャビティー１８内部に樹脂６を充填した後、キュアする（ステップＤ３；図１２（Ｃ）参照）。なお、樹脂６は、実装基板１の上部に形成してもよいし、図１３に示すようにアンダーフィル樹脂１９及びモールド樹脂２０にて薄膜受動素子チップ全体を覆うように形成してもよい。図１３の構造を経ることにより、研削加工時に薄膜受動素子チップにクラック等の不良発生頻度が減る利点がある。   Next, at least the cavity 18 is filled with the resin 6 and then cured (step D3; see FIG. 12C). The resin 6 may be formed on the mounting substrate 1 or may be formed so as to cover the entire thin film passive element chip with the underfill resin 19 and the mold resin 20 as shown in FIG. By passing through the structure of FIG. 13, there is an advantage that the frequency of occurrence of defects such as cracks in the thin film passive element chip during grinding is reduced.

次に、基板７の受動素子非形成面側から研削加工を行い、基板７の厚さが７μｍ程度になるまで、実装基板１、基板７および樹脂６を研削する（ステップＤ４；図１２（Ｄ）参照）。   Next, grinding is performed from the passive element non-formation surface side of the substrate 7, and the mounting substrate 1, the substrate 7 and the resin 6 are ground until the thickness of the substrate 7 becomes about 7 μm (step D4; FIG. 12D) )reference).

次に、基板７乃至薄膜受動素子４に下穴を形成し、下穴内に導体を充填し、貫通ビア８を形成する（ステップＤ５）。なお、下穴の形成では、例えば、レジストマスクを形成して、ＩＣＰエッチング装置で、反応性ガスとしてＳＦ６、ＣＨＦ３、Ｏ２の混合ガスを用いてφ５０μｍの下穴を形成することができる。Next, a pilot hole is formed in the substrate 7 to the thin film passive element 4, a conductor is filled in the pilot hole, and a through via 8 is formed (step D5). In forming the pilot hole, for example, a resist mask can be formed, and an ICP etching apparatus can form a pilot hole of φ50 μm using a mixed gas of SF 6 , CHF 3 , and O 2 as a reactive gas. .

次に、実施例１のステップＡ６と同様に、貫通ビア８と対応する位置にＬＳＩ接続パッド９を形成する（ステップＤ６；図１２（Ｅ）参照）。   Next, as in step A6 of the first embodiment, an LSI connection pad 9 is formed at a position corresponding to the through via 8 (step D6; see FIG. 12E).

以上により、図１１と同様な受動素子内蔵基板が完成する。実施例３においても、この後、図１の受動素子内蔵基板のＬＳＩ接続パッド９上に電極として無電解めっきでパッド側からＮｉおよびＡｕをそれぞれ３μｍ、０．０５μｍの厚みで成膜し、その後、Ｓｎ−Ａｇ−Ｃｕ半田を用いてＬＳＩ接続パッド９上の電極にＬＳＩを接続することになる。これにより、図２と同様な受動素子チップを内蔵した場合、キャパシタが正常に動作していることを確認した。   Thus, a passive element built-in substrate similar to that shown in FIG. 11 is completed. Also in Example 3, thereafter, Ni and Au were formed on the LSI connection pad 9 of the passive element built-in substrate of FIG. 1 as electrodes by electroless plating from the pad side to a thickness of 3 μm and 0.05 μm, respectively. Then, the LSI is connected to the electrode on the LSI connection pad 9 using Sn—Ag—Cu solder. As a result, it was confirmed that the capacitor was operating normally when a passive element chip similar to that shown in FIG. 2 was incorporated.

実施例３によれば、実施例１と同様な効果を奏するとともに、以下の効果を奏する。   According to the third embodiment, the same effects as in the first embodiment and the following effects can be achieved.

実施例３に係る受動素子内蔵基板の第１の効果は、実装基板１のキャビティー１８内にのみ樹脂６を形成している構造とすることにより、樹脂６の形成が容易になり、より低コスト化が可能な点にある。   The first effect of the passive element built-in substrate according to the third embodiment is that the resin 6 is formed only in the cavity 18 of the mounting substrate 1, thereby facilitating the formation of the resin 6. Cost is possible.

実施例３に係る受動素子内蔵基板の第２の効果は、キャビティー１８内に薄膜受動素子チップが内蔵される構造となることで、受動素子内蔵基板をより薄くできる効果がある。
本発明の全開示（請求の範囲を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。The second effect of the substrate with built-in passive element according to the third embodiment is that the thin film passive element chip is built in the cavity 18, so that the substrate with built-in passive element can be made thinner.
Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (14)

複数の第１接続パッドが形成された実装基板と、
基板に受動素子が形成されるとともに、前記第１接続パッドに対向する前記受動素子側の面に前記第１接続パッドに対応した端子電極が形成され、かつ、前記端子電極が前記第１接続パッドに接合された受動素子チップと、
前記受動素子チップと前記実装基板の間に充填されるとともに、前記受動素子チップの外周部に配された部分の上面が前記基板の上面と一致するように形成された樹脂と、
前記基板の上面に半導体素子又は半導体パッケージの端子に対応して形成された第２接続パッドと、
前記受動素子チップ内にて対応する前記第２接続パッドと前記端子電極とを電気的に接続するように形成された貫通ビアと、
を備えることを特徴とする受動素子内蔵基板。A mounting substrate on which a plurality of first connection pads are formed;
A passive element is formed on the substrate, a terminal electrode corresponding to the first connection pad is formed on the surface of the passive element facing the first connection pad, and the terminal electrode is the first connection pad. A passive element chip bonded to the
Filled between the passive element chip and the mounting substrate, and a resin formed such that the upper surface of the portion disposed on the outer peripheral portion of the passive element chip coincides with the upper surface of the substrate;
A second connection pad formed on the upper surface of the substrate corresponding to the terminal of the semiconductor element or semiconductor package;
A through via formed to electrically connect the corresponding second connection pad and the terminal electrode in the passive element chip;
A substrate with a built-in passive element, comprising: 前記基板の厚さは、１５μｍ以下であることを特徴とする請求項１記載の受動素子内蔵基板。   The passive element built-in substrate according to claim 1, wherein the thickness of the substrate is 15 μm or less. 前記樹脂は、前記実装基板の前記受動素子チップ側の面のうち前記受動素子チップ搭載領域以外の全面にも形成されていることを特徴とする請求項１又は２記載の受動素子内蔵基板。   3. The passive element-embedded substrate according to claim 1, wherein the resin is also formed on the entire surface of the mounting substrate on the passive element chip side other than the passive element chip mounting region. 4. 前記実装基板の前記受動素子チップ側の面のうち前記受動素子チップの外周に配設されたスティフナーを備え、
前記樹脂は、前記実装基板の前記受動素子チップ側の面のうち、前記スティフナーと前記受動素子チップの間と、前記スティフナーの外周にも形成され、
前記スティフナーの上面は、前記樹脂の上面とともに、前記基板の上面と一致するように形成されていることを特徴とする請求項１又は２記載の受動素子内蔵基板。A stiffener disposed on an outer periphery of the passive element chip of the surface of the mounting substrate on the passive element chip side;
The resin is also formed between the stiffener and the passive element chip on the surface of the mounting substrate on the passive element chip side, and also on the outer periphery of the stiffener.
3. The passive element built-in substrate according to claim 1, wherein the upper surface of the stiffener is formed so as to coincide with the upper surface of the substrate together with the upper surface of the resin. 前記実装基板は、上部にキャビティーが形成され、
前記接続パッドは、前記キャビティーの底面に形成され、
前記樹脂は、前記実装基板の前記受動素子チップ側の面のうち、前記キャビティーの側壁面と前記受動素子チップの間にも形成され、
前記実装基板の前記キャビティー以外の上面は、前記樹脂の上面とともに、前記基板の上面と一致するように形成されていることを特徴とする請求項１又は２記載の受動素子内蔵基板。The mounting substrate has a cavity formed on the top,
The connection pad is formed on the bottom surface of the cavity,
The resin is also formed between the side wall surface of the cavity and the passive element chip among the surface of the mounting substrate on the passive element chip side,
The passive element built-in substrate according to claim 1, wherein an upper surface of the mounting substrate other than the cavity is formed so as to coincide with an upper surface of the substrate together with the upper surface of the resin. 前記基板は、ガラス又はセラミックからなることを特徴とする請求項１乃至５のいずれか一に記載の受動素子内蔵基板。   The passive element built-in substrate according to claim 1, wherein the substrate is made of glass or ceramic. 前記基板は、シリコンからなり、
前記貫通ビアと前記基板の界面には、絶縁膜が形成されていることを特徴とする請求項１乃至５のいずれか一に記載の受動素子内蔵基板。The substrate is made of silicon;
6. The passive element built-in substrate according to claim 1, wherein an insulating film is formed at an interface between the through via and the substrate. 前記受動素子は、前記貫通ビアのうち第１貫通ビアと接続された第１電極と、前記貫通ビアのうち第２貫通ビアと接続された第２電極と、前記第１電極と前記第２電極の間に配された誘電体と、からなるキャパシタを含むことを特徴とする請求項１乃至７のいずれか一に記載の受動素子内蔵基板。   The passive element includes a first electrode connected to the first through via among the through vias, a second electrode connected to the second through via among the through vias, the first electrode, and the second electrode. A passive element-embedded substrate according to any one of claims 1 to 7, further comprising a capacitor including a dielectric disposed between the two. 前記誘電体は、ペロブスカイト型酸化物からなることを特徴とする請求項８記載の受動素子内蔵基板。   9. The passive element-embedded substrate according to claim 8, wherein the dielectric is made of a perovskite oxide. 請求項１乃至９のいずれか一に記載の受動素子内蔵基板と、
前記受動素子内蔵基板上に搭載された半導体素子又は半導体パッケージと、
を備えることを特徴とする半導体装置。A passive element built-in substrate according to any one of claims 1 to 9,
A semiconductor element or a semiconductor package mounted on the passive element built-in substrate;
A semiconductor device comprising: 基板上に受動素子を形成し前記受動素子上に端子電極を形成する工程と、
前記基板を切断し受動素子チップを形成する工程と、
前記受動素子チップの前記端子電極と実装基板上の接続パッドとを接合する工程と、
前記実装基板上に前記受動素子チップの前記基板と前記受動素子の界面よりも高くなるように樹脂で封止する工程と、
前記基板の厚さが１５μｍ以下になるまで前記基板及び前記樹脂を研削する工程と、
前記受動素子チップ内に前記端子電極に通ずる下穴を形成する工程と、
を含むことを特徴とする受動素子内蔵基板の製造方法。Forming a passive element on the substrate and forming a terminal electrode on the passive element;
Cutting the substrate to form a passive element chip;
Bonding the terminal electrode of the passive element chip and a connection pad on a mounting substrate;
Sealing with a resin on the mounting substrate so as to be higher than the interface between the substrate and the passive element of the passive element chip;
Grinding the substrate and the resin until the thickness of the substrate is 15 μm or less;
Forming a pilot hole communicating with the terminal electrode in the passive element chip;
The manufacturing method of the board | substrate with a built-in passive element characterized by including this. 前記樹脂で封止する工程では、前記実装基板の前記受動素子チップ側の面のうち前記受動素子チップ搭載領域以外の全面にも前記樹脂を形成することを特徴とする請求項１１記載の受動素子内蔵基板の製造方法。   12. The passive element according to claim 11, wherein, in the step of sealing with the resin, the resin is formed on the entire surface of the mounting substrate on the passive element chip side other than the passive element chip mounting region. A method for manufacturing a built-in substrate. 前記樹脂で封止する工程の前であって、前記端子電極と前記接続パッドとを接合する工程の前又は後に、スティフナーを前記実装基板に接着する工程を含み、
前記樹脂で封止する工程では、前記実装基板の前記受動素子チップ側の面のうち、前記スティフナーと前記受動素子チップの間と、前記スティフナーの外周にも前記樹脂を形成し、
前記基板及び前記樹脂を研削する工程では、前記スティフナーも研削することを特徴とする請求項１１記載の受動素子内蔵基板の製造方法。Before the step of sealing with the resin, before or after the step of bonding the terminal electrode and the connection pad, including the step of adhering a stiffener to the mounting substrate,
In the step of sealing with the resin, the resin is formed on the surface of the mounting substrate on the passive element chip side, between the stiffener and the passive element chip, and on the outer periphery of the stiffener,
The method for manufacturing a substrate with built-in passive elements according to claim 11, wherein the stiffener is also ground in the step of grinding the substrate and the resin. 前記端子電極と前記接続パッドとを接合する工程の前に、前記実装基板にキャビティーを形成し、前記キャビティーの底面に前記接続パッドを形成する工程を含み、
前記樹脂で封止する工程では、前記実装基板の前記受動素子チップ側の面のうち、前記キャビティーの側壁面と前記受動素子チップの間にも前記樹脂を形成し、
前記基板及び前記樹脂を研削する工程では、前記実装基板の前記キャビティー以外の上面も研削することを特徴とする請求項１１記載の受動素子内蔵基板の製造方法。Before the step of bonding the terminal electrode and the connection pad, including the step of forming a cavity in the mounting substrate, and forming the connection pad on the bottom surface of the cavity;
In the step of sealing with the resin, among the surface of the mounting substrate on the passive element chip side, the resin is also formed between the side wall surface of the cavity and the passive element chip,
The method for manufacturing a substrate with built-in passive elements according to claim 11, wherein in the step of grinding the substrate and the resin, an upper surface of the mounting substrate other than the cavity is also ground.
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