JP5333435B2 - Capacitor with through electrode, method for manufacturing the same, and semiconductor device - Google Patents

Abstract

Provided are a capacitor which has a through electrode, suppresses manufacture failure and has a high degree of freedom in manufacturing process, a method for manufacturing such capacitor, and a semiconductor device. The capacitor is provided with a substrate (2) having a plurality of through holes (4); through electrodes (7) applied in the through holes (4); an insulating cover film (8) formed on a first main surface (2A) of the substrate (2); a capacitor structure (13) formed on the insulating cover film (8); a protection insulating film (14) covering the capacitor structure (13); and a plurality of connecting pads (15), which are electrically connected with at least a part of the capacitor structure (13) through capacitor connecting vias (20, 21) that penetrate the protection insulating film (14) and are also electrically connected with the corresponding through electrodes (7) through a through electrode connecting via (9) which penetrates the protection insulating film (14) and the insulating cover film (8).

Description

  The present invention relates to a capacitor with a through electrode and a method for manufacturing the same. The present invention also relates to a semiconductor device on which the capacitor with the through electrode is mounted.

  As countermeasures against switching noise in LSI (Large Scale Integration), research and development have been conducted on a semiconductor package having a structure in which an interposer type capacitor as a decoupling capacitor is connected immediately below a semiconductor chip and its mounting structure.

In general, when an abrupt load (current) i due to a clock operation is applied to an LSI, a voltage drop ΔV represented by the following equation (1) is generated by a resistance R and an inductance L existing in a power supply and wiring between LSIs.
ΔV = R × i−L × (di / dt) (1)
The decoupling capacitor is connected in parallel between the power supply line connected to the LSI and the ground line in order to reduce the voltage drop ΔV.

  However, the voltage drop ΔV represented by the above formula (1) also occurs due to the influence of the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the decoupling capacitor. The voltage drop ΔV is also caused by the influence of the wiring resistance R1 and the wiring inductance L1 from the decoupling capacitor to the LSI.

  In recent years, the clock frequency has reached the order of GHz, and the inductance L1 due to the wiring between the decoupling capacitor and the LSI cannot be ignored. In order to cope with this, an interposer type capacitor capable of reducing the wiring inductance L1 as much as possible has been developed. Such interposer type capacitors are disclosed in, for example, Patent Documents 1 to 6. As an example, FIG. 9 shows a schematic structure of a chip carrier type capacitor disclosed in Patent Document 1.

  As shown in FIG. 9, the chip carrier type capacitor 100 includes a substrate 102 in which a through electrode 101 is formed in each via. A capacitor structure 106 including a lower electrode 103, a dielectric 104 and an upper electrode 105 is formed on the substrate 102. Such a configuration is manufactured by forming the capacitor structure 106 on the substrate 102 on which the through electrode 101 is previously formed.

Patent Document 7 will be described later.
JP 2002-8942 A JP 2005-33195 A JP 2001-338836 A JP 2006-253631 A JP-A-2005-123250 Japanese Patent No. 3465464 JP 2004-123250 A

  However, the method of forming the through electrode 101 on the substrate 102 and subsequently forming the capacitor structure 106 as in Patent Document 1 has the following problems. That is, there is a problem in that manufacturing defects are likely to occur due to the heat treatment of the substrate 102 performed during the formation process of the capacitor structure 106.

  On the other hand, a method of forming a through electrode separately after forming the capacitor structure on the substrate is also conceivable. However, in that case, there is a problem that the manufacturing process of the through electrode is limited due to the existence of the capacitor structure. For example, when the through electrode is formed, a crack is generated in the substrate, and the crack may progress to the capacitor structure and become defective. Further, when the through hole is provided in the substrate, the process is limited to a process in which the capacitor structure is not etched.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a capacitor with a through electrode that suppresses manufacturing defects and has a high degree of freedom in manufacturing processes, a manufacturing method thereof, and a semiconductor device. Is to provide.

A capacitor with a through electrode according to the present invention includes a substrate having a plurality of through holes, a through electrode made of a conductor filled in each of the through holes, and an inorganic formed on the first main surface of the substrate. An insulating cover film made of an insulator, a plurality of capacitor structures formed on the insulating cover film and made of a lower electrode, a dielectric, and an upper electrode, a protective insulating film covering the capacitor structure, and the capacitor at least a portion of the structure, the insulation layer is electrically connected through a capacitor connecting vias through and a corresponding said through electrodes, said through said protective insulating film and the insulating cover layer And a plurality of connection pads electrically connected through through-electrode connecting vias having a smaller diameter than the through-electrode . At least one of the connection pads is electrically connected to the upper electrode through the capacitor connection via, and at least one of the connection pads not electrically connected to the upper electrode is , And electrically connected to the lower electrode through the capacitor connecting via.

  A semiconductor device according to the first aspect of the present invention is one in which the capacitor with a through electrode is mounted.

The semiconductor device according to the second aspect of the present invention includes a capacitor with a through electrode that is disposed between the first component and the second component and electrically connects them, and the capacitor with the through electrode includes a plurality of capacitors. A substrate having a through hole, a through electrode made of a conductor filled in each of the through holes, an insulating cover film made of an inorganic insulator formed on the substrate, and an upper surface of the insulating cover film A plurality of capacitor structures formed of a lower electrode, a dielectric, and an upper electrode; a protective insulating film covering the capacitor structure; at least a part of the capacitor structure; and a capacitor connection penetrating the protective insulating film are electrically connected through via, and a corresponding said through electrode, for the protective insulating film and the made of smaller diameter than the penetrating electrode penetrating the insulating cover layer through electrodes connected Those having a plurality of connection pads that are electrically connected via the A. At least one of the connection pads is electrically connected to the upper electrode via the capacitor connection via, and is at least one of the connection pads not electrically connected to the upper electrode. Are electrically connected to the lower electrode through the capacitor connection via, the first component is a semiconductor element, and the second component is a semiconductor element or a mounting substrate.

In the method of manufacturing a capacitor with a through electrode according to the present invention, a plurality of through holes are formed in a substrate, a conductor is filled in each of the through holes to form a plurality of through electrodes, and the first main body of the substrate is formed. An insulating cover film made of an inorganic insulator is formed on the surface, and a lower electrode layer, a dielectric layer, and an upper electrode layer are laminated on the insulating cover film in this order, and the lower electrode layer and the dielectric After forming the pattern of the layer and the upper electrode layer, a protective insulating film is formed so as to cover the first main surface, and the via that penetrates from the surface of the protective insulating film to the surface of the upper electrode layer, the lower part Vias penetrating to the surface of the electrode layer and vias having a smaller diameter than the penetrating electrode penetrating to the surface of the through electrode are formed, and a plurality of connection pads are formed on the protective insulating film.

  According to the present invention, it is possible to provide a capacitor with a through electrode, a manufacturing method thereof, and a semiconductor device that can suppress manufacturing defects and have a high degree of freedom in manufacturing processes.

It is a typical sectional view of a capacitor with a penetration electrode concerning a form for carrying out the present invention. It is typical sectional drawing which shows an example of the semiconductor device for implementing this invention. 1 is a schematic cross-sectional view of a capacitor with a through electrode according to a first embodiment of the present invention. It is a schematic sectional drawing in alignment with the II-II line of FIG. It is a schematic plan view which shows the structure of the capacitor with a penetration electrode by 1st Embodiment of this invention. It is a schematic side view which shows a structure when a back surface pad and cover resin are provided in the capacitor with a penetration electrode by 1st Embodiment of this invention of FIG. It is a schematic sectional drawing of a semiconductor device when mounting the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a manufacturing process sectional view of the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a manufacturing process sectional view of the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a manufacturing process sectional view of the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a manufacturing process sectional view of the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a manufacturing process sectional view of the capacitor with a penetration electrode by a 1st embodiment of the present invention. It is a schematic side view which shows a structure when a back surface pad and cover resin are provided in the capacitor with a penetration electrode by 2nd Embodiment of this invention. It is manufacturing process sectional drawing of the capacitor with a penetration electrode by 2nd Embodiment of this invention. It is manufacturing process sectional drawing of the capacitor with a penetration electrode by 2nd Embodiment of this invention. It is manufacturing process sectional drawing of the capacitor with a penetration electrode by 2nd Embodiment of this invention. It is manufacturing process sectional drawing of the capacitor with a penetration electrode by 2nd Embodiment of this invention. It is manufacturing process sectional drawing of the capacitor with a penetration electrode by 2nd Embodiment of this invention. 6 is a partial cross-sectional view showing a schematic structure of a chip carrier type capacitor described in Patent Document 1. FIG.

Explanation of symbols

1 Capacitor with Through Electrode 2 Substrate 3 Surface Insulating Film (First Insulating Film)
4 Through-hole 5 Side wall insulating film (first insulating film)
6 Back surface insulating film 7 Through electrode 8 Insulating cover film (second insulating film)
9 Via 10 Lower electrode 11 Dielectric 12 Upper electrode 13 Capacitor structure 14 Protective insulating film 16 Lower electrode connection pad 17 Upper electrode connection pad 18 No capacitor connection pad 20 Lower electrode connection via 21 Upper electrode connection via 23 Back pad 24 Cover resin 25 Mounting substrate 26 Semiconductor element 31 Capacitor 32 with through electrode Substrate 33 Surface insulating film 50 Semiconductor device

  FIG. 1A is a schematic cross-sectional view of a capacitor with a through electrode according to an embodiment for carrying out the present invention. As shown in FIG. 1A, the capacitor with a through electrode 1a includes an interposer substrate (hereinafter abbreviated as “substrate”) 2a having a plurality of through holes 4a. Each through hole 4a is filled with a through electrode 7a made of a conductor. An insulating cover film 8a, a capacitor structure 13a, a protective insulating film 14a, a connection pad 15a, and the like are formed on the first main surface 2A of the substrate 2a.

  The capacitor structure 13a includes a lower electrode 10a, a dielectric 11a, and an upper electrode 12a, and is formed on the insulating cover film 8a. The protective insulating film 14a is formed so as to cover the capacitor structure 13a. The connection pad 15a is electrically connected to at least a part of the capacitor structure 13a via a capacitor connection via 20a penetrating the protective insulating film 14a. Furthermore, the connection pad 15a is electrically connected to the corresponding through electrode 7a through a through electrode connecting via 9a that penetrates the protective insulating film 14a and the insulating cover film 8a.

  At least one of the connection pads 15a is electrically connected to the upper electrode 12a through the capacitor connection via 20a. Further, at least one of the connection pads 15a not electrically connected to the upper electrode 12a is electrically connected to the lower electrode 10a through the capacitor connecting via 20a.

  The capacitor 1a with a through electrode is mounted on a semiconductor device and used as an interposer type capacitor. As an example of such a semiconductor device, FIG. 1B shows a schematic cross-sectional view of a semiconductor device according to an embodiment for carrying out the present invention.

  As shown in FIG. 1B, the semiconductor device 50a includes a capacitor 1a with a through electrode, a semiconductor element (semiconductor chip) 26a that is a first component, and a mounting substrate 25a that is a second component. The through-electrode capacitor 1a is mounted on the mounting substrate 25a on the second main surface 2B (see FIG. 1A) side opposite to the first main surface 2A (see FIG. 1A) on which the capacitor structure 13 is formed. . Further, on the first main surface 2A side, the semiconductor element 26a is electrically and physically connected. The second component may be mounted on a semiconductor element instead of the mounting substrate. That is, you may arrange | position the capacitor | condenser 1a with a penetration electrode between semiconductor elements. Further, the first component and the second component do not need to be one each, and a plurality of first components and / or second components may be connected to one through-electrode capacitor 1a. Good. Furthermore, the first component and the second component may be replaced with other components other than the semiconductor element and the mounting substrate without departing from the spirit of the present invention. Further, as shown in FIG. 1B, in addition to the mode of being arranged between the first component and the second component, it may be built in the mounting board.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

[First Embodiment]
FIG. 2 shows a cross-sectional view of a cut portion of the capacitor 1 with a through electrode according to the first embodiment of the present invention. The capacitor 1 with a through electrode includes an interposer substrate (hereinafter abbreviated as “substrate”) 2 having a plurality of through holes 4. Each of the through holes 4 is filled with a through electrode 7 made of a conductor. On the first main surface 2A of the substrate 2, an insulating cover film 8, a capacitor structure 13, a protective insulating film 14, a connection pad 15 and the like are formed.

  Regarding the material of the substrate 2, in the first embodiment, an example in which a semiconductor substrate is applied will be described. The material of the semiconductor substrate may be a compound semiconductor or the like, and is not particularly limited, but a single crystal of silicon (Si) or gallium arsenide (GaAs) is suitable. Among these, Si is suitable because it is excellent in workability. The size of the substrate 2 is not limited, but is preferably substantially equal to the size of the semiconductor chip to be connected. The thickness of the substrate 2 is preferably set to a thickness that can withstand handling during mounting. A preferable thickness of the substrate 2 is, for example, 100 μm to 400 μm. The size of the through hole 4 is not limited, but it is preferable that the resistance value after the conductor is filled is sufficiently small. From this viewpoint, it is preferable to set the diameter to about several μm to several tens of μm.

  The entire sidewall surface of each through hole 4 is covered with a sidewall insulating film (first insulating film) 5. The entire first main surface 2 </ b> A side of the substrate 2 is covered with a surface insulating film (first insulating film) 3. On the other hand, the second main surface 2B side opposite to the first main surface 2A of the substrate 2 is entirely covered with a back surface insulating film (first insulating film) 6.

  The inside of each through hole 4 is filled with a conductor. This conductor is penetrated in the thickness direction of the substrate 2 and functions as the through electrode 7. Here, each through electrode 7 is also filled in a pattern opening formed in the surface insulating film 3 formed on the main surface of the substrate 2 and the back surface insulating film 6 formed on the second main surface 2B of the substrate 2. ing.

The materials of the surface insulating film 3, the sidewall insulating film 5, and the back surface insulating film 6 are not particularly limited, but silicon oxide (SiO), silicon nitride (SiN _x ), silicon oxynitride (SiNO), aluminum oxide (Al ₂ O _3). Etc.) are preferred. The thicknesses of the surface insulating film 3, the side wall insulating film 5, and the back surface insulating film 6 are not particularly limited, but are preferably set to such a degree that insulation can be ensured, that is, about 0.1 to 5 μm. When Si is used for the substrate 2, the surface insulating film 3, the side wall insulating film 5, and the back surface insulating film 6 can be simultaneously formed by a thermal oxidation method.

  The conductor filled in the through hole 4 is not particularly limited, but a plated metal is preferable from the viewpoint of low electrical resistance, and copper (Cu) is particularly preferably used. Each through electrode 7 is formed by completely filling the inside of each through hole 4 with a metal such as copper. The surface of each through electrode 7 may be flush with the surface of the surface insulating film 3 by polishing by an electromechanical polishing (Chemical Mechanical Polishing, CMP) method. The same applies to the back surface insulating film 6 formed on the second main surface 2B of the substrate 2.

  The surface insulating film 3 and the through electrode 7 exposed on the first main surface 2A side of the substrate 2 are covered with an insulating cover film (second insulating film) 8. In the insulating cover film 8, a through electrode connecting via 9 having a diameter smaller than the diameter of the through electrode 7 is formed at a position directly above each through electrode 7.

  The material of the insulating cover film 8 is not limited, but silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and the like are preferable. The thickness of the insulating cover film 8 is not limited, but is preferably about 1 μm to 5 μm.

  The capacitor structure 13 is formed on the insulating cover film 8. The capacitor structure 13 has an MIM (metal-insulator-metal) configuration (three-layer configuration) including a lower electrode 10, a dielectric 11, and an upper electrode 12. The capacitor structure 13 may be provided as a single cell on the entire surface of the substrate 2 or may be divided into a plurality of cells.

  A dish-like depression is formed at a position directly above each through electrode 7. A semiconductor element bonding pad 15 is formed in each of these recesses. Each semiconductor element bonding pad 15 has a shape fitted in a corresponding recess.

  The material of the lower electrode 10 is not particularly limited, but a metal or an alloy that has excellent adhesion to the base substrate and little diffusion to the thin film dielectric 11 is desirable. For example, from the insulating cover film 8 side, active metals such as titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), platinum (Pt), ruthenium (Ru), titanium nitride (TiN), A film formed of a high barrier metal such as gold (Au) in this order is suitable. The active metal is suitable as an adhesion layer with the lower layer film of the lower electrode 10.

Tungsten (W), molybdenum (Mo), iron (Fe), nickel (Ni) and cobalt (Co) between the adhesion layer in contact with the substrate 2 side of the lower electrode 10 and the high barrier metal in contact with the dielectric 11 It is more preferable to sandwich a highly elastic metal film formed by any of the above.

  The material of the upper electrode 12 is not limited, but a material with little diffusion into the thin film dielectric 11 is desirable, and for example, Pt, Ru, TiN, and Au are suitable.

  A manufacturing method of the lower electrode 10 and the upper electrode 12 is not limited, but a sputtering method, a CVD (Chemical Vapor Deposition) method, a vapor deposition method, or a plating method is preferable.

The material of the dielectric 11 is not particularly limited as long as it is a highly insulating material. For example, tantalum oxide, aluminum oxide, silicon oxide, or the like can be applied. More preferably, it is a compound having a perovskite structure having a high dielectric constant. Examples of the compound having a perovskite structure include SrTiO ₃ and (Sr, Ba) TiO _{3 in} which a part of Sr in SrTiO ₃ is substituted with Ba. In addition, a composite perovskite compound in which the average valence of the A site is made divalent by substituting a part of the A site (Pb, Ba) with Sr, Ca, La, etc. using PbTiO ₃ or BaTiO ₃ as a skeleton, A composite perovskite compound in which a part of (Ti) is substituted with Mg, W, Nb, Zr, Ni, Zn or the like to make the average valence of the B site tetravalent is desirable.

  A method for manufacturing the dielectric 11 is not limited, but a sputtering method, a CVD method, or a sol-gel method is preferable.

  The protective insulating film 14 is formed so as to cover the exposed capacitor structure 13. However, the protective insulating film 14 is formed with an opening in a portion connected to each through electrode 7.

  The semiconductor element bonding pad 15 is formed so as to be fitted into a dish-shaped depression formed on each through electrode 7. In other words, the semiconductor element bonding pad 15 is in contact with the through electrode 7 at the bottom, and is in contact with the insulating cover film 8 and the protective insulating film 14 at the side surface.

  Three types of pads are formed in the semiconductor element bonding pad 15. That is, a pad (hereinafter referred to as “lower electrode connection pad”) 16 electrically connected to the lower electrode 10 of the capacitor structure 13 and a pad (hereinafter referred to as “upper electrode”) electrically connected to the upper electrode 12. There are a pad 17 (referred to as “electrode connection pad”) and a pad 18 (hereinafter referred to as “capacitor unconnected pad”) that is not electrically connected to the capacitor structure 13.

  The lower electrode connection pad 16 is electrically connected to the lower electrode 10 of the capacitor structure 13 via a capacitor connection via (hereinafter referred to as “lower electrode connection via”) 20 formed in the protective insulating film 14. It has been done. The upper electrode connection pad 17 is electrically connected to the upper electrode 12 of the capacitor structure 13 via a capacitor connection via (hereinafter referred to as “upper electrode connection via”) 21 formed in the protective insulating film 14. It has been done.

The material and thickness of the protective insulating film 14 are not particularly limited. Examples of suitable materials for the protective insulating film 14 include inorganic insulating films made of SiO ₂ and Si ₃ N ₄ and organic insulating films such as polyimide and epoxy resin.

  The material of the semiconductor element bonding pad 15 is not particularly limited, but is preferably a plated metal, and Cu is particularly suitable. An adhesion layer such as Ti may be provided on the Cu base. The thickness of the Cu plating film is not limited, but is preferably about 1 μm to 20 μm. When bonding to a semiconductor element, it is more preferable that the surface treatment is performed from the surface side with gold / nickel (Au / Ni), tin (Sn), or the like.

  Here, the lower electrode connection via 20 is formed integrally with the lower electrode connection pad 16. The upper electrode connection via 21 is formed integrally with the upper electrode connection pad 17.

  In FIG. 3, the top view of the capacitor 1 with a penetration electrode of the 1st embodiment is shown. In FIG. 3, the cross-sectional configuration along the line II-II corresponds to FIG. 2.

  In the first embodiment, the lower electrode connection pad 16 functions as a ground pad, the upper electrode connection pad 17 functions as a power supply pad, and the capacitor unconnected pad 18 functions as a signal pad. Of course, the lower electrode connection pad 16 may be a power supply pad and the upper electrode connection pad 17 may be a ground pad. Further, the lower electrode connection via 20 has a donut shape here, but is not limited to this shape, and the position and number thereof are not limited. Here, the upper electrode connection via 21 also has a triangular shape, but the shape, position, and number thereof are not limited. The shape of the semiconductor element bonding pad 15 is not limited to the illustrated one.

  In FIG. 4, a back pad 23 for mounting is formed on the second main surface 2B side of the capacitor 1 with the through electrode having the above-described configuration, and a cover resin (SR) is formed on each of the first main surface 2A and the second main surface 2B. ) 24 is a cross-sectional view of the state in which 24 is formed. In this state, the back surface pad 23 is formed on the second main surface 2B of the capacitor 1 with the through electrode at a position overlapping with each through electrode 7, and the other portions are covered with the cover resin 24. The first main surface 2A side of the capacitor 1 with through electrode is covered with a cover resin 24 so that an exposed surface is formed on each semiconductor element bonding pad 15.

  FIG. 5 is a schematic cross-sectional view showing an example of the semiconductor device 50 according to the first embodiment. The capacitor 1 with the through electrode is mounted on a mounting substrate 25 as shown in FIG. 5 with the back surface pad 23 and the cover resin 24. The mounting substrate 25 and the through-electrode capacitor 1 are electrically connected through the back surface pad 23. Similarly, the capacitor 1 with through electrode and the semiconductor element 26 are connected via the semiconductor element bonding pad 15. Thus, the through-electrode capacitor 1 can be used as a so-called interposer type capacitor. The capacitor 1 with a through electrode is a capacitor component particularly suitable for solder connection.

  The capacitor 1 with a through electrode according to the first embodiment described with reference to FIGS. 2 to 4 is easy to handle because the substrate 2 can be manufactured with a thickness that can be handled in the mounting process. Further, when a thermal change occurs, if there is no insulating cover film (second insulating film) 8, it penetrates from the first main surface 2 </ b> A of the substrate 2 due to a difference in thermal expansion between the substrate 2 and the through electrode 7. There arises a problem that the electrode 7 protrudes or is recessed, and the dielectric 11 of the capacitor structure 13 may be damaged. However, according to the capacitor 1 with the through electrode of the first embodiment, since the insulating cover film (second insulating film) 8 is provided, it penetrates on the side where the capacitor structure 13 is formed (upper side in FIG. 2). It is possible to suppress the electrode 7 from being deformed in the thickness direction of the substrate 2 (upward in FIG. 2). As a result, deterioration of the dielectric 11 of the capacitor structure 13 is prevented, and the highly reliable capacitor structure 13 can be realized.

(Manufacturing method of capacitor with through electrode)
Next, a method for manufacturing the above-described capacitor 1 with a through electrode will be described with reference to FIGS. 6A to 6E.

  First, after forming a plurality of through holes 4 in the substrate 2, a surface insulating film (first insulating film) 3 is formed on the first main surface 2 </ b> A of the substrate 2. As a result, the entire first main surface 2 </ b> A of the substrate 2 is covered with the surface insulating film 3. Further, a side wall insulating film (first insulating film) 5 is formed on the side wall of each through hole 4, and the entire side wall of the through hole 4 is covered with the side wall insulating film 5. Further, the back surface insulating film 6 is formed on the second main surface 2B of the substrate 2, and the entire back surface of the substrate 2 is covered with the side wall insulating film 5 (see FIG. 6A). In addition, when forming the surface insulating film 3, the side wall insulating film 5 and the back surface insulating film 6 may be formed simultaneously, or may be formed separately.

  Although the formation method of the through-hole 4 is not limited, Dry etching using an ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching) apparatus is preferably used. In particular, by using a “Bosch process” in which an etching gas and a sidewall protective film forming gas are alternately introduced, the through holes 4 can be formed with a high aspect ratio. A method for forming the surface insulating film 3, the sidewall insulating film 5, and the back surface insulating film 6 is not limited, but a CVD method is preferably used. When the substrate 2 is made of Si, a thermal oxidation method is preferably used.

  Next, a conductor is filled in each through hole 4 to form a through electrode 7. Here, the filling method of the conductor is not limited. For example, a plating method, a CVD method, a conductive paste filling method, or the like can be used. Of these, it is more preferable to use a plating method. This is because it is advantageous for forming the through electrode 7 having a low resistance such as Cu. Further, a barrier layer for preventing diffusion may be formed at the interface between the sidewall insulating film 5 and the through electrode 7 in the through hole 4. The material of the barrier layer is not limited, but titanium nitride, tantalum nitride, or the like is preferable. Each through electrode 7 is formed not only in the substrate 2 but also in the openings of the front surface insulating film 3 and the back surface insulating film 6.

  Next, an insulating cover film (second insulating film) 8 is formed on the surface insulating film 3 and on the upper end surface of the through electrode 7. That is, the insulating cover film 8 covers the entire upper surface of the surface insulating film 3 and the through electrode 7 (see FIG. 6B).

  Subsequently, the lower electrode 10, the dielectric 11, and the upper electrode 12 are stacked in this order on the insulating cover film 8 (see FIG. 6C). Here, in order to obtain the dielectric 11 having a high dielectric constant, it is necessary to heat the lower electrode 10, the dielectric 11, and the upper electrode 12 during or after film formation.

  Here, the method of forming the through electrode 101 on the substrate 102 and subsequently forming the capacitor structure 106 as in Patent Document 1 described above is manufactured by heat treatment of the substrate 102 performed during the formation process of the capacitor structure 106. There was a problem that defects were likely to occur. On the other hand, as described above, the method of separately forming the through electrode after forming the capacitor structure on the substrate has a problem that the manufacturing defect and the flexibility of the manufacturing process are reduced.

  According to the first embodiment, since the insulating cover film 8 is provided, the following effects can be obtained. That is, the direction of the capacitor structure 13 of the through electrode 7 caused by the difference in thermal expansion coefficient between the material of the substrate 2 and the material of the through electrode 7 during the heat treatment for forming the capacitor structure 13 (upward direction in FIG. 2). Expansion and contraction can be suppressed by the insulating cover film 8. As a result, it is possible to prevent the dielectric 11 of the capacitor structure 13 from being deteriorated due to the expansion and contraction of the through electrode 7 and to prevent the production failure. In addition, by making the lower electrode 10 a film configuration including a highly elastic metal film formed of any one of W, Mo, Fe, Ni, and Co, damage to the dielectric 11 due to thermal expansion of the through electrode 7 is further increased. Can be suppressed.

  Next, three layers of the lower electrode 10, the dielectric 11, and the upper electrode 12 are selectively removed by an etching method, and a recess is formed at a position overlapping with each through electrode 7. Thereafter, a protective insulating film 14 is formed on the three-layer capacitor structure 13 to cover the entire surface of the capacitor structure 13 (see FIG. 6D).

  Next, a plurality of through-electrode connecting vias 9 are formed by selectively removing the protective insulating film 14 and the insulating cover film 8 at positions overlapping with the respective through-electrodes 7. Further, the protective insulating film 14 is selectively removed at a position overlapping the lower electrode 10, and a lower electrode connection via 20 for connecting the lower electrode connection pad 16 to the lower electrode 10 is formed. Further, the protective insulating film 14 is selectively removed at a position overlapping with the upper electrode 12, and an upper electrode connection via 21 for connecting the upper electrode connection pad 17 to the upper electrode 12 is formed.

  Subsequently, a plurality of semiconductor element bonding pads 15 are formed at positions overlapping the respective depressions of the capacitor structure 13 on the protective insulating film 14 (see FIG. 6E). Thereby, the through electrode 7 and the semiconductor element bonding pad 15 are electrically connected. Through the above steps and the like, the through-electrode capacitor 1 shown in FIGS. 2 to 4 is completed.

  Thereafter, in order to be used between the semiconductor element 26 and the mounting substrate 25, a back surface pad 23 is formed on the second main surface 2B of the substrate 2 as shown in FIG. The cover resin 24 may be formed on the main surface 2A and the second main surface 2B.

  According to the capacitor 1 with the through electrode of the first embodiment of the present invention, the insulating cover film (second insulating film) 8 is formed on the first main surface 2A of the substrate 2. A capacitor structure 13 is formed on the insulating cover film 8. For this reason, even if the heating process for forming the capacitor structure 13 is performed, the penetration electrode 7 in the thickness direction of the substrate 2 caused by the difference in the thermal expansion coefficient between the material of the substrate 2 and the material of the penetration electrode 7. Expansion and contraction can be suppressed by the insulating cover film 8. As a result, it is possible to prevent the dielectric 11 of the capacitor structure 13 from being deteriorated due to the expansion and contraction of the through electrode 7 and to prevent the production failure.

  As described above, when the through electrode 7 is formed after the capacitor structure is formed on the substrate, a crack may occur in the substrate when the through electrode is formed, and the crack may progress to the capacitor structure and become defective. . Further, when the through electrode 7 is formed after the capacitor structure is formed on the substrate, when the through hole is provided in the substrate, the process is limited to a process in which the capacitor structure is not etched.

  Also, in both the method of forming the through electrode on the substrate first and the method of forming the through electrode on the substrate after forming the capacitor structure, the smaller the substrate thickness, the more the conductor is filled into the via (the through electrode). Formation) is easy. However, there is a problem that if the thickness of the substrate is reduced, handling in the manufacturing process becomes difficult and the substrate may be damaged in the mounting process.

  According to the capacitor 1 with the through electrode of the first embodiment of the present invention, since the method of forming the capacitor structure on the substrate 2 on which the through electrode 7 is disposed is employed, the degree of freedom of the manufacturing process is high. Therefore, the through electrode 7 can be formed with a high degree of freedom. Further, it is not necessary to force the substrate 2 to be thin in order to facilitate the formation of the through electrode 7. Therefore, the through electrode 7 can be easily formed and is not easily damaged during handling in the manufacturing process or the mounting process.

  In addition, since the first main surface 2A of the substrate 2 is covered with the surface insulating film 3 and the insulating cover film 8 and the capacitor structure 13 is provided on the insulating cover film 8, the cost is low. That's it.

  By the way, if passive elements are formed inside the mounting board, the mounting cost of passive element parts can be reduced, and the package and module can be downsized. It is active. Patent Document 7 discloses a multilayer ceramic capacitor having connection pads on upper and lower surfaces that can be mounted inside a mounting substrate.

  However, Patent Document 7 has a problem that connection pads cannot be formed with a narrow pitch. This is because the via size cannot be reduced to a level that can be formed with a multilayer ceramic capacitor.

  On the other hand, according to the capacitor with a through electrode according to the first embodiment, these problems can be solved. That is, it is possible to form connection pads at a narrower pitch than that in Patent Document 7.

  Each of the semiconductor element connection pads 15 is electrically connected to the corresponding through electrode 7. At least one of the semiconductor elements 26 is electrically connected to the upper electrode 12, and at least one of the semiconductor element connection pads 15 that are not electrically connected to the upper electrode 12 is electrically connected to the lower electrode 10. Yes. Thereby, the capacitor 1 with a through electrode can be used as an interposer type capacitor.

  In the first embodiment, the example in which the surface insulating film 3 is provided has been described. However, as an aspect in which the insulating cover film 8 is provided immediately above the first main surface of the substrate 2 without providing the surface insulating film 3. Also good.

[Second Embodiment]
FIG. 7 shows a capacitor 31 with a through electrode according to the second embodiment of the present invention. In the second embodiment, portions common to the configuration of the drawings described in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  A significant difference from the first embodiment is that an interposer substrate (hereinafter abbreviated as a substrate) 32 is formed of an insulator. Although the material of the board | substrate 32 will not be limited if it is an insulator, For example, glass, a ceramic, an oxide single crystal etc. can be utilized. Crystallized glass and low-temperature fired ceramic (a composite of glass and ceramic) can also be used suitably.

  In the capacitor 31 with through electrode of the second embodiment, an insulating cover film (surface insulating film) 33 is formed on the first main surface 32A of the substrate 32 and the upper surface of the through electrode 7 exposed therefrom. In the first embodiment, the insulating film is composed of two insulating films, that is, the surface insulating film 3 and the insulating cover film 8, whereas in the second embodiment, one layer of the insulating cover film 33 is formed. An insulating film is used.

  Unlike the first embodiment, an insulating film is not provided on the side wall of each through hole 4. This is because the substrate 32 is formed of an insulator, so that the insulation between the through electrode 7 inside each through hole 4 and the substrate 32 is unnecessary.

  When the substrate 32 is formed of an insulator, an insulating film that covers the first main surface 32A of the substrate 32 is usually unnecessary from the viewpoint of insulation. However, like the capacitor 1 with the through electrode of the first embodiment described above, the insulating cover film 33 is used to suppress deformation of the through electrode 7 due to the difference in thermal expansion between the through electrode 7 and the substrate 32. be able to.

  When the substrate 32 is formed of crystallized glass, ceramic, low-temperature sintered ceramic, etc., when the capacitor structure 13 is formed of a thin film, the capacitor structure 13 is manufactured due to the unevenness of the first main surface 32A of the substrate 32. There is a problem that yield and reliability are lowered. On the other hand, in the second embodiment, since the entire first main surface 32A of the substrate 32 is covered with the insulating cover film 33, the unevenness on the surface of the substrate 32 is absorbed by the insulating cover film 33, The surface of the insulating cover film 33 becomes flat. As a result, the yield and reliability of the capacitor structure 13 are improved.

  The material of the through electrode 7 is not limited, but Cu is preferable when it is formed by plating. When the substrate 32 is formed of ceramic or low-temperature sintered ceramic, Cu, Ag (silver), an alloy containing Ag, or the like formed by simultaneous sintering is preferably used.

  The material of the insulating cover film 33 is not limited. Preferable examples include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and the like. When the substrate 32 is made of ceramic or low-temperature sintered ceramic, a material formed of spin-on-glass (SOG) is also suitable. When an insulator is used for the substrate 32, there is no need to form an insulating film on the side wall of each through hole 4, and there is an advantage that the configuration can be simplified accordingly.

(Manufacturing method of capacitor with through electrode)
Next, a manufacturing method of the capacitor 31 with the through electrode according to the second embodiment will be described with reference to FIGS. 8A to 8E. In the following, portions common to the configuration of FIG. 6 described in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  First, a plurality of through holes 4 are formed in a substrate 32 made of an insulator, and then a through electrode 7 is formed inside each through hole 4 (see FIG. 8A). The through hole 4 may be formed by an ICP-RIE method or an etching method using hydrofluoric acid using photosensitive crystallized glass. When the substrate 32 is made of ceramic or low-temperature sintered ceramic, it may be formed by processing a ceramic green sheet.

  Although the formation method of the penetration electrode 7 is not limited, the plating method is suitable. When ceramic or low-temperature sintered ceramic is used for the substrate 32, the through electrode 7 may be formed by simultaneous sintering of paste. Further, a barrier layer for preventing diffusion may be formed between the through hole 4 and the through electrode 7. The material of the barrier layer is not limited, but titanium nitride, tantalum nitride, or the like is preferable.

  Next, an insulating cover film 33 is formed on the surface of the substrate 32 and the upper end surface of the through electrode 7 above the through electrode 7. Thereby, the surface protection film 33 covers the entire upper end surface of the substrate 32 and the through electrode 7 (see FIG. 8B). A method for forming the insulating cover film 33 is not limited, but a CVD method or an SOG method is preferably used.

  Next, the lower electrode 10, the dielectric 11, and the upper electrode 12 are laminated in this order on the insulating cover film 33 and the upper end surface of the through electrode 7 (see FIG. 8C). Here, as in the first embodiment described above, in order to obtain the dielectric 11 having a high dielectric constant, heating is required during or after the formation of the lower electrode 10, the dielectric 11, and the upper electrode 12. Become.

  According to the second embodiment, as described in the first embodiment, since the insulating cover film 33 is provided, the following effects can be obtained. That is, in the heat treatment for forming the capacitor structure 13, the direction of the capacitor structure 13 of the through electrode 7 caused by the difference in thermal expansion coefficient between the material of the substrate 2 and the material of the through electrode 7 (upper direction in FIG. 2) Expansion and contraction in the direction) can be suppressed by the insulating cover film 8. In addition, by making the lower electrode 10 a film configuration including a highly elastic metal film formed of any one of W, Mo, Fe, Ni, and Co, damage to the dielectric 11 due to thermal expansion of the through electrode 7 is further increased. Can be suppressed.

  In addition, when the substrate 32 having a relatively large unevenness on the surface, such as ceramic, is used, there is a problem in that the yield decreases due to defects or the like when the thin film dielectric 11 is formed thereon. On the other hand, in the present invention, since the insulating cover film 33 is formed, the unevenness of the first main surface 32A of the substrate 32 is suppressed, so that the yield is improved.

  Next, three layers of the lower electrode 10, the dielectric 11, and the upper electrode 12 are selectively removed by etching, and a recess is formed at a position overlapping with each through electrode 7. Thereafter, a protective insulating film 14 is formed on the three-layer capacitor structure 13 to cover the entire surface of the capacitor structure 13 (see FIG. 8D).

  Next, the protective insulating film 14 and the insulating cover film 8 are selectively removed at positions overlapping with the respective through electrodes 7 to form a plurality of through electrode connecting vias 9 (see FIG. 8E). Further, the protective insulating film 14 is selectively removed at a position overlapping the lower electrode 10, and a lower electrode connection via 20 for connecting the lower electrode connection pad 16 to the lower electrode 10 is formed. Further, the protective insulating film 14 is selectively removed at a position overlapping with the upper electrode 12, and an upper electrode connection via 21 for connecting the upper electrode 12 to the upper electrode 12 is formed.

  Subsequently, a plurality of semiconductor element bonding pads 15 are formed at positions overlapping the recesses of the capacitor structure 13 on the protective insulating film 14. Thereafter, in order to be used between the semiconductor element 26 and the mounting substrate 25, a back surface pad 23 is formed on the second main surface 2B of the substrate 2 as shown in FIG. Cover resin 24 is formed on main surface 32A and second main surface 32B. In this way, the capacitor 31 with the through electrode shown in FIG. 7 is completed.

  In the manufacturing method of the second embodiment described above, the side wall insulating film 5 and the back surface are formed on the side wall of the through hole 4 and the second main surface 32B of the substrate 32 as compared with the manufacturing method of the first embodiment shown in FIG. There is an advantage that the process of forming the insulating films 6 is not necessary, and the manufacturing process can be simplified accordingly.

  In the capacitor 31 with a through electrode according to the second embodiment of the present invention, as described above, the first main surface 32A of the substrate 32 made of an insulator is covered with the insulating cover film 33, and the insulating cover film 33 is formed. A capacitor structure 13 is formed thereon. For this reason, even if the heating process of the substrate 32 for forming the capacitor structure 13 is performed after the through electrode 7 is formed on the substrate 32, the difference in thermal expansion coefficient between the material of the substrate 32 and the material of the through electrode 7 The expansion and contraction of the through electrode 7 in the thickness direction of the substrate 32 is suppressed by the insulating cover film 33. As a result, deterioration of the dielectric 11 of the capacitor structure 13 can be prevented, that is, production defects can be prevented. Therefore, the process limitation when the through electrode 7 is formed after the capacitor structure 13 is formed on the substrate 32 is limited. The through electrode 7 can be formed with a high degree of freedom. Further, it is not necessary to force the substrate 32 to be thin in order to facilitate the formation of the through electrode 7. Therefore, the through electrode 7 can be easily formed and is not easily damaged during handling in the manufacturing process or the mounting process.

  In addition, since the first main surface 32A of the substrate 32 is covered with the insulating cover film 33 and the capacitor structure 13 is only provided on the insulating cover film 33, the cost can be reduced.

  Furthermore, since the through electrode 7 can be easily formed as described above, the thickness of the substrate 32 can be easily handled, and therefore handling in the manufacturing process is facilitated. Therefore, the capacitor 31 with a through electrode can be easily manufactured.

  Each of the semiconductor element connection pads 15 is electrically connected to the corresponding through electrode 7, and at least one of the semiconductor element connection pads 15 is electrically connected to the upper electrode 12 and electrically connected to the upper electrode 12. Since at least one of the non-connected semiconductor element connection pads 15 is electrically connected to the lower electrode 10, the capacitor 31 with a through electrode can be used as an interposer type capacitor.

  In order to describe the present invention in more detail, specific examples of the first embodiment and the second embodiment will be described below.

Example 1
In Example 1, the capacitor 1 with the through electrode shown in FIG. 4 (first embodiment) was manufactured using the method shown in FIG. 6 (first embodiment).

  First, a Si wafer having a thickness of 350 μm was prepared as the substrate (interposer substrate) 2. Then, by a Bosch process using an ICP-RIE apparatus, a plurality of through holes 4 having a diameter of 50 μm are formed in the substrate 2 so as to correspond to the positions of the terminals having a diameter of 50 μm of the semiconductor elements. .

  Next, a thermal oxidation process using water vapor is performed, a surface insulating film (first insulating film) 3 is formed on the first main surface 2A of the substrate 2, and a side wall insulating film (first insulating film) is formed on the side wall of each through hole 4. 5 and the back surface insulating film 6 were formed on the second main surface 2B of the substrate 2, respectively. Next, the respective films were formed with a thickness of 100 nm and 300 nm by the CVD method in the order of TiN as the barrier layer and Cu as the plating seed layer. Subsequently, filled plating of Cu was performed, and the inside of each through hole 4 was completely filled with Cu to form the through electrode 7. Thereafter, the first main surface 2A and the second main surface 2B of the substrate 2 were ground by CMP, and the plating film, the seed layer, and the barrier layer on both surfaces of the substrate 2 were removed.

Subsequently, the SiO ₂ film as the insulating cover film (second insulating film) 8 is formed to a thickness of 1 μm at 350 ° C. on the first main surface 2A of the substrate 2 by plasma CVD using TEOS (Tetraethoxysilane) as a raw material. Formed. Next, the lower electrode 10 for forming the capacitor structure 13 was formed by DC magnetron sputtering. Specifically, the lower electrode 10 was formed in the order of Ta and Ru with a thickness of 50 nm, respectively, without heating. Further, SrTiO ₃ (STO) to which 5% of Mn was added was deposited at 400 ° C. to a thickness of 50 nm as the dielectric 11 forming the capacitor structure 13 by RF sputtering. Further, Ru was formed to a thickness of 100 nm without heating the substrate 2 as the upper electrode 12 for forming the capacitor structure 13 by DC magnetron sputtering.

  Next, the upper electrode 12 was patterned by Ar (argon) ion milling using the photoresist film patterned by photolithography as a mask. The photoresist film was removed by methyl ethyl ketone cleaning and oxygen plasma cleaning, and then the dielectric 11 was patterned by an etching method using a mixed aqueous solution of hydrofluoric acid and nitric acid using the patterned photoresist film as a mask. After removing the photoresist film, the lower electrode 10 was patterned by Ar ion milling using the patterned resist as a mask. In this way, a groove was formed at a position overlapping each through electrode 7.

Next, a SiO ₂ film as the protective insulating film 14 was formed to a thickness of 1 μm by plasma CVD at 350 ° C. in the same manner as the insulating cover film 8. Then, the lower electrode connection via 20, the upper electrode connection via 21, and the through electrode connection via 9 were formed at predetermined positions of the protective insulating film 14 and the insulating cover film 8 by RIE processing using the photoresist film as a mask. After removing the photoresist film, Ti was deposited in order from the wafer side to a thickness of 50 nm and Cu to a thickness of 300 nm as a seed layer for electrolytic plating. The through-electrode connecting via 9 had a diameter of 30 μm.

  Next, Ti was deposited to a thickness of 50 nm and Cu to a thickness of 300 nm from the wafer side as a seed layer for electrolytic plating. Thereafter, a semiconductor element bonding pad 15 was formed of Cu by electrolytic plating using the resist film as a mask. Then, the resist film and the seed layer were removed to obtain the structure shown in FIG.

  Next, a photosensitive epoxy-phenolic resin as an insulating resin was applied to the first main surface 2A of the substrate 2 and patterned by exposure and development so that each semiconductor element bonding pad 15 was exposed. Next, curing was performed at 200 ° C., and a cover resin 24 was formed on the first main surface 2 </ b> A of the substrate 2. The back pad 23 and the cover resin 24 of the second main surface 2B were formed in the same manner as the cover resin 24. Thus, the structure shown in FIG. 4 was obtained.

  Next, on each semiconductor element bonding pad 15 made of Cu, Ni and Au were formed in thicknesses of 3 μm and 0.05 μm, respectively, from the terminal electrode side by electroless plating. Thereafter, the wafer was cut, and the obtained capacitor 1 with through electrodes was divided into chips.

  Through the above process, a through-electrode capacitor 1 having 9000 semiconductor element bonding pads 15, a capacity of 7.0 μF, and a size of 20 mm square was obtained.

  As shown in FIG. 5, the chip-shaped capacitor 1 with a through electrode is connected between the semiconductor element 26 and the mounting substrate 25 by a Sn—Ag—Cu solder, and the power supply voltage is 1 V, the maximum load current is 100 A, the clock frequency. When the 2 GHz semiconductor element 26 was operated, it was confirmed that the power supply noise was below the target 50 mV.

(Example 2)
In Example 2, using the method shown in FIG. 8 (second embodiment), the through-electrode capacitor 31 of FIG. 7 (second embodiment) was manufactured.

  As the interposer substrate 32, an alkali-free glass having a thickness of 200 μm was used. A plurality of through holes 4 and a plurality of semiconductor elements 26 corresponding to the terminal positions of the semiconductor element 26 having a diameter of 50 μm were formed by the RIE method.

  Next, the respective films were formed with a thickness of 100 nm and 300 nm by the CVD method in the order of TiN as the barrier layer and Cu as the plating seed layer. Subsequently, filled plating of Cu was performed, and the inside of each through hole 4 was completely filled with Cu to form a plurality of through electrodes 7.

Next, the first main surface 32A and the second main surface 32B of the substrate 32 were ground by CMP, and the plating film, the seed layer, and the barrier layer on both surfaces of the substrate 32 were removed. Subsequently, a SiO ₂ film as an insulating cover film 33 was formed to a thickness of 1 μm on the first main surface 32A of the substrate 32 at 350 ° C. by plasma CVD using TEOS as a raw material.

  The subsequent processes were performed in the same manner as in Example 1 except that the insulating cover film (second insulating film) 8 in Example 1 was replaced with the insulating cover film 33 in Example 2. A capacitor 31 with a through electrode having the structure of FIG. 7 was obtained.

  Next, Ni and Au were formed in a thickness of 3 μm and 0.05 μm, respectively, from the terminal electrode side on each Cu semiconductor element bonding pad 15 in the same manner as in Example 1. Thereafter, the wafer was cut, and the obtained capacitor 1 with through electrodes was divided into chips.

  Through the above steps, a through-electrode capacitor 31 with 9,000 semiconductor element bonding pads 15, a capacitance of 6, 9 μF, and a size of 20 mm square, which is substantially the same as in Example 1, was obtained.

  Further, in the same manner as in the first embodiment, a chip-like capacitor 31 with a through electrode is connected between the semiconductor element 26 and the mounting substrate 25 and power noise is evaluated. Good results of 50 mV or less were obtained.

(Example 3)
In Example 3, using the method shown in FIG. 8 (second embodiment), the through-electrode capacitor 31 of FIG. 7 (second embodiment) was manufactured.

  After processing a low-temperature sintered ceramic green sheet to form a plurality of through holes 4 having a diameter of 100 μm, the inside of each through hole 4 was filled with Ag paste and laminated. Thereafter, the low-temperature sintered ceramic and the Ag paste were simultaneously sintered to obtain a substrate 32 with through electrodes 7.

  Next, after applying the SOG material to the first main surface 32A of the substrate 32, the heat treatment was repeated to form an insulating cover film 33 having a thickness of 1 μm on the first main surface 32A of the substrate 32. Next, the lower electrode 10 constituting the capacitor structure 13 was formed. Specifically, the lower electrode 10 was formed by DC magnetron sputtering with a thickness of 50 nm, 1 μm, and 100 nm, respectively, in the order of Ta, Mo, and Ru, without heating. The dielectric 11 and the upper electrode 12 were formed in the same manner as in Example 1 described above.

  Subsequent steps were performed in the same manner as in Example 2. However, the size of the through-electrode connecting via 9 was 50 μm in diameter.

  Through the above process, a through-electrode capacitor 31 having 400 semiconductor element bonding pads 15, a capacitance of 1.7 μF, and a size of 10 mm square was obtained.

  When the power supply noise was evaluated by operating the capacitor 31 with a through electrode obtained in Example 3 at a power supply voltage of 3.3 V and a clock frequency of 1 GHz, the power supply noise was not only the target 50 mV or less, but was almost It was confirmed that there was no power supply noise.

  Although the present invention has been described with reference to the exemplary embodiments and examples, the present invention is not limited to the above exemplary embodiments and examples. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention without departing from the spirit of the present invention.

The present specification further discloses the following inventions.
(Supplementary note 1) a substrate having a plurality of through holes;
A first insulating film covering the surface of the substrate and each side wall of the through hole;
A through electrode made of a conductor filled in each of the through holes;
A second insulating film formed on the first insulating film and covering a surface of the substrate;
A capacitor structure comprising a lower electrode, a dielectric, and an upper electrode formed on the second insulating film;
A protective insulating film covering the capacitor structure;
A plurality of connection pads formed on the protective insulating film,
Each of the connection pads is electrically connected to the corresponding through electrode through a via penetrating the protective insulating film and the second insulating film,
At least one of the connection pads is electrically connected to the upper electrode through a via penetrating the protective insulating film,
At least one of the connection pads not electrically connected to the upper electrode is electrically connected to the lower electrode through a via penetrating the protective insulating film. With capacitor.

(Appendix 2) A substrate made of an insulator having a plurality of through holes;
An insulating film covering the surface of the substrate;
A through electrode made of a conductor filled in each of the through holes;
A capacitor structure formed of a lower electrode, a dielectric, and an upper electrode, formed on the insulating film;
A protective insulating film covering the capacitor structure;
A plurality of connection pads formed on the protective insulating film,
Each of the connection pads is electrically connected to the corresponding through electrode through a via that penetrates the protective insulating film and the insulating film,
At least one of the connection pads is electrically connected to the upper electrode through a via penetrating the protective insulating film,
At least one of the connection pads not electrically connected to the upper electrode is electrically connected to the lower electrode through a via penetrating the protective insulating film. With capacitor.

(Additional remark 3) The process of forming a several through-hole in a board | substrate,
Forming a first insulating film covering the surface of the substrate and the side walls of the through holes;
A step of filling a conductor in each of the through holes to form a plurality of through electrodes;
Forming a second insulating film covering the surface of the substrate on the first insulating film;
Forming a capacitor structure including a lower electrode, a dielectric, and an upper electrode on the second insulating film;
Forming a protective insulating film covering the capacitor;
Forming a plurality of connection pads on the protective insulating film,
Each of the connection pads is electrically connected to the corresponding through electrode through at least a via penetrating the second insulating film,
At least one of the connection pads is electrically connected to the upper electrode through a via penetrating the protective insulating film,
At least one of the connection pads not electrically connected to the upper electrode is electrically connected to the lower electrode through a via penetrating the protective insulating film. Of manufacturing a capacitor with a capacitor.

(Additional remark 4) The process of forming a several through-hole in the board | substrate consisting of an insulator,
Forming an insulating film covering the surface of the substrate;
A step of filling a conductor in each of the through holes to form a plurality of through electrodes;
Forming a capacitor structure including a lower electrode, a dielectric, and an upper electrode on the insulating film;
Forming a protective insulating film covering the capacitor;
Forming a plurality of connection pads on the protective insulating film,
Each of the connection pads is electrically connected to the corresponding through electrode through a via penetrating the insulating film,
At least one of the connection pads is electrically connected to the upper electrode through a via penetrating the protective insulating film,
At least one of the connection pads not electrically connected to the upper electrode is electrically connected to the lower electrode through a via penetrating the protective insulating film. Of manufacturing a capacitor with a capacitor.

  In addition, this application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-054166 for which it applied on March 4, 2008, and takes in those the indications of all here.

Claims (16)

A substrate having a plurality of through holes;
A through electrode made of a conductor filled in each of the through holes;
An insulating cover film made of an inorganic insulator formed on the first main surface of the substrate;
A plurality of capacitor structures formed on the insulating cover film and including a lower electrode, a dielectric, and an upper electrode;
A protective insulating film covering the capacitor structure;
It is electrically connected to at least a part of the capacitor structure through a capacitor connection via that penetrates the protective insulating film, and penetrates the corresponding through electrode, the protective insulating film, and the insulating cover film. A plurality of connection pads electrically connected through through-electrode connecting vias having a smaller diameter than the through-electrode,
At least one of the connection pads is electrically connected to the upper electrode through the capacitor connection via,
A capacitor with a through electrode, wherein at least one of the connection pads not electrically connected to the upper electrode is electrically connected to the lower electrode via the capacitor connection via.   The capacitor with a through electrode according to claim 1, wherein the lower electrode of the capacitor structure includes a highly elastic metal film formed of W, Mo, Fe, Ni, or Co. The substrate is a semiconductor substrate;
The insulating film is formed on the first main surface of the substrate, the second main surface opposite to the first main surface, and the side wall of the through hole. A capacitor with a through electrode according to 1 or 2.   4. The through-electrode capacitor according to claim 3, wherein the semiconductor substrate is made of silicon, gallium arsenide, or a compound semiconductor.   The capacitor with a through electrode according to claim 1, wherein the substrate is an insulating substrate.   The capacitor with a through electrode according to claim 5, wherein the insulating substrate is formed of any one of oxide single crystal, glass, and ceramics.   The capacitor with a through electrode according to claim 6, wherein the glass is crystallized glass.   The capacitor with a through electrode according to claim 6, wherein the ceramic is a low-temperature sintered ceramic.   A semiconductor device on which the capacitor with a through electrode according to claim 1 is mounted. A capacitor with a through electrode disposed between the first component and the second component and electrically connecting them;
The through electrode capacitor is
A substrate having a plurality of through holes;
A through electrode made of a conductor filled in each of the through holes;
An insulating cover film made of an inorganic insulator formed on the first main surface of the substrate;
A plurality of capacitor structures formed on the insulating cover film and including a lower electrode, a dielectric, and an upper electrode;
A protective insulating film covering the capacitor structure;
It is electrically connected to at least a part of the capacitor structure through a capacitor connection via that penetrates the protective insulating film, and penetrates the corresponding through electrode, the protective insulating film, and the insulating cover film. A plurality of connection pads electrically connected through through-electrode connecting vias having a smaller diameter than the through-electrode,
At least one of the connection pads is electrically connected to the upper electrode through the capacitor connection via,
At least one of the connection pads that is not electrically connected to the upper electrode is electrically connected to the lower electrode via the capacitor connection via,
The first component is one or more semiconductor elements;
A semiconductor device in which the second component is a mounting substrate or one or more semiconductor elements.   11. The semiconductor device according to claim 10, wherein the lower electrode of the capacitor structure includes a highly elastic metal film formed of W, Mo, Fe, Ni, or Co. The substrate is a semiconductor substrate;
The said 1st main surface of the said board | substrate, the 2nd main surface on the opposite side to the said 1st main surface, and the side wall of the said through-hole are coat | covered with the insulating film, The Claim 10 or 11 characterized by the above-mentioned. The semiconductor device described.   The semiconductor device according to claim 10, wherein the substrate is an insulating substrate. Forming a plurality of through holes in the substrate;
A plurality of through electrodes are formed by filling a conductor inside each of the through holes,
Forming an insulating cover film made of an inorganic insulator on the first main surface of the substrate;
On the insulating cover film, a lower electrode layer, a dielectric layer, and an upper electrode layer are laminated in this order,
After forming the pattern of the lower electrode layer, dielectric layer, upper electrode layer, a protective insulating film is formed so as to cover the first main surface,
Vias penetrating from the surface of the protective insulating film to the surface of the upper electrode layer, vias penetrating to the surface of the lower electrode layer, and vias having a smaller diameter than the through electrode penetrating to the surface of the through electrode are formed. And
A method of manufacturing a capacitor with a through electrode, wherein a plurality of connection pads are formed on the protective insulating film.   15. The heat treatment is performed so that the dielectric layer is activated when forming the dielectric layer, or after forming the dielectric layer and before forming a pattern. The manufacturing method of the capacitor with a penetration electrode of description. As the substrate, a semiconductor substrate is used,
15. An insulating film is formed on the first main surface of the substrate, the second main surface opposite to the first main surface, and the side wall of the through hole. 15. A method for producing a capacitor with a through electrode according to 15.

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