JP7225721B2 - Thin film capacitor, manufacturing method thereof, and circuit board incorporating thin film capacitor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a thin film capacitor, a method of manufacturing the same, and a circuit board containing the thin film capacitor. It relates to a circuit board that
Regarding.

A circuit board on which an IC is mounted usually has a decoupling capacitor mounted thereon in order to stabilize the potential of the power supply supplied to the IC. Laminated ceramic chip capacitors are generally used as decoupling capacitors, and required decoupling capacity is ensured by mounting a large number of laminated ceramic chip capacitors on the surface of a circuit board.

In recent years, however, there is often a shortage of space on circuit boards on which a large number of multilayer ceramic chip capacitors are mounted. For this reason, thin film capacitors that can be embedded in circuit boards are sometimes used instead of multilayer ceramic chip capacitors (see Patent Document 1).

JP 2007-81325 A

However, since the thin film capacitor described in Patent Document 1 has terminal electrodes only on one surface side, it is difficult to access the terminal electrodes from the back surface side of the thin film capacitor.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a thin film capacitor whose terminal electrodes can be accessed from both sides, a manufacturing method thereof, and a circuit board incorporating such a thin film capacitor.

A thin film capacitor according to the present invention comprises a capacitive layer in which one or more first internal electrode films and one or more second internal electrode films are alternately laminated via a capacitive insulating film; and one surface of the capacitive layer. and a rewiring layer provided on the other surface of the capacitive layer and including a first wiring connected to the first internal electrode film and a second wiring connected to the second internal electrode film , first and second through holes provided through the capacitive layer and the non-capacitive layer, and first and second surface terminals provided on the rewiring layer and connected to the first and second wirings, respectively. , and first and second rear terminals provided on the non-capacitive layer and connected to the first and second wirings through the first and second through holes, respectively.

According to the present invention, since the terminal electrodes are provided on the front and back sides of the thin film capacitor, it is possible to access the terminal electrodes from both sides. Moreover, since the capacitive layer and the non-capacitive layer are laminated, even if the capacitive layer is very thin, the non-capacitative layer can ensure sufficient strength. In particular, if a material having a coefficient of thermal expansion close to that of the capacitive layer is selected as the material for the non-capacitive layer, it is possible to prevent the occurrence of warping.

In the present invention, the non-capacitive layer is made of two or more first material layers made of the same material as the capacitive insulating film and made of the same material as the first and second internal electrode films, and is sandwiched between the two or more first material layers. and a second material layer. According to this, since the thermal expansion coefficients of the capacitive layer and the non-capacitive layer are substantially the same, it is possible to more effectively prevent the occurrence of warpage.

In the present invention, the first material layer may be thicker than the capacitive insulating film, and the second material layer may be thicker than the first and second internal electrode films. According to this, it is possible to sufficiently ensure the strength of the entire thin film capacitor.

A circuit board according to the present invention comprises first and second wiring layers, an insulating resin layer positioned between the first wiring layer and the second wiring layer, and the thin film capacitor embedded in the insulating resin layer, The first surface electrode is connected to the first power supply wiring provided on the first wiring layer, the second surface electrode is connected to the first ground wiring provided on the first wiring layer, and the first back electrode is connected to the first ground wiring provided on the first wiring layer. It is connected to the second power supply wiring provided on the second wiring layer, and the second back surface electrode is connected to the second ground wiring provided on the second wiring layer.

According to the present invention, it is possible to reduce the equivalent series inductance (ESL) because the wiring distance between the power wiring and the ground wiring and the thin film capacitor is shortened.

A method for manufacturing a thin film capacitor according to the present invention is a capacitor in which one or more first internal electrode films and one or more second internal electrode films are alternately laminated on a surface of a support via capacitive insulating films. forming a non-capacitive layer on one surface of the capacitive layer; forming first and second trenches in the non-capacitive layer reaching the capacitive layer; removing the support; By forming third and fourth trenches reaching the first and second trenches, respectively, from the other surface side of the capacitive layer, the first through-hole formed by the first and third trenches and the second and fourth through-holes are formed. A rewiring layer including a first wiring connected to the first internal electrode film and a second wiring connected to the second internal electrode film is formed on the other surface of the capacitor layer by forming a second through hole composed of a trench. forming, on the rewiring layer, first and second surface terminals respectively connected to the first and second wirings, and on the non-capacitive layer, the first and second through holes through the first and second through holes; It is characterized by forming first and second rear terminals respectively connected to the second wiring.

According to the present invention, it is possible to easily fabricate a thin film capacitor that has terminal electrodes on both sides and whose strength is ensured by the non-capacitive layer.

As described above, according to the present invention, it is possible to provide a thin film capacitor whose terminal electrodes are accessible from both sides, a manufacturing method thereof, and a circuit board incorporating such a thin film capacitor.

FIG. 1 is a schematic cross-sectional view showing the structure of a thin film capacitor 1 according to a preferred embodiment of the invention. FIG. 2 is a schematic enlarged view of a connection portion between the first wiring 31 and the first rear surface electrode E3 (a connection portion between the second wiring 32 and the second rear surface electrode E4). FIG. 3 is a schematic cross-sectional view showing the configuration of a circuit board 100 incorporating the thin film capacitor 1. As shown in FIG. 4A to 4D are process diagrams showing a method of manufacturing the thin film capacitor 1. First, as shown in FIG. 5A to 5D are process diagrams showing a method of manufacturing the thin film capacitor 1. First, as shown in FIG. 6A to 6D are process diagrams showing a method of manufacturing the thin film capacitor 1. First, as shown in FIG. 7A to 7D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 8A to 8D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 9A to 9D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 10A to 10D are process diagrams showing a method of manufacturing the thin film capacitor 1. First, as shown in FIG. 11A to 11D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 12A to 12D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 13A to 13D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 14A to 14D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 15A to 15D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 16A to 16D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 17A to 17D are process diagrams showing a method of manufacturing the thin film capacitor 1. FIG. 18A to 18D are process diagrams showing a manufacturing method according to a modification of the thin film capacitor 1. FIG. 19A to 19D are process diagrams showing a manufacturing method according to a modification of the thin film capacitor 1. FIG.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view showing the structure of a thin film capacitor 1 according to a preferred embodiment of the invention.

As shown in FIG. 1, the thin film capacitor 1 according to this embodiment includes a capacitive layer 10, a non-capacitive layer 20 provided on one surface of the capacitive layer 10 (lower surface in FIG. 1), and the other side of the capacitive layer 10. and a rewiring layer 30 provided on the surface of (upper surface in FIG. 1). First and second surface terminals E1 and E2 are provided on the surface of the rewiring layer 30, and first and second back terminals E3 and E4 are provided on the surface of the non-capacitance layer 20. FIG.

The capacitive layer 10 has a plurality of internal electrode films 11 to 17 stacked with capacitive insulating films 19 interposed therebetween. Of these internal electrode films 11 to 17, odd-numbered internal electrode films 11, 13, 15, and 17 when viewed from the rewiring layer 30 constitute first internal electrode films M1, The internal electrode films 12, 14 and 16 constitute the second internal electrode films M2. That is, the capacitive layer 10 has a structure in which four layers of the first internal electrode films M1 and three layers of the second internal electrode films M2 are alternately laminated with the capacitive insulating films 19 interposed therebetween.

The internal electrode films 11 to 17 are made of a conductive material containing, for example, nickel (Ni) or platinum (Pt), and in particular, a conductive material containing nickel (Ni) as a main component is preferably used. “Main component” means a component that accounts for 50% by mass or more of the whole. Further, when the main component of the internal electrode films 11 to 17 is nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), ruthenium (Ru), osmium (Os), Rhenium (Re), tungsten (W), chromium (Cr), tantalum (Ta) or silver (Ag) may be added. By adding these elements, the internal electrode films 11 to 17 are less likely to break, and the continuity of the films can be enhanced. Note that the internal electrode films 11 to 17 may contain a plurality of additive elements. Each thickness of the internal electrode films 11 to 17 is, for example, about 10 nm to 1000 nm.

The capacitive insulating film 19 is made of, for example, a perovskite-based dielectric material. Perovskite-based dielectric materials include BaTiO ₃ (barium titanate), (Ba _1-X Sr _X )TiO ₃ (barium strontium titanate), (Ba _1-X Ca _X )TiO ₃ , PbTiO ₃ , Pb( ( _Ferro )electric materials with a perovskite structure such as ZrXTi1 _-X ) _O3 , and composite perovskite relaxor-type ferroelectric materials such as Pb(Mg1 _{/ 3Nb2/3} ) _O3 . _{bismuth layered} compounds _such as Bi _{4 Ti 3} O ₁₂ and SrBi _{2 Ta 2} O _{9 ;} Examples include dielectric materials. Here, in the perovskite structure, the perovskite relaxor type ferroelectric material, the bismuth layered compound, and the tungsten bronze type ferroelectric material, the ratio of the A site to the B site is usually an integer ratio. You can deviate from the integer ratio. Incidentally, in order to control the characteristics of the capacitive insulating film 19, the capacitive insulating film 19 may contain an additive substance as an accessory component as appropriate. The capacitive insulating film 19 is fired and has a dielectric constant (ε _r ) of 100 or more, for example. It should be noted that the dielectric constant of the capacitive insulating film 19 is preferably as large as possible, and its upper limit is not particularly limited. The thickness of one capacitor insulating film 19 is, for example, 10 nm to 1000 nm.

The non-capacitive layer 20 has first material layers 21 and 23 made of the same material as the capacitive insulating film 19 and second material layers 22 made of the same material as the internal electrode films 11 to 17. 22 is sandwiched between first material layers 21 and 23 . Each thickness of the first material layers 21 and 23 is thicker than each thickness of the capacitive insulating film 19, and is, for example, about 1 μm to 5 μm. Similarly, the thickness of the second material layer 22 is greater than the thickness of each of the internal electrode films 11 to 17, and is, for example, about 1 μm to 5 μm.

The non-capacitive layer 20 is provided to ensure the mechanical strength of the thin film capacitor 1 and to facilitate handling. In general thin-film capacitors, a capacitive layer is formed on a support such as silicon (Si). In order to prevent the occurrence of , it is necessary to increase the thickness of the support to some extent. As a result, there arises a problem that the thickness of the entire thin film capacitor increases. Warping hardly occurs regardless of the thickness of the non-capacitive layer 20 .

In the example shown in FIG. 1, the non-capacitive layer 20 is composed of two first material layers 21 made of an insulating material and one second material layer 22 made of a conductive material, but the present invention is not limited to this. not something. For example, a non-capacitive layer 20 having a five-layer structure in which three first material layers 21 and two second material layers 22 are alternately laminated may be used, or four first material layers 21 and three second material layers 21 may be used. A non-capacitive layer 20 having a seven-layer structure in which layers 22 are alternately stacked may also be used. Further, it is not essential that the number of layers of the non-capacitance layer 20 is an odd number, and it may be an even number.

The rewiring layer 30 has a first wiring 31 connected to the first internal electrode film M1 and a second wiring 32 connected to the second internal electrode film M2. An insulating resin layer 33 is provided between the first and second wirings 31 and 32 and the capacitor layer 10 . The first and second wirings 31 and 32 are covered with an insulating resin layer 34, and first and second surface terminals E1 and E2 are provided on the surface of the insulating resin layer 34. As shown in FIG.

As a material for forming the terminals E1 to E4, it is preferable to use a metal material whose main component is nickel (Ni), copper (Cu), gold (Au), platinum (Pt), or an alloy containing these metals. In particular, it is preferable to use copper (Cu). When copper (Cu) is used as the material for the terminals E1 to E4, its purity is preferably as high as possible, preferably 99.99% by mass or more. When copper (Cu) is used as the material for the terminals E1 to E4, impurities include iron (Fe), titanium (Ti), nickel (Ni), aluminum (Al), magnesium (Mg), manganese (Mn), silicon ( Si) or transition metal elements such as chromium (Cr), vanadium (V), zinc (Zn), niobium (Nb), tantalum (Ta), yttrium (Y), lanthanum (La), cesium (Ce), or rare earth elements, etc. , chlorine (Cl), sulfur (S), phosphorus (P) and the like may be contained.

As shown in FIG. 1, trenches T1 to T7 are provided in the capacitor layer 10, and the internal electrode films 11 to 17 are exposed at the bottoms of the trenches T1 to T7, respectively. The internal electrode films 11, 13, 15 and 17 exposed at the bottoms of the trenches T1, T3, T5 and T7 are connected to the first wiring 31, and the internal electrode films 12 and 12 exposed at the bottoms of the trenches T2, T4 and T6. 14 and 16 are connected to the second wiring 32 . Furthermore, the capacitive layer 10 is further provided with trenches T8 and T9 penetrating the capacitive layer 10, and the non-capacitive layer 20 is provided with trenches T10 and T11 penetrating the non-capacitive layer 20. FIG. The trenches T8 and T10 are provided at positions overlapping each other in plan view, thereby forming a first through hole TH1 penetrating the capacitive layer 10 and the non-capacitive layer 20 . Similarly, the trenches T9 and T11 are provided at positions overlapping each other in a plan view, thereby forming a second through hole TH2 penetrating the capacitive layer 10 and the non-capacitive layer 20 .

The trenches T10 and T11 provided in the non-capacitance layer 20 are filled with a conductive material forming the first and second back electrodes E3 and E4, respectively. The first back electrode E3 is connected to the first wiring 31 of the rewiring layer 30 through the first through hole TH1, and the second back electrode E4 is connected to the rewiring layer 30 through the second through hole TH2. It is connected to the second wiring 32 . Therefore, the first surface electrode E1 and the first back electrode E3 have the same potential, and the second surface electrode E2 and the second back electrode E4 have the same potential.

FIG. 2 is a schematic enlarged view of a connection portion between the first wiring 31 and the first rear surface electrode E3 (a connection portion between the second wiring 32 and the second rear surface electrode E4).

As shown in FIG. 2, when the diameter at the tip of the first back electrode E3 (second back electrode E4) is φ1 and the diameter at the tip of the first wiring 31 (second wiring 32) is φ2, then φ1 The value of /φ2 is preferably in the range of 1.5-10. Specifically, φ1 is about 100 to 200 μm, and φ2 is about 20 to 60 μm. This is because when the value of φ1/φ2 is less than 1.5, the loss of the capacitance value is large, and when the value of φ1/φ2 exceeds 10, the adhesion between the first wiring 31 and the first back electrode E3 is large. This is because the properties (adhesion between the second wiring 32 and the second back surface electrode E4) become insufficient. Further, the depth D of the recesses formed at the tips of the first rear surface electrode E3 and the second rear surface electrode E4 may be about 1 to 3 μm.

FIG. 3 is a schematic cross-sectional view showing the configuration of a circuit board 100 incorporating the thin film capacitor 1. As shown in FIG.

The circuit board 100 shown in FIG. 3 includes wiring layers L1 to L4, an insulating resin layer 110 provided between the wiring layers L1 and L2, and an insulating resin layer 110 provided between the wiring layers L2 and L3. It has a layer 120 and an insulating resin layer 130 provided between the wiring layer L3 and the wiring layer L4. The wiring layer L1 and the wiring layer L2 are connected through via conductors 141 passing through the insulating resin layer 110, the wiring layers L2 and L3 are connected through via conductors 142 passing through the insulating resin layer 120, Wiring layer L<b>3 and wiring layer L<b>4 are connected via via conductors 143 penetrating insulating resin layer 130 .

The first surface electrode E1 provided on the thin film capacitor 1 is connected to the power supply wiring V3 provided on the wiring layer L3 through the via conductor 151, and the first back electrode E3 provided on the thin film capacitor 1 is connected to the via conductor 151. Via a conductor 153, it is connected to the power supply wiring V2 provided on the wiring layer L2. The power wiring V2 is connected to the power pattern V1 provided on the wiring layer L1 through the corresponding via conductors 141, and the power wiring V3 is connected to the power pattern V4 provided on the wiring layer L4 through the corresponding via conductors 143. connected to The power wiring V2 and the power wiring V3 may be short-circuited via the via conductors 142 .

The second surface electrode E2 provided on the thin film capacitor 1 is connected to the ground wiring G3 provided on the wiring layer L3 through the via conductor 152, and the second back surface electrode E4 provided on the thin film capacitor 1 is connected to the via conductor 152. Through a conductor 154, it is connected to the ground wiring G2 provided on the wiring layer L2. The ground wiring G2 is connected to the ground pattern G1 provided on the wiring layer L1 through the corresponding via conductors 141, and the ground wiring G3 is connected to the ground pattern G4 provided on the wiring layer L4 through the corresponding via conductors 143. connected to The ground wiring G2 and the ground wiring G3 may be short-circuited via the via conductors 142 .

An IC chip and various passive components can be mounted on the surface 101 of the wiring layer L1 or the surface 104 of the wiring layer L4. For example, when an IC chip is mounted on the surface 104 of the wiring layer L4, the power supply pad of the IC chip is connected to the power supply pattern V4, and the ground pad of the IC chip is connected to the ground pattern G4. 1 functions as a decoupling capacitor.

In this way, if the thin film capacitor 1 according to the present embodiment is embedded in the circuit board 100, it becomes possible to access the terminal electrodes E1 to E4 from both sides of the thin film capacitor 1 inside the circuit board 100, and the equivalent series inductance (ESL ) can be reduced. Specifically, the equivalent series inductance (ESL) can be reduced by about 20% compared to the case where the back electrodes E3 and E4 are not provided.

Next, a method for manufacturing the thin film capacitor 1 according to this embodiment will be described.

4 to 17 are process diagrams showing the method of manufacturing the thin film capacitor 1 according to this embodiment.

First, as shown in FIG. 4, the capacitive layer 10 and the non-capacitive layer 20 are laminated in this order on the surface of a support 50 made of nickel (Ni) or the like. The capacitor layer 10 is formed by alternately forming the internal electrode films 11 to 17 and the capacitor insulating film 19 . Examples of methods for forming the internal electrode films 11 to 17 include DC sputtering. As a method for forming the capacitive insulating film 19, a film formation technique such as a solution method, a PVD (Physical Vapor Deposition) method such as sputtering, or a CVD (Chemical Vapor Deposition) method can be used, but the sputtering method is more preferable. is. The non-capacitance layer 20 is formed in the same manner, and the non-capacitance layer 20 is formed by alternately forming the first material layer 21 and the second material layer 22 .

Firing is then performed to sinter the capacitive insulating film 19 . The firing temperature is preferably a temperature at which the dielectric material forming the capacitive insulating film 19 is sintered (crystallized). preferable. Also, the firing time can be set to about 5 minutes to 2 hours. The atmosphere during firing is not particularly limited, and may be an oxidizing atmosphere, a reducing atmosphere, or a neutral atmosphere. However, it is preferable to perform firing under at least an oxygen partial pressure that does not oxidize the internal electrode films 11 to 17. In such a firing process, the first material layer 21 constituting the non-capacitive layer 20 is also sintered at the same time.

Next, as shown in FIG. 5, trenches T10 and T11 are formed in the non-capacitive layer 20 by etching. The trenches T10 and T11 must have a depth that penetrates the non-capacitive layer 20 and reaches at least the internal electrode film 17 included in the capacitive layer 10 . After that, a passivation film 40 is formed over the entire surface of the non-capacitance layer 20 including the insides of the trenches T10 and T11.

Next, as shown in FIG. 6, after forming a conductive material 60 made of copper (Cu) or the like on the passivation film 40 so as to fill the trenches T10 and T11, as shown in FIG. First and second back electrodes E3 and E4 are formed by patterning. The conductive material 60 is preferably formed by forming a seed layer made of chromium (Cr) and copper (Cu) by sputtering or vapor deposition, and then electroplating to obtain the required film thickness. Thereafter, as shown in FIG. 8, the support 50 is removed using an etchant such as iron chloride (FeCl ₃ ) or hydrogen peroxide-based nitric acid (HNO ₃ ·H ₂ O ₂ ). Thereby, the other surface of the capacitive layer 10 is exposed. Here, if there is a defect in the first material layer 21 constituting the non-capacitive layer 20, the etchant used to remove the support 50 may penetrate inside through the defect. has two layers of the first material layer 21 , the possibility that the positions of the defects overlap is extremely low.

Next, as shown in FIG. 9, trenches T1, T13, T18, T15, T17 and T19 reaching the internal electrode film 11 are formed. These trenches T1, T13, T18, T15, T17 and T19 can be formed by patterning one layer of the internal electrode film and one layer of the capacitor insulating film. Among them, the trenches T13, T18, T15, T17 and T19 are provided at planar positions where the trenches T3, T8, T5, T7 and T9 shown in FIG. 1 are to be formed. This step completes the trench T1, and the internal electrode film 11 is exposed on the bottom surface thereof.

Next, as shown in FIG. 10, T23, T28, T27, T26, T29 and T2 are formed by patterning two layers of internal electrode films and two layers of capacitive insulating films. Among them, the trenches T23, T28, T27, T26 and T29 are provided at planar positions where the trenches T3, T8, T7, T6 and T9 shown in FIG. 1 are to be formed. The trench T2 is completed by this step, and the internal electrode film 12 is exposed on the bottom surface thereof. A trench T3 consisting of the trenches T13 and T23 is also completed, and the internal electrode film 13 is exposed on the bottom surface thereof.

Next, as shown in FIG. 11, T48, T45, T47, T46, T49 and T4 are formed by patterning the four layers of internal electrode films and the four layers of capacitor insulating films. Among them, the trenches T48, T45, T47, T46 and T49 are provided at planar positions where the trenches T8, T5, T7, T6 and T9 shown in FIG. 1 are to be formed. This step completes the trench T4, and the internal electrode film 14 is exposed on the bottom surface thereof. A trench T5 consisting of the trenches T15 and T45 is also completed, and the internal electrode film 15 is exposed on the bottom surface thereof. A trench T6 consisting of trenches T26 and T46 is also completed, and the internal electrode film 16 is exposed on the bottom surface thereof. A trench T7 consisting of trenches T17, T27 and T47 is also completed, and the internal electrode film 17 is exposed on the bottom surface thereof. Further, a trench T8 consisting of trenches T18, T28 and T48 is also completed, and the conductive material forming the first rear surface electrode E3 is exposed on the bottom surface thereof. Similarly, a trench T9 composed of trenches T19, T29, and T49 is also completed, and the conductive material forming the second back surface electrode E4 is exposed on the bottom surface thereof.

Next, as shown in FIG. 12, after forming an insulating resin layer 33 to fill the trenches T1 to T9, as shown in FIG. 33 is formed. As a result, the internal electrode films 11 to 17 are exposed at the bottoms of the trenches T1 to T7 through the opening patterns P1 to P7, respectively, and the internal electrode films 11 to 17 are exposed at the bottoms of the trenches T8 and T9 through the opening patterns P8 and P9, respectively. The conductive material forming the first and second backside electrodes E3 and E4 is exposed.

Next, as shown in FIG. 14, a rewiring 35 is formed on the entire surface of the insulating resin layer 33 including the insides of the trenches T1 to T9. As a result, the rewiring 35 and the internal electrode films 11 to 17 are connected at the bottoms of the trenches T1 to T7, and the conductive material forming the rewiring 35 and the first and second back electrodes E3 and E4 at the bottoms of the trenches T8 and T9. is connected. Then, as shown in FIG. 15, the rewiring 35 is patterned to separate the rewiring 35 into the first wiring 31 and the second wiring 32 . Thus, the first wiring 31 is commonly connected to the internal electrode films 11, 13, 15, 17 and the first rear surface electrode E3, and the second wiring 32 is connected to the internal electrode films 12, 14, 16 and the second rear surface electrode E3. It will be connected in common to E4.

Next, as shown in FIG. 16, after forming an insulating resin layer 34 covering the first wiring 31 and the second wiring 32, as shown in FIG. An opening 34 b for exposing the wiring 32 is formed in the insulating resin layer 34 . After that, a conductive material made of copper (Cu) or the like is formed on the insulating resin layer 34 so as to fill the openings 34a and 34b, and then the conductive material is patterned to form the first and second surfaces shown in FIG. Forming the electrodes E1 and E2 completes the thin film capacitor 1 according to the present embodiment. Also in the formation of the first and second surface electrodes E1 and E2, after forming a seed layer made of chromium (Cr) and copper (Cu) by a sputtering method or a vapor deposition method, it is possible to obtain a required film thickness by electroplating. preferable.

As described above, in the method of manufacturing the thin film capacitor 1 according to the present embodiment, the trenches T10 and T11 having a depth reaching the capacitive layer 10 are formed in the non-capacitive layer 20 before forming the trenches T1 to T9 in the capacitive layer 10. Therefore, it is possible to easily fabricate the thin film capacitor 1 having a double-sided electrode structure.

Moreover, the material of the first material layer 21 forming the non-capacitance layer 20 is the same as that of the capacitive insulating film 19, and the material of the second material layer 22 forming the non-capacitance layer 20 is the same as that of the internal electrode films 11 to 17. By using materials, the capacitive layer 10 and the non-capacitive layer 20 can be deposited using the same apparatus. In addition, since the first material layer 21 is formed thicker than the capacitive insulating film 19 and the second material layer 22 is formed thicker than the internal electrode films 11 to 17, the non-capacitive layer 20 It is possible to reduce the number of film forming processes.

It is also possible to perform the patterning of the conductive material 60 shown in FIG. 7 after the rewiring layer 30 is formed. In this case, after the structure shown in FIG. 18 is obtained by performing the steps shown in FIGS. The thin film capacitor 1 shown in FIG. 1 can be obtained by forming a conductive material 70 made of , and finally patterning the conductive materials 60 , 70 .

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.

For example, in the above-described embodiment, the capacitor layer 10 composed of the four layers of the first internal electrode films 11, 13, 15 and 17 and the three layers of the second internal electrode films 12, 14 and 16 is used. The number of layers of the first internal electrode films and the number of layers of the second internal electrode films constituting the layer 10 are not particularly limited. Therefore, it is sufficient to have a structure in which one or two or more first internal electrode films and one or two or more second internal electrode films are alternately laminated via capacitive insulating films.

In the above embodiment, the same material as that of the capacitive insulating film 19 is used as the material of the first material layer 21 constituting the non-capacitance layer 20, and the internal electrode is used as the material of the second material layer 22 constituting the non-capacitance layer 20. Although the same material as the films 11-17 is used, this is not essential as long as the thermal expansion coefficients of the capacitive layer 10 and the non-capacitive layer 20 are close to each other. However, as in the present embodiment, the same material as the capacitive insulating film 19 is used as the material of the first material layer 21 forming the non-capacitance layer 20, and the material of the second material layer 22 forming the non-capacitance layer 20 is the internal material. By using the same material as the electrode films 11 to 17, the thermal expansion coefficient of the capacitive layer 10 and the thermal expansion coefficient of the non-capacitor layer 20 can be substantially matched.

1 thin-film capacitor 10 capacitive layers 11 to 17 internal electrode film 19 capacitive insulating film 20 non-capacitive layer 30 rewiring layers 33, 34 insulating resin layers 34a, 34b opening 35 rewiring 40 passivation film 50 supports 60, 70 conductive material 100 Circuit boards 101, 104 Surfaces 110, 120, 130 of circuit boards Insulating resin layers 141 to 143, 151 to 154 Via conductors E1 First surface terminal E2 Second surface terminal E3 First rear terminal E4 Second rear terminal G1, G4 Ground Patterns G2, G3 Ground wiring L1 to L4 Wiring layers P1 to P9 Opening patterns T1 to T11, T13, T15, T17, T18, T19, T23, T26, T27 to T29, T45 to T49 Trench V1, V4 Power supply patterns V2, V3 power wiring

Claims (4)

a capacitive layer in which one or two or more first internal electrode films and one or two or more second internal electrode films are alternately laminated via capacitive insulating films;
a non-capacitive layer provided on one surface of the capacitive layer;
a rewiring layer provided on the other surface of the capacitive layer and including a first wiring connected to the first internal electrode film and a second wiring connected to the second internal electrode film;
first and second through holes provided through the capacitive layer and the non-capacitive layer;
first and second surface terminals provided on the rewiring layer and connected to the first and second wirings, respectively;
first and second rear terminals provided on the non-capacitive layer and connected to the first and second wirings through the first and second through holes, respectively ;
The non-capacitive layer is made of two or more first material layers made of the same material as the capacitive insulating film and made of the same material as the first and second internal electrode films, and is sandwiched between the two or more first material layers. and a second material layer . 2. The thin film capacitor according to claim 1, wherein said first material layer is thicker than said capacitive insulating film, and said second material layer is thicker than said first and second internal electrode films . first and second wiring layers;
an insulating resin layer positioned between the first wiring layer and the second wiring layer;
and the thin film capacitor according to claim 1 or 2 embedded in the insulating resin layer,
The first surface electrode is connected to a first power supply wiring provided on the first wiring layer,
The second surface electrode is connected to a first ground wiring provided on the first wiring layer,
The first back electrode is connected to a second power supply wiring provided on the second wiring layer,
The circuit board, wherein the second back electrode is connected to a second ground wiring provided on the second wiring layer. forming a capacitive layer in which one or two or more first internal electrode films and one or two or more second internal electrode films are alternately laminated via a capacitive insulating film on the surface of a support;
forming a non-capacitive layer on one surface of the capacitive layer;
forming first and second trenches reaching the capacitive layer in the non-capacitive layer;
After removing the support, the third and fourth trenches are formed from the other surface side of the capacitive layer covered with the support to reach the first and second trenches, respectively. forming a first through-hole consisting of first and third trenches and a second through-hole consisting of said second and fourth trenches;
forming a rewiring layer including a first wiring connected to the first internal electrode film and a second wiring connected to the second internal electrode film on the other surface of the capacitive layer;
forming first and second surface terminals respectively connected to the first and second wirings on the rewiring layer;
A method of manufacturing a thin film capacitor, comprising forming, on the non-capacitance layer, first and second rear terminals connected to the first and second wirings through the first and second through holes, respectively.

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