JP2019071336A - Thin film capacitor and manufacturing method thereof - Google Patents

Abstract

To provide a thin film capacitor in which the number of extraction electrodes is reduced, and a manufacturing method thereof.SOLUTION: In a laminate 22 of a thin film capacitor 1, an electrode layer 20 (that is, a second electrode layer 20B) connected to an extraction electrode 30A formed in a first region 23A and an electrode layer 20 (that is, a first electrode layers 20A) connected to an extraction electrode 30B formed in a second region 23B are alternately stacked via a dielectric layers 21. Therefore, in the thin film capacitor 1, even when the number of electrode layers 20 is large, the pair of extraction electrodes 30A and 30B is sufficient, and it is not necessary to increase the number of extraction electrodes.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a thin film capacitor and a method of manufacturing the same.

  Conventionally, a thin film capacitor is known which has a laminated structure in which an electrode layer and a dielectric layer are alternately laminated, and has a plurality of lead electrodes (contact holes) connected to the electrode layer. (For example, refer to the following patent documents 1 and 2)

JP, 2014-7239, A International Publication 07/046173

  However, the thin film capacitor according to the prior art described above has a configuration in which one lead electrode is formed for one electrode layer, so the number of lead electrodes increases as the number of electrode layers increases. As a result, particularly in the case of producing a thin film capacitor having a large number of stacked layers, the formation region of the lead electrode can not be used as a capacitance portion, and therefore, the capacitance is significantly reduced.

  An object of the present invention is to provide a thin film capacitor in which the number of extraction electrodes is reduced and a method of manufacturing the same.

  A thin film capacitor according to one aspect of the present invention includes a stacked body having a plurality of electrode layers and a plurality of dielectric layers, in which the electrode layers and the dielectric layers are alternately stacked, and A base metal comprising: a pair of depressions extending from the end face along the stacking direction; and a pair of lead-out electrodes continuously covering the side surfaces of each depression and a part of one end surface. And a first region in which the base metal region and the noble metal region are alternately arranged in the order from the one end surface to the near end from the one end surface. Opposite to the first region, a noble metal region and a base metal region are alternately arranged in a second region, and one of the pair of depressions is formed in the first region and the other is formed in the second region. So that the base metal area of each electrode layer leaves the depression A regression unit for regression, the base metal area and the lead-out electrode is insulated by the retractable line unit.

  In the thin film capacitor laminate, an electrode layer connected to the lead electrode formed in the first region and an electrode layer connected to the lead electrode formed in the second region alternate via the dielectric layer. Is stacked on. Therefore, in the thin film capacitor, even when the number of electrode layers is large, only one pair of lead electrodes is sufficient, and it is not necessary to increase the number of lead electrodes.

  In the thin film capacitor according to another aspect of the present invention, the plurality of electrode layers include a plurality of first electrode layers and a plurality of second electrode layers, and the first electrode layer is a recess portion of one of the pair of recess portions. And a noble metal region surrounding the entire edge of the other recess, wherein the second electrode layer surrounds the entire edge of one recess of the pair of recesses; And a base metal region surrounding the entire edge of the other recess, and in the laminate, the first electrode layer and the second electrode layer are alternately stacked via the dielectric layer. In this case, the work of patterning the noble metal region and the base metal region can be made efficient.

  In the thin film capacitor according to another aspect of the present invention, the regression portion is filled with an insulator. In this case, the insulation property between the base metal region and each lead electrode can be improved.

  A method of manufacturing a thin film capacitor according to one aspect of the present invention is a laminate including a plurality of electrode layers and a plurality of dielectric layers, and a laminate in which the electrode layers and the dielectric layers are alternately stacked. A method of manufacturing a thin film capacitor, comprising: a pair of depressions extending along the stacking direction from one end surface with respect to a direction; and a pair of lead-out electrodes continuously covering a side surface of each depression and a part of one end surface. Preparing a laminate in which an electrode layer having a base metal region composed of a base metal, an electrode layer having a noble metal and a noble metal region contacting with the base metal region, and a dielectric layer alternately stacked; A first region of a laminate in which base metal regions and a noble metal region are alternately arranged in order of closeness, and a second of a laminate in which a noble metal region and a base metal region are alternately arranged in the order of closeness from one end surface Depressions in each of the areas The step of forming, the step of removing the base metal region of each electrode layer exposed in the recess portion, and the step of forming a retreating portion in which the base metal region recedes away from the recess portion; And a forming step.

  According to the method of manufacturing the thin film capacitor, the electrode layer connected to the lead electrode formed in the first region and the electrode layer connected to the lead electrode formed in the second region intervene through the dielectric layer As a result, a laminate stacked alternately is obtained. Therefore, in the thin film capacitor manufactured by the above manufacturing method, even if the number of electrode layers is large, only one pair of lead electrodes is sufficient, and it is not necessary to increase the number of lead electrodes.

  In the method of manufacturing a thin film capacitor according to another aspect of the present invention, in the step of forming the regression part, the base metal is dissolved and removed using an etchant in which the base metal is dissolved.

  According to various aspects of the present invention, there are provided a thin film capacitor and a method of manufacturing the same in which the number of extraction electrodes is reduced.

FIG. 1 is a cross-sectional view showing a thin film capacitor according to an aspect of the present invention. FIG. 2 is a plan view showing a first electrode layer of the thin film capacitor shown in FIG. FIG. 3 is a plan view showing a second electrode layer of the thin film capacitor shown in FIG. FIG. 4 is a plan view of the thin film capacitor shown in FIG. FIG. 5 is a diagram showing each step of the method of manufacturing the thin film capacitor shown in FIG. FIG. 6 is a diagram showing each step of the method of manufacturing the thin film capacitor shown in FIG. FIG. 7 is a plan view showing a laminate according to the method of manufacturing the thin film capacitor shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same function will be denoted by the same reference symbols, without redundant description.

  As shown in FIG. 1, the thin film capacitor 1 according to the embodiment has a laminated structure, and a laminated body 22 in which a substrate 10 and electrode layers 20 and dielectric layers 21 are alternately laminated on the substrate 10. And.

  The substrate 10 contains Ni as a main component. In the present embodiment, the purity of Ni constituting the substrate 10 is 99.99% by weight or more. The substrate 10 may contain a slight amount of impurities. The impurities that may be contained in the substrate 10 include, for example, iron (Fe), titanium (Ti), copper (Cu), aluminum (Al), magnesium (Mg), manganese (Mn), silicon (Si) or chromium (Cr) ), Transition metal elements such as vanadium (V), zinc (Zn), niobium (Nb), tantalum (Ta), yttrium (Y), lanthanum (La), cesium (Ce) or rare earth elements, etc., chlorine (Cl) , Sulfur (S), phosphorus (P) and the like.

The thickness of the substrate 10 is preferably 5 to 100 μm, more preferably 20 to 70 μm, and still more preferably about 50 μm. When the thickness of the substrate 10 is too thin, it tends to be difficult to handle the substrate 10 at the time of manufacture of the thin film capacitor 1, and when the thickness of the base electrode 2 is too thick, the effect of suppressing leakage current tends to be small. . The area of base electrode 2 is, for example, about 1 × 0.5 mm ² .

  The laminate 22 includes a plurality of electrode layers 20 (four layers in the present embodiment) and a plurality of dielectric layers 21 (five layers in the present embodiment), and the electrode layers 20 and the dielectric layers 21 are alternately stacked. It is done. Specifically, dielectric layers 21 are stacked directly on the substrate 10, and electrode layers 20 and dielectric layers 21 are alternately stacked on the dielectric layer 21.

Each electrode layer 20 is composed of a conductive metal material or alloy material. The thickness of each electrode layer 20 is, for example, about 10 to 1000 nm. The area of the electrode layer 20 is, for example, about 0.9 × 0.4 mm ² .

Each dielectric layer 21 is made of BaTiO ₃ (barium titanate), (Ba _1-x Ca _x ) TiO ₃ , (Ba _1-x Sr _x ) TiO ₃ (barium strontium titanate), PbTiO ₃ , Pb (Zr _x (Ferroelectric) dielectric materials having a perovskite structure such as Ti _1-x ) _3, composite perovskite relaxor type ferroelectric materials represented by Pb (Mg _1/3 Nb _2/3 ) O ₃ etc, Bi Tungsten bronze type ferroelectric materials represented by bismuth layered compounds represented by ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ etc., (Sr _{1 -X} Ba _x ) Nb ₂ O ₆ , PbNb ₂ O ₆ etc. Etc. Here, in these perovskite structures, perovskite relaxor ferroelectric materials, bismuth layered compounds, and tungsten bronze ferroelectric materials, the ratio of A site to B site is usually an integer ratio, but the intention is to improve the characteristics. You may deviate from the integer ratio. In order to control the characteristics of the dielectric layer 21, the dielectric layer 21 may appropriately contain an additive substance as an accessory component. Each thickness of dielectric layer 21 is, for example, 10 to 1000 nm. Each area of dielectric layer 21 is, for example, about 0.9 × 0.5 mm ² .

  The stacked body 22 has a pair of holes 26A, 26B (recessed portions) extending along the stacking direction from the upper surface 22a (that is, one end surface in the stacking direction) to the lower surface 22b (that is, the other end surface in the stacking direction). ) Is formed. One hole 26A is formed in a first region 23A of a laminate 22 described later, and the other hole 26B is formed in a second region 23B of the laminate 22 described later. Each hole 26A, 26B extends from the top surface 22a of the laminate 22 to a depth reaching the dielectric layer 21 immediately above the substrate 10.

  Further, extraction electrodes 30A and 30B are provided in the pair of holes 26A and 26B, respectively. Each of the lead-out electrodes 30A, 30B continuously covers all the inner side surfaces of the corresponding holes 26A, 26B and a part of the laminate upper surface 22a around the holes 26A, 26B. Each extraction electrode 30A, 30B is made of, for example, a conductive material such as Cu.

  Subsequently, the above-described electrode layer 20 will be described with reference to FIGS.

  The plurality of electrode layers 20 are configured by a plurality of first electrode layers 20A (two layers in the present embodiment) and a plurality of second electrode layers 20B (two layers in the present embodiment). As shown in FIG. 2, the first electrode layer 20A is composed of a base metal region 24 composed of Ni and a noble metal region 25 composed of Pt. In the present embodiment, the base metal region 24 and the noble metal region 25 are divided into two (equally divided) at an intermediate position of the long side of the first electrode layer 20A having a rectangular shape.

  The base metal region 24 is mainly composed of Ni. The base metal region 24 is at least one selected from the group consisting of Pt, Pd, Ir, Rh, Ru, Os, Re, W, Cr, Ta and Ag (hereinafter referred to as "additional element"), preferably And at least one selected from Pd and Ir. By containing the additive element, breakage of the base metal region 24 is prevented, and oxidation at the interface between the base metal region 24 and the dielectric layer 21 is suppressed. The noble metal region 25 can be made of high purity Pt or Pt alloy. A known method can be employed to pattern the base metal region 24 and the noble metal region 25. For example, a lift-off method or a metal mask method can be used for the patterning.

  Like the first electrode layer 20A, the second electrode layer 20B is also composed of the base metal region 24 and the noble metal region 25. However, as shown in FIG. 3, the arrangement of the base metal region 24 and the noble metal region 25 is the first electrode It is different from layer 20A. That is, in the second electrode layer 20B, the base metal region 24 and the noble metal region 25 are divided into two at an intermediate position of the long side of the second electrode layer 20B having a rectangular shape, but the base metal region 24 and the noble metal region 25 Is reversed to the first electrode layer 20A.

  In the laminate 22, the first electrode layer 20 </ b> A and the second electrode layer 20 </ b> B described above are alternately stacked via the dielectric layer 21. In the present embodiment, as shown in FIG. 1, the first electrode layer 20A, the second electrode layer 20B, the first electrode layer 20A, and the second electrode layer 20B are arranged in order of proximity to the top surface 22a. Therefore, in the first region 23A of the multilayer body 22 corresponding to the base metal region 24 of the first electrode layer 20A which is the uppermost electrode layer 20, the base metal region 24, the noble metal region 25, the base metal region 24 and the noble metal region It is lined with 25. On the other hand, in the second region 23B of the multilayer body 22 corresponding to the noble metal region 25 of the first electrode layer 20A which is the uppermost electrode layer 20, the noble metal region 25, the base metal region 24, the noble metal region 25 and the base metal region It is aligned with 24.

  Then, as shown in FIG. 4, one hole 26A of the pair of holes 26A, 26B is formed in the first region 23A, and the other hole 26B is a second region of the laminate 22. It is formed in 23B.

  Here, in the base metal region 24 of each electrode layer 20, a retrogression portion 27 which retreats away from each hole 26A, 26B is formed. In the present embodiment, the retreating portion 27 is filled with an insulator. In the noble metal region 23 of each electrode layer 20, the above-mentioned retreating portion 27 is not formed. In the laminate 22, the base metal region 24 and the respective lead-out electrodes 30 </ b> A and 30 </ b> B provided in the holes 26 </ b> A and 26 </ b> B are insulated by the retreating portion 27. Therefore, in the first region 23A of the stacked body 22, the lead-out electrode 30A is insulated from the first electrode layer 20A and is conducted to the second electrode layer 20B. Further, in the second region 23B of the stacked body 22, the lead-out electrode 30B is insulated from the second electrode layer 20B and is conducted to the first electrode layer 20A.

  Next, with reference to FIGS. 5 and 6, a method of manufacturing the thin film capacitor 1 described above will be described.

  When manufacturing the thin film capacitor 1, first, the substrate 10 described above is prepared (FIG. 5 (a)). Then, the dielectric layer 21 which is the first layer of the laminate 22 is formed on the substrate 10 (FIG. 5B). For the formation of the dielectric layer 21, a film forming technique such as a solution coating baking method such as a sol gel method or MOD method (organic metal compound deposition method), a PVD method such as a sputtering method, or a CVD method can be used. Among these film forming techniques, sputtering is particularly preferably used. The dielectric layer 21 formed by the above method generally has a dielectric in an amorphous state.

  Next, the second electrode layer 20B is formed as the electrode layer 20 on the entire surface of the dielectric layer 21 (FIG. 5C). The composition of the electrode layer 20 may be the same as that of the electrode layer 20 provided in the thin film capacitor 1 after completion. Further, DC sputtering or the like can be used to form the electrode layer 20. The above-described lift-off method, metal mask method, or the like can be used to pattern the base metal region 24 and the noble metal region 25 in the second electrode layer 20B. Further, the dielectric layer 21 is formed on the entire surface of the second electrode layer 20B (FIG. 5 (d)), and the first electrode layer 20A as the electrode layer 20 is formed on the entire surface of the dielectric layer 21 (FIG. 5 (e)).

  Thereafter, the formation of the dielectric layer 21 and the formation of the electrode layer 20 described above are repeated to form a laminate 22 composed of four electrode layers 20 and five dielectric layers 21 (FIG. 6A). . Then, as shown in FIG. 7, the hole 26A is formed in the first region 23A of the laminate 22, and the hole 26B is formed in the second region 23B (FIG. 6 (b)). Dry etching (DeepRIE) can be used to form the holes 26A and 26B. As an example, argon gas is used for dry etching of the dielectric layer 21, argon gas is used for dry etching of the base metal region 24 of the electrode layer 20, and argon gas is used for dry etching of the noble metal region 25 of the electrode layer 20. be able to. Wet etching with ferric chloride can also be used to form the holes 26A, 26B.

  After the holes 26A and 26B are formed, a part of the base metal region 24 exposed to the holes 26A and 26B is dissolved and removed by etching to form the above-described retreating portion 27 (FIG. 6C). For this etching process, an etchant such as ferric chloride can be used as an example. Furthermore, the entire stack 22 is covered from above with the insulator film 29 made of alumina, silicon oxide, silicon nitride or the like, and the inner side surface and the bottom surface of the holes 26A, 26B are entirely covered with the insulator (FIG. 6). (D)). At this time, the regression part 27 is filled with an insulator. For the formation of the insulator film 29, CVD, TEOS or the like can be used. Then, the insulator film 29 other than the insulator filling the retrogression portion 27 is removed by etching (FIG. 6 (e)). Finally, the thin film capacitor 1 described above is completed by forming the lead-out electrodes 30A, 30B corresponding to the respective holes 26A, 26B by sputtering or CVD.

  As described above, the thin film capacitor 1 described above includes the multilayer body 22 including the plurality of electrode layers 20 and the plurality of dielectric layers 21, and the electrode layers 20 and the dielectric layers 21 are alternately stacked, A pair of holes 26A, 26B extending from the top surface 22a of the laminate 22 along the stacking direction, and a pair of lead electrodes 30A, 30B continuously covering the side surfaces of the holes 26A, 26B and part of the top surface 22a Have. Each electrode layer 20 has a base metal region 24 made of Ni, and a noble metal region 25 made of Pt and in contact with the base metal region 24. Further, the first region 23A in which the base metal regions 24 and the noble metal regions 25 are alternately arranged in the order from the upper surface 22a to the stacked body 22 and the noble metal region 25 and the base metal region opposite to the first regions 23A in the order from the upper surface 22a And 24 are alternately arranged. Furthermore, the hole 26A of the pair of holes 26A and 26B is formed in the first region 23A and the hole 26B is formed in the second region 23B. The base metal region 24 of the electrode layer 20 has a retreating portion 27 which retreats away from the holes 26A and 26B, and the retreating portion 27 insulates the base metal region 24 and the respective lead electrodes 30A and 30B.

  In the laminate 22 of such a thin film capacitor 1, the electrode layer 20 (that is, the second electrode layer 20B) connected to the lead electrode 30A formed in the first region 23A and the lead formed in the second region 23B The electrode layers 20 (that is, the first electrode layers 20A) connected to the electrodes 30B are alternately stacked via the dielectric layers 21. Therefore, in the thin film capacitor 1, even when the number of electrode layers 20 is large, the pair of lead electrodes 30A, 30B is sufficient, and it is not necessary to increase the number of lead electrodes.

  When the number of extraction electrodes is increased, the formation area of the extraction electrode can not be used as a capacitance portion particularly when manufacturing a thin film capacitor having a large number of laminated layers, and therefore, the capacity is significantly reduced. In addition, when the number of extraction electrodes is increased, labor and cost in the manufacturing process are increased.

  Further, in the thin film capacitor 1, the first electrode layer 20A has the base metal region 24 surrounding the entire edge of the hole 26A, and the noble metal region 25 surrounding the entire edge of the hole 26B, and the second electrode layer 20B is A noble metal region 25 surrounding the entire edge of the hole 26A, and a base metal region 24 surrounding the entire edge of the hole 26B, and in the laminate 22, the first electrode layer 20A and the second electrode layer 20B are dielectrics The layers 21 are alternately stacked. In this case, the work of patterning the base metal region 24 and the noble metal region 25 can be made efficient. In particular, when the base metal region 24 and the noble metal region 25 are divided into two at a predetermined position on the long side of the first electrode layer 20A having a rectangular shape as in the embodiment described above, a flat mask is used. The base metal region 24 and the noble metal region 25 can be easily patterned and formed by sliding in the long side direction.

  Furthermore, in the thin film capacitor 1, since the retreating portion 27 is filled with the insulator, the insulation between the base metal region 24 and each of the lead electrodes 30A and 30B is improved compared to the case where the recess is not filled with the insulator. doing.

  The thin film capacitor is not limited to the form described above, and can be variously modified.

  For example, the base metal region need not necessarily be composed of Ni, but may be Co or a Co alloy. The noble metal region does not necessarily have to be made of Pt, and may be Au or an Au alloy. In the thin film capacitor, the substrate 10 can be omitted as appropriate.

  The recess is not limited to the hole, and may be a groove formed on the upper surface of the laminate or a notch formed on the end face of the laminate. Further, the base metal region and the noble metal region do not necessarily have to be equally divided, and one region may be designed to be larger than the other region. In this case, the first electrode layer has a base metal region surrounding the entire edge of one recess of the pair of recesses and a noble metal region surrounding the entire edge of the other recess, and the second electrode layer has a pair It may be designed to have a noble metal region surrounding the entire edge of one recess of the recess and a base metal region surrounding the entire edge of the other recess.

  DESCRIPTION OF SYMBOLS 1 thin film capacitor 20 electrode layer 20A first electrode layer 20B second electrode layer 21 dielectric layer 22 laminated body 23A first region 23B second region 24 base metal Region 25: noble metal region 26A, 26B: hole portion 27: regression portion 30A, 30B: extraction electrode.

Claims (5)

A laminate having a plurality of electrode layers and a plurality of dielectric layers, wherein the electrode layers and the dielectric layers are alternately stacked;
A pair of depressions extending from one end face in the stacking direction of the stack along the stacking direction;
And a pair of lead-out electrodes continuously covering the side surface of each recess and a part of the one end surface,
Each of the electrode layers has a base metal region composed of a base metal, and a noble metal region composed of a noble metal and in contact with the base metal region,
The first region in which the base metal regions and the noble metal regions are alternately arranged in the order from the one end surface to the laminate, and the noble metal region and the base metal in the opposite order to the first region in the order from the one end surface And an alternating second area,
One of the pair of depressions is formed in the first area and the other is formed in the second area,
The thin film capacitor, wherein the base metal region of each of the electrode layers has a retreating portion that retreats away from the depression, and the retreating portion insulates the base metal region and the lead electrodes. The plurality of electrode layers include a plurality of first electrode layers and a plurality of second electrode layers,
The first electrode layer has the base metal region surrounding the entire edge of one recess of the pair of recesses and the noble metal region surrounding the entire edge of the other recess;
The second electrode layer includes the noble metal region surrounding the entire edge of one recess of the pair of recesses and the base metal region surrounding the entire edge of the other recess;
The thin film capacitor according to claim 1, wherein the first electrode layer and the second electrode layer are alternately stacked via the dielectric layer in the stacked body.   The thin film capacitor according to claim 1, wherein the regression part is filled with an insulator. A laminate having a plurality of electrode layers and a plurality of dielectric layers, wherein the electrode layers and the dielectric layers are alternately stacked;
A pair of depressions extending from one end face in the stacking direction of the stack along the stacking direction;
A method of manufacturing a thin film capacitor, comprising: a pair of lead-out electrodes continuously covering the side surface of each recess and a part of the one end surface,
Preparing a laminate in which the electrode layers each having a base metal region composed of a base metal and a noble metal region composed of a noble metal and in contact with the base metal region, and the dielectric layers are alternately stacked;
The first region of the laminate in which the base metal regions and the noble metal regions are alternately arranged in order of proximity to the one end surface, and the noble metal region and the base metal in the order of proximity to the one end surface Forming the depressions in each of the second regions of the laminate in which the regions are alternately arranged;
Removing the base metal region of each of the electrode layers exposed to the recess to form a retreating portion for retreating the base metal region away from the recess;
And a step of forming the lead-out electrode in each of the pair of depressions.   The method for manufacturing a thin film capacitor according to claim 4, wherein the base metal is dissolved and removed using an etchant in which the base metal dissolves in the step of forming the regression part.

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