JP2019186285A - Thin film capacitor manufacturing method and thin film capacitor - Google Patents

Abstract

To provide a thin film capacitor manufacturing method and a thin film capacitor which can suppress an electrode layer from being excessively etched.SOLUTION: A method for manufacturing a thin film capacitor 1 comprises: a lamination step of laminating a plurality of electrode layers (internal electrode layers 11 or base electrode layers 13) and dielectric films 12' each making a dielectric layer 12 so as to alternate, thereby forming a laminate W serving as a capacitance part 10; an etching step of etching the laminate W by a plasma etching device 100 to form an opening 14 extending in a lamination direction; an analyzing step S2 of making analysis of components that plasma contains during the etching step; and a stopping step S4 of stopping the etching when a component detected in analysis in the analyzing step S2 is matched to a component of the electrode layer which is a target.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a method for manufacturing a thin film capacitor and a thin film capacitor.

  Conventionally, a thin film capacitor having a capacitor portion in which a plurality of electrode layers and dielectric layers are alternately stacked is known. Thus, as a method for manufacturing a thin film capacitor, for example, Patent Document 1 discloses that a capacitor part is formed by alternately laminating electrode layers and dielectric layers, and a through hole is formed in the capacitor part by etching. And a step of exposing an electrode layer electrically connected to the thin film capacitor.

International Publication No. 2009/078225

  However, when etching is performed on a capacitor portion (capacitor portion) having a plurality of electrode layers to expose an electrode layer electrically connected to an external electrode, it is difficult to determine which layer is being etched. Therefore, it is difficult to stop etching at the timing when the target electrode layer is exposed, and the electrode layer may be excessively etched.

  The present invention has been made in view of the above, and an object thereof is to provide a method of manufacturing a thin film capacitor and a thin film capacitor capable of suppressing an electrode layer from being excessively etched.

  A method of manufacturing a thin film capacitor according to an aspect of the present invention includes a plurality of electrode layers and a plurality of dielectric layers, and a method of manufacturing a thin film capacitor including a capacitor portion in which electrode layers and dielectric layers are alternately stacked. The components of the electrode layers adjacent to each other in the stacking direction of the capacitor portion are different from each other, and a plurality of electrode layers and a dielectric film to be a dielectric layer are alternately stacked to form a stack to be a capacitor portion. A stacking step, an etching step of etching the stack using a plasma etching apparatus to form an opening extending in the stacking direction, an analysis step of analyzing components contained in the plasma during the etching step, And a stopping step of stopping etching when the component detected in the analysis in the analysis step matches the component of the target electrode layer.

  This thin film capacitor manufacturing method is an etching process in which, during the etching process, an analysis process for analyzing the components contained in the plasma and the components detected as a result of the analysis process match the target electrode layer components. And a stopping step of stopping the process. Thus, by analyzing the components contained in the plasma during etching, it is possible to determine which electrode layer is being etched. Therefore, it is possible to prevent the electrode layer from being etched excessively by stopping the etching when the target electrode layer component is detected.

  In one form, you may analyze the component contained in plasma based on the wavelength of the light of a plasma in an analysis process. According to this configuration, it is possible to easily analyze components contained in plasma as compared with other analysis methods.

  In one form, the components of all electrode layers may be different from one another. According to this configuration, since there are no electrode layers having the same components, it is possible to more easily determine which electrode layer is etched.

  A thin film capacitor according to an embodiment of the present invention includes a plurality of electrode layers and a plurality of dielectric layers, and includes a capacitor portion in which electrode layers and dielectric layers are alternately stacked, and is adjacent in the stacking direction of the capacitor portions. The components of the matching electrode layers are different from each other.

  In this thin film capacitor, the components of the electrode layers adjacent to each other in the stacking direction of the capacitor portion are different from each other. As a result, when etching is performed on the laminated body serving as the capacitor in the manufacturing process of the thin film capacitor, it is possible to determine which electrode layer is etched by analyzing the components contained in the plasma. Therefore, the etching can be stopped at the timing when the target electrode layer is exposed, and a thin film capacitor in which excessive etching of the electrode layer is suppressed can be obtained.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and thin film capacitor of a thin film capacitor which can suppress that an electrode layer is etched excessively are provided.

It is sectional drawing which shows roughly a part of thin film capacitor which concerns on one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the thin film capacitor of FIG. It is a figure for demonstrating the manufacturing method of the thin film capacitor of FIG. It is a figure which shows roughly an example of the plasma etching apparatus used for the manufacturing method of the thin film capacitor which concerns on one Embodiment of this invention. It is a flowchart which shows the manufacturing method of the thin film capacitor which concerns on one Embodiment of this invention.

  Hereinafter, various embodiments will be described in detail with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same or an equivalent part, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a cross-sectional view schematically showing a part of a thin film capacitor according to an embodiment of the present invention. As shown in FIG. 1, a thin film capacitor 1 has a plurality of electrode layers and a plurality of dielectric layers as a capacitor structure therein, and a capacitor portion 10 in which electrode layers and dielectric layers are alternately stacked. have. An electrode terminal 20 (20A, 20B, 20C) is drawn out from the capacitor 10 as an electrode terminal. Between the capacitor unit 10 and the electrode terminal 20, a wiring unit 40 that electrically connects the capacitor unit 10 and the electrode terminal 20 is provided.

  In the present specification, the “stacking direction” refers to a direction in which the layers sequentially overlap from the capacitor 10 toward the electrode terminal 20, such as the capacitor 10, the wiring 40, and the electrode terminal 20. Further, in the following description, the electrode terminal 20 side may be described as “upper” along the stacking direction, and the capacitor unit 10 side may be described as “lower” along the stacking direction.

  The capacitor unit 10 includes a plurality of internal electrode layers (electrode layers) 11 provided along the stacking direction, a dielectric layer 12 sandwiched between the internal electrode layers 11, and a plurality of internal electrode layers and dielectric layers 12. And a laminated base electrode layer (electrode layer) 13. The internal electrode layers 11 and the dielectric layers 12 are alternately stacked on the base electrode layer 13. In the present embodiment, the capacitor unit 10 includes three internal electrode layers 11 (11A, 11B, 11C), three dielectric layers 12 (12A, 12B, 13A), and one base electrode layer 13. It has a multilayer structure. Each layer of the capacitor 10 is formed in the order of the base electrode layer 13, the dielectric layer 12A, the internal electrode layer 11A, the dielectric layer 12B, the internal electrode layer 11B, the dielectric layer 12C, and the internal electrode layer 11C from the lower side in the stacking direction. Are stacked. In the following description, the internal electrode layer 11 and the base electrode layer 13 may be collectively described as an “electrode layer”.

  The capacitor 10 has a plurality of regions from which the internal electrode layers 11 and the dielectric layers 12 are partially removed. Thus, an opening 14 extending in the stacking direction in which the internal electrode layer 11 and the dielectric layer 12 are stacked is formed in the capacitor unit 10. The opening 14 passes through at least one internal electrode layer 11 and one dielectric layer 12. Within the opening 14, one of the plurality of internal electrode layers 11 or the base electrode layer 13 is exposed at the bottom surface of the opening 14. In FIG. 1, two openings 14 (openings 14A and 14B) are shown. The internal electrode layer 11A is exposed in one opening 14A, and the internal electrode layer 11B is exposed in the other opening 14B. The internal electrode layers 11A and 11B have exposed portions 15 exposed at the bottom surfaces of the openings 14A and 14B, and each exposed portion 15 is connected to a first wiring layer 43A described later. With such a structure, a multilayer capacitor structure is formed in the capacitor portion 10. Although omitted in FIG. 1, the base electrode layer 13 also has an exposed portion that is exposed at the bottom surface of the opening 14 and connected to the first wiring layer 43 </ b> A, like the internal electrode layer 11.

  The internal electrode layer 11 is formed of a conductive material. Specifically, a material containing nickel (Ni) or platinum (Pt) as a main component (a component having the highest content) is preferably used as the internal electrode layer 11, and Ni is particularly preferably used. When a material containing Ni as a main component is used for the internal electrode layer 11, the content is preferably 50% by mass or more with respect to the entire internal electrode layer 11. When the main component of the internal electrode layer 11 is Ni, platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), ruthenium (Ru), osmium (Os), rhenium (Re), It further contains at least one selected from the group consisting of tungsten (W), chromium (Cr), tantalum (Ta), and silver (Ag) (hereinafter referred to as “additive element”). When internal electrode layer 11 contains an additive element, discontinuity of internal electrode layer 11 can be suppressed. The internal electrode layer 11 may contain a plurality of additive elements. The thickness of the internal electrode layer 11 is, for example, about 10 nm to 1000 nm. The base electrode layer 13 can be formed of the same conductive material as that of the internal electrode layer 11. The thickness of the base electrode layer 13 can be, for example, 5 μm or more and 50 μm or less.

  The components of the electrode layers (internal electrode layers 11A, 11B, 11C and base electrode layer 13) adjacent in the stacking direction of the capacitor 10 are different from each other. In the present embodiment, the main components of each electrode layer are made of the same material, and the components of the electrode layers are different from each other by changing the type of additive element contained in each electrode layer. Moreover, in this embodiment, the components of all the electrode layers are different from each other. As an example, each electrode layer is mainly composed of nickel (Ni), the base electrode layer 13 does not contain an additive element, the internal electrode layer 11A contains titanium (Ti) as an additive element, and the internal electrode layer 11B is added. Palladium (Pd) is contained as an element, and the internal electrode layer 11C can be configured to contain platinum (Pt) as an additive element.

The dielectric layer 12 is made of a perovskite-based dielectric material. As the perovskite-based dielectric material in the present embodiment, BaTiO ₃ (barium titanate), (Ba _1-X Sr _X ) TiO ₃ (barium strontium titanate), (Ba _1-X Ca _X ) TiO ₃ , PbTiO _{3 3} , Pb (Zr _X Ti _1-X ) O _{3 and} other (strong) dielectric materials having a perovskite structure, and composite perovskite relaxor type typified by Pb (Mg _1/3 Nb _2/3 ) O ₃ Ferroelectric materials, bismuth layered compounds typified by Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , (Sr _1-X Ba _X ) Nb ₂ O ₆ , PbNb ₂ O _6, etc. It is composed of a tungsten bronze type ferroelectric material or the like. Here, in the perovskite structure, the perovskite relaxor type ferroelectric material, the bismuth layered compound, and the tungsten bronze type ferroelectric material, the ratio of A site to B site is usually an integer ratio. You may deviate from the integer ratio. In order to control the characteristics of the dielectric layer 12, the dielectric layer 12 may appropriately contain an additive substance as a subcomponent. In order to control the characteristics of the dielectric layer 12, the dielectric layer 12 may appropriately contain an additive substance as a subcomponent. The dielectric layer 12 is fired, and its relative dielectric constant (ε _r ) is, for example, 100 or more. The relative dielectric constant of the dielectric layer 12 is preferably as large as possible, and the upper limit value is not particularly limited. The thickness of the dielectric layer 12 is, for example, 10 nm to 1000 nm.

  The electrode terminal 20 is a terminal for electrically connecting the thin film capacitor 1 to an external electronic component or a wiring board (not shown). The electrode terminal 20 is laminated with respect to the wiring part 40 described later. In the present embodiment, the thin film capacitor 1 includes a plurality of electrode terminals 20. In FIG. 1, only three electrode terminals 20A, 20B, and 20C are shown.

  As a material constituting the electrode terminal 20, the main component is preferably nickel (Ni), copper (Cu), gold (Au), platinum (Pt), or an alloy containing these metals. The containing alloy is preferably used. The higher the purity of Cu constituting the electrode terminal 20, the better, and it is preferably 99.99% by weight or more. The electrode terminal 20 may contain a small amount of impurities. Examples of impurities that can be contained in the electrode terminal 20 made of an alloy containing Cu as a main component include iron (Fe), titanium (Ti), nickel (Ni), aluminum (Al), magnesium (Mg), manganese ( Transition metals such as Mn), silicon (Si) or chromium (Cr), vanadium (V), zinc (Zn), niobium (Nb), tantalum (Ta) yttrium (Y), lanthanum (La), cesium (Ce) Examples of the element include rare earth elements, chlorine (Cl), sulfur (S), phosphorus (P), and the like.

  The wiring part 40 is provided so as to cover the region where the capacitor part 10 is formed, and the passivation layer 41, the first insulating layer 42A, the second insulating layer 42B, the first wiring layer 43A, and the second wiring layer 43B. Is included. The first insulating layer 42A and the second insulating layer 42B function as an insulating layer on the capacitor unit 10. The first wiring layer 43A and the second wiring layer 43B are wiring layers in the wiring part 40.

  The passivation layer 41 directly covers the capacitor unit 10 and is made of an inorganic insulating material such as silicon oxide (SiO). The passivation layer 41 may be a single inorganic insulating material layer or a laminated structure of a plurality of inorganic insulating materials. However, the passivation layer 41 may not be provided. The thickness of the passivation layer 41 can be, for example, about 0.5 μm to 5 μm.

  The first insulating layer 42 </ b> A covers the capacitor unit 10 in each region where the capacitor is formed in the capacitor unit 10. The second insulating layer 42B covers a region where the first insulating layer 42A is not formed and partially covers the periphery of the first insulating layer 42A. That is, the capacitor portion 10 is covered with a two-stage structure of the first insulating layer 42A and the second insulating layer 42B.

The first insulating layer 42A and the second insulating layer 42B are not particularly limited as long as they are insulating materials. For example, non-conductive resins such as polyimide, silicon oxide (SiO), alumina (Al ₂ O ₃ ), An inorganic material such as silicon nitride (SiN) or an insulating material obtained by mixing or stacking these materials can be used. The thickness of the first insulating layer 42A is, for example, not less than 0.5 μm and not more than 10 μm, and the thickness of the second insulating layer 42B is, for example, not less than 0.5 μm and not more than 10 μm. Here, the “thickness of the first insulating layer 42A” is a distance between the upper surface of the passivation layer 41 and the upper surface of the first insulating layer 42A. The “thickness of the second insulating layer 42B” is the distance between the upper surface of the first insulating layer 42A and the upper surface of the second insulating layer 42B.

  A first wiring layer 43A is formed along the upper surface of the first insulating layer 42 between the first insulating layer 42A and the second insulating layer 42B. The first wiring layer 43A extends in the vertical direction along the upper surface of the first insulating layer 42A, and has a contact portion 44A in contact with the exposed portion 15 of the internal electrode layer 11 at the lower end thereof. A second wiring layer 43B is formed on the second insulating layer 42B along the upper surface of the second insulating layer 42B. The second wiring layer 43B extends in the vertical direction along the second insulating layer 42B, and has a contact portion 44B in contact with the first wiring layer 43A at the lower end thereof. Electrode terminals 20A, 20B, and 20C are formed on the second wiring layer 43B.

  The contact part 44B of the second wiring layer 43B on which the electrode terminal 20A is formed has a first wiring layer having a contact part 44A in contact with the internal electrode layer 11A located closest to the base electrode layer 13 among the three internal electrode layers 11. It is in contact with 43A. The contact portion 44B of the second wiring layer 43B on which the electrode terminal 20B is formed is in contact with the first wiring layer 43A having the contact portion 44A in contact with the internal electrode layer 11B located in the center among the three internal electrode layers 11. . The contact portion 44B of the second wiring layer 43B on which the electrode terminal 20C is formed has a first wiring layer 43A having a contact portion 44A in contact with the internal electrode layer 11C located closest to the electrode terminal 20 among the three internal electrode layers 11. Is in contact with As described above, each of the electrode terminals 20A, 20B, and 20C is electrically connected to the internal electrode layers 11A, 11B, and 11C through the second wiring layer 43B and the first wiring layer 43A, respectively.

  Next, a method for manufacturing the thin film capacitor 1 will be described with reference to FIGS. 2 and 3 are diagrams for explaining a method of manufacturing the thin film capacitor shown in FIG. FIG. 4 is a diagram schematically showing an example of a plasma etching apparatus used in the method for manufacturing a thin film capacitor according to an embodiment of the present invention. FIG. 5 is a flowchart showing a method of manufacturing a thin film capacitor according to an embodiment of the present invention. 2 and 3 are enlarged views of a part of the thin film capacitor 1 in the middle of manufacturing. Actually, after a plurality of thin film capacitors 1 are formed at a time, they are separated into individual thin film capacitors 1. In the following embodiments, the case where the dielectric layer 12 is formed by firing will be described. However, the dielectric layer 12 may be formed without firing.

  First, as shown in FIG. 2A, the base electrode layer 13 is prepared, and the internal electrode layer 11 (11A, 11B, 11C) and the dielectric layer 12 (12A, 12B, 12C) are formed on the base electrode layer 13. The dielectric films 12 ′ (dielectric films 12A ′, 12B ′, 12C ′) to be formed are alternately stacked to form a stacked body W (stacking step). With this process, in the stacked body W, the lower electrode layer 13, the dielectric film 12A ′, the internal electrode layer 11A, the dielectric film 12B ′, the internal electrode layer 11B, the dielectric film 12C ′, Each layer is laminated in the order of the electrode layer 11 </ b> C, and a portion to be the capacitor portion 10 is formed. Examples of the method for forming the internal electrode layer 11 include DC sputtering. As a method for forming the dielectric film 12 ′, a film formation technique such as a solution method, a PVD (Physical Vapor Deposition) method such as sputtering, or a CVD (Chemical Vapor Deposition) method can be used. This is a more preferable method.

  Next, as shown in FIG. 2B, the stacked body W is etched to form openings 14 (openings 14A and 14B). In the present embodiment, the opening 14A is first formed, and then the same process is repeated to form the opening 14B. The order in which the openings 14A and 14B are formed is not particularly limited. For example, the opening 14B may be formed first and the opening 14A may be formed later. Details of this step will be described later.

  Thereafter, the stacked body W is fired. By this step, the dielectric film 12 'is sintered to form the dielectric layer 12, and the capacitor portion 10 (see FIG. 2C) is formed. The firing temperature is preferably set to a temperature at which the dielectric film 12 ′ is sintered (crystallized), and specifically, about 800 ° C. to 1000 ° C. is preferable. The firing time can be about 5 minutes to 2 hours. The atmosphere during firing is not particularly limited, and any of an oxidizing atmosphere, a reducing atmosphere, and a neutral atmosphere may be used. However, it is preferable to perform firing at least under an oxygen partial pressure that does not oxidize the internal electrode layer 11. In addition, the timing of baking is not limited, For example, you may baking before forming the opening 14. FIG.

  Next, as shown in FIG. 2C, a passivation layer 41 is formed. As a result, the upper surface of the stacked body W and the bottom and side surfaces of the opening 14 are covered with the passivation layer 41. The passivation layer 41 can be formed by a PVD method such as sputtering.

  Next, as shown in FIG. 3A, after the first insulating layer 42 </ b> A is formed so as to cover the passivation layer 41, the passivation layer 41 formed on the bottom surface of the opening 14 is removed. Then, the first wiring layer 43A is formed on the first insulating layer 42A. The first insulating layer 42A may be formed, for example, by applying an uncured thermosetting resin, then curing it by heating or the like, and patterning. Alternatively, the first insulating layer 42A may be formed using other methods such as sputtering. The first wiring layer 43A is formed by performing patterning by etching after sputtering or vapor-depositing a conductive material such as copper (Cu). By this step, a plurality of first wiring layers 43A that are electrically independent from each other are formed, and the respective first wiring layers 43A are electrically connected to the internal electrode layers 11A, 11B, and 11C.

  Next, as shown in FIG. 3B, a second insulating layer 42B is formed on the first insulating layer 42A and the first wiring layer 43A. Then, the second wiring layer 43B is formed on the second insulating layer 42B. Similarly to the first insulating layer 42A, the second insulating layer 42B is formed, for example, by applying an uncured thermosetting resin, curing it by heating, and patterning. Similar to the first wiring layer 43A, the second wiring layer 43B is formed by performing patterning by etching after sputtering or vapor-depositing a conductive material such as copper (Cu). By this step, a plurality of second wiring layers 43B that are electrically independent from each other are formed. The respective second wiring layers 43B are electrically connected to the respective first wiring layers 43A, and the wiring portions 40 are formed.

  Thereafter, electrode terminals 20A, 20B, and 20C for electrically connecting the thin film capacitor 1 to external electronic components are formed on the respective second wiring layers 43B. The electrode terminals 20A, 20B, and 20C are formed, for example, by forming a layer of a conductive material such as copper (Cu) by plating or the like and then performing etching or the like. Finally, the thin film capacitor 1 shown in FIG. 1 is obtained by dividing into pieces by dicing or the like.

  Next, the etching process will be described in detail with reference to FIGS. In the method for manufacturing a thin film capacitor according to this embodiment, the stacked body W is etched using the plasma etching apparatus 100 shown in FIG. The plasma etching apparatus 100 is, for example, an inductively coupled etching apparatus. As shown in FIG. 4, the plasma etching apparatus 100 includes a chamber 110, a plasma generator 120 that generates plasma in the chamber 110, and a mounting table 130 that is provided in the chamber 110 and on which the stacked body W is mounted. And a light detection unit 140 that detects light of plasma in the chamber 110 and a control unit 150 that controls the entire plasma etching apparatus 100. A high frequency power source (not shown) is connected to each of the plasma generator 120 and the mounting table 130. The mounting table 130 is biased by a high frequency power source connected to the mounting table 130. As a result, the plasma generated by the plasma generator 120 is drawn into the stacked body W. The high frequency power source connected to the plasma generation unit 120 and the mounting table 130 can be controlled by the control unit 150. Accordingly, the control unit 150 can control the start and stop of the etching of the stacked body W.

  The light detection unit 140 is attached to a detection window 111 provided in the chamber 110, for example. As the light detection unit 140, for example, a device capable of specifying a wavelength of a detection destination such as a CCD camera can be used. The light detection unit 140 is connected to the control unit 150 and transmits information related to the detected plasma light to the control unit 150.

  The control unit 150 is a computer including a processor, a storage unit, an input device, a display device, and the like, for example, and controls each unit of the plasma etching apparatus 100. The control unit 150 stores information on the wavelength of light corresponding to at least the component of the target electrode layer (the electrode layer that is desired to be exposed at the bottom surface of the opening 14), and the information transmitted from the light detection unit 140 and By comparing the information stored in the control unit 150 in advance, it is possible to determine which electrode layer is etched. The controller 150 may store information on the wavelength of light corresponding to all the electrode layer components.

  As shown in FIG. 5, in the etching process of the method for manufacturing the thin film capacitor 1, first, the etching of the multilayer body W is started (etching process S1). During the etching process, the controller 150 analyzes the components included in the plasma (analysis process S2). In the present embodiment, the light of the plasma in the chamber 110 is detected by the light detection unit 140. During the etching, components constituting the electrode layer and the dielectric film 12 ′ of the stacked body W diffuse into the chamber 110. For this reason, the wavelength of the plasma light in the chamber 110 changes in accordance with the component of the layer being etched (in this embodiment, the additive element contained in the electrode layer). For this reason, it is possible to analyze the components contained in the plasma based on the light of the plasma.

  Next, the control unit 150 determines whether or not the component detected in the analysis in the analysis step S2 matches the component of the target electrode layer (that is, the electrode layer desired to be exposed on the bottom surface of the opening 14). (Stop process S3). As a result of the determination, when the component detected in the analysis step S2 does not match the component of the target electrode layer (S3-NO), the control unit 150 determines that the target electrode layer is not exposed, The plasma etching apparatus 100 is controlled so as to continue the etching. As a result of the determination, when the component detected in the analysis step S2 matches the component of the target electrode layer (S3-YES), the control unit 150 determines that the target electrode layer is exposed and performs etching. The plasma etching apparatus 100 is controlled to stop (stop process S4).

  As described above, in the method of manufacturing the thin film capacitor 1 according to the present embodiment, during the etching process, the analysis process for analyzing the components contained in the plasma and the components detected as a result of the analysis process are targeted. And a stopping step of stopping the etching step when it coincides with the component of the electrode layer. Thus, by analyzing the components contained in the plasma during etching, it is possible to determine which electrode layer is being etched. Therefore, it is possible to prevent the electrode layer from being etched excessively by stopping the etching when the target electrode layer component is detected.

  In the analysis step, components contained in the plasma are analyzed based on the wavelength of the plasma light. Thereby, compared with other analysis methods, such as mass spectrometry, the component contained in plasma can be analyzed easily, for example.

  Further, in the thin film capacitor 1, the components of all the electrode layers included in the capacitor portion 10 are different from each other. In this way, when the components of all the electrode layers are different from each other, there is no electrode layer having the same component, so it is possible to more easily determine which electrode layer is etched.

  When the capacitor 10 includes electrode layers having the same component (for example, the internal electrode layer 11A and the internal electrode layer 11C both include Ni as a main component and Ti includes an additive element), the target electrode When the layer is the internal electrode layer 11A, it is possible to determine which electrode layer is etched by counting the number of times the wavelength corresponding to Ti is detected. In this example, the second time when the wavelength corresponding to Ti is detected is the timing at which the internal electrode layer 11A is exposed.

  Further, in the thin film capacitor 1 according to the present embodiment, the components of the electrode layers adjacent in the stacking direction of the capacitor 10 are different from each other. This makes it possible to determine which electrode layer is being etched by analyzing the components contained in the plasma when etching the laminated body W serving as the capacitor 10 in the manufacturing process of the thin film capacitor 1. it can. Therefore, the etching can be stopped at the timing when the target electrode layer is exposed, and the thin film capacitor 1 in which excessive etching of the electrode layer is suppressed can be obtained.

As mentioned above, although embodiment of this invention has been described, this invention is not limited to said embodiment, A various change can be made. For example, in the above embodiment, the case where the capacitance unit 10 of the thin film capacitor 1 includes the two internal electrode layers 11, the three dielectric layers 12, and the one base electrode layer 13 has been described. The numbers of the internal electrode layers 11 and the dielectric layers 12 are not particularly limited and can be arbitrarily changed. For example, the capacitor portion 10 may include one internal electrode layer 11, one dielectric layer 12, and one base electrode layer 13, or more internal electrode layers 11 and dielectric layers 12. You may have. Further, an insulating base material may be provided instead of the base electrode layer 13, and the internal electrode layers 11 and the dielectric layers 12 may be alternately laminated on the insulating base material. As an example, when the capacitor 10 includes five internal electrode layers 11A to 11E and one base electrode layer 13, the components of each electrode layer can be configured as follows.
Base electrode layer 13: Main component Ni (no additional elements)
Internal electrode layer 11A: Main component Ni + added element Ti
Internal electrode layer 11B: Main component Ni + additive element Pd
Internal electrode layer 11C: Main component Ni + additive element Pt
Internal electrode layer 11D: Main component Ni + added element Si
Internal electrode layer 11E: Main component Ni + added element Cr

  Further, in the above embodiment, the example in which the main component of each electrode layer is the same and the components of each electrode layer are different from each other by changing the additive element has been described. However, the main component of each electrode layer is changed. Thus, the components of each electrode layer may be different from each other.

  In the above-described embodiment, the example in which the components of all the electrode layers are different from each other has been described. However, the components of the electrode layers adjacent in the stacking direction may be different from each other. For example, two types of electrode layers having different components may be combined such that the base electrode layer 13 and the internal electrode layer 11B are made of only Ni, and the internal electrode layers 11A and 11C are made of Ni and Ti.

  In the above embodiment, an example of analyzing a component contained in plasma based on the wavelength of plasma light has been described. However, a method for analyzing a component contained in plasma is not particularly limited. For example, components contained in plasma may be analyzed by mass spectrometry or the like. In this case, the component contained in the plasma can be analyzed by attaching a mass analyzer to the plasma etching apparatus 100 instead of the light detection unit 140.

  In the above-described embodiment, the example in which the components of the dielectric layer 12 are all the same has been described. However, the components of the dielectric layers 12 adjacent in the stacking direction may be different from each other. In this case, the timing at which the target electrode layer is exposed can be more reliably determined by determining whether or not the component of the dielectric layer 12 is also included in the plasma. The analysis of the components of the dielectric layer 12 can be performed by the same method as the analysis method of the electrode layer.

  In the above embodiment, the dielectric film 12 'is baked to improve the relative dielectric constant of the dielectric layer 12. However, the dielectric layer 12 may not be baked.

  DESCRIPTION OF SYMBOLS 1 ... Thin film capacitor, 10 ... Capacitance part, 11 ... Internal electrode layer (electrode layer), 12 ... Dielectric layer, 12 '... Dielectric film, 13 ... Base electrode layer (electrode layer), 14 ... Opening, 100 ... Plasma Etching device, W ... laminate.

Claims (4)

A method of manufacturing a thin film capacitor having a plurality of electrode layers and a plurality of dielectric layers, and comprising a capacitor portion in which the electrode layers and the dielectric layers are alternately stacked,
The components of the electrode layers adjacent in the stacking direction of the capacitor portion are different from each other
A stacking step of alternately stacking the plurality of electrode layers and a dielectric film to be the dielectric layer to form a stack to be the capacitor portion;
An etching step of forming an opening extending in the stacking direction by etching the stack using a plasma etching apparatus;
An analysis step of analyzing components contained in the plasma during the etching step;
And a stopping step of stopping the etching when a component detected in the analysis in the analysis step coincides with a target component of the electrode layer.   2. The method of manufacturing a thin film capacitor according to claim 1, wherein in the analyzing step, a component contained in the plasma is analyzed based on a wavelength of light of the plasma.   The method for manufacturing a thin film capacitor according to claim 1, wherein all the electrode layers have different components. It has a plurality of electrode layers and a plurality of dielectric layers, and includes a capacitor portion in which the electrode layers and the dielectric layers are alternately stacked,
A thin film capacitor in which the components of the electrode layers adjacent in the stacking direction of the capacitor portion are different from each other.

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