JP3645808B2 - Thin-film electronic component, its manufacturing method and substrate - Google Patents

Thin-film electronic component, its manufacturing method and substrate Download PDF

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Publication number
JP3645808B2
JP3645808B2 JP2000364769A JP2000364769A JP3645808B2 JP 3645808 B2 JP3645808 B2 JP 3645808B2 JP 2000364769 A JP2000364769 A JP 2000364769A JP 2000364769 A JP2000364769 A JP 2000364769A JP 3645808 B2 JP3645808 B2 JP 3645808B2
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Prior art keywords
hole
thin film
protective film
insulating protective
insulator layer
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JP2001345233A (en
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尚謙 永仮
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Kyocera Corp
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Kyocera Corp
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【0001】
【発明の属する技術分野】
本発明は薄膜電子部品に関し、例えば、薄膜コンデンサに好適に用いられる高周波用途の薄膜電子部品およびその製法並びに基板に関するものである。
【0002】
【従来技術】
近年、電子機器の小型化、高機能化に伴い、電子機器内に設置される電子部品にも小型化、薄型化、高周波対応などの要求が強くなってきている。
【0003】
特に、大量の情報を高速に処理する必要のあるコンピュータの高速デジタル回路では、パーソナルコンピュータレベルにおいても、CPUチップ内のクロック周波数は200MHzから1GHz、チップ間バスのクロック周波数も75MHzから133MHzという具合に高速化が顕著である。
【0004】
また、LSIの集積度が高まりチップ内の素子数の増大につれ、消費電力を抑えるために電源電圧は低下の傾向にある。これらIC回路の高速化、高密度化、低電圧化に伴い、コンデンサ等の受動部品も小型大容量化と併せて、高周波もしくは高速パルスに対して優れた特性を示すことが必須になってきている。コンデンサの小型・大容量化を実現するためには、誘電体層の薄膜化、電極パターンの小型化が有効であり、種々の薄膜コンデンサが提案されている。
【0005】
誘電体層の薄膜化による弊害として、絶縁特性の劣化が懸念される。これら薄膜電子部品の絶縁特性を向上するため、種々の手法が提案されている。例えば、特開平7−183165号公報、特開平8−31951号公報には絶縁体層の微構造を改良し、絶縁体層自身のリーク特性を改良した例が開示されている。また、特開平9−199373号公報には上側電極が絶縁体層端部を被覆しない様なエアブリッジ構造を採用し、絶縁体層端部での絶縁性劣化を改善した例が開示されている。
【0006】
薄膜コンデンサとしては、例えば、図7に示すように、支持基板41上に、絶縁体層43(誘電体薄膜)と下側電極45、上側電極47を有する薄膜素子Aが複数設けられて構成され、絶縁体層43は電極45、47により挟持されて薄膜素子A(容量素子)を構成することが考えられる。
【0007】
また、薄膜素子Aは絶縁性保護膜49で被覆されており、この絶縁性保護膜49には、底面に上側電極47が露出する貫通孔51が形成されている。この貫通孔51内には、ハンダバリア層53を介してハンダバンプからなる外部端子55が形成されている。この薄膜コンデンサでは、上側電極47は、下側電極45との導通を防止するため、貫通孔51の周りが環状に除去され(xで示す)、上側電極47の一部が分割されている。
【0008】
このような薄膜コンデンサは、支持基板上にスパッタリング法、CVD法等の気相合成法を用いて下側電極を形成し、フォトリソグラフィ技術を用いて、パターン加工を行う工程と、パターン加工された下側電極上に、気相合成法やゾルゲル法などで絶縁体層を形成し、フォトリソグラフィを用いてパターン加工する工程と、パターン加工された絶縁体層上に上側電極を形成し、フォトリソグラフィ技術を用いて、パターン加工を行う工程と、上側電極上に絶縁性保護膜を形成する工程と、この絶縁性保護膜に貫通孔を形成し、この貫通孔内に、下側電極および上側電極にそれぞれ電気的に接続する外部端子を形成する工程を経て作製される。
【0009】
【発明が解決しようとする課題】
しかしながら、上述した様な工程で薄膜電子部品を作製する場合、絶縁体層上に上側電極を形成した後、上側電極が下側電極と電気的に接続されないように余分な上側電極をパターン加工して除去していたため、絶縁体層上に上側電極のエッチング残渣が生じ、この絶縁体層上のエッチング残渣による表面リーク電流が発生し、薄膜電子部品の絶縁特性が劣化してしまうという問題があった。
【0010】
本発明は、高容量、高絶縁性を有する小型の薄膜電子部品およびその製法並びに基板を提供することを目的とする。
【0011】
【課題を解決するための手段】
本発明の薄膜電子部品は、支持基板上に、電極が絶縁体層上に形成された薄膜素子を設けるとともに、該薄膜素子を絶縁性保護膜で被覆してなり、該絶縁性保護膜に、前記電極と電気的に接続する外部端子が設けられる貫通孔を形成してなる薄膜電子部品であって、前記貫通孔の周りの前記絶縁体層上に、前記電極を分割する環状の絶縁ダム部が形成されていることを特徴とする。貫通孔の周りの絶縁性保護膜に環状の隆起部が形成されている。
【0013】
このような薄膜電子部品は、支持基板上に、下側電極、絶縁体層を順次積層する工程と、前記絶縁体層に前記下側電極が露出する第1貫通孔および第2貫通孔を形成する工程と、前記第1貫通孔の周りの前記絶縁体層表面に環状の第1絶縁性保護膜を形成する工程と、前記絶縁体層上、並びに前記第1貫通孔および第2貫通孔の内面に上側電極を形成する工程と、該上側電極および前記第1絶縁性保護膜の上面に第2絶縁性保護膜を形成する工程と、該第2絶縁性保護膜における前記第1貫通孔および第2貫通孔の形成位置に、前記上側電極と電気的に接続する外部端子が設けられる貫通孔を形成する工程とを具備する製法により得られる。
【0014】
上側電極は加工した絶縁体層上に直接スパッタ法で形成され、フォトレジストを用いたエッチング加工により、絶縁体層上の上側電極の一部が除去され、絶縁体層上の同一面上に形成された極性の異なる電極間(上側電極と下側電極との間)の電気的な導通が阻止されていたが、本発明では、上側電極の一部を除去していた部分、即ち、下側電極に電気的に接続される外部端子用の貫通孔(第1貫通孔)の周りに、予め環状の第1絶縁性保護膜を形成し、この後、上側電極を形成し、絶縁体層上、並びに第1貫通孔および第2貫通孔の内面だけに上側電極が形成されるよう、第1絶縁性保護膜上の上側電極のみをエッチング加工することにより、絶縁体層上の上側電極の一部(極性の異なる電極間)をエッチング加工する必要がなく、下側電極と確実に絶縁することができ、エッチング残渣による異なる極性の電極間の表面リーク電流の発生を低減でき、これに起因する絶縁不良を防止できる。
【0015】
第1絶縁性保護膜の膜厚は上側電極よりも厚いことが望ましい。上側電極よりも第1絶縁性保護膜の膜厚を大きくすることにより、電極間の障壁の高さが高くなり、異なる極性の電極間の表面リーク電流の発生を防止できる。
【0016】
このように第1絶縁性保護膜の膜厚を上側電極よりも厚くすることにより、下側電極と電気的に接続される外部端子の周りの絶縁性保護膜に環状の隆起部が形成されることになる。
【0017】
絶縁性保護膜に形成された環状の隆起部または絶縁ダム部の高さは2μm以上であることが望ましい。これは、上側電極と第1絶縁性保護膜との高低差が大きくなり、この第1絶縁性保護膜により異なる極性の電極間を確実に絶縁することができるとともに、異なる極性の電極間の表面リーク電流の発生をさらに確実に防止できる。このような隆起部は、第1絶縁性保護膜(絶縁ダム部)の膜厚を上側電極よりも2μm以上厚くすることにより得られる。
【0018】
また、本発明の薄膜電子部品では、絶縁体層非形成領域にハンダバンプからなる外部端子が形成されるため、絶縁体層の厚みに対して非常に大きな外部端子がリフロー時に収縮しても、リフロー工程で生じる外部端子の熱収縮に伴う応力に対して絶縁体層が直接ダメージを受けず、絶縁体層に過大な応力が発生することがなく、絶縁体層におけるクラック発生を防止することができ、クラックに半田が流れ込むことがなく、これにより絶縁性を確保することができ、素子特性を維持した状態で、かつ実装信頼性も確保できる。
【0019】
【発明の実施の形態】
図1は、本発明の薄膜コンデンサからなる薄膜電子部品を示すもので、この薄膜コンデンサは、支持基板1上に、絶縁体層3(誘電体薄膜)と下側電極5、上側電極7を有する薄膜素子Aが複数設けられて構成されている。電極5、7はAuから構成され、絶縁体層3は電極5、7により挟持されて薄膜素子A(容量素子)が構成されている。
【0020】
また、薄膜素子Aは絶縁性保護膜9で被覆されており、この絶縁性保護膜9には、底面に下側電極5または上側電極7が露出する貫通孔11が形成されている。この貫通孔11内には、ハンダバリア層13を介してハンダバンプからなる外部端子15a、15bが突出して形成されている。
【0021】
薄膜コンデンサの誘電体薄膜を構成する絶縁体層3は、高周波領域において高い比誘電率を有するペロブスカイト型酸化物結晶からなる誘電体でよく、例えばPb(Mg,Nb)O3系、Pb(Mg,Nb)O3−PbTiO3系、Pb(Zr,Ti)O3系、Pb(Mg,Nb)O3−Pb(Zr,Ti)O3系、(Pb,La)ZrTiO3系、BaTiO3系、(Sr,Ba)TiO3系、あるいはこれに他の添加物を添加したり、置換した化合物であってもよく、特に限定されるものではない。
【0022】
また、絶縁体層3の膜厚は、高容量と絶縁性を確保するため0.3〜1.0μmが望ましい。これは0.3μmよりも薄い場合には被覆性が低下し、絶縁性が低下する場合があり、1.0μmよりも厚い場合には容量が小さくなる傾向があるからである。絶縁体層3の膜厚は0.4〜0.8μmが望ましい。
【0023】
Auからなる電極5、7の膜厚は、高周波領域でのインピーダンスと膜の被覆性を考慮すると0.3〜0.5μmが望ましい。電極5、7の膜厚が0.3μmよりも薄い場合には、一部に被覆されない部分が発生する虞があるからであり、また0.5μmよりも厚い場合は、高周波領域における導体の表皮効果を考慮すると導体層の抵抗は殆ど変化しないからである。
【0024】
支持基板1としては、アルミナ、サファイア、窒化アルミ、MgO単結晶、SrTiO3単結晶、表面酸化シリコン、ガラス、石英等から選択されるもので特に限定されない。
【0025】
絶縁性保護膜9は、例えば、Si34、SiO2、ポリイミド樹脂、BCB(ベンゾシクロブテン)等から構成されている。
【0026】
ハンダバリア層13は、Ti、Cr、Ni、Cu、Pd、Pt、およびこれらの金属から選ばれる2種以上からなる合金のうちいずれかからなり、スパッタ、蒸着、メッキ等で形成可能であれば良い。ハンダバリア層13の厚みは、ハンダバリアとしての機能を発現するためには0.3μm以上の厚みであればよい。
【0027】
そして、下側電極5は外部端子15bを取り囲むように環状にエッチングされ、容量を形成する下側電極5aと、容量を形成せず、上側電極7に接続する下側電極5bに分割されている。また、上側電極7は、絶縁体層3上において、外部端子15aを取り囲むように環状に形成されていない部分があり、容量を形成する上側電極7aと、容量を形成せず、下側電極5aに接続される上側電極7bに分割されている。上側電極7aと上側電極7bとの間には、絶縁ダム部16が形成されている。薄膜素子Aは下側電極5aと上側電極7aにより、絶縁体層3を挟持して構成されている。下側電極5aと電気的に接続される外部端子15a(貫通孔11)の周りの絶縁性保護膜9には、図1および図2に示すように、リング状の隆起部17が形成されている。この隆起部17の形状は環状であれば良く、円形状、四角形状等、特に限定されない。また、絶縁体層3は、絶縁体層非形成領域Bを除く全面に、下側電極(金属層5bも含む)5および上側電極(金属層7bも含む)7は、環状にエッチングされた部分を除いて全面に形成されている。
【0028】
この隆起部17の高さhは2μm以上であることが望ましい。これは、極性の異なる電極間の障壁の高さを十分に高くできるため、表面リーク電流の発生を確実に防止できるからである。
【0029】
このような薄膜電子部品は、例えば、先ず、図3(a)に示すように、支持基板1上に下側電極5をスパッタ法により形成し、図3(b)に示すように、フォトリソグラフィ技術を用いて下側電極5をパターン加工し、上側電極7に接続される外部端子15bの周りに該当する部分を環状に除去し、下側電極5a、5bを形成する。
【0030】
次に、図3(c)に示すように、全面に、例えば、ゾルゲル法にて合成した塗布溶液を塗布し、乾燥させた後、熱処理して焼成し、絶縁体層3を形成する。この絶縁体層3を、フォトリソグラフィ技術を用いて、図3(d)に示すように、下側電極5が露出するように絶縁体層3を加工し、絶縁体層3に下側電極5が露出する第1貫通孔21および第2貫通孔23を形成する。
【0031】
そして、図3(e)に示すように、第1貫通孔21の周りの絶縁体層3表面、即ち、下側電極5aと接続される外部端子15aの周りに、例えば、感光性のBCB樹脂を塗布し、環状の第1絶縁性保護膜25を形成する。この環状の第1絶縁性保護膜25は、全面にBCB樹脂を塗布し、露光現像することにより形成でき、絶縁ダム部16となる。
【0032】
次に、第1絶縁性保護膜25表面、絶縁体層3表面、並びに第1貫通孔21および第2貫通孔23の内面に上側電極7を形成し、第1絶縁性保護膜25表面の上側電極7をフォトリソグラフィ技術を用いて除去し、図3(f)に示すような上側電極7a、7bを形成する。
【0033】
この後、図3(g)に示すように、上側電極7および第1絶縁性保護膜25の上面に、例えば、感光性のBCB樹脂を塗布して第2絶縁性保護膜9を形成する。これにより第1絶縁性保護膜25が形成された部分では、第2絶縁性保護膜9が隆起し、隆起部17を形成することになる。尚、第1絶縁性保護膜25と第2絶縁性保護膜9は一体となる。
【0034】
この後、図3(h)に示すように、第2絶縁性保護膜9における第1貫通孔21および第2貫通孔23の形成位置に、露光、現像により上側電極7が露出する貫通孔11を形成し、この貫通孔11内面に、図3(i)に示すように、例えば、蒸着法によりハンダバリア層13を形成し、例えば、スクリーン印刷を用いて共晶半田ペーストを印刷し、リフローを行い、半田バンプからなる外部端子15a、15bを形成することにより、本発明の薄膜コンデンサが作製される。
【0035】
本発明の基板は、図4に示すように、上記のようにして構成された薄膜電子部品30の外部端子15を、絶縁材料からなる基体31の表面に形成された電極33に接続して構成されている。
【0036】
また、上記例では、本発明を薄膜コンデンサに適用した例について説明したが、本発明では上記例に限定されるものではなく、例えば、薄膜インダクタ、薄膜LCフィルタ、薄膜抵抗、薄膜RCフィルタ、あるいは、薄膜コンデンサ、薄膜インダクタ、薄膜LCフィルタ、薄膜抵抗、薄膜RCフィルタを複合した薄膜複合部品に適用しても良い。
【0037】
また、上記例では、一層の絶縁体層を電極で挟持した単板型を示したが、複数の絶縁体層と電極とを交互に積層した積層型の薄膜コンデンサであっても良い。
【0038】
さらに、本発明の薄膜電子部品では、半田バンプからなる外部端子15a、15bを保護膜9の貫通孔11に設けた例について説明したが、本発明は上記例に限定されるものではなく、要旨を変更しない範囲で変更できる。
【0039】
例えば、半田バンプを形成しない場合には、図5に示すように、保護膜9の貫通孔11内に形成されたハンダバリア層13が外部端子となる。尚、図5は、半田バンプからなる外部端子を設けない以外は、図1と同一であるため同一符号を付した。
【0040】
この場合には、母基板に実装する段階で導電性部材により、母基板の表面電極とハンダバリア層13が接続される。導電性部材としては、形状的には、バンプ状、箔状、板状、ワイヤ、ペースト状等があり、特に限定されるものではなく、複数の形状を組合せても良い。また、材質は、Pb、Sn、Au、Cu、Pt、Pd、Ag、Al、Ni、Bi、In、Sb、Znなどがあり、導電性のものであれば良く、複数の材料を組合せても良い。導電性樹脂であっても良い。
【0041】
尚、ハンダバリア層13が形成されない場合や、ハンダバリア層13の上面に半田密着層が形成される場合には、保護膜9の貫通孔内に露出した層が外部端子となる。
【0042】
【実施例】
電極ならびにハンダバリア層の形成は高周波マグネトロンスパッタ法にて、絶縁体層はゾルゲル法にて作製した。
【0043】
先ず、アルミナからなる支持基板上にTiからなる3nmの密着層を形成し、この密着層の上面に、0.3μmのAu層を形成し、密着層とAu層からなる下側電極とした。
【0044】
フォトリソグラフィ技術を用いて下側電極をパターン加工した。加工された下側電極に、ゾルゲル法にて合成したPb(Mg1/3Nb2/3)O3−PbTiO3−PbZrO3塗布溶液をスピンコート法を用いて塗布し、乾燥させた後、380℃で熱処理、815℃で焼成を行い、膜厚0.7μmのPb(Mg1/3Nb2/3)O3−PbTiO3−PbZrO3からなる絶縁体層を形成した。その後フォトリソグラフィ技術を用いて、下側電極が露出するように、絶縁体層を加工し、第1貫通孔、第2貫通孔を形成した。
【0045】
次に感光性のBCB樹脂を絶縁体層上に塗布・成膜し、上側電極の形成部分が露出するようなネガパターンで加工し、厚み2μmの第1絶縁性保護膜(絶縁ダム部)を形成した。
【0046】
次に、絶縁体層表面、第1絶縁性保護膜表面、第1貫通孔および第2貫通孔の内面に、膜厚30nmのTiからなる密着層と膜厚0.3μmのAu層を形成し、フォトリソグラフィ技術を用いて、第1絶縁性保護膜表面のAu層とTi層を除去し、上側電極とした。
【0047】
この後、再度光感光性BCBを全面に塗布し、露光、現像を行い、上側電極のAu層が露出するように、直径約100μm、深さ1μmの貫通孔を有する第2絶縁性保護膜を形成した。この時点で、薄膜コンデンサには、高さhが2μmの環状の隆起部が形成されていた。
【0048】
第2絶縁性保護膜上および貫通孔内に、膜厚1.5μmのハンダバリア層を形成し、この後、膜厚0.1μmの半田密着層Auを形成し、貫通孔の内壁面、および保護膜表面における貫通孔周囲が残留するように、貫通孔を中心に直径120μmの形状にフォトリソグラフィを用いて加工した。
【0049】
最後に、スクリーン印刷を用いて半田密着層上にPbが63重量%、Snが37重量%からなる共晶半田ペーストを転写し、リフローを行い、半田バンプからなる外部端子を形成し、図1に示したような薄膜コンデンサを得た。
【0050】
得られた薄膜コンデンサの有効電極面積は1.4mm2であり、周波数1kHzでの静電容量は約40nFであった。
【0051】
比較例として、図7に示した様な、第1絶縁性保護膜を形成せず、上側電極の一部をエッチングすることにより異なる極性の電極間を離間した薄膜コンデンサを作製した。この薄膜コンデンサには、環状の隆起部は形成されなかった。
【0052】
両者の構造の違いを比較するため、大気中(室温・湿度60%)でのリーク電流−電界強度との関係を評価した。その結果を図6に示す。
【0053】
図6によると、本発明の薄膜コンデンサにおいては、電界強度が約100V/μmで破壊するのに対し、比較例の薄膜コンデンサでは、高々50V/μmと低く、かつバラツキも大きいことが判る。この様に、本発明の薄膜コンデンサでは高い絶縁性を確保できることが判る。
【0054】
また、第1絶縁性保護膜の厚みを3μmとする以外は、上記と同様にして薄膜コンデンサを作製したところ、上記と同様高い破壊電圧強度を有していた。
【0055】
【発明の効果】
以上の詳述したように、本発明によれば、下側電極に電気的に接続される外部端子用の貫通孔の周りに、予め環状の第1絶縁性保護膜(絶縁ダム部)を形成し、この後、受動素子を形成する絶縁体層上、並びに第1貫通孔および第2貫通孔の内面だけに上側電極が形成されるよう、第1絶縁性保護膜上の上側電極のみがエッチング加工されるため、絶縁体層上の上側電極の一部(極性の異なる電極間)をエッチング加工する必要がなく、異なる極性の電極間を確実に絶縁することができ、エッチング残渣による異なる極性の電極間の表面リーク電流の発生を防止でき、これに起因する絶縁不良を防止できる。
【図面の簡単な説明】
【図1】本発明の薄膜電子部品の断面図である。
【図2】図1の平面図である。
【図3】本発明の薄膜電子部品の製法を説明するための工程図である。
【図4】本発明の基板を示す断面図である。
【図5】ハンダバリア層が外部端子となる場合の本発明の薄膜電子部品を示す断面図である。
【図6】リーク電流−破壊電圧との関係を示すグラフである。
【図7】薄膜電子部品を示す断面図である。
【符号の説明】
1・・・支持基板
3・・・絶縁体層
5、7・・電極
9・・・第2絶縁性保護膜
11・・・貫通孔
15・・・外部端子
17・・・隆起部
16・・・絶縁ダム部
21・・・第1貫通孔
23・・・第2貫通孔
25・・・第1絶縁性保護膜
30・・・薄膜コンデンサ
31・・・基体
A・・・薄膜素子
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film electronic component, for example, a high frequency thin film electronic component suitably used for a thin film capacitor, a manufacturing method thereof, and a substrate.
[0002]
[Prior art]
In recent years, with the downsizing and high functionality of electronic devices, there has been an increasing demand for downsizing, thinning, and high frequency compatibility for electronic components installed in electronic devices.
[0003]
In particular, in a high-speed digital circuit of a computer that needs to process a large amount of information at high speed, even at the personal computer level, the clock frequency in the CPU chip is 200 MHz to 1 GHz, the clock frequency of the inter-chip bus is 75 MHz to 133 MHz, and so on. The speedup is remarkable.
[0004]
As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to reduce power consumption. As these IC circuits increase in speed, density, and voltage, passive components such as capacitors have become essential to exhibit excellent characteristics for high-frequency or high-speed pulses in conjunction with downsizing and large capacity. Yes. In order to reduce the size and increase the capacity of the capacitor, it is effective to reduce the thickness of the dielectric layer and the electrode pattern, and various thin film capacitors have been proposed.
[0005]
As an adverse effect of thinning the dielectric layer, there is a concern about deterioration of insulation characteristics. Various techniques have been proposed to improve the insulation characteristics of these thin-film electronic components. For example, JP-A-7-183165 and JP-A-8-31951 disclose examples in which the microstructure of the insulator layer is improved and the leak characteristics of the insulator layer itself are improved. Japanese Patent Application Laid-Open No. 9-199373 discloses an example in which an air bridge structure is employed in which the upper electrode does not cover the end portion of the insulator layer to improve the insulation deterioration at the end portion of the insulator layer. .
[0006]
As the thin film capacitor, for example, as shown in FIG. 7, a plurality of thin film elements A having an insulating layer 43 (dielectric thin film), a lower electrode 45, and an upper electrode 47 are provided on a support substrate 41. It is conceivable that the insulator layer 43 is sandwiched between the electrodes 45 and 47 to form the thin film element A (capacitance element).
[0007]
The thin film element A is covered with an insulating protective film 49, and the insulating protective film 49 has a through hole 51 in which the upper electrode 47 is exposed on the bottom surface. In the through hole 51, an external terminal 55 made of a solder bump is formed via a solder barrier layer 53. In this thin film capacitor, the upper electrode 47 is annularly removed around the through hole 51 (indicated by x) to prevent conduction with the lower electrode 45, and a part of the upper electrode 47 is divided.
[0008]
In such a thin film capacitor, a lower electrode is formed on a supporting substrate using a vapor phase synthesis method such as a sputtering method or a CVD method, and a pattern processing is performed using a photolithography technique. An insulator layer is formed on the lower electrode by a vapor phase synthesis method or a sol-gel method, and a pattern process is performed using photolithography. An upper electrode is formed on the patterned insulator layer, and photolithography is performed. A step of performing pattern processing using a technique, a step of forming an insulating protective film on the upper electrode, a through hole is formed in the insulating protective film, and a lower electrode and an upper electrode are formed in the through hole. Each is manufactured through a step of forming external terminals that are electrically connected to each other.
[0009]
[Problems to be solved by the invention]
However, when a thin film electronic component is manufactured by the process as described above, after forming the upper electrode on the insulator layer, the excess upper electrode is patterned so that the upper electrode is not electrically connected to the lower electrode. As a result, an etching residue of the upper electrode is generated on the insulator layer, a surface leakage current is generated due to the etching residue on the insulator layer, and the insulating characteristics of the thin film electronic component are deteriorated. It was.
[0010]
An object of the present invention is to provide a small-sized thin-film electronic component having a high capacity and high insulation, a method for manufacturing the same, and a substrate.
[0011]
[Means for Solving the Problems]
The thin film electronic component of the present invention is provided with a thin film element in which an electrode is formed on an insulator layer on a support substrate, and the thin film element is covered with an insulating protective film. A thin-film electronic component formed by forming a through hole in which an external terminal electrically connected to the electrode is provided , and an annular insulating dam portion that divides the electrode on the insulator layer around the through hole Is formed. An annular raised portion is formed in the insulating protective film around the through hole.
[0013]
In such a thin film electronic component, a step of sequentially laminating a lower electrode and an insulator layer on a support substrate, and a first through hole and a second through hole in which the lower electrode is exposed in the insulator layer are formed. A step of forming an annular first insulating protective film on the surface of the insulator layer around the first through-hole, and the step of forming the first through-hole and the second through-hole on the insulator layer Forming an upper electrode on the inner surface; forming a second insulating protective film on the upper surface of the upper electrode and the first insulating protective film; and the first through-holes in the second insulating protective film; And a step of forming a through hole in which an external terminal electrically connected to the upper electrode is provided at a position where the second through hole is formed.
[0014]
The upper electrode is formed directly on the processed insulator layer by sputtering, and a part of the upper electrode on the insulator layer is removed by etching using a photoresist and formed on the same surface on the insulator layer. However, in the present invention, a portion from which a part of the upper electrode is removed, that is, the lower side, is prevented from being electrically connected between the electrodes having different polarities (between the upper electrode and the lower electrode). An annular first insulating protective film is formed in advance around a through hole (first through hole) for an external terminal that is electrically connected to the electrode, and then an upper electrode is formed on the insulator layer. Further, only the upper electrode on the first insulating protective film is etched so that the upper electrode is formed only on the inner surfaces of the first through hole and the second through hole. There is no need to etch parts (between electrodes of different polarity) And can reliably be insulated, it is possible to reduce the occurrence of surface leak current between electrodes of different polarities due to etching residues, insulation failure can be prevented due to this.
[0015]
The film thickness of the first insulating protective film is desirably thicker than that of the upper electrode. By making the film thickness of the first insulating protective film larger than that of the upper electrode, the height of the barrier between the electrodes is increased, and the occurrence of surface leakage current between electrodes of different polarities can be prevented.
[0016]
Thus, by making the film thickness of the first insulating protective film thicker than that of the upper electrode, an annular ridge is formed in the insulating protective film around the external terminal electrically connected to the lower electrode. It will be.
[0017]
It is desirable that the height of the annular raised portion or insulating dam portion formed on the insulating protective film is 2 μm or more. This is because the difference in height between the upper electrode and the first insulating protective film is large, and the electrodes having different polarities can be reliably insulated by the first insulating protective film, and the surface between the electrodes having different polarities can be obtained. Generation of leakage current can be prevented more reliably. Such a raised portion can be obtained by making the thickness of the first insulating protective film (insulating dam portion) 2 μm or more thicker than the upper electrode.
[0018]
Further, in the thin film electronic component of the present invention, since the external terminals made of solder bumps are formed in the insulator layer non-formation region, even if an external terminal that is very large relative to the thickness of the insulator layer contracts during reflow, reflow The insulator layer is not directly damaged by the stress caused by the thermal contraction of the external terminals that occur in the process, so that excessive stress is not generated in the insulator layer and cracks in the insulator layer can be prevented. In addition, solder does not flow into the crack, thereby ensuring insulation, maintaining device characteristics, and ensuring mounting reliability.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a thin film electronic component comprising a thin film capacitor of the present invention. This thin film capacitor has an insulating layer 3 (dielectric thin film), a lower electrode 5 and an upper electrode 7 on a support substrate 1. A plurality of thin film elements A are provided. The electrodes 5 and 7 are made of Au, and the insulator layer 3 is sandwiched between the electrodes 5 and 7 to form a thin film element A (capacitance element).
[0020]
The thin film element A is covered with an insulating protective film 9, and the insulating protective film 9 has a through-hole 11 in which the lower electrode 5 or the upper electrode 7 is exposed on the bottom surface. In the through hole 11, external terminals 15 a and 15 b made of solder bumps are formed so as to protrude through the solder barrier layer 13.
[0021]
The insulator layer 3 constituting the dielectric thin film of the thin film capacitor may be a dielectric made of a perovskite type oxide crystal having a high relative dielectric constant in a high frequency region. For example, Pb (Mg, Nb) O 3 type, Pb (Mg) , Nb) O 3 —PbTiO 3 system, Pb (Zr, Ti) O 3 system, Pb (Mg, Nb) O 3 —Pb (Zr, Ti) O 3 system, (Pb, La) ZrTiO 3 system, BaTiO 3 It may be a system, (Sr, Ba) TiO 3 system, or a compound in which other additives are added or substituted thereto, and is not particularly limited.
[0022]
The film thickness of the insulator layer 3 is preferably 0.3 to 1.0 μm in order to ensure high capacity and insulation. This is because when the thickness is smaller than 0.3 μm, the covering property may be lowered and the insulating property may be lowered. When the thickness is larger than 1.0 μm, the capacity tends to be smaller. The film thickness of the insulator layer 3 is preferably 0.4 to 0.8 μm.
[0023]
The film thickness of the electrodes 5 and 7 made of Au is preferably 0.3 to 0.5 μm in consideration of impedance in the high frequency region and film coverage. This is because when the thickness of the electrodes 5 and 7 is thinner than 0.3 μm, there is a possibility that a portion that is not partially covered may occur, and when it is thicker than 0.5 μm, the skin of the conductor in the high frequency region. This is because the resistance of the conductor layer hardly changes in consideration of the effect.
[0024]
The support substrate 1 is not particularly limited as it is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO 3 single crystal, surface silicon oxide, glass, quartz and the like.
[0025]
The insulating protective film 9 is made of, for example, Si 3 N 4 , SiO 2 , polyimide resin, BCB (benzocyclobutene), or the like.
[0026]
The solder barrier layer 13 is made of any one of Ti, Cr, Ni, Cu, Pd, Pt, and an alloy of two or more selected from these metals, and can be formed by sputtering, vapor deposition, plating, or the like. good. The thickness of the solder barrier layer 13 may be 0.3 μm or more in order to exhibit a function as a solder barrier.
[0027]
The lower electrode 5 is annularly etched so as to surround the external terminal 15b, and is divided into a lower electrode 5a that forms a capacitor and a lower electrode 5b that does not form a capacitor and is connected to the upper electrode 7. . Further, the upper electrode 7 has a portion which is not formed in an annular shape so as to surround the external terminal 15a on the insulator layer 3, and the upper electrode 7a which forms a capacitance, and the lower electrode 5a which does not form a capacitance. Is divided into upper electrodes 7b connected to each other. An insulating dam portion 16 is formed between the upper electrode 7a and the upper electrode 7b. The thin film element A is configured by sandwiching the insulator layer 3 between a lower electrode 5a and an upper electrode 7a. As shown in FIGS. 1 and 2, a ring-shaped raised portion 17 is formed on the insulating protective film 9 around the external terminal 15a (through hole 11) electrically connected to the lower electrode 5a. Yes. The shape of the raised portion 17 may be an annular shape, and is not particularly limited to a circular shape, a square shape, or the like. Further, the insulator layer 3 is a portion where the lower electrode (including the metal layer 5b) 5 and the upper electrode (including the metal layer 7b) 7 are annularly etched on the entire surface except the insulator layer non-forming region B. It is formed on the entire surface except for.
[0028]
The height h of the raised portion 17 is preferably 2 μm or more. This is because the height of the barrier between electrodes of different polarities can be made sufficiently high, so that the occurrence of surface leakage current can be reliably prevented.
[0029]
In such a thin film electronic component, for example, first, as shown in FIG. 3A, the lower electrode 5 is formed on the support substrate 1 by sputtering, and as shown in FIG. The lower electrode 5 is patterned using a technique, and a portion corresponding to the periphery of the external terminal 15b connected to the upper electrode 7 is annularly removed to form the lower electrodes 5a and 5b.
[0030]
Next, as shown in FIG. 3C, a coating solution synthesized by, for example, a sol-gel method is applied to the entire surface, dried, and then heat-treated and baked to form the insulator layer 3. As shown in FIG. 3D, the insulator layer 3 is processed using the photolithography technique so that the lower electrode 5 is exposed, and the lower electrode 5 is formed on the insulator layer 3. The 1st through-hole 21 and the 2nd through-hole 23 which are exposed are formed.
[0031]
Then, as shown in FIG. 3E, for example, photosensitive BCB resin is formed around the surface of the insulating layer 3 around the first through hole 21, that is, around the external terminal 15a connected to the lower electrode 5a. Is applied to form an annular first insulating protective film 25. The annular first insulating protective film 25 can be formed by applying BCB resin to the entire surface, exposing and developing, and becomes the insulating dam portion 16.
[0032]
Next, the upper electrode 7 is formed on the surface of the first insulating protective film 25, the surface of the insulator layer 3, and the inner surfaces of the first through hole 21 and the second through hole 23, and the upper side of the surface of the first insulating protective film 25. The electrode 7 is removed using a photolithography technique to form upper electrodes 7a and 7b as shown in FIG.
[0033]
Thereafter, as shown in FIG. 3G, for example, a photosensitive BCB resin is applied to the upper surfaces of the upper electrode 7 and the first insulating protective film 25 to form the second insulating protective film 9. As a result, the second insulating protective film 9 is raised at the portion where the first insulating protective film 25 is formed, and the raised portion 17 is formed. The first insulating protective film 25 and the second insulating protective film 9 are integrated.
[0034]
Thereafter, as shown in FIG. 3 (h), the through hole 11 in which the upper electrode 7 is exposed by exposure and development at the position where the first through hole 21 and the second through hole 23 are formed in the second insulating protective film 9. As shown in FIG. 3 (i), for example, a solder barrier layer 13 is formed on the inner surface of the through-hole 11 by vapor deposition, and eutectic solder paste is printed using screen printing, for example. The thin film capacitor of the present invention is manufactured by forming external terminals 15a and 15b made of solder bumps.
[0035]
As shown in FIG. 4, the substrate of the present invention is configured by connecting the external terminal 15 of the thin film electronic component 30 configured as described above to an electrode 33 formed on the surface of a base 31 made of an insulating material. Has been.
[0036]
In the above example, the example in which the present invention is applied to a thin film capacitor has been described. However, the present invention is not limited to the above example, and for example, a thin film inductor, a thin film LC filter, a thin film resistor, a thin film RC filter, The thin film capacitor, thin film inductor, thin film LC filter, thin film resistor, and thin film RC filter may be applied to a thin film composite component.
[0037]
In the above example, a single plate type in which one insulator layer is sandwiched between electrodes is shown, but a multilayer thin film capacitor in which a plurality of insulator layers and electrodes are alternately stacked may be used.
[0038]
Furthermore, in the thin film electronic component of the present invention, the example in which the external terminals 15a and 15b made of solder bumps are provided in the through hole 11 of the protective film 9 has been described. However, the present invention is not limited to the above example, and Can be changed without changing
[0039]
For example, when solder bumps are not formed, as shown in FIG. 5, the solder barrier layer 13 formed in the through hole 11 of the protective film 9 serves as an external terminal. Since FIG. 5 is the same as FIG. 1 except that an external terminal made of a solder bump is not provided, the same reference numeral is assigned.
[0040]
In this case, the surface electrode of the mother board and the solder barrier layer 13 are connected by the conductive member at the stage of mounting on the mother board. Examples of the conductive member include a bump shape, a foil shape, a plate shape, a wire, and a paste shape. The conductive member is not particularly limited, and a plurality of shapes may be combined. Moreover, there are materials such as Pb, Sn, Au, Cu, Pt, Pd, Ag, Al, Ni, Bi, In, Sb, and Zn, and any material may be used as long as it is conductive. good. A conductive resin may be used.
[0041]
When the solder barrier layer 13 is not formed, or when a solder adhesion layer is formed on the upper surface of the solder barrier layer 13, the layer exposed in the through hole of the protective film 9 becomes an external terminal.
[0042]
【Example】
The electrodes and the solder barrier layer were formed by a high-frequency magnetron sputtering method, and the insulator layer was formed by a sol-gel method.
[0043]
First, a 3 nm adhesion layer made of Ti was formed on a support substrate made of alumina, and a 0.3 μm Au layer was formed on the upper surface of the adhesion layer to form a lower electrode made of the adhesion layer and the Au layer.
[0044]
The lower electrode was patterned using photolithography technology. A Pb (Mg 1/3 Nb 2/3 ) O 3 —PbTiO 3 —PbZrO 3 coating solution synthesized by a sol-gel method is applied to the processed lower electrode using a spin coating method and dried. Heat treatment was performed at 380 ° C. and firing was performed at 815 ° C. to form an insulator layer made of Pb (Mg 1/3 Nb 2/3 ) O 3 —PbTiO 3 —PbZrO 3 having a thickness of 0.7 μm. Thereafter, the insulator layer was processed using a photolithography technique so that the lower electrode was exposed to form the first through hole and the second through hole.
[0045]
Next, a photosensitive BCB resin is applied and formed on the insulator layer, processed with a negative pattern that exposes the formation portion of the upper electrode, and a first insulating protective film (insulating dam portion) having a thickness of 2 μm is formed. Formed.
[0046]
Next, an adhesion layer made of Ti with a thickness of 30 nm and an Au layer with a thickness of 0.3 μm are formed on the surface of the insulator layer, the surface of the first insulating protective film, the inner surfaces of the first through hole and the second through hole. The Au layer and the Ti layer on the surface of the first insulating protective film were removed using a photolithography technique to form an upper electrode.
[0047]
Thereafter, a photosensitive BCB is again applied to the entire surface, exposed and developed, and a second insulating protective film having a through hole having a diameter of about 100 μm and a depth of 1 μm is exposed so that the Au layer of the upper electrode is exposed. Formed. At this time, an annular ridge having a height h of 2 μm was formed in the thin film capacitor.
[0048]
A solder barrier layer having a thickness of 1.5 μm is formed on the second insulating protective film and in the through hole, and thereafter, a solder adhesion layer Au having a thickness of 0.1 μm is formed, and the inner wall surface of the through hole, and The periphery of the through hole on the surface of the protective film was processed using photolithography into a shape having a diameter of 120 μm around the through hole.
[0049]
Finally, eutectic solder paste composed of 63% by weight of Pb and 37% by weight of Sn is transferred onto the solder adhesion layer using screen printing, and reflow is performed to form external terminals composed of solder bumps. A thin film capacitor as shown in FIG.
[0050]
The effective electrode area of the obtained thin film capacitor was 1.4 mm 2 , and the capacitance at a frequency of 1 kHz was about 40 nF.
[0051]
As a comparative example, as shown in FIG. 7, the first insulating protective film was not formed, and a thin film capacitor in which electrodes having different polarities were separated by etching a part of the upper electrode was manufactured. This thin film capacitor did not have an annular ridge.
[0052]
In order to compare the difference in structure between the two, the relationship between leakage current and electric field strength in the atmosphere (room temperature and humidity 60%) was evaluated. The result is shown in FIG.
[0053]
According to FIG. 6, the electric field strength of the thin film capacitor of the present invention is broken at about 100 V / μm, whereas the thin film capacitor of the comparative example is at most as low as 50 V / μm and has a large variation. Thus, it can be seen that the thin film capacitor of the present invention can ensure high insulation.
[0054]
Further, when a thin film capacitor was produced in the same manner as described above except that the thickness of the first insulating protective film was 3 μm, it had a high breakdown voltage strength as described above.
[0055]
【The invention's effect】
As described above in detail, according to the present invention, the annular first insulating protective film (insulating dam portion) is formed in advance around the through hole for the external terminal that is electrically connected to the lower electrode. Thereafter, only the upper electrode on the first insulating protective film is etched so that the upper electrode is formed only on the insulator layer forming the passive element and on the inner surfaces of the first through hole and the second through hole. Because it is processed, it is not necessary to etch part of the upper electrode on the insulator layer (between electrodes of different polarities), it is possible to reliably insulate between electrodes of different polarities, Generation of surface leakage current between the electrodes can be prevented, and insulation failure caused by this can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a thin film electronic component of the present invention.
2 is a plan view of FIG. 1. FIG.
FIG. 3 is a process diagram for explaining a method of manufacturing a thin film electronic component of the present invention.
FIG. 4 is a cross-sectional view showing a substrate of the present invention.
FIG. 5 is a cross-sectional view showing a thin film electronic component of the present invention when a solder barrier layer serves as an external terminal.
FIG. 6 is a graph showing the relationship between leakage current and breakdown voltage.
FIG. 7 is a cross-sectional view showing a thin film electronic component.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Support substrate 3 ... Insulator layer 5, 7, ... Electrode 9 ... 2nd insulating protective film 11 ... Through-hole 15 ... External terminal 17 ... Raised part 16 ... · Insulation dam portion 21 ··· first through hole 23 ··· second through hole 25 ··· first insulating protective film 30 ··· thin film capacitor 31 ··· substrate A · · · thin film element

Claims (7)

支持基板上に、電極が絶縁体層上に形成された薄膜素子を設けるとともに、該薄膜素子を絶縁性保護膜で被覆してなり、該絶縁性保護膜に、前記電極と電気的に接続する外部端子が設けられる貫通孔を形成してなる薄膜電子部品であって、前記貫通孔の周りの前記絶縁体層上に、前記電極を分割する環状の絶縁ダム部が形成されていることを特徴とする薄膜電子部品。A thin film element in which an electrode is formed on an insulator layer is provided on a support substrate, and the thin film element is covered with an insulating protective film, and is electrically connected to the insulating protective film with the electrode. A thin-film electronic component formed with a through hole in which an external terminal is provided, wherein an annular insulating dam portion for dividing the electrode is formed on the insulator layer around the through hole. Thin film electronic components. 貫通孔の周りの絶縁性保護膜に環状の隆起部が形成されていることを特徴とする請求項1記載の薄膜電子部品。 2. The thin film electronic component according to claim 1 , wherein an annular raised portion is formed in the insulating protective film around the through hole . 貫通孔内に電極と電気的に接続される外部端子が形成されており、該外部端子が絶縁性保護膜から突出していることを特徴とする請求項1または2記載の薄膜電子部品。3. The thin-film electronic component according to claim 1, wherein an external terminal electrically connected to the electrode is formed in the through hole, and the external terminal protrudes from the insulating protective film. 隆起部の高さは2μm以上であることを特徴とする請求項記載の薄膜電子部品。Thin film electronic component according to claim 2, wherein the height of the raised portion is 2μm or more. 支持基板上に、下側電極、絶縁体層を順次積層する工程と、前記絶縁体層に前記下側電極が露出する第1貫通孔および第2貫通孔を形成する工程と、前記第1貫通孔の周りの前記絶縁体層表面に環状の第1絶縁性保護膜を形成する工程と、前記絶縁体層上、並びに前記第1貫通孔および第2貫通孔の内面に上側電極を形成する工程と、該上側電極および前記第1絶縁性保護膜の上面に第2絶縁性保護膜を形成する工程と、該第2絶縁性保護膜における前記第1貫通孔および第2貫通孔の形成位置に、前記上側電極と電気的に接続する外部端子が設けられる貫通孔を形成する工程とを具備することを特徴とする薄膜電子部品の製法。A step of sequentially laminating a lower electrode and an insulator layer on a support substrate, a step of forming a first through hole and a second through hole in which the lower electrode is exposed in the insulator layer, and the first through hole Forming an annular first insulating protective film on the surface of the insulator layer around a hole; and forming an upper electrode on the insulator layer and on the inner surfaces of the first and second through holes. A step of forming a second insulating protective film on the upper surface of the upper electrode and the first insulating protective film, and a position where the first through hole and the second through hole are formed in the second insulating protective film. And a step of forming a through-hole in which an external terminal electrically connected to the upper electrode is provided. 第1絶縁性保護膜の膜厚は上側電極よりも厚いことを特徴とする請求項5記載の薄膜電子部品の製法。6. The method of manufacturing a thin film electronic component according to claim 5, wherein the thickness of the first insulating protective film is thicker than that of the upper electrode. 絶縁材料からなる基体の表面に、請求項1乃至4のうちいずれかに記載の薄膜電子部品を設けてなることを特徴とする基板。5. A substrate comprising the thin film electronic component according to claim 1 provided on a surface of a base made of an insulating material.
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