WO2018032327A1 - 一种电流采样保持电路及信号采集系统 - Google Patents

一种电流采样保持电路及信号采集系统 Download PDF

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WO2018032327A1
WO2018032327A1 PCT/CN2016/095465 CN2016095465W WO2018032327A1 WO 2018032327 A1 WO2018032327 A1 WO 2018032327A1 CN 2016095465 W CN2016095465 W CN 2016095465W WO 2018032327 A1 WO2018032327 A1 WO 2018032327A1
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Prior art keywords
current
mos transistor
type mos
circuit
drain
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PCT/CN2016/095465
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English (en)
French (fr)
Inventor
张孟文
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深圳市汇顶科技股份有限公司
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Priority to KR1020177023792A priority Critical patent/KR101947303B1/ko
Priority to EP16890897.8A priority patent/EP3486912B1/en
Priority to PCT/CN2016/095465 priority patent/WO2018032327A1/zh
Priority to CN201680000741.7A priority patent/CN106415282B/zh
Priority to US15/690,333 priority patent/US10186328B2/en
Publication of WO2018032327A1 publication Critical patent/WO2018032327A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0046—Arrangements for measuring currents or voltages or for indicating presence or sign thereof characterised by a specific application or detail not covered by any other subgroup of G01R19/00
    • G01R19/0053—Noise discrimination; Analog sampling; Measuring transients
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H03F3/45753—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/028—Current mode circuits, e.g. switched current memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45273—Mirror types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors

Definitions

  • the present application relates to the field of current sampling and holding technology, and in particular, to a current sampling and holding circuit and a signal collecting system.
  • the current type sensor 11 outputs an alternating current portion of the current, so that the cancel circuit 12 is usually added to acquire and cancel the direct current component of the current output from the current type sensor 11.
  • the limited settling time of the cancellation circuit 12 can affect the latency of subsequent circuits, thereby reducing the efficiency of the overall acquisition system.
  • the first switch S1 when the first enable signal sh is high, the first switch S1 is closed, and at this time, the gate and the drain of the first P-type MOS transistor M1 are short-circuited, so the first P-type MOS transistor M1 Equivalent to a resistance of 1/gm1, gm1 is the transconductance of the first P-type MOS transistor M1.
  • the time constant ⁇ 1 will be very large, so that the settling speed of the canceling circuit 12 becomes slow.
  • the bias current source I1 in order to speed up the establishment speed of the cancellation circuit 12, it is common practice to increase the bias current source I1 so that the direct current flowing through the first P-type MOS transistor M1 is increased, thereby increasing the first P-type MOS transistor.
  • the transconductance gm1 of M1 eventually causes the time constant ⁇ 1 to decrease to speed up the establishment of the cancellation circuit 12.
  • the increased bias current introduces a large amount of current noise, which affects the signal-to-noise ratio of the signal acquisition system.
  • the present application provides a current sample and hold circuit and a signal acquisition system, The above technical problem is solved in whole or in part.
  • a current sample and hold circuit comprising:
  • the cancellation circuit is connected in series between the VDD terminal and the current type sensor, and is turned on according to the first enable signal, and the output current cancels the DC current component in the current type sensor;
  • a mirror circuit connected in parallel with the series-connected cancellation circuit and the current-type sensor between the VDD terminal and the ground voltage, and being turned on according to a second enable signal opposite to the first enable signal, Current is transmitted by the mirror current of the shunt current and the current difference obtained by the output current of the current sensor.
  • a signal acquisition system having a current sample and hold circuit, comprising: a current sample and hold circuit and a current type sensor, the current sample and hold circuit comprising:
  • the cancellation circuit is connected in series between the VDD terminal and the current type sensor, and is turned on according to the first enable signal, and the output current cancels the DC current component in the current type sensor;
  • a mirror circuit connected in parallel with the series-connected cancellation circuit and the current-type sensor between the VDD terminal and the ground voltage, and being turned on according to a second enable signal opposite to the first enable signal, Current is transmitted by the mirror current of the shunt current and the current difference obtained by the output current of the current sensor.
  • the current sample-and-hold circuit and the signal acquisition system provided by the present application maintain a large current of each current branch connected to the current-type sensor based on the cancellation circuit and the image circuit, and ensure the establishment of each node by transmitting a current difference. speed. Thereby, the settling speed of the current sample-and-hold circuit is improved and the noise of the current sample-and-hold circuit output is reduced.
  • the current sample-and-hold circuit of the present application also has a large dynamic range and unconditionally stable characteristics.
  • FIG. 1 is a schematic structural view of an embodiment of a current sample and hold circuit in the prior art
  • FIG. 2 is a block diagram showing an embodiment of a current sample and hold circuit of the present application.
  • an embodiment of the present application provides a current sample and hold circuit, where the current sample and hold circuit includes:
  • the cancel circuit 21 is connected in series between the VDD terminal and the current sensor 11, and is turned on according to the first enable signal, and the output current cancels the DC current component in the current sensor 11.
  • the mirror circuit 22 is connected in parallel with the series-connected cancellation circuit 21 and the current-type sensor 11 between the VDD terminal and the ground voltage, and is turned on according to a second enable signal opposite to the first enable signal. Current transfer is performed using the mirror current of the shunt current and the current difference obtained by the output current of the current sensor 11.
  • the cancel circuit 21 is turned on according to the first enable signal, the DC current component in the current sensor 11 can be cancelled, and the mirror circuit 22 is turned on according to the second enable signal opposite to the first enable signal.
  • a large current of each current branch connected to the current type sensor 11 is maintained, and the establishing speed of each node is ensured by transmitting a current difference, thereby increasing the settling speed of the current sampling and holding circuit. Since there is no need to increase the direct current in order to increase the settling speed of the current sample-and-hold circuit, the noise output from the current sample-and-hold circuit is reduced.
  • Vgs Gate source voltage
  • Vod the overdrive voltage
  • Vth the threshold voltage.
  • Vth 0.5 to 1 V
  • Vod 0.1 to 0.2 V
  • Vgs Vth + Vod. Therefore, its dynamic range has been improved.
  • the cancellation circuit 21 includes: a first P-type MOS transistor M1, a first capacitor C1, and a first switch S1 that is turned off according to the first enable signal, the first The source of the P-type MOS transistor M1 is connected to the VDD terminal, the gate is respectively connected to one end of the first capacitor C1 and one end of the first switch S1, and the drain is connected to the current-type sensor, the first capacitor The other end of C1 is connected to the VDD terminal, and the other end of the first switch S1 is connected to the current output terminal.
  • the cancellation circuit 21 adopts the same circuit structure as the existing cancellation circuit 12 in FIG. 1, is turned on according to the first enable signal, and the first switch S1 is also turned off according to the first enable signal. Turning on, the drain of the first P-type MOS transistor M1 is connected to the output of the current-type sensor 11 to cancel the DC current component in the current-type sensor 11.
  • the application further includes a second switch S2, one end of the second switch S2 is connected to the drain of the first P-type MOS transistor M1, and the other end is connected to the current-type sensor 11, according to The first enable signal is closed, the cancellation circuit 21 is turned on, and otherwise the cancellation circuit is turned off.
  • the second switch S2 is used as the first enable signal is closed according to the first enable signal, and the cancellation circuit 21 is turned on to facilitate operation control, and the circuit design is simpler.
  • the present application further includes a third switch S3, one end of the third switch S3 is respectively connected to the current type sensor 11 and the second switch S2, and the other end is connected to the mirror circuit 22,
  • the mirror circuit 22 is turned on according to the second enable signal being closed, and otherwise the mirror circuit is turned off.
  • the third switch S3 is used as the application according to the second enable signal to close, the mirror circuit 22 is turned on, which is convenient for operation control, and the circuit design is simpler.
  • the mirror circuit 22 includes a first current mirror circuit 221, a second current mirror circuit 222, a third current mirror circuit 223, and a fourth current mirror circuit 224, the first current mirror circuit 221 and the second current mirror circuit.
  • 222 is connected in series between the VDD terminal and the ground voltage.
  • One end of the third current mirror circuit 223 is connected to the first current mirror circuit 221, and the other end is connected to the ground voltage.
  • One end of the fourth current mirror circuit 224 is connected to the VDD end, and the other end is connected to the first Second electric Flow mirror circuit 222.
  • the present application performs current transfer by the current difference generated by the first current mirror circuit 221, the second current mirror circuit 222, the third current mirror circuit 223, and the fourth current mirror circuit 224, thereby improving the settling speed of the current sample-and-hold circuit.
  • the image circuit 22 includes: a fourth P-type MOS transistor (M4), a fifth P-type MOS transistor (M5), a sixth N-type MOS transistor (M6), and a seventh N-type.
  • the gate is connected to the VDD terminal, the gate is respectively connected to the mirror circuit and the drain, and the drain is respectively connected to the drain and the gate of the sixth N-type MOS transistor (M6), and the sixth N-type MOS transistor (
  • the gate of M6) is further connected to the mirror circuit, the source is connected to the ground voltage, the source of the fifth P-type MOS transistor M5 is connected to the VDD terminal, and the gate is respectively connected to the fourth P-type MOS transistor.
  • the ninth N-type MOS transistor M4 a drain connected to a drain of the eighth N-type MOS transistor M8 and one end of the third switch S3, wherein the fifth P-type MOS transistor M5 mirrors the fourth P-type
  • the MOS transistor M4 the source of the seventh N-type MOS transistor M7 is connected to the ground voltage, the gate is respectively connected to the drain and the gate of the sixth N-type MOS transistor M6, and the drain is respectively connected to the tenth a drain and a current output terminal of a P-type MOS transistor M11, the seventh N-type MOS transistor M7 mirroring the sixth N-type MOS transistor M6, the eighth The source of the N-type MOS transistor M8 is connected to the ground voltage, the gate is connected to the gate of the ninth N-type MOS transistor M9, and the source of the ninth N-type MOS transistor M9 is connected to the ground voltage, and the drain Connected to the drain and the gate of the tenth P-type MOS transistor M10, the ninth N-type MO
  • the mirror ratio of all current mirrors is set to 1. Since the current source Ib, the serially connected fourth P-type MOS transistor M4 and the sixth N-type MOS transistor M6 form the bias circuit 22, the fifth P-type MOS transistor M5 mirrors the fourth P-type MOS transistor M4, and the seventh N-type MOS The tube M7 mirrors the sixth N-type MOS transistor M6, so the drain currents of the fifth P-type MOS transistor M5 and the seventh N-type MOS transistor M7 are both Ib.
  • the first switch S1 and the third switch S3 are closed, and the second switch S2 is disconnected.
  • the drain current of the fifth P-type MOS transistor M5 is Ib, and the current-type sensor 11 shunts the drain current Ib of the fifth P-type MOS transistor M5, that is, the drain current Ib of the fifth P-type MOS transistor M5 is shunted into a current-type sensor.
  • the output current I0 of 11 and the current Ic of the eighth N-type MOS transistor M8. Therefore, the current Ic Ib - I0 (Equation 3) flowing through the eighth N-type MOS transistor M8.
  • the ninth N-type MOS transistor M9 mirrors the current of the eighth N-type MOS transistor M8, and the eleventh P-type MOS transistor M11 mirrors the tenth P-type MOS transistor M10, the ninth N-type MOS transistor M9, the tenth P
  • the drain currents of the MOS transistor M10 and the eleventh P-type MOS transistor M11 are both Ic.
  • the Vb node has no large capacitance, the time constant of the node Vb is close to 0, and the establishment speed of the node Vb is very fast. The setup time relative to node Va is negligible.
  • the drain current of the seventh N-type MOS transistor M7 is Ib
  • the drain current Ib of the seventh N-type MOS transistor M7 is the eleventh P-type MOS.
  • the pole is connected to the output of the current type sensor 11, and since the output current of the first P-type MOS transistor M1 is I0, the direct current component in the current type sensor 11 can be cancelled.
  • the drain current Ie of the MOS transistor M1 is much smaller, that is, the current noise in the present application is much smaller.
  • Vgs the gate-source voltage
  • Vod the overdrive voltage
  • Vth the threshold voltage.
  • Vth 0.5 to 1 V
  • Vod 0.1 to 0.2 V
  • Vgs Vth + Vod. Therefore the circuit can operate below very low voltages, so its dynamic range is improved.
  • FIG. 2 another embodiment of the present application provides a signal acquisition system having a current sample and hold circuit, including: a current sample and hold circuit and a current type sensor 11, the current sample and hold circuit including:
  • the cancel circuit 21 is connected in series between the VDD terminal and the current sensor 11, and is turned on according to the first enable signal, and the output current cancels the DC current component in the current sensor 11.
  • the mirror circuit 22 is connected in parallel with the series-connected cancellation circuit and the current sensor between the VDD terminal and the ground voltage, and is turned on according to a second enable signal opposite to the first enable signal. Current transfer is performed by the mirror current of the shunt current and the current difference obtained by the output current of the current sensor 11.
  • the cancel circuit 21 is turned on according to the first enable signal, the DC current component in the current sensor 11 can be cancelled, and the mirror circuit 22 is turned on according to the second enable signal opposite to the first enable signal.
  • the bias circuit 22 outputs the current source bias current, the large current of each current branch connected to the current sensor 11 is maintained, and the establishing speed of each node is ensured by transmitting the current difference, thereby improving the speed.
  • the speed at which the current sample-and-hold circuit is established. Since there is no need to increase the direct current in order to increase the settling speed of the current sample-and-hold circuit, the noise output from the current sample-and-hold circuit is reduced.
  • Vgs the gate-source voltage
  • Vod the overdrive voltage
  • Vth the threshold voltage.
  • Vth 0.5 to 1 V
  • Vod 0.1 to 0.2 V
  • Vgs Vth + Vod.
  • the circuit can operate below very low voltages, so Its dynamic range has been improved.
  • the cancellation circuit 21 includes: a first P-type MOS transistor M1, a first capacitor C1, and a first switch S1 that is turned off according to the first enable signal, the first The source of the P-type MOS transistor M1 is connected to the VDD terminal, the gate is respectively connected to one end of the first capacitor C1 and one end of the first switch S1, and the drain is connected to the current-type sensor, the first capacitor The other end of C1 is connected to the VDD terminal, and the other end of the first switch S1 is connected to the current output terminal.
  • the cancellation circuit 21 adopts the same circuit structure as the existing cancellation circuit 11 in FIG. 1, is turned on according to the first enable signal, and the first switch S1 is also turned off according to the first enable signal. Turning on, the drain of the first P-type MOS transistor M1 is connected to the output of the current-type sensor 11 to cancel the DC current component in the current-type sensor 11.
  • the application further includes a second switch S2, one end of the second switch S2 is connected to the drain of the first P-type MOS transistor M1, and the other end is connected to the current-type sensor 11, according to The first enable signal is closed, the cancellation circuit 21 is turned on, and otherwise the cancellation circuit 21 is turned off.
  • the second switch S2 is used as the first enable signal is closed according to the first enable signal, and the cancellation circuit 21 is turned on to facilitate operation control, and the circuit design is simpler.
  • the present application further includes a third switch S3, one end of the third switch S3 is respectively connected to the current type sensor 11 and the second switch S2, and the other end is connected to the mirror circuit 22,
  • the mirror circuit 22 is turned on according to the second enable signal being closed, and otherwise the cancel circuit 22 is turned off.
  • the third switch S3 is used as the application according to the second enable signal to close, the mirror circuit 22 is turned on, which is convenient for operation control, and the circuit design is simpler.
  • the mirror circuit 22 includes a first current mirror circuit 221, a second current mirror circuit 222, a third current mirror circuit 223, and a fourth current mirror circuit 224, the first current mirror circuit 221 and the second current mirror circuit.
  • 222 is connected in series between the VDD terminal and the ground voltage.
  • One end of the third current mirror circuit 223 is connected to the first current mirror circuit 221, and the other end is connected to the ground voltage.
  • One end of the fourth current mirror circuit 224 is connected to the VDD end, and the other end is connected to the first Two current mirror circuit 222.
  • the present application performs current transfer by the current difference generated by the first current mirror circuit 221, the second current mirror circuit 222, the third current mirror circuit 223, and the fourth current mirror circuit 224, thereby improving the settling speed of the current sample-and-hold circuit.
  • the image circuit 22 includes: a fourth P-type MOS transistor M4, a fifth P-type MOS transistor M5, a sixth N-type MOS transistor M6, a seventh N-type MOS transistor M7, and an eighth N-type MOS transistor M8, ninth N-type MOS transistor M9, tenth P-type MOS transistor M10, eleventh P-type MOS transistor M11, the source of the fourth P-type MOS transistor (M4) is connected to the VDD terminal
  • the gate is respectively connected to the mirror circuit and the drain, the drain is respectively connected to the drain and the gate of the sixth N-type MOS transistor M6, and the gate of the sixth N-type MOS transistor M6 is further connected to the mirror a circuit, the source is connected to the ground voltage, the source of the fifth P-type MOS transistor M5 is connected to the VDD terminal, and the gate is respectively connected to the gate and the drain of the fourth P-type MOS transistor M4, and the drain Connected to the drain of the eighth N-type MOS transistor
  • the seventh N-type MOS transistor M7 mirrors the sixth N-type MOS transistor M6, and the eighth N-type MOS transistor
  • the source of M8 is connected to the ground voltage
  • the gate is connected to the gate of the ninth N-type MOS transistor M9
  • the source of the ninth N-type MOS transistor M9 is connected to the ground voltage
  • the drain is connected to the ground respectively.
  • a drain and a gate of the tenth P-type MOS transistor M10, the ninth N-type MOS transistor M9 mirroring the eighth N-type MOS transistor M8, and a source of the tenth P-type MOS transistor M10 is connected to the VDD
  • the gate is connected to the gate of the eleventh P-type MOS transistor M11, the source of the eleventh P-type MOS transistor M11 is connected to the VDD terminal, and the eleventh P-type MOS transistor M11 is mirrored.
  • the tenth P-type MOS transistor M10 is described.
  • the mirror ratio of all current mirrors is set to 1. Since the current source Ib, the serially connected fourth P-type MOS transistor M4 and the sixth N-type MOS transistor M6 form the bias circuit 22, the fifth P-type MOS transistor M5 mirrors the fourth P-type MOS transistor M4, and the seventh N-type MOS The tube M7 mirrors the sixth N-type MOS transistor M6, so the drain currents of the fifth P-type MOS transistor M5 and the seventh N-type MOS transistor M7 are both Ib.
  • the drain current of the fifth P-type MOS transistor M5 is Ib, and the current-type sensor 11 is shunted fifth.
  • the ninth N-type MOS transistor M9 mirrors the current of the eighth N-type MOS transistor M8, and the eleventh P-type MOS transistor M11 mirrors the tenth P-type MOS transistor M10, the ninth N-type MOS transistor M9, the tenth P
  • the drain currents of the MOS transistor M10 and the eleventh P-type MOS transistor M11 are both Ic.
  • the Vb node has no large capacitance, the time constant of the node Vb is close to 0, and the establishment speed of the node Vb is very fast. The setup time relative to node Va is negligible.
  • the drain current of the seventh N-type MOS transistor M7 is Ib
  • the drain current Ib of the seventh N-type MOS transistor M7 is the eleventh P-type MOS.
  • the drain current Ie of the first P-type MOS transistor M1 in the present application is much smaller, that is, the current noise in the present application is much smaller.
  • Vgs the gate-source voltage
  • Vod the overdrive voltage
  • Vth the threshold voltage.
  • Vth 0.5 to 1 V
  • Vod 0.1 to 0.2 V
  • Vgs Vth + Vod.
  • the circuit can operate below very low voltages, so its dynamic range is improved.
  • modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment.
  • the modules or units or components of the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of sub-modules or sub-units or sub-components.
  • any combination of the features disclosed in the specification, including the accompanying claims, the abstract and the drawings, and any methods so disclosed or All processes or units of the device are combined.
  • Each feature disclosed in this specification (including the accompanying claims, the abstract and the drawings) may be replaced by alternative features that provide the same, equivalent or similar purpose.
  • the various component embodiments of the present application can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof.
  • a microprocessor or digital signal processor may be used in practice to implement some or all of the functionality of some or all of the components of the message alerting in accordance with embodiments of the present application.
  • the application can also be implemented as a device or device program (e.g., a computer program and a computer program product) adapted to perform some or all of the methods described herein.
  • Such a program implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such signals may be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
  • "an embodiment," or "an embodiment," or "one or more embodiments" as used herein means that the particular features, structures, or characteristics described in connection with the embodiments are included in at least one embodiment of the present application.
  • phrase "in one embodiment" is not necessarily referring to the same embodiment.

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Abstract

一种电流采样保持电路及信号采集系统，电流采样保持电路包括：抵消电路（21），串接在VDD端与电流型传感器（11）之间，根据第一使能信号接通，输出电流抵消电流型传感器（11）中的直流电流成份；镜像电路（22），与串接的抵消电路（21）及电流型传感器（11）并联连接在VDD端与地电压之间，根据与第一使能信号相反的第二使能信号接通，利用分流电流的镜像电流以及电流型传感器（11）的输出电流所获得的电流差进行电流传递。电流采样保持电路及信号采集系统提高了建立速度，减小了输出噪声。

Description

一种电流采样保持电路及信号采集系统 技术领域
本申请涉及电流采样保持技术领域，具体涉及一种电流采样保持电路及信号采集系统。
背景技术
参见图1，在信号采集系统中，电流型传感器11输出电流的交流部分，因此通常会加入抵消电路12来获取并抵消电流型传感器11所输出电流的直流成分。但是，抵消电路12的有限建立时间会影响到后续电路的等待时间，从而降低整个采集系统的效率。
但是，在采样阶段，当第一使能信号sh为高，第一开关S1闭合，此时第一P型MOS管M1的栅极、漏极短接，因此所述第一P型MOS管M1等效为一个阻值为1/gm1的电阻，gm1为所述第一P型MOS管M1的跨导。所述等效电阻与第一电容C1、电流型传感器电容C0形成的时间常数为τ1＝(C0+C1)/gm1(公式1)。因此，在第一P型MOS管M1的跨导gm1很小、电流型传感器电容C0很大的情况下，该时间常数τ1将会非常大，从而使得该抵消电路12的建立速度变得缓慢。并且，为了加快抵消电路12的建立速度，通常的做法是增加偏置电流源I1，以使得流过所述第一P型MOS管M1的直流电流增加，从而增加所述第一P型MOS管M1的跨导gm1，最终使得时间常数τ1减小，以加快抵消电路12的建立速度。但是增加的偏置电流又会引入大量的电流噪声，从而影响了信号采集系统的信噪比。
因此，如何更好的实现电流采样保持，成为现有技术中亟需解决的技术问题。
发明内容
鉴于上述问题，本申请提供一种电流采样保持电路及信号采集系统，其 全部或者部分地解决上述技术问题。
根据本申请的第一个方面，提供了一种电流采样保持电路，所述电流采样保持电路包括：
抵消电路，串接在VDD端与电流型传感器之间，根据第一使能信号接通，输出电流抵消所述电流型传感器中的直流电流成份；
镜像电路，与串接的所述抵消电路及电流型传感器并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器的输出电流所获得的电流差进行电流传递。
根据本申请的第二个方面，提供了一种具有电流采样保持电路的信号采集系统，包括：电流采样保持电路以及电流型传感器，所述电流采样保持电路包括：
抵消电路，串接在VDD端与电流型传感器之间，根据第一使能信号接通，输出电流抵消所述电流型传感器中的直流电流成份；
镜像电路，与串接的所述抵消电路及电流型传感器并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器的输出电流所获得的电流差进行电流传递。
本申请所提供电流采样保持电路及信号采集系统，基于抵消电路以及镜像电路，保持所述电流型传感器所连接的各条电流支路的大电流，并且通过传递电流差的方式保证各个节点的建立速度。从而提高了电流采样保持电路的建立速度和减小了电流采样保持电路输出的噪声。此外，本申请电流采样保持电路还具有较大的动态范围和无条件稳定的特点。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本申请的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1示出现有技术中一种电流采样保持电路的一实施例结构示意图；
图2示出本申请一种电流采样保持电路的一实施例结构图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
参见图2，本申请一实施例提供一种电流采样保持电路，所述电流采样保持电路包括：
抵消电路21，串接在VDD端与电流型传感器11之间，根据第一使能信号接通，输出电流抵消所述电流型传感器11中的直流电流成份。
镜像电路22，与串接的所述抵消电路21及电流型传感器11并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器11的输出电流所获得的电流差进行电流传递。
由于抵消电路21根据第一使能信号接通时，可以抵消所述电流型传感器11中的直流电流成份，而镜像电路22根据与所述第一使能信号相反的第二使能信号接通时，保持所述电流型传感器11所连接的各条电流支路的大电流，并且通过传递电流差的方式保证各个节点的建立速度，从而提高了电流采样保持电路的建立速度。由于无需为了提高电流采样保持电路的建立速度而增大直流电流，从而减小了电流采样保持电路输出的噪声。
此外，本申请每条电流支路的最低工作电压可以达到Vgs+Vod，Vgs是 栅源电压，Vod是过驱动电压，Vth是阈值电压。一般的，Vth＝0.5～1V，Vod＝0.1～0.2V，Vgs＝Vth+Vod。因此其动态范围得到了提高。
在本申请另一具体实现中，所述抵消电路21包括：第一P型MOS管M1、第一电容C1以及根据所述第一使能信号关闭导通的第一开关S1，所述第一P型MOS管M1的源极接所述VDD端，栅极分别接所述第一电容C1的一端和所述第一开关S1的一端，漏极接所述电流型传感器，所述第一电容C1的另一端接所述VDD端，所述第一开关S1的另一端接电流输出端。
具体地，所述抵消电路21采用和图1中现有的抵消电路12相同的电路结构，根据第一使能信号接通，且所述第一开关S1也根据所述第一使能信号关闭导通，第一P型MOS管M1的漏极接到电流型传感器11的输出抵消所述电流型传感器11中的直流电流成份。
在本申请再一具体实现中，本申请还包括第二开关S2，所述第二开关S2一端连接所述第一P型MOS管M1的漏极，另一端连接所述电流型传感器11，根据所述第一使能信号闭合，接通所述抵消电路21，否则，断开所述抵消电路。
本申请采用第二开关S2作为根据所述第一使能信号闭合，接通所述抵消电路21，便于操作控制，且电路设计更加简单。
在本申请再一具体实现中，本申请还包括第三开关S3，所述第三开关S3一端分别连接所述电流型传感器11和所述第二开关S2，另一端连接所述镜像电路22，根据所述第二使能信号闭合，接通所述镜像电路22，否则，断开所述镜像电路。
本申请采用第三开关S3作为根据所述第二使能信号闭合，接通所述镜像电路22，便于操作控制，且电路设计更加简单。
所述镜像电路22包括第一电流镜电路221、第二电流镜电路222、第三电流镜电路223以及第四电流镜电路224，所述第一电流镜电路221与所述第二电流镜电路222串联连接在所述VDD端与地电压之间。所述第三电流镜电路223的一端连接所述第一电流镜电路221，另一端连接所述地电压，所述第四电流镜电路224的一端连接所述VDD端，另一端连接所述第二电 流镜电路222。
本申请通过第一电流镜电路221、第二电流镜电路222、第三电流镜电路223以及第四电流镜电路224所产生的电流差进行电流传递，提高了电流采样保持电路的建立速度。
在本申请再一具体实现中，所述镜像电路22包括：第四P型MOS管(M4)、第五P型MOS管(M5)、第六N型MOS管(M6)、第七N型MOS管M7、第八N型MOS管M8、第九N型MOS管M9、第十P型MOS管M10、第十一P型MOS管M11，所述第四P型MOS管(M4)的源极接所述VDD端，栅极分别接所述镜像电路和漏极，漏极分别接所述第六N型MOS管(M6)的漏极和栅极，所述第六N型MOS管(M6)的栅极还接所述镜像电路，源极接所述地电压，所述第五P型MOS管M5的源极接所述VDD端，栅极分别接所述第四P型MOS管M4的栅极和漏极，漏极分别接所述第八N型MOS管M8的漏极和所述第三开关S3的一端，所述第五P型MOS管M5镜像所述第四P型MOS管M4，所述第七N型MOS管M7的源极接所述地电压，栅极分别接所述第六N型MOS管M6的漏极和栅极，漏极分别接所述第十一P型MOS管M11的漏极和电流输出端，所述第七N型MOS管M7镜像所述第六N型MOS管M6，所述第八N型MOS管M8的源极接所述地电压，栅极接所述第九N型MOS管M9的栅极，所述第九N型MOS管M9的源极接所述地电压，漏极分别接所述第十P型MOS管M10的漏极和栅极，所述第九N型MOS管M9镜像所述第八N型MOS管M8，所述第十P型MOS管M10的源极接所述VDD端，栅极接所述第十一P型MOS管M11的栅极，所述第十一P型MOS管M11的源极接所述VDD端，所述第十一P型MOS管M11镜像所述第十P型MOS管M10。
具体地，所有电流镜的镜像比都设为1。由于电流源Ib、串接的第四P型MOS管M4和第六N型MOS管M6组成偏置电路22，第五P型MOS管M5镜像第四P型MOS管M4，第七N型MOS管M7镜像第六N型MOS管M6，因此第五P型MOS管M5、第七N型MOS管M7的漏极电流均为Ib。
若此时第一使能信号sh＝1，第一开关S1、第三开关S3闭合，第二开关 S2断开。第五P型MOS管M5的漏极电流为Ib，电流型传感器11分流第五P型MOS管M5的漏极电流Ib，即第五P型MOS管M5的漏极电流Ib分流为电流型传感器11的输出电流I0以及第八N型MOS管M8的电流Ic。因此流过第八N型MOS管M8的电流Ic＝Ib-I0(公式3)。这里假设Ib＝αI0(公式4)，那么Ic＝(α-1)I0，通常α是一个远大于2的正实数。因此，由于所述第八N型MOS管M8的跨导gm8远大于图1中所述第一P型MOS管M1所提供的跨导gm1。本实施例中Va节点的时间常数τ2＝C0/gm8(公式5)，图1中时间常数τ1＝(C0+C1)/gm1(公式1)，因此τ2<<τ1。由于时间节点τ2<<τ1，因此本实施例中节点Va和电流Ic的建立速度得到极大的提高。
由于所述第九N型MOS管M9镜像第八N型MOS管M8的电流、第十一P型MOS管M11镜像第十P型MOS管M10，因此第九N型MOS管M9、第十P型MOS管M10、第十一P型MOS管M11的漏极电流均为Ic，此外由于Vb节点并无较大的电容，因此节点Vb的时间常数接近为0，节点Vb的建立速度非常快，相对于节点Va的建立时间可以忽略不计。
由于第七N型MOS管M7镜像第六N型MOS管M6，第七N型MOS管M7的漏极电流为Ib，第七N型MOS管M7的漏极电流Ib为第十一P型MOS管M11的漏极电流Ic与第一P型MOS管M1的漏极电流Ie之和。因此，结合公式二可知，本实施例中第一P型MOS管M1的漏极电流为Ie＝Ib-Ic＝I0(公式6)，即为电流型传感器11的输出电流I0。由于此时节点Vsh的时间常数τ3＝C1/gm1(公式7)，与图1中的电流型传感器电容C0和时间常数τ1比较，由于C1<<C0，因此τ3<<τ1，也即节点Vsh和第一P型MOS管M1的漏极电流Ie的建立速度也得到极大的提高。
若此时与第一使能信号相反的第二使能信号s－h＝1时，第一开关S1、第三开关S3断开，第二开关S2闭合，第一P型MOS管M1的漏极接到电流型传感器11的输出，由于第一P型MOS管M1的输出电流为I0，因此可以抵消电流型传感器11中的直流电流成分。此时第一P型MOS管M1的电流噪声功率谱密度为INN＝4kTgm1γ(公式8)，而且gm1∝Ie(亚阈值区)，因此相比于图1通过提高Ie电流来增加建立速度的方式，本申请中的第一P 型MOS管M1的漏极电流Ie要小很多，也即本本申请中的电流噪声也会小很多。
此外，本申请每条电流支路的最低工作电压可以达到Vgs+Vod，Vgs是栅源电压，Vod是过驱动电压，Vth是阈值电压。一般的，Vth＝0.5～1V，Vod＝0.1～0.2V，Vgs＝Vth+Vod。因此该电路可以工作在极低的电压下面，因此其动态范围得到了提高。
由于环路电路会造成电路稳定性差等缺陷，本申请在第一使能信号在sh＝1、与第一使能信号相反的第二使能信号s－h＝1两个阶段，电路都没有形成环路，因此本申请不存在稳定性问题。
参见图2，本申请另一实施例提供一种具有电流采样保持电路的信号采集系统，包括：电流采样保持电路以及电流型传感器11，所述电流采样保持电路包括：
抵消电路21，串接在VDD端与电流型传感器11之间，根据第一使能信号接通，输出电流抵消所述电流型传感器11中的直流电流成份。
镜像电路22，与串接的所述抵消电路及电流型传感器并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器11的输出电流所获得的电流差进行电流传递。
由于抵消电路21根据第一使能信号接通时，可以抵消所述电流型传感器11中的直流电流成份，而镜像电路22根据与所述第一使能信号相反的第二使能信号接通时，利用偏置电路22输出电流源偏置电流，保持所述电流型传感器11所连接的各条电流支路的大电流，并且通过传递电流差的方式保证各个节点的建立速度，从而提高了电流采样保持电路的建立速度。由于无需为了提高电流采样保持电路的建立速度而增大直流电流，从而减小了电流采样保持电路输出的噪声。
此外，本申请每条电流支路的最低工作电压可以达到Vgs+Vod，Vgs是栅源电压，Vod是过驱动电压，Vth是阈值电压。一般的，Vth＝0.5～1V，Vod＝0.1～0.2V，Vgs＝Vth+Vod。该电路可以工作在极低的电压下面，因此 其动态范围得到了提高。
在本申请另一具体实现中，所述抵消电路21包括：第一P型MOS管M1、第一电容C1以及根据所述第一使能信号关闭导通的第一开关S1，所述第一P型MOS管M1的源极接所述VDD端，栅极分别接所述第一电容C1的一端和所述第一开关S1的一端，漏极接所述电流型传感器，所述第一电容C1的另一端接所述VDD端，所述第一开关S1的另一端接电流输出端。
具体地，所述抵消电路21采用和图1中现有的抵消电路11相同的电路结构，根据第一使能信号接通，且所述第一开关S1也根据所述第一使能信号关闭导通，第一P型MOS管M1的漏极接到电流型传感器11的输出抵消所述电流型传感器11中的直流电流成份。
在本申请再一具体实现中，本申请还包括第二开关S2，所述第二开关S2一端连接所述第一P型MOS管M1的漏极，另一端连接所述电流型传感器11，根据所述第一使能信号闭合，接通所述抵消电路21，否则，断开所述抵消电路21。
本申请采用第二开关S2作为根据所述第一使能信号闭合，接通所述抵消电路21，便于操作控制，且电路设计更加简单。
在本申请再一具体实现中，本申请还包括第三开关S3，所述第三开关S3一端分别连接所述电流型传感器11和所述第二开关S2，另一端连接所述镜像电路22，根据所述第二使能信号闭合，接通所述镜像电路22，否则，断开所述抵消电路22。
本申请采用第三开关S3作为根据所述第二使能信号闭合，接通所述镜像电路22，便于操作控制，且电路设计更加简单。
所述镜像电路22包括第一电流镜电路221、第二电流镜电路222、第三电流镜电路223以及第四电流镜电路224，所述第一电流镜电路221与所述第二电流镜电路222串联连接在所述VDD端与地电压之间。所述第三电流镜电路223的一端连接所述第一电流镜电路221，另一端连接所述地电压，所述第四电流镜电路224的一端连接所述VDD端，另一端连接所述第二电流镜电路222。
本申请通过第一电流镜电路221、第二电流镜电路222、第三电流镜电路223以及第四电流镜电路224所产生的电流差进行电流传递，提高了电流采样保持电路的建立速度。
在本申请再一具体实现中，所述镜像电路22包括：第四P型MOS管M4、第五P型MOS管M5、第六N型MOS管M6、第七N型MOS管M7、第八N型MOS管M8、第九N型MOS管M9、第十P型MOS管M10、第十一P型MOS管M11，所述第四P型MOS管(M4)的源极接所述VDD端，栅极分别接所述镜像电路和漏极，漏极分别接所述第六N型MOS管M6的漏极和栅极，所述第六N型MOS管M6的栅极还接所述镜像电路，源极接所述地电压，所述第五P型MOS管M5的源极接所述VDD端，栅极分别接所述第四P型MOS管M4的栅极和漏极，漏极分别接所述第八N型MOS管M8的漏极和所述第三开关S3的一端，所述第五P型MOS管M5镜像所述第四P型MOS管M4，所述第七N型MOS管M7的源极接所述地电压，栅极分别接所述第六N型MOS管M6的漏极和栅极，漏极分别接所述第十一P型MOS管M11的漏极和电流输出端，所述第七N型MOS管M7镜像所述第六N型MOS管M6，所述第八N型MOS管M8的源极接所述地电压，栅极接所述第九N型MOS管M9的栅极，所述第九N型MOS管M9的源极接所述地电压，漏极分别接所述第十P型MOS管M10的漏极和栅极，所述第九N型MOS管M9镜像所述第八N型MOS管M8，所述第十P型MOS管M10的源极接所述VDD端，栅极接所述第十一P型MOS管M11的栅极，所述第十一P型MOS管M11的源极接所述VDD端，所述第十一P型MOS管M11镜像所述第十P型MOS管M10。
具体地，所有电流镜的镜像比都设为1。由于电流源Ib、串接的第四P型MOS管M4和第六N型MOS管M6组成偏置电路22，第五P型MOS管M5镜像第四P型MOS管M4，第七N型MOS管M7镜像第六N型MOS管M6，因此第五P型MOS管M5、第七N型MOS管M7的漏极电流均为Ib。
若此时第一使能信号sh＝1，第一开关S1、第三开关S3闭合，第二开关S2断开。第五P型MOS管M5的漏极电流为Ib，电流型传感器11分流第五 P型MOS管M5的漏极电流Ib，即第五P型MOS管M5的漏极电流Ib分流为电流型传感器11的输出电流I0以及第八N型MOS管M8的电流Ic。因此流过第八N型MOS管M8的电流Ic＝Ib-I0(公式3)。这里假设Ib＝αI0(公式4)，那么Ic＝(α-1)I0，通常α是一个远大于2的正实数。因此，由于所述第八N型MOS管M8的跨导gm8远大于图1中所述第一P型MOS管M1所提供的跨导gm1。本实施例中Va节点的时间常数τ2＝C0/gm8(公式5)，图1中时间常数τ1＝(C0+C1)/gm1(公式1)，因此τ2<<τ1。由于时间节点τ2<<τ1，因此本实施例中节点Va和电流Ic的建立速度得到极大的提高。
由于所述第九N型MOS管M9镜像第八N型MOS管M8的电流、第十一P型MOS管M11镜像第十P型MOS管M10，因此第九N型MOS管M9、第十P型MOS管M10、第十一P型MOS管M11的漏极电流均为Ic，此外由于Vb节点并无较大的电容，因此节点Vb的时间常数接近为0，节点Vb的建立速度非常快，相对于节点Va的建立时间可以忽略不计。
由于第七N型MOS管M7镜像第六N型MOS管M6，第七N型MOS管M7的漏极电流为Ib，第七N型MOS管M7的漏极电流Ib为第十一P型MOS管M11的漏极电流Ic与第一P型MOS管M1的漏极电流Ie之和。因此，结合公式二可知，本实施例中第一P型MOS管M1的漏极电流为Ie＝Ib-Ic＝I0(公式6)，即为电流型传感器11的输出电流I0。由于此时节点Vsh的时间常数τ3＝C1/gm1(公式7)，与图1中的电流型传感器电容C0和时间常数τ1比较，由于C1<<C0，因此τ3<<τ1，也即节点Vsh和第一P型MOS管M1的漏极电流Ie的建立速度也得到极大的提高。
若此时第二使能信号sh＝1时，第一开关S1、第三开关S3断开，第二开关S2闭合，第一P型MOS管M1的漏极接到电流型传感器11的输出，由于第一P型MOS管M1的输出电流为I0，因此可以抵消电流型传感器11中的直流电流成分。此时第一P型MOS管M1的电流噪声功率谱密度为INN＝4kTgm1γ(公式8)，而且gm1∝Ie(亚阈值区)，因此相比于图1通过提高Ie电流来增加建立速度的方式，本申请中的第一P型MOS管M1的漏极电流Ie要小很多，也即本本申请中的电流噪声也会小很多。
此外，本申请每条电流支路的最低工作电压可以达到Vgs+Vod，Vgs是栅源电压，Vod是过驱动电压，Vth是阈值电压。一般的，Vth＝0.5～1V，Vod＝0.1～0.2V，Vgs＝Vth+Vod。该电路可以工作在极低的电压下面，因此其动态范围得到了提高。
由于环路电路会造成电路稳定性差等缺陷，本申请在第一使能信号在sh＝1、第二使能信号sh＝0两个阶段，电路都没有形成环路，因此本申请不存在稳定性问题。
在此提供的算法和显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与基于在此的示教一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本申请也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本申请的内容，并且上面对特定语言所做的描述是为了披露本申请的最佳实施方式。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本申请的示例性实施例的描述中，本申请的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本申请要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本申请的单独实施例。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或 者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本申请的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
本申请的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSN)来实现根据本申请实施例的消息提醒的装置中的一些或者全部部件的一些或者全部功能。本申请还可以实现为适于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本申请的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
应该注意的是上述实施例对本申请进行说明而不是对本申请进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本申请可以 借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。

Claims (10)

  1. 一种电流采样保持电路，其特征在于，所述电流采样保持电路包括：
    抵消电路，串接在VDD端与电流型传感器之间，根据第一使能信号接通，输出电流抵消所述电流型传感器中的直流电流成份；
    镜像电路，与串接的所述抵消电路及电流型传感器并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器的输出电流所获得的电流差进行电流传递。
  2. 如权利要求1所述的电流采样保持电路，其特征在于，包括第二开关(S2)，所述第二开关(S2)一端连接所述抵消电路，另一端连接所述电流型传感器，根据所述第一使能信号闭合，接通所述抵消电路，否则，断开所述抵消电路。
  3. 如权利要求2所述的电流采样保持电路，其特征在于，包括第三开关(S3)，所述第三开关(S3)一端分别连接所述电流型传感器和所述第二开关(S2)，另一端连接所述镜像电路，根据所述第二使能信号闭合，接通所述镜像电路，否则，断开所述镜像电路。
  4. 如权利要求5所述的电流采样保持电路，其特征在于，所述镜像电路包括第一电流镜电路、第二电流镜电路、第三电流镜电路以及第四电流镜电路，所述第一电流镜电路与所述第二电流镜电路串联连接在所述VDD端与地电压之间，所述第三电流镜电路的一端连接所述第一电流镜电路，另一端连接所述地电压，所述第四电流镜电路的一端连接所述VDD端，另一端连接所述第二电流镜电路。
  5. 如权利要求4所述的电流采样保持电路，其特征在于，所述镜像电路包括：第四P型MOS管(M4)、第五P型MOS管(M5)、第六N型MOS管(M6)、第七N型MOS管(M7)、第八N型MOS管(M8)、第九N型MOS管(M9)、第十P型MOS管(M10)、第十一P型MOS管(M11)，所 述第四P型MOS管(M4)的源极接所述VDD端，栅极分别接所述镜像电路和漏极，漏极分别接所述第六N型MOS管(M6)的漏极和栅极，所述第六N型MOS管(M6)的栅极还接所述镜像电路，源极接所述地电压，所述第五P型MOS管(M5)的源极接所述VDD端，栅极分别接所述第四P型MOS管(M4)的栅极和漏极，漏极分别接所述第八N型MOS管(M8)的漏极和所述第三开关(S3)的一端，所述第五P型MOS管(M5)镜像所述第四P型MOS管(M4)，所述第七N型MOS管(M7)的源极接所述地电压，栅极分别接所述第六N型MOS管(M6)的漏极和栅极，漏极分别接所述第十一P型MOS管(M11)的漏极和电流输出端，所述第七N型MOS管(M7)镜像所述第六N型MOS管(M6)，所述第八N型MOS管(M8)的源极接所述地电压，栅极接所述第九N型MOS管(M9)的栅极，所述第九N型MOS管(M9)的源极接所述地电压，漏极分别接所述第十P型MOS管(M10)的漏极和栅极，所述第九N型MOS管(M9)镜像所述第八N型MOS管(M8)，所述第十P型MOS管(M10)的源极接所述VDD端，栅极接所述第十一P型MOS管(M11)的栅极，所述第十一P型MOS管(M11)的源极接所述VDD端，所述第十一P型MOS管(M11)镜像所述第十P型MOS管(M10)。
  6. 一种具有电流采样保持电路的信号采集系统，包括：电流采样保持电路以及电流型传感器，其特征在于，所述电流采样保持电路包括：
    抵消电路，串接在VDD端与电流型传感器之间，根据第一使能信号接通，输出电流抵消所述电流型传感器中的直流电流成份；
    镜像电路，与串接的所述抵消电路及电流型传感器并联连接在所述VDD端与地电压之间，根据与所述第一使能信号相反的第二使能信号接通，利用所述分流电流的镜像电流以及所述电流型传感器的输出电流所获得的电流差进行电流传递。
  7. 如权利要求8所述的具有电流采样保持电路的信号采集系统，其特征在于，包括第二开关(S2)，所述第二开关(S2)一端连接所述抵消电路，另一端连接所述电流型传感器，根据所述第一使能信号闭合，接通所述抵消电路，否则，断开所述抵消电路。
  8. 如权利要求7所述的具有电流采样保持电路的信号采集系统，其特征 在于，包括第三开关(S3)，所述第三开关(S3)一端分别连接所述电流型传感器和所述第二开关(S2)，另一端连接所述镜像电路，根据所述第二使能信号闭合，接通所述镜像电路，否则，断开所述镜像电路。
  9. 如权利要求8所述的信号采集系统，其特征在于，所述镜像电路包括第一电流镜电路、第二电流镜电路、第三电流镜电路以及第四电流镜电路，所述第一电流镜电路与所述第二电流镜电路串联连接在所述VDD端与地电压之间，所述第三电流镜电路的一端连接所述第一电流镜电路，另一端连接所述地电压，所述第四电流镜电路的一端连接所述VDD端，另一端连接所述第二电流镜电路。
  10. 如权利要求9所述的信号采集系统，其特征在于，所述镜像电路包括：第四P型MOS管(M4)、第五P型MOS管(M5)、第六N型MOS管(M6)、第七N型MOS管(M7)、第八N型MOS管(M8)、第九N型MOS管(M9)、第十P型MOS管(M10)、第十一P型MOS管(M11)，所述第四P型MOS管(M4)的源极接所述VDD端，栅极分别接所述镜像电路和漏极，漏极分别接所述第六N型MOS管(M6)的漏极和栅极，所述第六N型MOS管(M6)的栅极还接所述镜像电路，源极接所述地电压，所述第五P型MOS管(M5)的源极接所述VDD端，栅极分别接所述第四P型MOS管(M4)的栅极和漏极，漏极分别接所述第八N型MOS管(M8)的漏极和所述第三开关(S3)的一端，所述第五P型MOS管(M5)镜像所述第四P型MOS管(M4)，所述第七N型MOS管(M7)的源极接所述地电压，栅极分别接所述第六N型MOS管(M6)的漏极和栅极，漏极分别接所述第十一P型MOS管(M11)的漏极和电流输出端，所述第七N型MOS管(M7)镜像所述第六N型MOS管(M6)，所述第八N型MOS管(M8)的源极接所述地电压，栅极接所述第九N型MOS管(M9)的栅极，所述第九N型MOS管(M9)的源极接所述地电压，漏极分别接所述第十P型MOS管(M10)的漏极和栅极，所述第九N型MOS管(M9)镜像所述第八N型MOS管(M8)，所述第十P型MOS管(M10)的源极接所述VDD端，栅极接所述第十一P型MOS管(M11)的栅极，所述第十一P型MOS管(M11)的源极接所述VDD端，所述第十一P型MOS管(M11)镜像所述第十P型MOS管(M10)。
PCT/CN2016/095465 2016-08-16 2016-08-16 一种电流采样保持电路及信号采集系统 WO2018032327A1 (zh)

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KR1020177023792A KR101947303B1 (ko) 2016-08-16 2016-08-16 전류 샘플링 유지 회로 및 신호 수집 시스템
EP16890897.8A EP3486912B1 (en) 2016-08-16 2016-08-16 Current sampling and holding circuit and signal acquisition system
PCT/CN2016/095465 WO2018032327A1 (zh) 2016-08-16 2016-08-16 一种电流采样保持电路及信号采集系统
CN201680000741.7A CN106415282B (zh) 2016-08-16 2016-08-16 一种电流采样保持电路及信号采集系统
US15/690,333 US10186328B2 (en) 2016-08-16 2017-08-30 Current sampling and holding circuit and signal acquisition system

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Publication number Priority date Publication date Assignee Title
CN107005248B (zh) * 2017-02-17 2020-07-28 深圳市汇顶科技股份有限公司 相关双采样积分电路
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023489A (en) * 1989-05-10 1991-06-11 U.S. Philips Corporation Integrator circuit
US5760616A (en) * 1995-09-05 1998-06-02 Lucent Technologies, Inc. Current copiers with improved accuracy
CN1234902A (zh) * 1996-09-16 1999-11-10 爱特梅尔股份有限公司 用于开关电流存储单元的时钟直通减少系统
CN1720661A (zh) * 2003-08-04 2006-01-11 精工爱普生株式会社 差分电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3441320B2 (ja) * 1996-11-28 2003-09-02 株式会社東芝 電流増幅装置およびこれを用いた電流モードのアナログ−ディジタル変換器
US6011414A (en) * 1998-02-03 2000-01-04 Philips Electronics North America Corporation Arrangement for reducing the effects of capacitive coupling in a control circuit for a switched-mode power supply
US8582266B2 (en) * 2006-02-17 2013-11-12 Broadcom Corporation Current-monitoring apparatus
US7701734B2 (en) * 2006-08-17 2010-04-20 System General Corp. Detection circuit to detect input voltage of transformer and detecting method for the same
US7746119B2 (en) * 2008-09-18 2010-06-29 Power Integrations, Inc. Leakage compensation for sample and hold devices
US20100158055A1 (en) * 2008-12-18 2010-06-24 Symbol Technologies, Inc. Method and apparatus for controlling and monitoring laser power in barcode readers
CN101629973B (zh) * 2009-06-09 2011-04-20 中国人民解放军国防科学技术大学 适用于低电压供电的无运放高精度电流采样电路
CN101840241B (zh) * 2010-03-30 2015-01-21 北京中星微电子有限公司 一种差分电流采样电路及线性调压器
US20130154714A1 (en) * 2011-12-20 2013-06-20 Conexant Systems, Inc. Current-mode sample and hold for dead time control of switched mode regulators
CN104977450B (zh) 2014-04-03 2019-04-30 深圳市中兴微电子技术有限公司 一种电流采样电路及方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023489A (en) * 1989-05-10 1991-06-11 U.S. Philips Corporation Integrator circuit
US5760616A (en) * 1995-09-05 1998-06-02 Lucent Technologies, Inc. Current copiers with improved accuracy
CN1234902A (zh) * 1996-09-16 1999-11-10 爱特梅尔股份有限公司 用于开关电流存储单元的时钟直通减少系统
CN1720661A (zh) * 2003-08-04 2006-01-11 精工爱普生株式会社 差分电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3486912A4 *

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CN106415282B (zh) 2019-06-21
EP3486912B1 (en) 2021-04-21
CN106415282A (zh) 2017-02-15
KR20180033116A (ko) 2018-04-02
EP3486912A1 (en) 2019-05-22
KR101947303B1 (ko) 2019-02-12
US20180053564A1 (en) 2018-02-22
US10186328B2 (en) 2019-01-22

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