WO2016066075A1 - 一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路 - Google Patents

一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路 Download PDF

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WO2016066075A1
WO2016066075A1 PCT/CN2015/092895 CN2015092895W WO2016066075A1 WO 2016066075 A1 WO2016066075 A1 WO 2016066075A1 CN 2015092895 W CN2015092895 W CN 2015092895W WO 2016066075 A1 WO2016066075 A1 WO 2016066075A1
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transistor
output
voltage
stage circuit
substrate driving
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PCT/CN2015/092895
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English (en)
French (fr)
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唐样洋
张臣雄
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华为技术有限公司
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Priority to EP15854770.3A priority Critical patent/EP3214759A4/en
Priority to KR1020177014439A priority patent/KR101926003B1/ko
Priority to JP2017523450A priority patent/JP2017533666A/ja
Publication of WO2016066075A1 publication Critical patent/WO2016066075A1/zh
Priority to US15/581,445 priority patent/US10270391B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/38—Positive-feedback circuit arrangements without negative feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
    • H03F3/45219—Folded cascode stages
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    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45273—Mirror types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45659—Controlling the loading circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/135—Indexing scheme relating to amplifiers there being a feedback over one or more internal stages in the global amplifier
    • H—ELECTRICITY
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/153—Feedback used to stabilise the amplifier
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    • H03F2200/87—Indexing scheme relating to amplifiers the cross coupling circuit being realised only by MOSFETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45028—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are folded cascode coupled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45036—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are single transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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    • H03F2203/45054—Indexing scheme relating to differential amplifiers the cascode stage of the cascode dif amp being a current mirror
    • H—ELECTRICITY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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    • H03F2203/45114—Indexing scheme relating to differential amplifiers the differential amplifier contains another differential amplifier in its feedback circuit
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    • H03F2203/45124—Indexing scheme relating to differential amplifiers the folded cascode stage of the folded cascode dif amp being a current mirror
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    • H03F2203/45134—Indexing scheme relating to differential amplifiers the whole differential amplifier together with other coupled stages being fully differential realised
    • H—ELECTRICITY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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    • H03F2203/45221—Indexing scheme relating to differential amplifiers the output signal being taken from the two complementary outputs of the differential amplifier
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45281—One SEPP output stage being added to the differential amplifier
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45288—Differential amplifier with circuit arrangements to enhance the transconductance
    • H—ELECTRICITY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC

Definitions

  • the present invention claims the prior application priority of the application No. 201410603919.X, entitled “An Ultra Low Operating Voltage Rail-to-Rail Operational Amplifier and Its Differential Input Amplifier Stage Circuit and Output Stage Circuit", filed on October 30, 2014.
  • the content of the above-mentioned prior application is incorporated herein by reference.
  • the present invention relates to the field of electronic technologies, and in particular, to an ultra-low operating voltage rail-to-rail operational amplifier and a differential input amplification stage circuit and an output stage circuit thereof.
  • the transconductance of the differential input stage is caused by a change in the threshold voltage and equivalent channel length of the substrate driving transistor due to physical factors in the process or noise factors in the actual operating state.
  • the difference that is, the current input to the amplifier stage will produce a corresponding nonlinear change, resulting in instability of the operational amplifier.
  • the existing rail-to-rail output circuit is very complicated and relatively expensive when the operational amplifier is operated under ultra-low voltage.
  • Embodiments of the present invention provide an ultra-low operating voltage rail-to-rail operational amplifier and a differential input amplification stage circuit thereof to improve stability of an ultra-low operating voltage rail-to-rail operational amplifier under different noise conditions. Sex.
  • the present invention also provides an output stage circuit to reduce the cost of an ultra low operating voltage rail-to-rail operational amplifier.
  • a first aspect of the present invention provides a differential input amplification stage circuit for connecting an output stage circuit to differentially amplify the received first and second input voltages and output the same to an output stage circuit
  • the differential input amplification stage circuit including a voltage unit, a first substrate driving transistor, a second substrate driving transistor, a first mirror current source, a second mirror current source, and a differential amplifying unit
  • the voltage unit includes a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal, the first voltage output terminal being coupled to the first and second substrate driving transistors to output a control voltage to the first and second substrate driving transistors
  • the first and the The two substrate driving transistors respectively receive the first input voltage and the second input voltage, and respectively convert the first and second input voltages into first and second output currents
  • the first mirror current source is connected to the a first substrate driving transistor to receive the first output current
  • the second mirror current source being coupled to the second substrate driving transistor to receive the second output a differential amplification unit connected to the first to
  • a control end of the first substrate driving transistor is grounded, and a first end of the first substrate driving transistor is connected to the first voltage output end, Receiving a control voltage, a substrate of the first substrate driving transistor receives the first input voltage, and a second end of the first substrate driving transistor is coupled to the first mirror current source to output the first An output current is supplied to the first mirror transistor, a control terminal of the second substrate driving transistor is grounded, and a first end of the second substrate driving transistor is connected to the first voltage output terminal to receive a control voltage
  • the substrate of the second substrate driving transistor receives the second input voltage, and the second end of the second substrate driving transistor is coupled to the second mirror current source to output the second output current To the second mirror transistor.
  • the voltage unit includes a third substrate driving transistor, a fourth substrate driving transistor, and a first transistor, and a control terminal of the third substrate driving transistor receives a first bias voltage to control the first to third voltages a voltage outputted from the output terminal, a first end of the third substrate driving transistor receives an operating voltage, and a second end of the third substrate driving transistor serves as a second voltage output terminal, the third substrate driving transistor a substrate connected to a control end of the fourth substrate driving transistor, a first end of the fourth substrate driving transistor receiving the operating voltage, and a second end of the fourth substrate driving transistor as the a voltage output end, a substrate of the fourth substrate driving transistor is connected to a control end of the first transistor, a first end of the first transistor receives the operating voltage, and a second of the first transistor The terminal serves as the third voltage output terminal.
  • the differential amplifying unit includes a fifth substrate driving transistor, a second transistor, a third transistor, a fourth transistor, and a fifth a transistor and a sixth transistor, a control end of the fifth substrate driving transistor is connected to a second end of the fourth substrate driving transistor, and a first end of the fifth substrate driving transistor receives the operating voltage, a second end of the fifth substrate driving transistor is connected to a first end of the second transistor, and a substrate of the fifth substrate driving transistor is connected to a second end of the fourth substrate driving transistor, a control end of the second transistor is coupled to a second end of the second transistor, a first end of the second transistor is further coupled to a first end of the third transistor, and a second end of the third transistor
  • the terminal is further connected to the second end of the fourth transistor, the control end of the third transistor is connected to the second end of the third transistor, and the control end of the fourth transistor is connected to the third voltage output end , said a first end of the
  • the first mirror current source includes a seventh transistor, an eighth transistor, and a ninth transistor, and the seventh transistor is controlled.
  • the first end of the seventh transistor is connected to the second end of the eighth transistor to receive the first output current and the first regulated current
  • the seventh transistor a second end connected to the second voltage output terminal and connected to the control terminal of the eighth transistor
  • the control terminal of the eighth transistor being further connected to the control terminal of the ninth transistor
  • the eighth a first end of the transistor is grounded
  • a first end of the ninth transistor is grounded
  • a second end of the ninth transistor is coupled to the output stage circuit for outputting the first predetermined current to the output stage circuit .
  • the second image current source includes a tenth transistor, an eleventh transistor, and a twelfth transistor, the tenth transistor
  • the control terminal receives the operating voltage
  • the first end of the tenth transistor is coupled to the second end of the eleventh transistor to receive the second output current and the second regulated current
  • a second end of the ten transistor is connected to the third voltage output terminal and is connected to a control end of the eleventh transistor
  • a control end of the eleventh transistor is further connected to a control end of the twelfth transistor
  • the first end of the eleventh transistor is grounded, the first end of the twelfth transistor is grounded, and the second end of the twelfth transistor is connected to the output stage circuit for outputting the second A predetermined current is supplied to the output stage circuit.
  • the first to fifth substrate driving transistors are N-type substrate driving transistors, and the first to fifth linings
  • the control terminal, the first end and the second end of the bottom driving transistor are respectively a gate, a source and a drain of the N-type substrate driving transistor
  • the first to third transistors are N-type transistors
  • the control terminal, the first terminal and the second terminal of the third transistor are respectively a gate, a source and a drain of the N-type transistor
  • the fourth to twelfth transistors are P-type transistors
  • the control terminal, the first terminal and the second terminal of the two transistors are respectively a gate, a source and a drain of the fourth to twelfth transistors.
  • an output stage circuit for connecting to a differential input amplification stage circuit for receiving first and second predetermined currents, the output stage circuit comprising an amplification unit and an output unit, the amplification unit being coupled to
  • the differential input amplification stage circuit receives the first and second predetermined currents, and amplifies the first and second predetermined currents, and outputs first and second amplification currents, the output unit is connected to
  • the amplifying unit receives the first and second amplifying currents, and inversely inverts the first and second amplifying currents, and converts them into an output voltage, so that the output voltage is in the work Between voltage and zero volts.
  • the amplifying unit includes first to fourth transistors, and a control end of the first transistor is connected to a control end of the second transistor, the first transistor The first end receives the operating voltage, and the second end of the first transistor is connected to the third transistor a second end, the second end of the first transistor is further connected to the output unit to output a first amplification current, and a control end of the second transistor is further connected to a second end of the fourth transistor, a first terminal of the second transistor receives the operating voltage, a second end of the second transistor is coupled to a second terminal of the fourth transistor, and a control terminal of the third transistor receives a first bias voltage a second terminal of the third transistor is connected to the differential input amplifier stage circuit to receive the first predetermined current, and a control terminal of the fourth transistor receives the first bias voltage, the fourth transistor One end is grounded, a second end of the fourth transistor is connected to the differential input amplification stage circuit to receive the second predetermined current, and a second end of the
  • the output unit includes a substrate driving transistor and a fifth transistor, and a control end of the first substrate driving transistor is connected to a second end of the first transistor to receive the first amplification current, a first end of the first substrate driving transistor receives the operating voltage, and a second end of the first substrate driving transistor is connected Up to a second end of the fifth transistor, a substrate of the substrate driving transistor receives a second bias voltage, and a control end of the fifth transistor is coupled to a second end of the third transistor to receive The second amplification current is described, the first end of the fifth transistor is grounded, and the second end of the fifth transistor outputs the output voltage.
  • the output unit further includes a first resistor, a second resistor, a first capacitor, and a second capacitor, the first resistor Between the control terminal of the substrate driving transistor and the second terminal of the substrate driving transistor in series with the first capacitor, the second resistor and the second capacitor are connected in series with the fifth transistor The control terminal is between the second end of the fifth transistor.
  • the amplifying unit further includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, the first transistor The second end is connected to the second end of the third transistor through the sixth and seventh transistors, and the second end of the second transistor is connected to the fourth transistor through the seventh and eighth transistors a second end, the control terminal of the sixth transistor receives the operating voltage, a first end of the sixth transistor is connected to a second end of the seventh transistor, and a second end of the sixth transistor is connected to the second end a first end of the seventh transistor, a control terminal of the seventh transistor is grounded, and a control terminal of the eighth transistor Receiving a ground, a first end of the eighth transistor is coupled to a second end of the ninth transistor, and a second end of the eighth transistor is coupled to a first end of the ninth transistor, the ninth transistor The control terminal receives the operating voltage.
  • the first transistor, the second transistor, the seventh transistor, and the eighth transistor are N-type transistors, a control terminal, a first end and a second end of a transistor are respectively a gate, a source and a drain of the N-type transistor, the third transistor, the fourth transistor, the fifth transistor, the The sixth transistor and the ninth transistor are P-type transistors, and the control terminal and the first end of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the ninth transistor And the second end is a gate, a source and a drain of the P-type transistor, respectively.
  • an ultra-low operating voltage rail-to-rail operational amplifier including the differential input amplification stage circuit provided by any of the above possible implementation manners, and the output stage circuit provided by any of the above possible implementation manners.
  • the differential input amplification stage circuit is coupled to the output stage circuit.
  • the differential input amplification stage circuit includes a differential amplification unit, and the differential amplification unit is under the action of the control voltage outputted by the first to third voltage output terminals.
  • the differential input amplifier stage circuit can output a correct and stable current value, which improves the stability of the output of the differential input amplifier stage circuit, thereby enabling an ultra-low operating voltage rail-to-rail operation of the differential input amplifier stage circuit.
  • the amplifier has good stability.
  • FIG. 1 is a block diagram of a differential input amplification stage circuit according to an embodiment of the first aspect of the present invention
  • Figure 2 is a circuit diagram of Figure 1;
  • FIG. 3 is a block diagram of an output stage circuit according to an embodiment of a second aspect of the present invention.
  • Figure 4 is a circuit diagram of Figure 3;
  • FIG. 5 is a block diagram of an ultra-low operating voltage rail-to-rail operational amplifier according to an embodiment of the third aspect of the present invention.
  • FIG. 6 is a first simulation diagram of an ultra-low operating voltage rail-to-rail operational amplifier according to a third aspect of the present invention.
  • FIG. 7 is a second simulation diagram of an ultra-low operating voltage rail-to-rail operational amplifier according to a third aspect of the present invention.
  • FIG. 8 is a third simulation diagram of an ultra-low operating voltage rail-to-rail operational amplifier according to a third aspect of the present invention.
  • Embodiments of the present invention provide an ultra-low operating voltage rail-to-rail operational amplifier and a differential input amplification stage circuit and an output stage circuit thereof for improving the stability of an ultra-low operating voltage rail-to-rail operational amplifier and reducing an ultra-low operating voltage.
  • a first embodiment of the present invention provides a differential input amplification stage circuit 100.
  • the differential input amplifier stage circuit 100 is configured to connect an output stage circuit 200 to differentially amplify the received first and second input voltages V in- and V in+ to the output stage circuit 200.
  • the differential input amplification stage circuit 100 includes a voltage unit 10, a first substrate driving transistor 20, a second substrate driving transistor 30, a first mirror current source 40, a second mirror current source 50, and a differential amplifying unit 60.
  • the voltage unit 10 includes a first voltage output terminal 11 , a second voltage output terminal 12 , and a third voltage output terminal 13 .
  • the first voltage output terminal 11 is connected to the first substrate driving transistor 20 and the second substrate driving transistor 30 to output a control voltage V s to the first substrate driving transistor 20 and the first The two substrate drive transistors 30.
  • the first and second substrate driving transistors 20 and 30 respectively receive the first input voltage V in ⁇ and the second input voltage V in+ , and respectively turn the first and second input voltages V in ⁇ and V in+
  • the first and second output currents are generated.
  • the first mirror current source 40 is coupled to the first substrate drive transistor 20 to receive the first output current.
  • the second mirror current source 50 is coupled to the second substrate drive transistor 30 to receive the second output current.
  • the differential amplifying unit 60 is connected to the first to third voltage output terminals 11-13 to output a first regulated current to the voltage under the voltages output by the first to third voltage output terminals 11-13. First mirroring the current source 40 and outputting a second regulated current to the second mirror current source 50, the first and second mirror current sources 40 and 50 being coupled to the second and third voltage output terminals 12, respectively And 13, to receive the control voltage.
  • the first mirror current source 40 outputs a first predetermined current I out+ to the output stage circuit 200 according to the first output current and the first adjustment current
  • the second mirror current source 50 is according to the second adjusting the output current and the second current output of the second predetermined current I out- to the output stage circuit 200, so that the differential input circuit of the transconductance amplifier stage 100 constant.
  • the control terminal of the first substrate driving transistor 20 is grounded.
  • a first end of the first substrate driving transistor 20 is coupled to the first voltage output terminal 11 to receive a control voltage V s .
  • the substrate of the first substrate driving transistor 20 receives the first input voltage V in- .
  • a second end of the first substrate driving transistor 30 is coupled to the first mirror current source 40 to output the first output current to the first mirror transistor 40.
  • a control terminal of the second substrate driving transistor 30 is grounded, and a first end of the second substrate driving transistor 30 is connected to the first voltage output terminal 11 to receive a control voltage V s , the second lining a substrate of the bottom drive transistor 30 receives the second input voltage V in+ , and a second end of the second substrate drive transistor 30 is coupled to the second mirror current source 50 to output the second output current to The second mirror transistor 50.
  • the differential input amplifier stage circuit 100 includes a differential amplifying unit 60, and the differential amplifying unit 50 outputs the first respectively under the action of the control voltages outputted by the first to third voltage output terminals 11-13.
  • the differential input amplification stage circuit 100 can output a correct and stable current value, improving the stability of the output of the differential input amplification stage circuit 100, so that the ultra-low operating voltage rail of the differential input amplification stage circuit 100 is Rail op amps have good stability.
  • the output current of the differential input amplifier stage circuit 100 of the present scheme is always kept correct and constant.
  • the level is such that the ultra low operating voltage rail-to-rail operational amplifier with the differential input amplification stage 100 has good stability under different noise conditions.
  • the voltage unit 10 includes a third substrate driving transistor MB1, a fourth substrate driving transistor MB, and a first transistor MB11.
  • the third control terminal of the drive transistor MB1 substrate receives a first bias voltage V b, a first control voltage to the third voltage output from the output terminal 11-13.
  • a first end of the third substrate driving transistor MB1 receives an operating voltage, and a second end of the third substrate driving transistor MB1 serves as the second voltage output terminal 12.
  • the substrate of the third substrate driving transistor MB1 is connected to the control terminal of the fourth substrate driving transistor MB.
  • the first end of the fourth substrate driving transistor MB receives the operating voltage, and the second end of the fourth substrate driving transistor MB serves as the first voltage output terminal 11.
  • the substrate of the fourth substrate driving transistor MB is connected to the control terminal of the first transistor MB11.
  • the first end of the first transistor MB11 receives the operating voltage, and the second end of the first transistor MB11 serves as the third voltage output terminal 13.
  • the differential amplifying unit 60 includes a fifth substrate driving transistor MP4, a second transistor MP2, a third transistor MP21, a fourth transistor MN2, a fifth transistor MN21, and a sixth transistor MP3.
  • a control terminal of the fifth substrate driving transistor MP4 is connected to a second terminal of the fourth substrate driving transistor MB.
  • the first end of the fifth substrate driving transistor MP4 receives the operating voltage.
  • the second end of the fifth substrate driving transistor MP4 is connected to the first end of the second transistor MP2.
  • a substrate of the fifth substrate driving transistor MP4 is connected to a second end of the fourth substrate driving transistor MB.
  • a control end of the second transistor MP2 is connected to the second end of the second transistor MP2, and a first end of the second transistor MP2 is further connected to the first end of the third transistor MP21, the third The second end of the transistor MP21 is also connected to the second end of the fourth transistor MN2, and the control end of the third transistor MP21 is connected to the second end of the third transistor MP21.
  • the control terminal of the fourth transistor MN2 is connected to the third voltage output terminal 13.
  • the first end of the fourth transistor MN2 is grounded, and the second end of the fourth transistor MN2 is connected to the first mirror current source 40 to output the first regulated current to the first mirror current source 40.
  • the first end of the fifth transistor MN21 is grounded, and the second end of the fifth transistor MN21 is connected to the second end of the second transistor MP2 and is connected to the second mirror current source 50 to output the first Second, the current is regulated to the second mirror current source 50.
  • a control terminal of the fifth substrate driving transistor MP4 is further connected to the second voltage output terminal 12.
  • the control terminal of the sixth transistor MP3 receives the bias voltage V b .
  • the first end of the sixth transistor MP3 receives the operating voltage.
  • the second end of the sixth transistor MP3 is connected to the first end of the third transistor MP21.
  • the first voltage output terminal 11 is connected to the control terminal and the substrate of the fifth substrate driving transistor MP4, and controls the voltage of the control terminal of the fifth substrate driving transistor MP4 and the substrate. Voltage (ie back bias voltage). At this time, the first end of the fifth substrate driving transistor MP4 is an operating voltage. Therefore, the fifth substrate driving transistor MP4 functions to control the voltage of the substrate of the fifth substrate driving transistor MP4 by the first voltage output terminal 11 to change its conductivity and its second end output. Current. Further, the first voltage output terminal 11 outputs a voltage V s is adaptive, i.e., the first voltage output terminal 11 of the output voltage V s by adaptively changing of the bias voltage V b.
  • the differential input amplification stage circuit 100 employs an adaptive mechanism.
  • the first mirror current source 40 includes a seventh transistor MN4, an eighth transistor MN1, and a ninth transistor MN3.
  • the control terminal of the seventh transistor MN4 receives the operating voltage.
  • the first end of the seventh transistor MN4 is coupled to the second end of the eighth transistor MN1 to receive the first output current and the first regulated current.
  • the second end of the seventh transistor MN4 is connected to the second voltage output terminal 12 and is connected to the control terminal of the eighth transistor MN1.
  • the control terminal of the eighth transistor MN1 is also connected to the control terminal of the ninth transistor MN3.
  • the first end of the eighth transistor MN1 is grounded.
  • the first end of the ninth transistor MN3 is grounded, and the second end of the ninth transistor MN3 is connected to the output stage circuit 200 for outputting the first predetermined current I out+ to the output stage circuit 200.
  • the second mirror current source 50 includes a tenth transistor MN41, an eleventh transistor MN11, and a twelfth transistor MN31.
  • the control terminal of the tenth transistor MN41 receives the operating voltage.
  • the first end of the tenth transistor MN41 is coupled to the second end of the eleventh transistor MN11 to receive the second output current and the second regulated current.
  • the second end of the tenth transistor MN41 is connected to the third voltage output terminal 13 and is connected to the control terminal of the eleventh transistor MN11.
  • the control terminal of the eleventh transistor MN11 is also connected to the control terminal of the twelfth transistor MN31.
  • the first end of the eleventh transistor MN11 is grounded.
  • the twelfth transistor MN31 of the first terminal, the second terminal of the twelfth transistor MN31 is connected to the output stage circuit 200 for outputting a second predetermined current to the output stage I out- Circuit 200.
  • the differential input amplification stage circuit 100 is applied to an ultra low voltage substrate driven adaptive rail-to-rail ultra low operating voltage rail-to-rail operational amplifier.
  • the first to fifth substrate driving transistors 20, 30, MB1, MB, and MP4 are N-type substrate driving transistors, and the control of the first to fifth substrate driving transistors 20, 30, MB1, MB, and MP4
  • the terminal, the first terminal and the second terminal are respectively a gate, a source and a drain of the N-type substrate driving transistor.
  • the first to third transistors MB11, MP2, and MP21 are N-type transistors.
  • the control terminal, the first terminal and the second terminal of the first to third transistors MB11, MP2 and MP21 are respectively a gate, a source and a drain of the N-type transistor.
  • the fourth to twelfth transistors MN2, MN21, MP3, MN4, MN1, MN3, MN41, MN11, and MN31 are P-type transistors, and the fourth to twelfth transistors MN2, MN21, MP3, MN4, MN1
  • the control terminals, the first terminals, and the second terminals of the MN3, MN41, MN11, and MN31 are respectively a gate, a source, and a drain of the P-type transistor.
  • the first substrate driving transistor 20 is the same as the second substrate driving transistor 30.
  • the second transistor MP2 is identical to the third transistor MP21.
  • the fourth transistor MN2 is the same as the third transistor MN21.
  • the body tube MN41 is the same.
  • the eighth transistor MN1 is the same as the eleventh transistor MN11.
  • the ninth transistor MN3 is the same as the twelfth transistor MN31.
  • the transconductance of the differential input amplification stage circuit 100 can be determined as:
  • g mn1 is a transconductance of the eighth transistor MN1 and the eleventh transistor MN11; g mn2 is a transconductance of the fourth transistor MN2 and the third transistor MN21; g mp2 is the second The transconductance of the transistor MP2 and the third transistor MP21; g mp2 is the transconductance of the fourth substrate driving transistor MB.
  • VDD is the operating voltage
  • V s is the voltage of the output terminal 11 to output a first voltage
  • MN1 to MN3 beta] is a scaling ratio of the size of the size of the MN11 and MN31 scaling ratio
  • ⁇ is the body effect coefficient
  • K mp2 ⁇ p C ox (W / L) mp2
  • K mp4 ⁇ p C ox (W / L) mp4
  • ⁇ p is the carrier effective mobility
  • C ox is Unit gate oxide capacitance
  • W is the transistor channel width
  • L is the channel length of the transistor
  • ⁇ is the substrate Fermi level coefficient
  • V cm is the input voltage value
  • I mp3 is the drain current of the MP3 transistor.
  • the transconductance G m of the differential input amplification stage circuit 100 is within the full operating voltage range. Will remain at a constant value. That is, the output current through the differential input amplifier stage circuit 100 is always maintained at a constant level under the influence of an indeterminate line of process or a threshold voltage or an equivalent communication uncertainty, thereby improving the differential input.
  • the ultra-low operating voltage rail-to-rail operational amplifier of amplifier stage 100 is stable under different noise conditions.
  • an embodiment of the second aspect of the present invention provides an output stage circuit 200 for connecting to the differential input amplification stage circuit 100 to receive first and second predetermined currents I out+ and I. Out- .
  • the output stage circuit 200 includes an amplifying unit 210 and an output unit 220.
  • the amplifying unit 210 is connected to the differential input amplification stage circuit 100 to receive the first and second predetermined currents I out+ and I out- , and to the first and second predetermined currents I out+ and I out - performing amplification and outputting the first and second amplification currents.
  • the output unit 220 is connected to the amplifying unit 210, to receive the first and second amplified current, and the first and second inverted amplified current difference is evaluated and converted to an output voltage V out, so that the output voltage V out between the operating voltage and zero volts.
  • the amplification unit 210 includes first to fourth transistors MP5, MP51, MP7, and MP71.
  • the control terminal of the first transistor MP5 is connected to the control terminal of the second transistor MP51, and the first terminal of the first transistor MP5 receives the operating voltage.
  • the second end of the first transistor MP5 is connected to the second end of the third transistor MP7.
  • the second end of the first transistor MP5 is connected to the output unit 220 to output the first amplified current.
  • the control terminal of the second transistor MP51 is also connected to the second terminal of the fourth transistor MP71.
  • the first end of the second transistor MP51 receives the operating voltage.
  • the second end of the second transistor MP51 is connected to the second end of the fourth transistor MP71.
  • the control terminal of the third transistor MP7 receives the first bias voltage V bn .
  • the second end of the third transistor MP7 is connected to the differential input amplification stage circuit to receive the first predetermined current I out+ , and the control end of the fourth transistor MP71 receives the first bias voltage V bn .
  • the first end of the fourth transistor MP71 is grounded, and the second end of the fourth transistor MP71 is connected to the differential input amplification stage circuit 100 to receive the second predetermined current I out- , the third two
  • the second end of the pole tube MP7 is further connected to the output unit 220 to output the second amplification current, so that the output unit 220 performs differential inversion on the first and second amplification circuits, and turns The output voltage V out is formed .
  • the third and fourth transistors MN71 and MN7 constitute a mirror current source to perform a stable function such that under the adjustment of the first bias voltage V bn , the other one is
  • the mirror current source formed by the first and second transistors MP51 and MP5 acts as a bias. That is, the mirror current source formed by the first and second transistors MP51 and MP5 is controlled by the operating voltage to function as a current source.
  • the mirror current source formed by the first and second transistors MP51 and MP5 and the mirror current source formed by the third and fourth transistors MN71 and MN7 ensure that the output stage circuit can be input at a minimum current (ie, In the case of the first predetermined current I out+ and the second predetermined current I out- ), normal current amplification is also ensured, and the stability of the output is also ensured.
  • the output unit 220 includes a substrate driving transistor MPO and a fifth transistor MNO.
  • a control end of the first substrate driving transistor MPO is connected to a second end of the first transistor MP5 to receive the first amplification current.
  • the first end of the substrate driving transistor MPO receives the operating voltage.
  • a second end of the substrate driving transistor MPO is connected to a second end of the fifth transistor MNO.
  • the substrate of the substrate driving transistor MPO receives a second bias voltage V bp .
  • the control terminal of the fifth transistor MNO is connected to the second terminal of the third transistor MP7 to receive the second amplification current, and the first terminal of the fifth transistor MNO is grounded.
  • the second end of the fifth transistor MNO outputs the output voltage V out .
  • the output unit 220 further includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.
  • the first resistor R1 is connected in series with the first capacitor C1 on the substrate.
  • the second resistor R2 and the second capacitor C2 are connected in series at the control terminal of the fifth transistor MNO and the fifth transistor Between the second ends of the MNO.
  • first resistor R1 and the first capacitor C1 constitute a first filter circuit to filter the first amplification current output by the amplification unit 210 to provide stability of the output stage circuit 200.
  • second resistor R2 and the second capacitor C2 constitute a first filter circuit to filter the second amplification current output by the amplification unit 210 to provide stability of the output stage circuit 200.
  • the amplifying unit 210 further includes a sixth transistor MN4, a seventh transistor MP6, an eighth transistor MP61, and a ninth transistor MN41.
  • the second end of the first transistor MP5 is connected to the second end of the third transistor MN7 through the sixth and seventh transistors MN4 and MP6.
  • the second end of the second transistor MP51 is connected to the second end of the fourth transistor MN71 through the seventh and eighth transistors MP61 and MN41.
  • the control terminal of the sixth transistor MN4 receives the operating voltage.
  • the first end of the sixth transistor MN4 is connected to the second end of the seventh transistor MP6.
  • the second end of the sixth transistor MN4 is connected to the first end of the seventh transistor MP6.
  • the control terminal of the seventh transistor MP6 is grounded.
  • the control terminal of the eighth transistor MP61 is grounded.
  • the first end of the eighth transistor MP61 is connected to the second end of the ninth transistor MN41.
  • the second end of the body tube MP61 is connected to the first end of the ninth transistor MN41.
  • the control terminal of the ninth transistor MN41 receives the operating voltage.
  • control terminals of the seventh transistor MP6 and the eighth transistor MP61 are grounded, and the control terminals of the sixth transistor MN4 and the ninth transistor MN4 receive the operating voltage and remain normally open. state.
  • the seventh transistor MP6 and the eighth transistor MP61 and the sixth transistor MN4 and the ninth transistor MN4 function to amplify a current passing therethrough.
  • the first transistor MP5, the second transistor MP51, the seventh transistor MP6, and the eighth transistor MP61 are N-type transistors.
  • the control terminal, the first terminal and the second terminal of the first transistor MP5 are respectively a gate, a source and a drain of the N-type transistor.
  • the third transistor MP7, the fourth transistor MP71, the fifth transistor MNO, the sixth transistor MN4, and the ninth transistor MN41 are P-type transistors.
  • the control terminal, the first end, and the second end of the third transistor MP7, the fourth transistor MP71, the fifth transistor MNO, the sixth transistor MN4, and the ninth transistor MN41 are respectively the P The gate, source and drain of the transistor.
  • the output stage circuit 200 can realize the function of the rail-to-rail output stage of the ultra-low operating voltage rail-to-rail operational amplifier by using only 10 transistors, compared with the existing complicated rail-to-rail.
  • the output stage circuit simplifies the rail-to-rail output stage, saving the cost of ultra-low operating rail-to-rail op amps.
  • an embodiment of a third aspect of the present invention provides an ultra-low operating voltage rail-to-rail operational amplifier 300.
  • the ultra low operating voltage rail-to-rail operational amplifier 300 includes an embodiment of the first aspect described above that provides the differential input amplification stage circuit 100 and the output stage circuit 200 provided by an embodiment of the second aspect described above. Wherein the differential input amplification stage circuit is connected to the output stage circuit. Since the differential input amplifier stage circuit 100 and the output stage circuit 200 have been specifically described in the embodiments of the first embodiment and the second embodiment, details are not described herein.
  • the ultra low operating voltage rail-to-rail operational amplifier 300 includes the differential input amplification stage circuit 100.
  • the differential input amplifier stage circuit 100 includes a differential amplifying unit 60 that outputs first and second regulated currents respectively under the action of the control voltages outputted by the first to third voltage output terminals.
  • the first and second mirror current sources 40 and 50 are configured such that the first mirror current source 40 outputs the first predetermined current I out+ according to the first output current and the first regulated current, the second The mirror current source 50 outputs the second predetermined current I out- according to the second output current and the second regulated current to maintain a constant transconductance of the differential input amplification stage circuit 100. Therefore, the ultra-low operating voltage rail-to-rail operational amplifier has good stability under different noise conditions.
  • the ultra low operating voltage rail-to-rail operational amplifier 300 includes the output stage circuit 200.
  • the output stage circuit 200 can realize the function of the rail-to-rail output stage of the ultra-low operating voltage rail-to-rail operational amplifier 300 by using only 10 transistors, compared with the existing complex rail-to-rail output stage circuit.
  • the purpose of the rail-to-rail output stage is simplified, thereby saving the cost of the ultra-low operating voltage rail-to-rail operational amplifier 300.
  • FIG. 6 shows the ultra-low working voltage rail when the output voltage V out and the case where the bias voltage at the operational amplifier input voltage rail 300.
  • the load respectively and 17pF 50pF;
  • V out is the output voltage;
  • V in is the input voltage;
  • Offset bias voltage is Known from FIG. 6:
  • the output voltage V out remains substantially linear relationship, and the output voltage V out to reach rail to rail output voltage, i.e., rail to rail voltage of 0V to 900mV, compared to the work The range of voltages.
  • FIG. 7 for a simulation of the simulation of the ultra low operating voltage rail-to-rail operational amplifier 300.
  • the transconductance variation of the ultra-low operating voltage rail-to-rail operational amplifier 300 in the differential input amplification stage of the ultra-low operating voltage rail-to-rail operational amplifier using the adaptive mechanism and the adaptive mechanism is shown in FIG. situation.
  • the transconductance of the ultra-low operating voltage rail-to-rail operational amplifier 300 in the differential input amplifier stage circuit under the adaptive mechanism remains substantially unchanged under different differential input voltage conditions.
  • the transconductance of the differential input amplifier stage circuit 100 of the ultra-low operating voltage rail-to-rail operational amplifier 300 in the present scheme remains substantially unchanged. That is, the current that substantially maintains the output is constant, thereby counteracting the effects of other uncertainties (such as changes in temperature, effects of parasitic resistance, etc.) on the operating state of the ultra-low operating voltage rail-to-rail operational amplifier 300.
  • FIG. 8 is a simulation diagram of simulating the ultra low operating voltage rail-to-rail operational amplifier 300 .
  • Figure 8 shows the total harmonic distortion (THD) condition with different input voltages within the operating voltage range at different output settings of 17kF and 50pF, respectively, at frequencies of 10kHZ and 100kHZ.
  • TDD total harmonic distortion
  • the total harmonic distortion rate of the output harmonic is used to measure ultra-low working power
  • the index of the noise level of the rail-to-rail op amp As can be seen from FIG. 8, the distortion rate of the ultra-low operating voltage rail-to-rail operational amplifier 300 is substantially maintained at -50 db. Therefore, the output noise of the ultra-low operating voltage rail-to-rail operational amplifier 300 is greatly reduced.

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Abstract

一种差分输入放大级电路（100），包括电压单元（10）、第一及第二衬底驱动晶体管（20、30）、第一及第二镜像电流源（40、50）及差分放大单元（60），电压单元（10）包括第一至第三电压输出端（11、12、13），第一电压输出端（11）连接至第一及第二衬底驱动晶体管（20、30），第一及第二衬底驱动晶体管（20、30）分别接收第一及第二输入电压，并将其转出成第一及第二输出电流，差分放大单元（60）在第一至第三电压输出端（11、12、13）的电压作用下分别输出第一及第二调节电流，第一及第二镜像电流源（40、50）分别根据第一输出电流和第一调节电流、及第二输出电流和第二调节电流输出第一及第二预定电流（I out +、I out -），从而维持差分输入放大级电路（100）的跨导恒定，因此，提高了输出的稳定性。另外还提供了输出级电路（200）及超低工作电压轨到轨运算放大电路（300）。

Description

一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路
本发明要求2014年10月30日递交的发明名称为“一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路”的申请号201410603919.X的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及电子技术领域，尤其是涉及一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路。
背景技术
现代半导体工艺的高速发展给传统的模拟器件设计带来了更多的挑战。随着供电电压的持续减小，供电电压自身要求更小且更高完整性。另外，由于互补金属氧化物半导体的阈值电压没有随着晶体管大小的迁徙而相对的线性变化，这样以来，给传统模拟器件设计的调整电压的裕度空间也越来越小，尤其是模拟器件供电在1伏特之下的供电情况。其中，运算放大器是模拟器件中最常用的器件之一，亦是主要器件。随着超低电压供电，运算放大器亟待解决的问题则是宽泛的工作电压范围，以及输出电压的稳定性。
面对超低压衬底驱动的运算放大器，由于工艺上的物理因素或者实际工作状态下噪声因素所造成的衬底驱动晶体管的阈值电压及等效沟道长度的变化而导致差分输入级的跨导不同，即输入到放大级的电流会产生相应的非线性变化，从而导致运算放大器具有不稳定性。另外，运算放大器工作再超低压的状态下，现有的轨到轨输出电路非常复杂，成本相对较高。
发明内容
本发明实施例提供了一种超低工作电压轨到轨运算放大器及其差分输入放大级电路，以提高超低工作电压轨到轨运算放大器在不同噪声情况下的稳定 性。
本发明还提供一种输出级电路，以降低超低工作电压轨到轨运算放大器的成本。
本发明第一方面提供一种差分输入放大级电路，用于连接输出级电路，以将接收的第一及第二输入电压进行差分放大后输出至输出级电路，所述差分输入放大级电路包括电压单元、第一衬底驱动晶体管、第二衬底驱动晶体管、第一镜像电流源、第二镜像电流源及差分放大单元，所述电压单元包括第一电压输出端、第二电压输出端及第三电压输出端，所述第一电压输出端连接至所述第一及第二衬底驱动晶体管，以输出控制电压至所述第一及第二衬底驱动晶体管，所述第一及第二衬底驱动晶体管分别接收第一输入电压及第二输入电压，并分别将所述第一及第二输入电压转出成第一及第二输出电流，所述第一镜像电流源连接至所述第一衬底驱动晶体管，以接收所述第一输出电流，所述第二镜像电流源连接至所述第二衬底驱动晶体管，以接收所述第二输出电流，所述差分放大单元连接至所述第一至第三电压输出端，以在所述第一至第三电压输出端输出的电压作用下输出第一调节电流至所述第一镜像电流源，并输出第二调节电流至所述第二镜像电流源，所述第一及第二镜像电流源分别连接至所述第二及第三电压输出端，以接收控制电压，所述第一镜像电流源根据所述第一输出电流及所述第一调节电流输出第一预定电流至所述输出级电路，所述第二镜像电流源根据所述第二输出电流及所述第二调节电流输出第二预定电流至所述输出级电路，从而维持所述差分输入放大级电路的跨导恒定。
在第一方面的第一种可能的实现方式中，所述第一衬底驱动晶体管的控制端接地，所述第一衬底驱动晶体管的第一端连接至所述第一电压输出端，以接收控制电压，所述第一衬底驱动晶体管的衬底接收所述第一输入电压，所述第一衬底驱动晶体管的第二端连接至所述第一镜像电流源，以输出所述第一输出电流至所述第一镜像晶体管，所述第二衬底驱动晶体管的控制端接地，所述第二衬底驱动晶体管的第一端连接至所述第一电压输出端，以接收控制电压，所述第二衬底驱动晶体管的衬底接收所述第二输入电压，所述第二衬底驱动晶体管的第二端连接至所述第二镜像电流源，以输出所述第二输出电流至所述第二镜像晶体管。
结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所 述电压单元包括第三衬底驱动晶体管、第四衬底驱动晶体管及第一晶体管，所述第三衬底驱动晶体管的控制端接收第一偏置电压，以控制所述第一至第三电压输出端输出的电压，所述第三衬底驱动晶体管的第一端接收工作电压，所述第三衬底驱动晶体管的第二端作为第二电压输出端，所述第三衬底驱动晶体管的衬底连接至所述第四衬底驱动晶体管的控制端，所述第四衬底驱动晶体管的第一端接收所述工作电压，所述第四衬底驱动晶体管的第二端作为所述第一电压输出端，所述第四衬底驱动晶体管的衬底连接至所述第一晶体管的控制端，所述第一晶体管的第一端接收所述工作电压，所述第一晶体管的第二端作为所述第三电压输出端。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述差分放大单元包括第五衬底驱动晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管及第六晶体管，所述第五衬底驱动晶体管的控制端连接至所述第四衬底驱动晶体管的第二端，所述第五衬底驱动晶体管的第一端接收所述工作电压，所述第五衬底驱动晶体管的第二端连接至所述第二晶体管的第一端，所述第五衬底驱动晶体管的衬底连接至所述第四衬底驱动晶体管的第二端，所述第二晶体管的控制端连接至所述第二晶体管的第二端，所述第二晶体管的第一端还连接至所述第三晶体管的第一端，所述第三晶体管的第二端还连接至所述第四晶体管的第二端，所述第三晶体管的控制端连接至所述第三晶体管的第二端，所述第四晶体管的控制端连接所述第三电压输出端，所述第四晶体管的第一端接地，所述第四晶体管的第二端连接至所述第一镜像电流源，以输出所述第一调节电流至所述第一镜像电流源，所述第五晶体管的第一端接地，所述第五晶体管的第二端连接至所述第二晶体管的第二端连接至所述第二镜像电流源，以输出所述第二调节电流至所述第二镜像电流源，所述第五衬底驱动晶体管的控制端还连接至所述第二电压输出端，所述第六晶体管的控制端接收所述偏置电压，所述第六晶体管的第一端接收所述工作电压，所述第六晶体管的第二端连接至所述第三晶体管的第一端。
结合第一方面的第三种可能的实现方式，在第四种可能的实现方式中，所述第一镜像电流源包括第七晶体管、第八晶体管及第九晶体管，所述第七晶体管的控制端接收所述工作电压，所述第七晶体管的第一端连接至所述第八晶体管的第二端，以接收所述第一输出电流及所述第一调节电流，所述第七晶体管 的第二端连接至所述第二电压输出端，并连接至所述第八晶体管的控制端，所述第八晶体管的控制端还连接至所述第九晶体管的控制端，所述第八晶体管的第一端接地，所述第九晶体管的第一端接地，所述第九晶体管的第二端连接至所述输出级电路，用于输出所述第一预定电流至所述输出级电路。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述第二镜像电流源包括第十晶体管、第十一晶体管及第十二晶体管，所述第十晶体管的控制端接收所述工作电压，所述第十晶体管的第一端连接至所述第十一晶体管的第二端，以接收所述第二输出电流及所述第二调节电流，所述第十晶体管的第二端连接至所述第三电压输出端，并连接至所述第十一晶体管的控制端，所述第十一晶体管的控制端还连接至所述第十二晶体管的控制端，所述第十一晶体管的第一端接地，所述第十二晶体管的第一端接地，所述第十二晶体管的第二端连接至所述输出级电路，用于输出所述第二预定电流至所述输出级电路。
结合第一方面的第五种可能的实现方式，在第六种可能的实现方式中，所述第一至第五衬底驱动晶体管为N型衬底驱动晶体管，所述第一至第五衬底驱动晶体管的控制端、第一端及第二端分别为N型衬底驱动晶体管的栅极、源极及漏极，所述第一至第三晶体管为N型晶体管，所述第一至第三晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极，所述第四至第十二晶体管为P型晶体管，所述第四至第十二晶体管的控制端、第一端及第二端分别为所述第四至第十二晶体管的栅极、源极及漏极。
第二方面，提供了一种输出级电路，用于连接至差分输入放大级电路，以接收第一及第二预定电流，所述输出级电路包括放大单元及输出单元，所述放大单元连接至所述差分输入放大级电路，以接收所述第一及第二预定电流，并对所述第一及第二预定电流进行放大，并输出第一及第二放大电流，所述输出单元连接至所述放大单元，以接收所述第一及第二放大电流，并将所述第一及第二放大电流进行求差反相，并转化成输出电压，从而使得所述输出电压在所述工作电压与零伏之间。
在第二方面的第一种可能的实现方式中，所述放大单元包括第一至第四晶体管，所述第一晶体管的控制端连接至所述第二晶体管的控制端，所述第一晶体管的第一端接收工作电压，所述第一晶体管的第二端连接至第三晶体管的第 二端，所述第一晶体管的第二端还连接至所述输出单元，以输出第一放大电流，所述第二晶体管的控制端还连接至所述第四晶体管的第二端，所述第二晶体管的第一端接收所述工作电压，所述第二晶体管的第二端连接至所述第四晶体管的第二端，所述第三晶体管的控制端接收第一偏置电压，所述第三晶体管的第二端连接所述差分输入放大级电路，以接收所述第一预定电流，所述第四晶体管的控制端接收所述第一偏置电压，所述第四晶体管的第一端接地，所述第四晶体管的第二端连接至所述差分输入放大级电路，以接收所述第二预定电流，所述第三二极管的第二端还连接至所述输出单元，以输出所述第二放大电流，以使得所述输出单元对所述第一及第二放大电路进行求差反相，并转成成所述输出电压。
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述输出单元包括衬底驱动晶体管及第五晶体管，所述第一衬底驱动晶体管的控制端连接至所述第一晶体管的第二端，以接收所述第一放大电流，所述第一衬底驱动晶体管的第一端接收所述工作电压，所述第一衬底驱动晶体管的第二端连接至所述第五晶体管的第二端，所述衬底驱动晶体管的衬底接收第二偏置电压，所述第五晶体管的控制端连接至所述第三晶体管的第二端，以接收所述第二放大电流，所述第五晶体管的第一端接地，所述第五晶体管的第二端输出所述输出电压。
结合第二方面的第二种可能的实现方式，在第三种可能的实现方式中，所述输出单元还包括第一电阻、第二电阻、第一电容及第二电容，所述第一电阻与所述第一电容串联在所述衬底驱动晶体管的控制端与所述衬底驱动晶体管的第二端之间，所述第二电阻与所述第二电容串联在所述第五晶体管的控制端与所述第五晶体管的第二端之间。
结合第二方面的第一种可能的实现方式，在第四种可能的实现方式中，所述放大单元还包括第六晶体管、第七晶体管、第八晶体管及第九晶体管，所述第一晶体管的第二端通过所述第六及第七晶体管连接至第三晶体管的第二端，所述第二晶体管的第二端通过所述第七及第八晶体管连接至所述第四晶体管的第二端，所述第六晶体管的控制端接收所述工作电压，所述第六晶体管的第一端连接至所述第七晶体管的第二端，所述第六晶体管的第二端连接至所述第七晶体管的第一端，所述第七晶体管的控制端接地，所述第八晶体管的控制端 接收接地，所述第八晶体管的第一端连接至所述第九晶体管的第二端，所述第八晶体管的第二端连接至所述第九晶体管的第一端，所述第九晶体管的控制端接收所述工作电压。
结合第二方面的第四种可能的实现方式，在第五种可能的实现方式中，所述第一晶体管、所述第二晶体管、第七晶体管及第八晶体管为N型晶体管，所述第一晶体管的控制端、第一端及第二端分别为所述N型晶体管的栅极、源极及漏极，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及所述第九晶体管为P型晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及所述第九晶体管的控制端、第一端及第二端分别为所述P型晶体管的栅极、源极及漏极。
第四方面，提供了一种超低工作电压轨到轨运算放大器，包括上述任一种可能实现方式提供的所述差分输入放大级电路及上述任一种可能实现方式提供的所述输出级电路，所述差分输入放大级电路连接至所述输出级电路。
从以上技术方案可以看出，本发明实施例提供的所述差分输入放大级电路包括差分放大单元，所述差分放大单元在所述第一至第三电压输出端输出的控制电压的作用下，分别输出第一及第二调节电流至所述第一及第二镜像电流源及，使得所述第一镜像电流源根据所述第一输出电流及所述第一调节电流输出所述第一预定电流，所述第二镜像电流源根据所述第二输出电流及所述第二调节电流输出所述第二预定电流，从而维持所述差分输入放大级电路的跨导的恒定。因此，所述差分输入放大级电路可以输出正确且稳定的电流值，提高了所述差分输入放大级电路输出的稳定，从而使得具有所述差分输入放大级电路的超低工作电压轨到轨运算放大器具有良好的稳定性。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一方案的实施例提供的一种差分输入放大级电路框图；
图2为图1的电路图；
图3为本发明第二方案的实施例提供的一种输出级电路框图；
图4为图3的电路图；
图5为本发明第三方案的实施例提供的一种超低工作电压轨到轨运算放大器的框图；
图6为本发明第三方案的一种超低工作电压轨到轨运算放大器的第一仿真图；
图7为本发明第三方案的一种超低工作电压轨到轨运算放大器的第二仿真图；
图8为本发明第三方案的一种超低工作电压轨到轨运算放大器的第三仿真图。
具体实施方式
本发明实施例提供了一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路，用于提高超低工作电压轨到轨运算放大器的稳定性及降低超低工作电压轨到轨运算放大器的成本。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面通过具体实施例，分别进行详细的说明。
请参考图1及图2，本发明第一实施例提供一种差分输入放大级电路100。所述差分输入放大级电路100用于连接一输出级电路200，以将接收的第一及第二输入电压Vin-和Vin+进行差分放大后输出至所述输出级电路200。所述差分输入放大级电路100包括电压单元10、第一衬底驱动晶体管20、第二衬底驱动晶体管30、第一镜像电流源40、第二镜像电流源50及差分放大单元60。所述电压单元10包括第一电压输出端11、第二电压输出端12及第三电压输出端13。所述第一电压输出端11连接至所述第一衬底驱动晶体管20及所述第二衬底驱动晶体管30，以输出控制电压Vs至所述第一衬底驱动晶体管20及所述第二衬底驱动晶体管30。所述第一及第二衬底驱动晶体管20及30分别接收第一输入电压Vin-及第二输入电压Vin+，并分别将所述第一及第二输入电压Vin-和Vin+转出成第一及第二输出电流。所述第一镜像电流源40连接至所述第一衬底驱动晶体管20，以接收所述第一输出电流。所述第二镜像电流源50连接至所述第二衬底驱动晶体管30，以接收所述第二输出电流。所述差分放大单元60连接至所述第一至第三电压输出端11-13，以在所述第一至第三电压输出端11-13输出的电压作用下输出第一调节电流至所述第一镜像电流源40，并输出第二调节电流至所述第二镜像电流源50，所述第一及第二镜像电流源40及50分别连接至所述第二及第三电压输出端12及13，以接收控制电压。所述第一镜像电流源40根据所述第一输出电流及所述第一调节电流输出第一预定电流Iout+至所述输出级电路200，所述第二镜像电流源50根据所述第二输出电流及所述第二调节电流输出第二预定电流Iout-至所述输出级电路200，从而使得所述差分输入放大级电路100的跨导恒定。
具体地，所述第一衬底驱动晶体管20的控制端接地。所述第一衬底驱动晶体管20的第一端连接至所述第一电压输出端11，以接收控制电压Vs。所述第一衬底驱动晶体管20的衬底接收所述第一输入电压Vin-。所述第一衬底驱动晶体管30的第二端连接至所述第一镜像电流源40，以输出所述第一输出电流至所述第一镜像晶体管40。所述第二衬底驱动晶体管30的控制端接地，所述第二衬底驱动晶体管30的第一端连接至所述第一电压输出端11，以接收控制电压Vs，所述第二衬底驱动晶体管30的衬底接收所述第二输入电压Vin+，所述第二衬底驱动晶体管30的第二端连接至所述第二镜像电流源50，以输出所述第二输出电流至所述第二镜像晶体管50。
需要说明的是，由于在现有的差分输入放大级电路中，由于工艺上的物理因素或者实际工作状态下噪声因素(包括温度改变，工作电压波动以及器件的寄生电阻/寄生电容)等不稳定因素存在，导致差分输入放大级电路不能输出正确的电流。在本方案中，所述差分输入放大级电路100包括差分放大单元60，所述差分放大单元50在所述第一至第三电压输出端11-13输出的控制电压的作用下，分别输出第一及第二调节电流至所述第一及第二镜像电流源40及50，使得所述第一镜像电流源40根据所述第一输出电流及所述第一调节电流输出所述第一预定电流Iout+，所述第二镜像电流源50根据所述第二输出电流及所述第二调节电流输出所述第二预定电流Iout-，从而维持所述差分输入放大级电路100的跨导的恒定。因此，所述差分输入放大级电路100可以输出正确且稳定的电流值，提高了所述差分输入放大级电路100输出的稳定，使得具有所述差分输入放大级电路100的超低工作电压轨到轨运算放大器具有良好的稳定性。
因此，即使超低工作电压轨到轨运算放大器存在工艺上或阀值电压或等效沟通等不确定因素影响下，由于本方案所述差分输入放大级电路100的输出电流始终保持在正确且恒定水准，使得具有所述差分输入放大级100的所述超低工作电压轨到轨运算放大器在不同噪声情况下具有良好的稳定性。
请继续参阅图2，具体地，所述电压单元10包括第三衬底驱动晶体管MB1、第四衬底驱动晶体管MB及第一晶体管MB11。所述第三衬底驱动晶体管MB1的控制端接收第一偏置电压Vb，以控制所述第一至第三电压输出端11-13输出的电压。所述第三衬底驱动晶体管MB1的第一端接收工作电压，所述第三衬底驱动晶体管MB1的第二端作为所述第二电压输出端12。所述第三衬底驱动晶体管MB1的衬底连接至所述第四衬底驱动晶体管MB的控制端。所述第四衬底驱动晶体管MB的第一端接收所述工作电压，所述第四衬底驱动晶体管MB的第二端作为所述第一电压输出端11。所述第四衬底驱动晶体管MB的衬底连接至所述第一晶体管MB11的控制端。所述第一晶体管MB11的第一端接收所述工作电压，所述第一晶体管MB11的第二端作为所述第三电压输出端13。
所述差分放大单元60包括第五衬底驱动晶体管MP4、第二晶体管MP2、第三晶体管MP21、第四晶体管MN2、第五晶体管MN21及第六晶体管MP3。 所述第五衬底驱动晶体管MP4的控制端连接至所述第四衬底驱动晶体管MB的第二端。所述第五衬底驱动晶体管MP4的第一端接收所述工作电压。所述第五衬底驱动晶体管MP4的第二端连接至所述第二晶体管MP2的第一端。所述第五衬底驱动晶体管MP4的衬底连接至所述第四衬底驱动晶体管MB的第二端。所述第二晶体管MP2的控制端连接至所述第二晶体管MP2的第二端，所述第二晶体管MP2的第一端还连接至所述第三晶体管MP21的第一端，所述第三晶体管MP21的第二端还连接至所述第四晶体管MN2的第二端，所述第三晶体管MP21的控制端连接至所述第三晶体管MP21的第二端。所述第四晶体管MN2的控制端连接所述第三电压输出端13。所述第四晶体管MN2的第一端接地，所述第四晶体管MN2的第二端连接至所述第一镜像电流源40，以输出所述第一调节电流至所述第一镜像电流源40。所述第五晶体管MN21的第一端接地，所述第五晶体管MN21的第二端连接至所述第二晶体管MP2的第二端连接至所述第二镜像电流源50，以输出所述第二调节电流至所述第二镜像电流源50。所述第五衬底驱动晶体管MP4的控制端还连接至所述第二电压输出端12。所述第六晶体管MP3的控制端接收所述偏置电压Vb。所述第六晶体管MP3的第一端接收所述工作电压。所述第六晶体管MP3的第二端连接至所述第三晶体管MP21的第一端。
需要说明的是，所述第一电压输出端11连接至所述第五衬底驱动晶体管MP4的控制端及衬底，控制了所述第五衬底驱动晶体管MP4的控制端的电压及衬底的电压(即背偏置电压)。此时，所述第五衬底驱动晶体管MP4的第一端为工作电压。因此，所述第五衬底驱动晶体管MP4的作用是通过所述第一电压输出端11控制所述第五衬底驱动晶体管MP4的衬底的电压来改变其导通性及其第二端输出电流。另外，所述第一电压输出端11输出的电压Vs是自适应的，即所述第一电压输出端11输出的电压Vs通过所述偏置电压Vb的改变而自适应。同理，所述第二及第二电压输出端12及13输出的电压也是自适应的，即所述第二及第三电压输出端输出的电压通过所述偏置电压的改变而自适应。因此，所述差分输入放大级电路100采用自适应机制。
所述第一镜像电流源40包括第七晶体管MN4、第八晶体管MN1及第九晶体管MN3。所述第七晶体管MN4的控制端接收所述工作电压。所述第七晶体管MN4的第一端连接至所述第八晶体管MN1的第二端，以接收所述第一 输出电流及所述第一调节电流。所述第七晶体管MN4的第二端连接至所述第二电压输出端12，并连接至所述第八晶体管MN1的控制端。所述第八晶体管MN1的控制端还连接至所述第九晶体管MN3的控制端。所述第八晶体管MN1的第一端接地。所述第九晶体管MN3的第一端接地，所述第九晶体管MN3的第二端连接至所述输出级电路200，用于输出所述第一预定电流Iout+至所述输出级电路200。
所述第二镜像电流源50包括第十晶体管MN41、第十一晶体管MN11及第十二晶体管MN31。所述第十晶体管MN41的控制端接收所述工作电压。所述第十晶体管MN41的第一端连接至所述第十一晶体管MN11的第二端，以接收所述第二输出电流及所述第二调节电流。所述第十晶体管MN41的第二端连接至所述第三电压输出端13，并连接至所述第十一晶体管MN11的控制端。所述第十一晶体管MN11的控制端还连接至所述第十二晶体管MN31的控制端。所述第十一晶体管MN11的第一端接地。所述第十二晶体管MN31的第一端接地，所述第十二晶体管MN31的第二端连接至所述输出级电路200，用于输出所述第二预定电流Iout-至所述输出级电路200。
在本实施方式中，所述差分输入放大级电路100应用于超低压衬底驱动自适应轨到轨超低工作电压轨到轨运算放大器中。所述第一至第五衬底驱动晶体管20、30、MB1、MB及MP4为N型衬底驱动晶体管，所述第一至第五衬底驱动晶体管20、30、MB1、MB及MP4的控制端、第一端及第二端分别为N型衬底驱动晶体管的栅极、源极及漏极。所述第一至第三晶体管MB11、MP2及MP21为N型晶体管。所述第一至第三晶体管MB11、MP2及MP21的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。所述第四至第十二晶体管MN2、MN21、MP3、MN4、MN1、MN3、MN41、MN11及MN31为P型晶体管，所述第四至第十二晶体管MN2、MN21、MP3、MN4、MN1、MN3、MN41、MN11及MN31的控制端、第一端及第二端分别为所述P型晶体管的栅极、源极及漏极。
需要说明的是，所述第一衬底驱动晶体管20与所述第二衬底驱动晶体管30相同。所述第二晶体管MP2与所述第三晶体管MP21相同。所述第四晶体管MN2与所述第三晶体管MN21相同。所述第七晶体管MN4与所述第十晶 体管MN41相同。所述第八晶体管MN1与所述第十一晶体管MN11相同。所述第九晶体管MN3与所述第十二晶体管MN31相同。
根据图2及上述的所述差分输入放大级电路100的电路结构，可以确定所述差分输入放大级电路100的跨导为：
Figure PCTCN2015092895-appb-000001
其中，gmn1为所述第八晶体管MN1及所述第十一晶体管MN11的跨导；gmn2为所述第四晶体管MN2与所述第三晶体管MN21的跨导；gmp2为所述第二晶体管MP2与所述第三晶体管MP21的跨导；gmp2为所述第四衬底驱动晶体管MB的跨导。
将所述差分输入放大级电路中的各个相应晶体管的跨导带入上述公式可以得到：
Figure PCTCN2015092895-appb-000002
其中，VDD为所述工作电压；Vs为所述第一电压输出端11输出的电压；β为MN3对MN1的大小缩放比以及MN31对MN11的大小缩放比；Vb和Vs为自适应偏置电压；Υ为体效应系数、Kmp2＝μpCox(W/L)mp2、Kmp4＝μpCox(W/L)mp4；μp为载流子有效迁移率；Cox为单位栅氧化物电容；W为晶体管沟道宽度，L为晶体管的沟道长度，Φ为衬底费米能级系数；Vcm为输入电压值；Imp3为MP3晶体管的漏极电流。
通过实验证明：当所述第六晶体管MP3与所述第五衬底驱动晶体管MP4的缩放比例为预设比例时，在全操作电压范围内，所述差分输入放大级电路100的跨导Gm将保持为恒定值。即，在工艺上的不确定行或阀值电压或等效沟通的不确定因素影响下，通过所述差分输入放大级电路100的输出电流始终保持在恒定水准，从而提高了具有所述差分输入放大级100的所述超低工作电压轨到轨运算放大器在不同噪声情况下的稳定性。
请参考图3及图4，本发明第二方案的实施例提供一种输出级电路200，用于连接至所述差分输入放大级电路100，以接收第一及第二预定电流Iout+和Iout-。所述输出级电路200包括放大单元210及输出单元220。所述放大单元210连接至所述差分输入放大级电路100，以接收所述第一及第二预定电流Iout+和Iout-，并对所述第一及第二预定电流Iout+和Iout-进行放大，并输出第一及第二放大电流。所述输出单元220连接至所述放大单元210，以接收所述第一及第二放大电流，并将所述第一及第二放大电流进行求差反相，并转化成输出电压Vout，从而使得所述输出电压Vout在所述工作电压与零伏之间。
具体地，所述放大单元210包括第一至第四晶体管MP5、MP51、MP7、MP71。所述第一晶体管MP5的控制端连接至所述第二晶体管MP51的控制端，所述第一晶体管MP5的第一端接收所述工作电压。所述第一晶体管MP5的第二端连接至第三晶体管MP7的第二端。所述第一晶体管MP5的第二端连接至所述输出单元220，以输出所述第一放大电流。所述第二晶体管MP51的控制端还连接至所述第四晶体管MP71的第二端。所述第二晶体管MP51的第一端接收所述工作电压。所述第二晶体管MP51的第二端连接至所述第四晶体管MP71的第二端。所述第三晶体管MP7的控制端接收第一偏置电压Vbn。所述第三晶体管MP7的第二端连接所述差分输入放大级电路，以接收所述第一预定电流Iout+，所述第四晶体管MP71的控制端接收所述第一偏置电压Vbn。所述第四晶体管MP71的第一端接地，所述第四晶体管MP71的第二端连接至所述差分输入放大级电路100，以接收所述第二预定电流Iout-，所述第三二极管MP7的第二端还连接至所述输出单元220，以输出所述第二放大电流，以使得所述输出单元220对所述第一及第二放大电路进行求差反相，并转成成所述输出电压Vout。
需要说明的是，所述第三及第四晶体管MN71和MN7构成镜像电流源，以起到稳定的作用，使得其在所述第一偏置电压Vbn的调节下对另外一个由所述第一及第二晶体管MP51和MP5构成的镜像电流源起到偏置作用。即，所述第一及第二晶体管MP51和MP5构成的镜像电流源被工作电压控制而起到电流源的作用。其中，所述第一及第二晶体管MP51和MP5构成的镜像电流源与由所述第三及第四晶体管MN71和MN7构成镜像电流源确保了所述输出 级电路可以在极小电流输入(即第一预定电流Iout+及第二预定电流Iout-)的情况之下还能保证正常的电流放大作用，同时还保证输出的稳定性。
所述输出单元220包括衬底驱动晶体管MPO及第五晶体管MNO。所述第一衬底驱动晶体管MPO的控制端连接至所述第一晶体管MP5的第二端，以接收所述第一放大电流。所述衬底驱动晶体管MPO的第一端接收所述工作电压。所述衬底驱动晶体管MPO的第二端连接至所述第五晶体管MNO的第二端。所述衬底驱动晶体管MPO的衬底接收第二偏置电压Vbp。所述第五晶体管MNO的控制端连接至所述第三晶体管MP7的第二端，以接收所述第二放大电流，所述第五晶体管MNO的第一端接地。所述第五晶体管MNO的第二端输出所述输出电压Vout。
进一步地，所述输出单元220还包括第一电阻R1、第二电阻R2、第一电容C1及第二电容C2，所述第一电阻R1与所述第一电容C1串联在所述衬底驱动晶体管MPO的控制端与所述衬底驱动晶体管MPO的第二端之间，所述第二电阻R2与所述第二电容C2串联在所述第五晶体管MNO的控制端与所述第五晶体管MNO的第二端之间。
需要说明的是，所述第一电阻R1与所述第一电容C1构成第一滤波电路来对所述放大单元210输出的第一放大电流进行滤波，以提供所述输出级电路200的稳定性。同理，所述第二电阻R2与所述第二电容C2构成第一滤波电路来对所述放大单元210输出的第二放大电流进行滤波，以提供所述输出级电路200的稳定性。
进一步地，所述放大单元210还包括第六晶体管MN4、第七晶体管MP6、第八晶体管MP61及第九晶体管MN41。所述第一晶体管MP5的第二端通过所述第六及第七晶体管MN4及MP6连接至第三晶体管MN7的第二端。所述第二晶体管MP51的第二端通过所述第七及第八晶体管MP61及MN41连接至所述第四晶体管MN71的第二端。所述第六晶体管MN4的控制端接收所述工作电压。所述第六晶体管MN4的第一端连接至所述第七晶体管MP6的第二端。所述第六晶体管MN4的第二端连接至所述第七晶体管MP6的第一端。所述第七晶体管MP6的控制端接地。所述第八晶体管MP61的控制端接地。所述第八晶体管MP61的第一端连接至所述第九晶体管MN41的第二端。所述第八晶 体管MP61的第二端连接至所述第九晶体管MN41的第一端。所述第九晶体管MN41的控制端接收所述工作电压。
需要说明的是，所述第七晶体管MP6和所述第八晶体管MP61的控制端接地，及所述第六晶体管MN4和所述第九晶体管MN4的控制端接收所述工作电压而保持在常开态。为此，所述第七晶体管MP6和所述第八晶体管MP61及所述第六晶体管MN4和所述第九晶体管MN4起到了对经过其上的电流进行放大的作用。
在本实施例中，所述第一晶体管MP5、所述第二晶体管MP51、第七晶体管MP6及第八晶体管MP61为N型晶体管。所述第一晶体管MP5的控制端、第一端及第二端分别为所述N型晶体管的栅极、源极及漏极。所述第三晶体管MP7、所述第四晶体管MP71、所述第五晶体管MNO、所述第六晶体管MN4及所述第九晶体管MN41为P型晶体管。所述第三晶体管MP7、所述第四晶体管MP71、所述第五晶体管MNO、所述第六晶体管MN4及所述第九晶体管MN41的控制端、第一端及第二端分别为所述P型晶体管的栅极、源极及漏极。
在本实施例中，所述输出级电路200仅使用了10个晶体管即可实现超低工作电压轨到轨运算放大器的轨到轨输出级的功能，相较于现有的复杂的轨到轨输出级电路实现了简化轨到轨输出级的目的，从而节省了超低工作电压轨到轨运算放大器的成本。
请参阅图5，本发明第三方案的实施例提供一种超低工作电压轨到轨运算放大器300。所述超低工作电压轨到轨运算放大器300包括上述第一方案的实施例提供所述差分输入放大级电路100及上述第二方案的实施例提供的输出级电路200。其中，所述差分输入放大级电路连接至所述输出级电路。由于所述差分输入放大级电路100及输出级电路200已在第一方案的实施例和第二方案的实施例中进行了具体详实地描述，在此不再进行赘述。
在本方案中，所述超低工作电压轨到轨运算放大器300包括所述差分输入放大级电路100。所述差分输入放大级电路100包括差分放大单元60，所述差分放大单元50在所述第一至第三电压输出端输出的控制电压的作用下，分别输出第一及第二调节电流至所述第一及第二镜像电流源40及50，使得所述第一镜像电流源40根据所述第一输出电流及所述第一调节电流输出所述第一预定电流Iout+，所述第二镜像电流源50根据所述第二输出电流及所述第二调节 电流输出所述第二预定电流Iout-，从而维持所述差分输入放大级电路100的跨导的恒定。因此，所述超低工作电压轨到轨运算放大器在不同噪声情况下均具有良好的稳定性。另外，所述超低工作电压轨到轨运算放大器300包括所述输出级电路200。所述输出级电路200仅使用了10个晶体管即可实现超低工作电压轨到轨运算放大器300的轨到轨输出级的功能，相较于现有的复杂的轨到轨输出级电路实现了简化轨到轨输出级的目的，从而节省了超低工作电压轨到轨运算放大器300的成本。
请参阅图6，为对超低工作电压轨到轨运算放大器300进行仿真的防振图。图6中显示出当所述超低工作电压轨到轨运算放大器300的输入电压变化下的输出电压Vout情况及其偏置电压值。其中，负载分别为17pF和50pF；Vout为输出电压；Vin为输入电压；Offset为偏置电压。从图6中可知道：由图中可以看出，输出电压Vout基本保持线性关系，及输出电压Vout能达到轨到轨的输出电压，即轨到轨电压为0V到900mV，则为工作电压的范围。从Vin＝200mV到Vin＝800mV的范围内，偏置电压保持不变，为此在基本的工作电压范围内，偏置电压保持不变。因此可知，所述超低工作电压轨到轨运算放大器300的输出稳定。
请参阅图7，为对超低工作电压轨到轨运算放大器300进行仿真的仿真图。图7中显示了所述超低工作电压轨到轨运算放大器300在采用自适应机制下与不采用自适应机制下所述超低工作电压轨到轨运算放大器的差分输入放大级的跨导变化状况。从图7可知：所述超低工作电压轨到轨运算放大器300在自适应机制下的差分输入放大级电路的跨导在不同差分输入电压情况下基本保持不变。由于本方案的超低工作电压轨到轨运算放大器300采用的是自适应机制，故本方案中的超低工作电压轨到轨运算放大器300的差分输入放大级电路100的跨导基本保持不变，也即基本保持输出的电流恒定，从而对抗了其他不确定因素(如温度的变化，寄生电阻的影响等)对所述超低工作电压轨到轨运算放大器300工作状态的影响。
请参阅图8，为对所述超低工作电压轨到轨运算放大器300进行仿真的仿真图。其中，图8显示的是在输出负载分别为17pF和50pF的情况下，频率为10kHZ和100kHZ的不同设定下，随着输入电压在工作电压变化范围内，谐波总失真率(THD)状况。其中，所述输出谐波总失真率是用来衡量超低工作电 压轨到轨运算放大器的噪声大小的指数。从图8可知：所述超低工作电压轨到轨运算放大器300的失真率基本保持在-50db。因此，所述超低工作电压轨到轨运算放大器300的输出噪声被大大地降低。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上对本发明所提供的一种存储单元、存储器及存储单元控制方法进行了详细介绍，对于本领域的一般技术人员，依据本发明实施例的思想，在具体实施例及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (14)

  1. 一种差分输入放大级电路，用于连接输出级电路，以将接收的第一及第二输入电压进行差分放大后输出至输出级电路，其特征在于：所述差分输入放大级电路包括电压单元、第一衬底驱动晶体管、第二衬底驱动晶体管、第一镜像电流源、第二镜像电流源及差分放大单元，所述电压单元包括第一电压输出端、第二电压输出端及第三电压输出端，所述第一电压输出端连接至所述第一及第二衬底驱动晶体管，以输出控制电压至所述第一及第二衬底驱动晶体管，所述第一及第二衬底驱动晶体管分别接收第一输入电压及第二输入电压，并分别将所述第一及第二输入电压转出成第一及第二输出电流，所述第一镜像电流源连接至所述第一衬底驱动晶体管，以接收所述第一输出电流，所述第二镜像电流源连接至所述第二衬底驱动晶体管，以接收所述第二输出电流，所述差分放大单元连接至所述第一至第三电压输出端，以在所述第一至第三电压输出端输出的电压作用下输出第一调节电流至所述第一镜像电流源，并输出第二调节电流至所述第二镜像电流源，所述第一及第二镜像电流源分别连接至所述第二及第三电压输出端，以接收控制电压，所述第一镜像电流源根据所述第一输出电流及所述第一调节电流输出第一预定电流至所述输出级电路，所述第二镜像电流源根据所述第二输出电流及所述第二调节电流输出第二预定电流至所述输出级电路，从而维持所述差分输入放大级电路的跨导恒定。
  2. 根据权利要求1所述的差分输入放大级电路，其特征在于：所述第一衬底驱动晶体管的控制端接地，所述第一衬底驱动晶体管的第一端连接至所述第一电压输出端，以接收控制电压，所述第一衬底驱动晶体管的衬底接收所述第一输入电压，所述第一衬底驱动晶体管的第二端连接至所述第一镜像电流源，以输出所述第一输出电流至所述第一镜像晶体管，所述第二衬底驱动晶体管的控制端接地，所述第二衬底驱动晶体管的第一端连接至所述第一电压输出端，以接收控制电压，所述第二衬底驱动晶体管的衬底接收所述第二输入电压，所述第二衬底驱动晶体管的第二端连接至所述第二镜像电流源，以输出所述第二输出电流至所述第二镜像晶体管。
  3. 根据权利要求2所述的差分输入放大级电路，其特征在于：所述电压单元包括第三衬底驱动晶体管、第四衬底驱动晶体管及第一晶体管，所述第三 衬底驱动晶体管的控制端接收第一偏置电压，以控制所述第一至第三电压输出端输出的电压，所述第三衬底驱动晶体管的第一端接收工作电压，所述第三衬底驱动晶体管的第二端作为第二电压输出端，所述第三衬底驱动晶体管的衬底连接至所述第四衬底驱动晶体管的控制端，所述第四衬底驱动晶体管的第一端接收所述工作电压，所述第四衬底驱动晶体管的第二端作为所述第一电压输出端，所述第四衬底驱动晶体管的衬底连接至所述第一晶体管的控制端，所述第一晶体管的第一端接收所述工作电压，所述第一晶体管的第二端作为所述第三电压输出端。
  4. 根据权利要求3所述的磁性存储器，其特征在于：所述差分放大单元包括第五衬底驱动晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管及第六晶体管，所述第五衬底驱动晶体管的控制端连接至所述第四衬底驱动晶体管的第二端，所述第五衬底驱动晶体管的第一端接收所述工作电压，所述第五衬底驱动晶体管的第二端连接至所述第二晶体管的第一端，所述第五衬底驱动晶体管的衬底连接至所述第四衬底驱动晶体管的第二端，所述第二晶体管的控制端连接至所述第二晶体管的第二端，所述第二晶体管的第一端还连接至所述第三晶体管的第一端，所述第三晶体管的第二端还连接至所述第四晶体管的第二端，所述第三晶体管的控制端连接至所述第三晶体管的第二端，所述第四晶体管的控制端连接所述第三电压输出端，所述第四晶体管的第一端接地，所述第四晶体管的第二端连接至所述第一镜像电流源，以输出所述第一调节电流至所述第一镜像电流源，所述第五晶体管的第一端接地，所述第五晶体管的第二端连接至所述第二晶体管的第二端连接至所述第二镜像电流源，以输出所述第二调节电流至所述第二镜像电流源，所述第五衬底驱动晶体管的控制端还连接至所述第二电压输出端，所述第六晶体管的控制端接收所述偏置电压，所述第六晶体管的第一端接收所述工作电压，所述第六晶体管的第二端连接至所述第三晶体管的第一端。
  5. 根据权利要求4所述的磁性存储器，其特征在于：所述第一镜像电流源包括第七晶体管、第八晶体管及第九晶体管，所述第七晶体管的控制端接收所述工作电压，所述第七晶体管的第一端连接至所述第八晶体管的第二端，以接收所述第一输出电流及所述第一调节电流，所述第七晶体管的第二端连接至所述第二电压输出端，并连接至所述第八晶体管的控制端，所述第八晶体管的 控制端还连接至所述第九晶体管的控制端，所述第八晶体管的第一端接地，所述第九晶体管的第一端接地，所述第九晶体管的第二端连接至所述输出级电路，用于输出所述第一预定电流至所述输出级电路。
  6. 根据权利要求5所述的磁性存储器，其特征在于：所述第二镜像电流源包括第十晶体管、第十一晶体管及第十二晶体管，所述第十晶体管的控制端接收所述工作电压，所述第十晶体管的第一端连接至所述第十一晶体管的第二端，以接收所述第二输出电流及所述第二调节电流，所述第十晶体管的第二端连接至所述第三电压输出端，并连接至所述第十一晶体管的控制端，所述第十一晶体管的控制端还连接至所述第十二晶体管的控制端，所述第十一晶体管的第一端接地，所述第十二晶体管的第一端接地，所述第十二晶体管的第二端连接至所述输出级电路，用于输出所述第二预定电流至所述输出级电路。
  7. 根据权利要求6所述的磁性存储器，其特征在于：所述第一至第五衬底驱动晶体管为N型衬底驱动晶体管，所述第一至第五衬底驱动晶体管的控制端、第一端及第二端分别为N型衬底驱动晶体管的栅极、源极及漏极，所述第一至第三晶体管为N型晶体管，所述第一至第三晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极，所述第四至第十二晶体管为P型晶体管，所述第四至第十二晶体管的控制端、第一端及第二端分别为所述第四至第十二晶体管的栅极、源极及漏极。
  8. 一种输出级电路，用于连接至差分输入放大级电路，以接收第一及第二预定电流，其特征在于：所述输出级电路包括放大单元及输出单元，所述放大单元连接至所述差分输入放大级电路，以接收所述第一及第二预定电流，并对所述第一及第二预定电流进行放大，并输出第一及第二放大电流，所述输出单元连接至所述放大单元，以接收所述第一及第二放大电流，并将所述第一及第二放大电流进行求差反相，并转化成输出电压，从而使得所述输出电压在所述工作电压与零伏之间。
  9. 根据权利要求8所述的输出级电路，其特征在于，所述放大单元包括第一至第四晶体管，所述第一晶体管的控制端连接至所述第二晶体管的控制端，所述第一晶体管的第一端接收工作电压，所述第一晶体管的第二端连接至第三晶体管的第二端，所述第一晶体管的第二端还连接至所述输出单元，以输出第一放大电流，所述第二晶体管的控制端还连接至所述第四晶体管的第二 端，所述第二晶体管的第一端接收所述工作电压，所述第二晶体管的第二端连接至所述第四晶体管的第二端，所述第三晶体管的控制端接收第一偏置电压，所述第三晶体管的第二端连接所述差分输入放大级电路，以接收所述第一预定电流，所述第四晶体管的控制端接收所述第一偏置电压，所述第四晶体管的第一端接地，所述第四晶体管的第二端连接至所述差分输入放大级电路，以接收所述第二预定电流，所述第三二极管的第二端还连接至所述输出单元，以输出所述第二放大电流，以使得所述输出单元对所述第一及第二放大电路进行求差反相，并转成成所述输出电压。
  10. 根据权利要求9所述的输出级电路，其特征在于，所述输出单元包括衬底驱动晶体管及第五晶体管，所述第一衬底驱动晶体管的控制端连接至所述第一晶体管的第二端，以接收所述第一放大电流，所述第一衬底驱动晶体管的第一端接收所述工作电压，所述第一衬底驱动晶体管的第二端连接至所述第五晶体管的第二端，所述衬底驱动晶体管的衬底接收第二偏置电压，所述第五晶体管的控制端连接至所述第三晶体管的第二端，以接收所述第二放大电流，所述第五晶体管的第一端接地，所述第五晶体管的第二端输出所述输出电压。
  11. 根据权利要求10所述的输出级电路，其特征在于，所述输出单元还包括第一电阻、第二电阻、第一电容及第二电容，所述第一电阻与所述第一电容串联在所述衬底驱动晶体管的控制端与所述衬底驱动晶体管的第二端之间，所述第二电阻与所述第二电容串联在所述第五晶体管的控制端与所述第五晶体管的第二端之间。
  12. 根据权利要求9所述的输出级电路，其特征在于，所述放大单元还包括第六晶体管、第七晶体管、第八晶体管及第九晶体管，所述第一晶体管的第二端通过所述第六及第七晶体管连接至第三晶体管的第二端，所述第二晶体管的第二端通过所述第七及第八晶体管连接至所述第四晶体管的第二端，所述第六晶体管的控制端接收所述工作电压，所述第六晶体管的第一端连接至所述第七晶体管的第二端，所述第六晶体管的第二端连接至所述第七晶体管的第一端，所述第七晶体管的控制端接地，所述第八晶体管的控制端接收接地，所述第八晶体管的第一端连接至所述第九晶体管的第二端，所述第八晶体管的第二端连接至所述第九晶体管的第一端，所述第九晶体管的控制端接收所述工作电压。
  13. 根据权利要求12所述的输出级电路，其特征在于，所述第一晶体管、所述第二晶体管、第七晶体管及第八晶体管为N型晶体管，所述第一晶体管的控制端、第一端及第二端分别为所述N型晶体管的栅极、源极及漏极，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及所述第九晶体管为P型晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及所述第九晶体管的控制端、第一端及第二端分别为所述P型晶体管的栅极、源极及漏极。
  14. 一种超低工作电压轨到轨运算放大器，包括如权利要求1-7任一项所述的差分输入放大级电路及如权利要求8-13任一项所述的输出级电路，所述差分输入放大级电路连接至所述输出级电路。
PCT/CN2015/092895 2014-10-30 2015-10-27 一种超低工作电压轨到轨运算放大器及其差分输入放大级电路及输出级电路 WO2016066075A1 (zh)

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