WO2018099305A1 - 一种全局快门cmos像素单元及图像采集方法 - Google Patents

一种全局快门cmos像素单元及图像采集方法 Download PDF

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WO2018099305A1
WO2018099305A1 PCT/CN2017/112353 CN2017112353W WO2018099305A1 WO 2018099305 A1 WO2018099305 A1 WO 2018099305A1 CN 2017112353 W CN2017112353 W CN 2017112353W WO 2018099305 A1 WO2018099305 A1 WO 2018099305A1
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transistor
unit
source
signal
terminal
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PCT/CN2017/112353
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French (fr)
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段杰斌
任铮
蒋宇
温建新
皮常明
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上海集成电路研发中心有限公司
成都微光集电科技有限公司
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Priority to US16/465,218 priority Critical patent/US10939059B2/en
Publication of WO2018099305A1 publication Critical patent/WO2018099305A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H04N25/573—Control of the dynamic range involving a non-linear response the logarithmic type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/73—Circuitry for compensating brightness variation in the scene by influencing the exposure time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to the field of image sensor technologies, and in particular, to a global shutter CMOS pixel unit and an image acquisition method.
  • CMOS image sensor Due to its high-speed output, the global shutter CMOS image sensor has been widely used in monitoring, scientific applications, industrial vision and other fields. At present, high speed and high dynamic imaging have become an increasingly wide demand for image sensors in many applications.
  • the traditional global shutter CMOS image sensor has a low dynamic range of one-shot output image.
  • a multi-exposure composite image can be used to achieve high dynamic images, its digital algorithm is complicated, and the frame rate is greatly reduced, which weakens the advantages of the global shutter pixel high speed.
  • the present invention provides a global shutter CMOS pixel single And comprising: a power source, a pixel generating unit, a signal sample holding unit and a signal output unit; wherein the power source is connected to the pixel generating unit, the signal sample holding unit and the signal output unit; the output end of the pixel generating unit and the signal An input end of the sample and hold unit is connected, and an output end of the signal sample and hold unit is connected to an input end of the signal output unit;
  • the pixel generating unit includes: a first current source, a second current source, a first control signal terminal, a second control signal terminal, a bias voltage signal terminal, a column selection signal terminal, a photodiode, a first transistor, and a second transistor a third transistor, a fourth transistor, a fifth transistor, a first current source, and a second current source; wherein a drain of the first transistor is connected to a positive terminal of the power source, and a gate of the first transistor is connected to a bias voltage terminal, The source of the first transistor is connected to the drain of the second transistor, the drain of the third transistor, and the source of the fourth transistor to a node; the source of the second transistor is connected to the cathode of the photodiode, and the second The gate of the transistor is connected to the column selection signal terminal; the anode of the photodiode is connected to the negative terminal of the power source; the source of the third transistor is connected to the anode of the first current source, and the gate of the third
  • the signal sample-and-hold unit includes: a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, a third control signal terminal, and a fourth control signal terminal; and a source of the sixth transistor as a signal sample-and-hold unit
  • the input terminal is connected to the source of the fifth transistor
  • the drain of the sixth transistor is connected to the source of the seventh transistor and the end of the first capacitor, and the gate of the sixth transistor is connected to the third control signal terminal;
  • the drain of the seventh transistor is connected to one end of the second capacitor
  • the gate of the seventh transistor is connected to the fourth control signal end; the other end of the first capacitor and the other end of the second capacitor are connected to the negative pole of the power source.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all NMOS transistors.
  • the signal output unit includes: an eighth transistor, a ninth transistor, a third current source, and a row selection signal terminal; wherein a gate of the eighth transistor is connected as an input end of the signal output unit to a drain of the seventh transistor, The drain of the eighth transistor is connected to the anode of the power supply, the source of the eighth transistor is connected to the source of the ninth transistor; the drain of the ninth transistor is connected to the anode of the third current source and serves as the final output of the signal output unit The gate of the ninth transistor is connected to the row selection signal terminal; the other end of the third current source is connected to the negative terminal of the power source.
  • the eighth transistor is an NMOS.
  • the present invention further provides an image acquisition method using the global shutter CMOS pixel unit of claim 4, comprising:
  • Step 01 The photodiode starts to be exposed, and after the exposure, the fourth transistor is turned on;
  • Step 02 Turn on the second transistor, the sixth transistor, and the seventh transistor. At this time, the first transistor is maintained in the set sub-threshold region, and then the seventh transistor is turned off. At this time, the second capacitor remains at the first Voltage;
  • Step 03 Turn on the third transistor, at this time, the first transistor is in the saturation region, Afterwards, the sixth transistor is turned off, and at this time, the first capacitor is maintained at the second voltage;
  • Step 04 turning off the second transistor and the third transistor, and then turning off the fourth transistor;
  • Step 05 Turn on the ninth transistor, at this time, the signal output unit outputs a first output voltage, and then, the seventh transistor is turned on, and the signal output unit outputs the second output voltage;
  • Step 06 Turn off the seventh transistor, then turn off the ninth transistor to complete a reading process of the image signal.
  • the invention effectively increases the dynamic range of the signal output by setting the pixel output voltage-photocurrent to a logarithmic relationship, so that the dynamic range of the image output signal is improved while reading at a high speed; further, the pixel unit of the present invention has Eliminate the characteristics of process deviation and effectively improve pixel consistency.
  • FIG. 1 is a circuit diagram of a highly dynamic global shutter CMOS pixel unit in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a timing diagram of an image acquisition method in accordance with a preferred embodiment of the present invention.
  • FIGS. 1 to 2 specific embodiments. It should be noted that the drawings are in a very simplified form, using a non-precise ratio, and are only used to facilitate the purpose of the present embodiment.
  • the global shutter CMOS pixel unit of the embodiment includes: a power supply, a pixel generating unit 1, a signal sample and hold unit 2, and a signal output unit 3; a power supply and pixel generating unit 1, a signal sample and hold unit 2, and a signal output.
  • the unit 3 is connected; the output of the pixel generating unit 1 is connected to the input of the signal sample-and-hold unit 2, and the output of the signal sample-and-hold unit 2 is connected to the input of the signal output unit 3.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 used herein are all NMOS.
  • the pixel generating unit 1 includes: a first current source I1, a second current source I2, a first control signal terminal S1, a second control signal terminal S2, a bias voltage signal terminal BIAS, a column selection signal terminal TX, a photodiode PD, and a a transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first current source I1 and a second current source I2; the drain of the first transistor M1 is connected to the positive terminal VDD of the power supply, The gate of the first transistor M1 is connected to the bias voltage terminal BIAS, and the source of the first transistor M1 is connected to the drain of the second transistor M2, the drain of the third transistor M3, and the source of the fourth transistor M4.
  • a source of the second transistor M2 is connected to a cathode of the photodiode PD, a gate of the second transistor M2 is connected to the column selection signal terminal TX; an anode of the photodiode PD is connected to a cathode VSS of the power source; a source of the third transistor M3 The pole is connected to the anode of the first current source I1, and the gate of the third transistor M3 is opposite to the first control signal terminal S1 The other end of the first current source I1 is connected to the negative terminal VSS of the power supply; the drain of the fourth transistor M4 is connected to the gate of the fifth transistor M5, and the gate of the fourth transistor M4 is connected to the second control terminal S2; The drain of the fifth transistor M5 is connected to the anode VDD of the power source, the source of the fifth transistor M5 is connected to the anode of the second current source I2 and serves as the output terminal of the pixel generating unit; the other end of the second current source I2
  • the signal sample-and-hold unit 2 includes a sixth transistor M6, a seventh transistor M7, a first capacitor C1, a second capacitor C2, a third control signal terminal S3, and a fourth control signal terminal S4.
  • the source of the sixth transistor M6 serves as a signal.
  • the input end of the sample and hold unit 2 is connected to the source of the fifth transistor M5, the drain of the sixth transistor M6 is connected to the source of the seventh transistor M7, one end of the first capacitor C1, and the gate of the sixth transistor M7
  • the third control signal terminal S3 is connected; the drain of the seventh transistor M7 and one end of the second capacitor C2 are connected to each other and serve as an output end of the signal sample-and-hold unit 2, and the gate of the seventh transistor M7 is connected to the fourth control signal terminal S4.
  • the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected to the anode VSS of the power source.
  • the signal output unit 3 includes an eighth transistor M8, a ninth transistor M9, a third current source I3, and a row selection signal terminal RS.
  • the gate of the eighth transistor M8 serves as an input terminal of the signal output unit 3 and a seventh transistor M7.
  • the drain of the eighth transistor M8 is connected to the anode of the power supply VDD, the source of the eighth transistor M8 is connected to the source of the ninth transistor M9, and the drain of the ninth transistor M9 is connected to the third current source I3.
  • the positive terminal is connected and as the final output terminal of the signal output unit 3, the gate of the ninth transistor M9 is connected to the row selection signal terminal RS; the other end of the third current source I3 is connected to the negative electrode VSS of the power source.
  • an image acquisition method performed by using the global shutter CMOS pixel unit of the embodiment described above includes:
  • Step 01 The photodiode starts to be exposed, and after the exposure, the fourth transistor is turned on;
  • Step 02 Turn on the second transistor, the sixth transistor, and the seventh transistor. At this time, the first transistor is maintained in the set sub-threshold region, and then the seventh transistor is turned off. At this time, the second capacitor remains at the first Voltage;
  • the source voltage of the fifth transistor is equal to the first voltage
  • the first voltage is:
  • Va is the value of the first voltage
  • Vbias is the bias voltage
  • Ibias is the bias current
  • Vth M1 is the threshold voltage of the first transistor
  • Vth M5 is the threshold voltage of the fifth transistor
  • n is the subthreshold region ideal Factor
  • I0 is the leakage current when the MOS tube gate source voltage is equal to the threshold voltage
  • Vt is the thermoelectric potential
  • Ip is the photo-generated current of the photodiode
  • IL is the photo-induced diode photo-generated current
  • ⁇ 5 uCox
  • u is the carrier migration
  • Cox is the gate oxide capacitance per unit area.
  • Step 03 Turn on the third transistor, at this time, the first transistor is in the saturation region, and then turn off the sixth transistor, at this time, the first capacitor is maintained at the second voltage;
  • the source voltage of the fifth transistor is equal to the second voltage
  • the second voltage is:
  • Vb is the value of the second voltage
  • Vbias is the bias voltage
  • I1 is the current of the first current source
  • I2 is the current of the second current source
  • Vth M1 is the threshold voltage of the first transistor
  • Vth M5 is the first The threshold voltage of the five transistors
  • ⁇ 1 u1Cox
  • ⁇ 5 u5Cox
  • u1 is the carrier mobility of the first transistor
  • u5 is the carrier mobility of the fifth transistor
  • Cox is the gate oxide capacitance per unit area.
  • Step 04 turning off the second transistor and the third transistor, and then turning off the fourth transistor;
  • Step 05 Turn on the ninth transistor, at this time, the signal output unit outputs a first output voltage, and then, the seventh transistor is turned on, and the signal output unit outputs the second output voltage;
  • the first output voltage is equal to the first voltage
  • Step 06 Turn off the seventh transistor, then turn off the ninth transistor to complete a reading process of the image signal.
  • the threshold voltage of the fifth transistor is opposite to the first voltage and the second voltage. All of them have an influence, and since the first output voltage is equal to the first voltage, the second output voltage is related to the first voltage, and therefore, the first output voltage and the second output voltage are affected, thereby affecting the image signal, and therefore, Can be the first output voltage and the first The two output voltages are subtracted to eliminate the influence of the threshold voltage of the fifth transistor.
  • the specific principle is as follows:
  • the difference between the first voltage Va and the second voltage Vb is:
  • Vout2 (Va+Vb)/2
  • Vout1-Vout2 (Va-Vb)/2.
  • Vout1-Vout2 can eliminate the influence of the threshold voltage of the fifth transistor on the image signal, thereby effectively improving the consistency of the pixel output image.

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Abstract

本发明公开了一种全局快门CMOS像素单元及图像采集方法，该像素单元包括：电源、像素产生单元、信号采样保持单元和信号输出单元；像素产生单元的输出端与信号采样保持单元的输入端相连，信号采样保持单元的输出端与信号输出单元的输入端相连。本发明通过将像素输出电压-光生电流设置为对数关系，有效提高了信号输出的动态范围，使其在高速读取的同时提高了图像输出信号的动态范围；此外，本发明的像素单元具有消除工艺偏差的特点，有效提高了像素单元所输出的图像信号的一致性。

Description

一种全局快门CMOS像素单元及图像采集方法
本申请要求于2016年11月30日提交中国专利局、申请号为CN201611090316.X、名称为“一种全局快门CMOS像素单元 及图像采集方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及图像传感器技术领域，尤其涉及一种全局快门CMOS像素单元及图像采集方法。
技术背景
全局快门CMOS图像传感器由于其高速输出的优点，在监控、科学应用，工业视觉等领域获得了广泛应用。目前，在诸多应用场合中，高速且高动态成像成为图像传感器愈加广泛的需求。
传统全局快门CMOS图像传感器一次曝光输出图像动态范围不高，虽然可以采用多次曝光合成图像实现高动态图像，但其数字算法复杂，而且会大大降低帧率，弱化了全局快门像素高速的优点。
发明概要
本发明的目的在于弥补上述现有技术的不足，本发明旨在提供一种高动态的全局快门CMOS像素单元，从而提高全局快门像素速度。
为了达到上述目的，本发明提供了一种全局快门CMOS像素单 元，其包括：电源、像素产生单元、信号采样保持单元和信号输出单元；其中，电源与像素产生单元、信号采样保持单元和信号输出单元相连；所述像素产生单元的输出端与所述信号采样保持单元的输入端相连，所述信号采样保持单元的输出端与所述信号输出单元的输入端相连；
所述像素产生单元包括：第一电流源、第二电流源、第一控制信号端、第二控制信号端、偏置电压信号端、列选信号端、感光二极管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电流源和第二电流源；其中，第一晶体管的漏极与电源的正极相连，第一晶体管的栅极连接于偏置电压端，所述第一晶体管的源极与第二晶体管的漏极、第三晶体管的漏极、第四晶体管的源极相连接于一节点；第二晶体管的源极与感光二极管的阴极相连，第二晶体管的栅极连接于列选信号端；感光二极管的阳极与电源的负极相连；第三晶体管的源极与第一电流源的正极相连，第三晶体管的栅极与第一控制信号端相连；第一电流源的另一端与电源的负极相连；第四晶体管的漏极与第五晶体管的栅极相连，第四晶体管的栅极与第二控制端相连；第五晶体管的漏极与电源的正极相连，第五晶体管的源极与第二电流源的正极相连并且作为像素产生单元的输出端；第二电流源的另一端与电源的负极相连。
优选地，所述信号采样保持单元包括：第六晶体管、第七晶体管、第一电容、第二电容、第三控制信号端和第四控制信号端；第六晶体管的源极作为信号采样保持单元的输入端与第五晶体管的源极相连， 第六晶体管的漏极与第七晶体管的源极、第一电容的一端相互连接，第六晶体管的栅极与第三控制信号端相连；第七晶体管的漏极与第二电容的一端相互连接并作为信号采样保持单元的输出端，第七晶体管的栅极与第四控制信号端相连；第一电容的另一端、第二电容的另一端均与电源的负极相连。
优选地，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管均为NMOS管。
优选地，信号输出单元包括：第八晶体管、第九晶体管、第三电流源和行选信号端；其中，第八晶体管的栅极作为信号输出单元的输入端与第七晶体管的漏极相连，第八晶体管的漏极与电源的正极相连，第八晶体管的源极与第九晶体管的源极相连；第九晶体管的漏极与第三电流源的正极相连并且作为信号输出单元的最终输出端，第九晶体管的栅极与行选信号端相连；第三电流源的另一端与电源的负极相连。
优选地，所述第八晶体管为NMOS。
为了达到上述目的，本发明还提供了一种采用权利要求4所述的全局快门CMOS像素单元进行的图像采集方法，其特征在于，包括：
步骤01：感光二极管开始曝光，曝光之后，打开第四晶体管；
步骤02：打开第二晶体管、第六晶体管、第七晶体管，此时，第一晶体管保持在所设定的亚阈值区，然后，关断第七晶体管，此时，第二电容保持在第一电压；
步骤03：打开第三晶体管，此时，第一晶体管处在饱和区，然 后，关断第六晶体管，此时，第一电容保持在第二电压；
步骤04：关断第二晶体管、第三晶体管，然后，关断第四晶体管；
步骤05：打开第九晶体管，此时，信号输出单元输出第一输出电压，然后，打开第七晶体管，信号输出单元输出第二输出电压；
步骤06：关断第七晶体管，然后关断第九晶体管，完成对图像信号的一次读取过程。
本发明通过将像素输出电压-光生电流设置为对数关系，有效提高了信号输出的动态范围，使其在高速读取的同时提高了图像输出信号的动态范围；此外，本发明的像素单元具有消除工艺偏差的特点，有效提高了像素的一致性。
附图说明
为能更清楚理解本发明的目的、特点和优点，以下将结合附图对本发明的较佳实施例进行详细描述，其中：
图1为本发明的一个较佳实施例的高动态的全局快门CMOS像素单元的电路示意图
图2为本发明的一个较佳实施例的图像采集方法的时序图。
发明内容
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例，本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
以下结合附图1～2和具体实施例对本发明作进一步详细说明。需说明的是，附图均采用非常简化的形式、使用非精准的比例，且仅用以方便、清晰地达到辅助说明本实施例的目的。
请参阅图1，本实施例的全局快门CMOS像素单元，包括：电源、像素产生单元1、信号采样保持单元2和信号输出单元3；电源与像素产生单元1、信号采样保持单元2和信号输出单元3相连；像素产生单元1的输出端与信号采样保持单元2的输入端相连，信号采样保持单元2的输出端与信号输出单元3的输入端相连。这里所采用的第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8均为NMOS。
像素产生单元1包括：第一电流源I1、第二电流源I2、第一控制信号端S1、第二控制信号端S2、偏置电压信号端BIAS、列选信号端TX、感光二极管PD、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第一电流源I1和第二电流源I2；第一晶体管M1的漏极与电源的正极VDD相连，第一晶体管M1的栅极连接于偏置电压端BIAS，第一晶体管M1的源极与第二晶体管M2的漏极、第三晶体管M3的漏极、第四晶体管M4的源极相连接于一节点；第二晶体管M2的源极与感光二极管PD的阴极相连，第二晶体管M2的栅极连接于列选信号端TX；感光二极管PD的阳极与电源的负极VSS相连；第三晶体管M3的源极与第一电流源I1的正极相连，第三晶体管M3的栅极与第一控制信号端S1相 连；第一电流源I1的另一端与电源的负极VSS相连；第四晶体管M4的漏极与第五晶体管M5的栅极相连，第四晶体管M4的栅极与第二控制端S2相连；第五晶体管M5的漏极与电源的正极VDD相连，第五晶体管M5的源极与第二电流源I2的正极相连并且作为像素产生单元的输出端；第二电流源I2的另一端与电源的负极VSS相连。
信号采样保持单元2包括：第六晶体管M6、第七晶体管M7、第一电容C1、第二电容C2、第三控制信号端S3和第四控制信号端S4；第六晶体管M6的源极作为信号采样保持单元2的输入端与第五晶体管M5的源极相连，第六晶体管M6的漏极与第七晶体管M7的源极、第一电容C1的一端相互连接，第六晶体管M7的栅极与第三控制信号端S3相连；第七晶体管M7的漏极与第二电容C2的一端相互连接并作为信号采样保持单元2的输出端，第七晶体管M7的栅极与第四控制信号端S4相连；第一电容C1的另一端、第二电容C2的另一端均与电源的负极VSS相连。
信号输出单元3包括：第八晶体管M8、第九晶体管M9、第三电流源I3和行选信号端RS；其中，第八晶体管M8的栅极作为信号输出单元3的输入端与第七晶体管M7的漏极相连，第八晶体管M8的漏极与电源的正极VDD相连，第八晶体管M8的源极与第九晶体管M9的源极相连；第九晶体管M9的漏极与第三电流源I3的正极相连并且作为信号输出单元3的最终输出端，第九晶体管M9的栅极与行选信号端RS相连；第三电流源I3的另一端与电源的负极VSS相连。
请参阅图2并结合图1，采用本实施例上述的全局快门CMOS像素单元进行的图像采集方法，包括：
步骤01：感光二极管开始曝光，曝光之后，打开第四晶体管；
步骤02：打开第二晶体管、第六晶体管、第七晶体管，此时，第一晶体管保持在所设定的亚阈值区，然后，关断第七晶体管，此时，第二电容保持在第一电压；
具体的，本步骤02中，当第一晶体管处于所设定的亚阈值区时，第五晶体管的源极电压等于第一电压；
第一电压为：
Figure PCTCN2017112353-appb-000001
其中，Va为第一电压的值，Vbias为偏置电压，Ibias为偏置电流，Vth,M1为第一晶体管的阈值电压，Vth,M5为第五晶体管的阈值电压，n为亚阈值区理想因子，I0为MOS管栅源电压等于阈值电压时的漏电流；Vt为热电势，Ip为感光二极管的光生电流，IL为感光二极管的反向光生电流，β5＝uCox，u为载流子迁移率，Cox为单位面积栅氧化层电容。
步骤03：打开第三晶体管，此时，第一晶体管处在饱和区，然后，关断第六晶体管，此时，第一电容保持在第二电压；
具体的，本步骤03中，当第一晶体管处于饱和区时，第五晶体管的源极电压等于第二电压；
第二电压为：
Figure PCTCN2017112353-appb-000002
其中，Vb为第二电压的值，Vbias为偏置电压，I1为第一电流源的电流，I2为第二电流源的电流，Vth,M1为第一晶体管的阈值电压，Vth,M5为第五晶体管的阈值电压，β1＝u1Cox，β5＝u5Cox，u1为第一晶体管载流子迁移率，u5为第五晶体管载流子迁移率，Cox为单位面积栅氧化层电容。
步骤04：关断第二晶体管、第三晶体管，然后，关断第四晶体管；
步骤05：打开第九晶体管，此时，信号输出单元输出第一输出电压，然后，打开第七晶体管，信号输出单元输出第二输出电压；
具体的，第一输出电压等于第一电压，第二输出电压为：V2＝(Va*C2+Vb*C1)/(C1+C2)，其中，Va为第一电压的值，C2为第二电容的值，Vb为第二输出电压的值，C1为第一电容的值。
步骤06：关断第七晶体管，然后关断第九晶体管，完成对图像信号的一次读取过程。
此外，对图像信号读取并传输到外电路之后，还可以继续对图像信号进行处理，从式(1)和(2)可以看出，第五晶体管的阈值电压对第一电压和第二电压均有影响，并且，由于第一输出电压等于第一电压，第二输出电压与第一电压有关系，因此，会影响到第一输出电压和第二输出电压，从而影响到图像信号，因此，可以将第一输出电压和第 二输出电压进行相减，消去第五晶体管的阈值电压影响，具体原理如下：
第一电压Va和第二电压Vb的差值为：
Figure PCTCN2017112353-appb-000003
由于第一输出电压Vout1＝Va，第二输出电压Vout2＝(Va*C2+Vb*C1)/(C1+C2)，
则有，当C1＝C2时，Vout2＝(Va+Vb)/2
则，Vout1-Vout2＝(Va-Vb)/2。
因此，后续像素处理电路中，将Vout1-Vout2即可消去第五晶体管的阈值电压对图像信号的影响，从而有效地提高了像素输出图像的一致性。
虽然本发明已以较佳实施例揭示如上，然所述实施例仅为了便于说明而举例而已，并非用以限定本发明，本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰，本发明所主张的保护范围应以权利要求书所述为准。

Claims (6)

  1. 一种全局快门CMOS像素单元，其特征在于，包括：电源、像素产生单元、信号采样保持单元和信号输出单元；其中，电源与像素产生单元、信号采样保持单元和信号输出单元相连；所述像素产生单元的输出端与所述信号采样保持单元的输入端相连，所述信号采样保持单元的输出端与所述信号输出单元的输入端相连；
    所述像素产生单元包括：第一电流源、第二电流源、第一控制信号端、第二控制信号端、偏置电压信号端、列选信号端、感光二极管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电流源和第二电流源；其中，第一晶体管的漏极与电源的正极相连，第一晶体管的栅极连接于偏置电压端，所述第一晶体管的源极与第二晶体管的漏极、第三晶体管的漏极、第四晶体管的源极相连接于一节点；第二晶体管的源极与感光二极管的阴极相连，第二晶体管的栅极连接于列选信号端；感光二极管的阳极与电源的负极相连；第三晶体管的源极与第一电流源的正极相连，第三晶体管的栅极与第一控制信号端相连；第一电流源的另一端与电源的负极相连；第四晶体管的漏极与第五晶体管的栅极相连，第四晶体管的栅极与第二控制端相连；第五晶体管的漏极与电源的正极相连，第五晶体管的源极与第二电流源的正极相连并且作为像素产生单元的输出端；第二电流源的另一端与电源的负极相连。
  2. 根据权利要求1所述的一种全局快门CMOS像素单元，其特征在于，所述信号采样保持单元包括：第六晶体管、第七晶体管、第一电容、 第二电容、第三控制信号端和第四控制信号端；第六晶体管的源极作为信号采样保持单元的输入端与第五晶体管的源极相连，第六晶体管的漏极与第七晶体管的源极、第一电容的一端相互连接，第六晶体管的栅极与第三控制信号端相连；第七晶体管的漏极与第二电容的一端相互连接并作为信号采样保持单元的输出端，第七晶体管的栅极与第四控制信号端相连；第一电容的另一端、第二电容的另一端均与电源的负极相连。
  3. 根据权利要求2所述的一种全局快门CMOS像素单元，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管均为NMOS管。
  4. 根据权利要求2所述的一种全局快门CMOS像素单元，其特征在于，信号输出单元包括：第八晶体管、第九晶体管、第三电流源和行选信号端；其中，第八晶体管的栅极作为信号输出单元的输入端与第七晶体管的漏极相连，第八晶体管的漏极与电源的正极相连，第八晶体管的源极与第九晶体管的源极相连；第九晶体管的漏极与第三电流源的正极相连并且作为信号输出单元的最终输出端，第九晶体管的栅极与行选信号端相连；第三电流源的另一端与电源的负极相连。
  5. 根据权利要求4所述的一种全局快门CMOS像素单元，其特征在于，所述第八晶体管为NMOS。
  6. 一种采用权利要求4所述的全局快门CMOS像素单元进行的图像采集方法，其特征在于，包括：
    步骤01：感光二极管开始曝光，曝光之后，打开第四晶体管；
    步骤02：打开第二晶体管、第六晶体管、第七晶体管，此时，第一晶 体管保持在所设定的亚阈值区，然后，关断第七晶体管，此时，第二电容保持在第一电压；
    步骤03：打开第三晶体管，此时，第一晶体管处在饱和区，然后，关断第六晶体管，此时，第一电容保持在第二电压；
    步骤04：关断第二晶体管、第三晶体管，然后，关断第四晶体管；
    步骤05：打开第九晶体管，此时，信号输出单元输出第一输出电压，然后，打开第七晶体管，信号输出单元输出第二输出电压；
    步骤06：关断第七晶体管，然后关断第九晶体管，完成对图像信号的一次读取过程。
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