WO2018001014A1 - 像素电路及其驱动方法、图像传感器及图像获取装置 - Google Patents

像素电路及其驱动方法、图像传感器及图像获取装置 Download PDF

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Publication number
WO2018001014A1
WO2018001014A1 PCT/CN2017/086141 CN2017086141W WO2018001014A1 WO 2018001014 A1 WO2018001014 A1 WO 2018001014A1 CN 2017086141 W CN2017086141 W CN 2017086141W WO 2018001014 A1 WO2018001014 A1 WO 2018001014A1
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Prior art keywords
module
control
voltage
photoelectric conversion
transistor
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PCT/CN2017/086141
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English (en)
French (fr)
Inventor
杨盛际
董学
薛海林
陈小川
刘英明
王海生
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/572,717 priority Critical patent/US10212374B2/en
Publication of WO2018001014A1 publication Critical patent/WO2018001014A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/142—Energy conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • Embodiments of the present disclosure relate to the field of image sensing technologies, and in particular, to a pixel circuit and a driving method thereof, an image sensor, and an image acquiring device.
  • CMOS Complementary Metal-Oxide Semiconductor
  • CMOS is a circuit composed of a PMOS and an NMOS transistor.
  • the NMOS transistor and the PMOS transistor are complementary. Therefore, the circuit formed by the CMOS is called a complementary MOS, that is, CMOS.
  • CMOS complementary MOS
  • the PMOS and NMOS transient states include: PMOS only, NMOS only, or both, CMOS is more efficient than triode, power consumption Lower.
  • CMOS image sensor In a CMOS image sensor, a CMOS device is used to generate and output an output signal corresponding to incident light according to an electrical signal generated by the photoelectric conversion device.
  • the threshold voltage of a transistor for generating an output signal has a voltage drift due to a process or the like, and therefore, different output signals may be generated corresponding to the same incident light, different CMOS devices, or the same CMOS device at different times.
  • the image obtained by the CMOS image sensor is distorted.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an image sensor, and an image acquiring device.
  • an embodiment of the present disclosure provides a pixel circuit including: an initialization module, a photoelectric conversion module, a photoelectric conversion control module, an output signal generation module, a compensation module, a storage module, and an output control module.
  • the initialization module is configured to initialize the voltage stored by the storage module.
  • the photoelectric conversion module is configured to convert incident light into an electrical signal.
  • the photoelectric conversion control module is coupled to the photoelectric conversion module and configured to control the photoelectric conversion module to convert the incident light to the electrical signal and store the same to the storage module.
  • the output signal generating module is coupled to the photoelectric conversion control module and configured to generate an output signal of the pixel circuit corresponding to the incident light according to the electrical signal converted by the photoelectric conversion module.
  • the compensation module is coupled to the output signal generation module and configured to acquire a threshold voltage of the output signal generation module and store the same to the storage module.
  • the storage module is coupled to the photoelectric conversion control module and the output signal generating module, and configured to store the electrical signal converted by the photoelectric conversion module and the threshold voltage of the output signal generating module.
  • the output control module is coupled to the output signal generation module and configured to control an output of the pixel circuit corresponding to the output signal of the incident light.
  • the output signal generating module includes a control end, a first end, and a second end.
  • the compensation module includes a control end, a first end, and a second end.
  • the control end of the compensation module is connected to the second scan signal end, the first end is connected to the control end of the output signal generating module, and the second end is connected to the second end of the output signal generating module.
  • the output signal generating module includes a third transistor.
  • the control terminal of the third transistor is a control terminal of the output signal generating module
  • the first terminal of the third transistor is a first end of the output signal generating module
  • the second end of the third transistor is a second end of the output signal generating module.
  • the compensation module includes a second transistor.
  • the control end of the second transistor is the control end of the compensation module
  • the first end of the second transistor is the first end of the compensation module
  • the second end of the second transistor is the second end of the compensation module.
  • the storage module includes: a first storage module, and a second storage module.
  • the first memory module is configured to store a threshold voltage of the output signal generation module.
  • the second memory module is configured to store an electrical signal stored by the photoelectric conversion module.
  • the initialization module includes: a first initialization module, and a second initialization module.
  • the first initialization module is configured to initialize the first storage module.
  • the second initialization module is configured to initialize the second storage module.
  • the first initialization module includes a control end, a first end, and a second end.
  • the second initialization module includes a control end, a first end, and a second end.
  • the photoelectric conversion module includes a first end and a second end.
  • the photoelectric conversion control module includes a control end, a first end, and a second end.
  • the first storage module includes a first end and a second end.
  • the second storage module includes a first end and a second end.
  • the output control module includes a control end, a first end, and a second end. The control end of the first initialization module is connected to the first scan signal end, the first end is connected to the first voltage end, and the second end is connected to the second end of the first storage module.
  • the control end of the second initialization module is connected to the third scan signal end, the first end is connected to the second voltage end, and the second end is connected to the second end of the second storage module.
  • the first end of the photoelectric conversion module is connected to the third voltage end, and the second end is connected to the first end of the photoelectric conversion control module.
  • the control end of the photoelectric conversion control module is connected to the first scan signal end, and the second end is connected to the second end of the second storage module.
  • the control end of the output signal generating module is connected to the second end of the first storage module, the first end is connected to the second end of the second storage module, and the second end is connected to the first end of the output control module.
  • the first end of the first memory module is connected to the second voltage terminal.
  • the first end of the second storage module is connected to the third voltage end.
  • the control end of the output control module is connected to the fourth scan signal end, and the second end is connected to the signal output end.
  • the first initialization module includes a first transistor.
  • the control end of the first transistor is the control end of the first initialization module
  • the first end of the first transistor is the first end of the first initialization module
  • the second end of the first transistor is the second end of the first initialization module.
  • the second initialization module includes a fourth transistor.
  • the control end of the fourth transistor is the control end of the second initialization module
  • the first end of the fourth transistor is the first end of the second initialization module
  • the second end of the fourth transistor is the second end of the second initialization module.
  • the photoelectric conversion module includes a photoelectric conversion device.
  • the first end of the photoelectric conversion device is a first end of the photoelectric conversion module, and the second end of the photoelectric conversion device is a second end of the photoelectric conversion module.
  • the photoelectric conversion device is a photodiode.
  • the photoelectric conversion control module includes a fifth transistor.
  • the control end of the fifth transistor is the control end of the photoelectric conversion control module
  • the first end of the fifth transistor is the first end of the photoelectric conversion control module
  • the second end of the fifth transistor is the second end of the photoelectric conversion control module.
  • the first memory module includes a first capacitor.
  • the first end of the first capacitor is a first end of the first memory module, and the second end of the first capacitor is a second end of the first memory module.
  • the second storage module includes a second capacitor.
  • the first end of the second capacitor is the first end of the second memory module, and the second end of the second capacitor is the second end of the second memory module.
  • the output control module includes a sixth transistor.
  • the control end of the sixth transistor is the control end of the output control module, the first end of the sixth transistor is the first end of the output control module, and the second end of the sixth transistor is the second end of the output control module.
  • an embodiment of the present disclosure provides a driving method of a pixel circuit for driving the pixel circuit described above, including: an initialization phase, an initialization of a voltage stored by the memory module by the initialization module; and a photoelectric conversion phase, Under the control of the photoelectric conversion control module, the incident light is converted into an electrical signal by the photoelectric conversion module and stored in the storage module; in the compensation phase, the threshold voltage of the output signal generating module is obtained by the compensation module and stored in the storage module; Under the control of the output control module, the output signal generating module generates an output signal corresponding to the incident light of the pixel circuit based on the electrical signal stored by the storage module, and the output signal is output by the pixel circuit.
  • the storage module includes: a first storage module, and a second storage module.
  • the first memory module is configured to store a threshold voltage of the output signal generation module.
  • the second memory module is configured to store an electrical signal stored by the photoelectric conversion module.
  • the initialization module includes: a first initialization module, and a second initialization module.
  • the first initialization module is configured to initialize the first storage module.
  • the second initialization module is configured to initialize the second storage module.
  • the first initialization module includes a control end, a first end, and a second end.
  • the second initialization module includes a control end, a first end, and a second end.
  • the photoelectric conversion module includes a first end and a second end.
  • the photoelectric conversion control module includes a control end, a first end, and a second end.
  • the output signal generating module includes a control end, a first end, and a second end.
  • the compensation module includes a control end, a first end, and a second end.
  • the first storage module includes a first end and a second end.
  • the second storage module includes a first end and a second end.
  • the output control module includes a control end, a first end, and a second end. The control end of the first initialization module is connected to the first scan signal end, the first end is connected to the first voltage end, and the second end is connected to the second end of the first storage module.
  • the control end of the second initialization module is connected to the third scan signal end, and the first end is connected to the second voltage end, The two ends are connected to the second end of the second storage module.
  • the first end of the photoelectric conversion module is connected to the third voltage end, and the second end is connected to the first end of the photoelectric conversion control module.
  • the control end of the photoelectric conversion control module is connected to the first scan signal end, and the second end is connected to the second end of the second storage module.
  • the control end of the output signal generating module is connected to the second end of the first storage module, the first end is connected to the second end of the second storage module, and the second end is connected to the first end of the output control module.
  • the control end of the compensation module is connected to the second scan signal end, the first end is connected to the control end of the output signal generating module, and the second end is connected to the second end of the output signal generating module.
  • the first end of the first memory module is connected to the second voltage terminal.
  • the first end of the second storage module is connected to the third voltage end.
  • the control end of the output control module is connected to the fourth scan signal end, and the second end is connected to the signal output end.
  • the voltage at the first voltage terminal is a low level
  • the voltage at the second voltage terminal is a high level
  • the voltage at the third voltage terminal is a low level.
  • the voltage of the first scan signal terminal is an active level
  • the voltage of the second scan signal terminal is an inactive level
  • the voltage of the third scan signal terminal is an active level
  • the voltage of the fourth scan signal terminal is an inactive level.
  • the voltage of the first scanning signal terminal is an active level
  • the voltage of the second scanning signal terminal is an inactive level
  • the voltage of the third scanning signal terminal is an inactive level
  • the voltage of the fourth scanning signal terminal is an inactive level.
  • the voltage of the first scanning signal terminal is an inactive level
  • the voltage of the second scanning signal terminal is an active level
  • the voltage of the third scanning signal terminal is an inactive level
  • the voltage of the fourth scanning signal terminal is an inactive level.
  • the voltage of the first scanning signal terminal is an inactive level
  • the voltage of the second scanning signal terminal is an inactive level
  • the voltage of the third scanning signal terminal is an active level
  • the voltage of the fourth scanning signal terminal is an active level.
  • the voltage of the second end of the second memory module is Vdata, which is an electrical signal converted by the photoelectric conversion module.
  • Vdata-Vth which is a threshold voltage that causes the output signal generation module to generate an output signal.
  • Vvdd is the voltage at the second voltage terminal.
  • an embodiment of the present disclosure provides an image sensor including the pixel circuit described above.
  • an embodiment of the present disclosure provides an image acquisition apparatus including the image sensor described above.
  • the compensation module may compensate for voltage drift of the threshold voltage of the output signal generating module such that different pixel circuits correspond to the same incident light , or the same pixel circuit at different times, can produce the same output signal.
  • the pixel circuit and the driving method thereof, the image sensor, and the image acquiring device of the embodiments of the present disclosure can alleviate or eliminate distortion of the acquired image.
  • 1 is a pixel circuit diagram as an example
  • FIG. 2 is a block diagram of a pixel circuit in accordance with a first embodiment of the present disclosure
  • FIG. 3 is a schematic circuit diagram of the pixel circuit shown in FIG. 2;
  • FIG. 4 is a flow chart showing a driving method of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a signal timing diagram corresponding to the driving method shown in FIG. 4;
  • FIG. 6 is a schematic diagram showing a state of the pixel circuit shown in FIG. 3 in an initialization phase
  • FIG. 7 is a schematic view showing a state of the pixel circuit shown in FIG. 3 in a photoelectric conversion phase
  • FIG. 8 is a schematic diagram showing a state of the pixel circuit shown in FIG. 3 in a compensation phase
  • FIG. 9 is a view showing a state of the pixel circuit shown in FIG. 3 in an output stage.
  • FIG. 1 is a pixel circuit diagram as an example.
  • the pixel circuit is referred to as an active pixel structure or an Active Pixel Sensor (APS).
  • the pixel circuit includes three transistors and one photodiode PD, and is therefore also referred to as 3T APS.
  • the three transistors include a source follower Tsf, a selection switching transistor Tsel, and a reset switching transistor Trst.
  • the reset switching transistor Trst is turned on by a reset signal to reverse bias the photodiode PD using the reset voltage Vrst, and the reset voltage Vrst charges the PN junction capacitance of the photodiode PD.
  • the photoelectric conversion stage when incident light is irradiated on the PN junction of the photodiode PD, electron-hole pairs are generated on the PN junction, the charges on the PN junction capacitance are recombined, and the voltage stored in the PN junction capacitance changes.
  • the selection switching transistor Tsel is turned on, the voltage stored in the PN junction capacitance causes the gate potential of the source follower Tsf to decrease, and the source follower Tsf produces an output signal.
  • This output signal is ultimately output to the column output bus and is read by the read circuit. Based on the output signal, the image sensor acquires the final image.
  • the pixel circuit 10 includes an initialization module 1, a photoelectric conversion module 2, a photoelectric conversion control module 3, an output signal generation module 4, a compensation module 5, a storage module 6, and an output control module 7.
  • the initialization module 1 is configured to initialize the voltage stored by the memory module 6 in the pixel circuit 10.
  • the photoelectric conversion module 2 is configured to convert incident light into an electrical signal.
  • the photoelectric conversion control module 3 is connected to the photoelectric conversion module 2, and is configured to control the photoelectric conversion module 2 to convert incident light into an electrical signal and store it in the storage module 6.
  • the output signal generating module 4 is connected to the photoelectric conversion control module 3, and is configured to generate an output signal of the pixel circuit 10 corresponding to the incident light according to the electrical signal converted by the photoelectric conversion module 2.
  • the compensation module 5 is connected to the output signal generating module 4 and configured to acquire the threshold voltage of the output signal generating module 4 and store it in the storage module 6.
  • the memory module 6 is connected to the photoelectric conversion control module 3 and the output signal generating module 4, and is configured to store the electrical signal converted by the photoelectric conversion module 2 and the threshold voltage of the output signal generating module 4.
  • the output control module 7 is coupled to the output signal generation module 4 and is configured to control the output of the output signal of the pixel circuit corresponding to the incident light.
  • the compensation module may compensate for the voltage drift of the threshold voltage of the output signal generating module such that the same pixel circuit corresponding to the same incident light, different pixel circuits, or different periods may be generated The same output signal.
  • the pixel circuit of an embodiment of the present disclosure can alleviate or eliminate distortion of an acquired image.
  • the storage module 6 includes: a first storage module, and a second storage module.
  • the first memory module is configured to store a threshold voltage of the output signal generation module 4.
  • the second memory module is configured to store an electrical signal stored by the photoelectric conversion module 2.
  • the initialization module 1 includes a first initialization module and a second initialization module.
  • the first initialization module is configured to initialize the first storage module.
  • the second initialization module is configured to initialize the second storage module.
  • FIG. 3 is a schematic circuit diagram of the pixel circuit shown in FIG. 2.
  • the first initialization module includes a control end, a first end, and a second end.
  • the first initialization module includes a first transistor M1.
  • the control end of the first transistor M1 is the control end of the first initialization module
  • the first end of the first transistor M1 is the first end of the first initialization module
  • the second end of the first transistor M1 is the second end of the first initialization module end.
  • the second initialization module includes a control end, a first end, and a second end.
  • the second initialization module includes a fourth transistor M4.
  • the control end of the fourth transistor M4 is the control end of the second initialization module
  • the first end of the fourth transistor M4 is the first end of the second initialization module
  • the second end of the fourth transistor M4 is the second end of the second initialization module end.
  • the photoelectric conversion module 2 includes a first end and a second end.
  • the photoelectric conversion module 2 includes a photoelectric conversion device.
  • the first end of the photoelectric conversion device is the first end of the photoelectric conversion module 2, and the second end of the photoelectric conversion device is the second end of the photoelectric conversion module 2.
  • the photoelectric conversion device may be a photodiode PD.
  • the photoelectric conversion control module 3 includes a control end, a first end, and a second end.
  • the photoelectric conversion control module 3 includes a fifth transistor M5.
  • the control terminal of the fifth transistor M5 is the control terminal of the photoelectric conversion control module 3
  • the first terminal of the fifth transistor M5 is the first end of the photoelectric conversion control module 3
  • the second terminal of the fifth transistor M5 is the photoelectric conversion control module 3. The second end.
  • the output signal generating module 4 includes a control end, a first end, and a second end.
  • the output signal generating module 4 includes a third transistor M3.
  • the control terminal of the third transistor M3 is the control terminal of the output signal generating module 4, and the first terminal of the third transistor M3 is the first terminal of the output signal generating module 4,
  • the second end of the three transistor M3 is the second end of the output signal generating module 4.
  • the compensation module 5 includes a control end, a first end, and a second end.
  • the compensation module 5 includes a second transistor M2.
  • the control terminal of the second transistor M2 is the control terminal of the compensation module 5
  • the first terminal of the second transistor M2 is the first end of the compensation module 5
  • the second terminal of the second transistor M2 is the second terminal of the compensation module 5.
  • the first storage module includes a first end and a second end.
  • the first storage module includes a first capacitor C1.
  • the first end of the first capacitor C1 is the first end of the first storage module, and the second end of the first capacitor C1 is the second end of the first storage module.
  • the second storage module includes a first end and a second end.
  • the second storage module includes a second capacitor C2.
  • the first end of the second capacitor C2 is the first end of the second storage module, and the second end of the second capacitor C2 is the second end of the second storage module.
  • the output control module 7 includes a control end, a first end, and a second end.
  • the output control module 7 includes a sixth transistor M6.
  • the control terminal of the sixth transistor M6 is the control terminal of the output control module 7, the first terminal of the sixth transistor M6 is the first end of the output control module 7, and the second terminal of the sixth transistor M6 is the second of the output control module 7. end.
  • the control end of the first initialization module is connected to the first scan signal terminal S1, the first end is connected to the first voltage terminal Vint, and the second end is connected to the second end of the first storage module.
  • the control end of the second initialization module is connected to the third scan signal terminal RS.
  • the first end is connected to the second voltage terminal Vdd, and the second end is connected to the second end of the second storage module.
  • the first end of the photoelectric conversion module 2 is connected to the third voltage terminal GND, and the second end is connected to the first end of the photoelectric conversion control module 3.
  • the control end of the photoelectric conversion control module 3 is connected to the first scan signal terminal S1, and the second end is connected to the second end of the second storage module.
  • the control end of the output signal generating module 4 is connected to the second end of the first storage module, the first end is connected to the second end of the second storage module, and the second end is connected to the first end of the output control module 3.
  • the control end of the compensation module 5 is connected to the second scan signal terminal S2.
  • the first end is connected to the control end of the output signal generating module 4, and the second end is connected to the second end of the output signal generating module 4.
  • the first end of the first memory module is coupled to the second voltage terminal Vdd.
  • the first end of the second storage module is connected to the third voltage terminal GND.
  • the control terminal of the output control module 7 is connected to the fourth scan signal terminal EM, and the second terminal is connected to the signal output terminal OP.
  • the second transistor of the compensation module may compensate for voltage drift of the threshold voltage of the third transistor of the output signal generating module such that it corresponds to the same incident light, different pixel circuits, or different The same pixel circuit of the period can produce the same output signal.
  • the pixel circuit of an embodiment of the present disclosure can alleviate or eliminate distortion of an acquired image.
  • the driving method includes: an initialization phase, which is initialized by the initialization module for the pixel circuit.
  • the photoelectric conversion stage under the control of the photoelectric conversion control module, the incident light is converted into an electrical signal by the photoelectric conversion module and stored in the storage module.
  • the compensation phase the threshold voltage of the output signal generating module is obtained by the compensation module and stored in the storage module.
  • the output signal generating module under the control of the output control module, the output signal generating module generates an output signal corresponding to the incident light of the pixel circuit based on the electrical signal stored by the storage module, and the output signal is output by the pixel circuit.
  • the voltage drift of the threshold voltage of the output signal generating module may be compensated so that the same pixel circuit corresponding to the same incident light, different pixel circuits, or different periods may be used. Produces the same output signal.
  • the driving method of the pixel circuit of the embodiment of the present disclosure can reduce or eliminate distortion of the acquired image.
  • Fig. 5 is a timing chart of signals corresponding to the driving method shown in Fig. 4.
  • the voltage of the first scan signal terminal S1 is an active level
  • the voltage of the second scan signal terminal S2 is an inactive level
  • the third scan signal terminal RS The voltage of the fourth scanning signal terminal EM is an inactive level.
  • the voltage of the first scanning signal terminal S1 is an active level
  • the voltage of the second scanning signal terminal S2 is an inactive level
  • the voltage of the third scanning signal terminal RS is an inactive level
  • the fourth scanning signal terminal EM The voltage is an inactive level.
  • the voltage of the first scanning signal terminal S1 is an inactive level
  • the voltage of the second scanning signal terminal S2 is an active level
  • the voltage of the third scanning signal terminal RS is an inactive level
  • the fourth scanning signal terminal EM The voltage is an inactive level.
  • the voltage of the first scanning signal terminal S1 is an inactive level
  • the voltage of the second scanning signal terminal S2 is an inactive level
  • the voltage of the third scanning signal terminal RS is an active level
  • the fourth scanning signal terminal EM The voltage is an active level.
  • a voltage is an active level means that when the voltage is applied to a corresponding module, the module can function (e.g., the switching transistor in the module is turned on).
  • the voltage is inactive it means that the module can not function when the voltage is applied to the corresponding module (for example, the switching transistor in the module is turned off).
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are switching transistors
  • the third transistor M3 is a driving transistor and operates as a source follower.
  • the effective level is a low level and the inactive level is a high level.
  • the high level and the low level are only used to distinguish whether the voltage can make the transistor turn on, and the value of the voltage is not limited.
  • a low level may refer to a ground level or a negative level.
  • the selection of a P-type TFT transistor is schematically illustrated, and is not a specific limitation on the type of transistor. Those skilled in the art can make appropriate selections and adjustments to the types of transistors without departing from the spirit of the present disclosure, and such selections and adjustments are also considered to fall within the scope of the present disclosure.
  • FIG. 6 is a schematic view showing a state of the pixel circuit shown in FIG. 3 in an initialization phase.
  • FIG. 7 is a schematic view showing a state of the pixel circuit shown in FIG. 3 in a photoelectric conversion stage.
  • FIG. 8 is a schematic diagram showing a state of the pixel circuit shown in FIG. 3 in a compensation phase.
  • FIG. 9 is a view showing a state of the pixel circuit shown in FIG. 3 in an output stage.
  • "X" indicates that the transistor is turned off, and the arrow indicates the direction of the current.
  • the voltage of the first voltage terminal Vint is a low level
  • the voltage of the second voltage terminal Vdd is a high level
  • the voltage of the third voltage terminal GND is a low level.
  • the voltage of the first voltage terminal Vint may be equal to the voltage of the third voltage terminal GND.
  • the first voltage terminal Vint can be connected to the third voltage terminal GND, which can further reduce the number of ports required.
  • the first transistor M1, the fourth transistor M4, and the fifth transistor M5 are turned on, and the second transistor M2, the third transistor M3, and the sixth transistor M6 are turned off.
  • the first node N1 of the second end of the first capacitor C1 connected to the control terminal of the third transistor M3 is connected to the first voltage terminal Vint.
  • the voltage of the first node N1 is initialized to a low level, for example, may be 0V.
  • a second node of the second capacitor C2 connected to the first end of the third transistor M3 N2 is connected to the second voltage terminal Vdd.
  • the voltage of the second node N2 initializes a high level, that is, a voltage Vvdd of the second voltage terminal Vdd.
  • the fifth transistor M5 is turned on, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
  • the photoelectric conversion device for example, the photodiode PD receives the irradiation of the incident light, is excited by the photon, generates an electron-hole pair at the PN junction of the photodiode PD, recombines the charge on the PN junction capacitance, and the voltage of the second node N2 is reduced to Vdata.
  • Vdata is an electrical signal converted by a photodiode PD.
  • the second capacitor C2 stores the voltage Vdata.
  • the second transistor M2 and the third transistor M3 are turned on, and the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off. Since the voltage of the first node N1 is 0V, the third transistor M3 is turned on, and the voltage Vdata sequentially starts to the first node N1 through the fifth transistor M5, the third transistor M3, and the second transistor M2 (ie, the first capacitor C1). Charging, the voltage of the first node N1 is charged until Vdata - Vth, that is, the voltage difference between the first pole and the control pole of the third transistor M3 is Vth, and Vth is such that the third transistor M3 generates an output signal. Threshold voltage. When charging is completed, the voltage of the first node N1 (ie, the voltage of the second terminal of the first capacitor C1) is maintained at Vdata - Vth.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, and the first transistor M1, the second transistor M2, and the fifth transistor M5 are turned off.
  • the first terminal of the third transistor M3 is connected to the second voltage terminal Vdd, and the voltage of the first terminal of the third transistor M3 is Vvdd.
  • the current I is output to the signal reading line RL via the signal output terminal OP.
  • Vvdd is a constant value
  • Vdata is generated by the photodiode PD, which is related to incident light.
  • the driving method of the pixel circuit of the embodiment of the present disclosure the voltage drift of the threshold voltage of the third transistor of the output signal generating module is compensated so as to correspond to the same incident light, Different pixel circuits, or the same pixel circuit at different times, can produce the same output signal.
  • the driving method of the pixel circuit of the embodiment of the present disclosure can reduce or eliminate distortion of the acquired image.
  • Embodiments of the present disclosure also provide an image sensor including the pixel circuit described above.
  • Embodiments of the present disclosure also provide an image acquisition apparatus including the image sensor described above.
  • the image acquisition device may be any product or component having an image acquisition function such as a camera, a camera, a video camera, a mobile phone, a tablet computer, or the like.
  • the compensation module may compensate for the voltage drift of the output signal generation module such that the same pixel circuit corresponding to the same incident light, different pixel circuits, or different periods may be used. Produces the same output signal.
  • the pixel circuit and the driving method thereof, the image sensor, and the image acquiring device of the embodiments of the present disclosure can alleviate or eliminate distortion of the acquired image.

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Abstract

一种像素电路（10）及其驱动方法、图像传感器及图像获取装置。像素电路（10）包括：初始化模块（1），初始化存储模块（6）；光电转换模块（2），将入射光转换为电信号；光电转换控制模块（3），控制光电转换模块（2）将入射光转换为电信号；输出信号产生模块（4），根据光电转换模块（2）转换的电信号产生像素电路（10）的对应于入射光的输出信号；补偿模块（5），获取输出信号产生模块（4）的阈值电压；存储模块（6），存贮光电转换模块（2）转换的电信号和输出信号产生模块（4）的阈值电压；输出控制模块（7），控制像素电路（10）的对应于入射光的输出信号的输出；补偿模块（5）可以对于输出信号产生模块（4）的阈值电压的电压漂移进行补偿，使得对应于相同的入射光，产生相同的输出信号，减轻或者消除获取的图像的失真。

Description

像素电路及其驱动方法、图像传感器及图像获取装置
相关申请的交叉引用
本申请要求2016年6月29日递交的中国专利申请第201610505408.3号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及图像传感技术领域，尤其涉及像素电路及其驱动方法、图像传感器及图像获取装置。
背景技术
在图像传感技术领域，互补性金属氧化物半导体(Complementary Metal-Oxide Semiconductor，CMOS)技术得到广泛应用。CMOS是由PMOS和NMOS管共同构成的电路，NMOS管和PMOS管是互补的，因此其构成的电路被称为互补型MOS，即CMOS。以一对的PMOS管和NMOS管组成的非门电路为例，PMOS管和NMOS管瞬间状态包括：仅PMOS导通，仅NMOS导通，或者都截止，CMOS比三极管电路效率更高，功耗更低。
在CMOS图像传感器中，CMOS器件用于根据光电转换器件产生的电信号，产生并且输出对应于入射光的输出信号。由于工艺等原因，用于产生输出信号的晶体管的阈值电压具有电压漂移，因此，对应于相同的入射光，不同的CMOS器件，或者不同时期的同一CMOS器件，可能产生不同的输出信号，这会使得CMOS图像传感器得到的图像失真。
发明内容
本公开的实施例提供了像素电路及其驱动方法、图像传感器及图像获取装置。
根据第一个方面，本公开的实施例提供了一种像素电路，包括：初始化模块，光电转换模块，光电转换控制模块，输出信号产生模块，补偿模块，存储模块，以及输出控制模块。初始化模块被配置为初始化存储模块存储的电压。光电转换模块被配置为将入射光转换为电信号。光电转换控制模块与光电转换模块连接，被配置为控制光电转换模块将转换从入射光到电信号，并存储到存储模块。输出信号产生模块与光电转换控制模块连接，被配置为根据光电转换模块转换的电信号产生像素电路的对应于入射光的输出信号。补偿模块与输出信号产生模块连接，被配置为获取输出信号产生模块的阈值电压，并存储到存储模块。存储模块与光电转换控制模块以及输出信号产生模块连接，被配置为存贮光电转换模块转换的电信号和输出信号产生模块的阈值电压。输出控制模块与输出信号产生模块连接，被配置为控制像素电路的对应于入射光的输出信号的输出。
在本公开的实施例中，输出信号产生模块包括控制端、第一端和第二端。补偿模块包括控制端、第一端和第二端。补偿模块的控制端与第二扫描信号端连接，第一端与输出信号产生模块的控制端连接，第二端与输出信号产生模块的第二端连接。
在本公开的实施例中，输出信号产生模块包括第三晶体管。第三晶体管的控制端是输出信号产生模块的控制端，第三晶体管的第一端是输出信号产生模块的第一端，第三晶体管的第二端是输出信号产生模块的第二端。
在本公开的实施例中，补偿模块包括第二晶体管。第二晶体管的控制端是补偿模块的控制端，第二晶体管的第一端是补偿模块的第一端，第二晶体管的第二端是补偿模块的第二端。
在本公开的实施例中，存储模块包括：第一存储模块，以及第二存储模块。第一存储模块被配置为存储输出信号产生模块的阈值电压。第二存储模块被配置为存储存贮光电转换模块转换的电信号。初始化模块包括：第一初始化模块，以及第二初始化模块。第一初始化模块被配置为初始化第一存储模块。第二初始化模块被配置为初始化第二存储模块。
在本公开的实施例中，第一初始化模块包括控制端、第一端和第二端。 第二初始化模块包括控制端、第一端和第二端。光电转换模块包括第一端和第二端。光电转换控制模块包括控制端、第一端和第二端。第一存储模块包括第一端和第二端。第二存储模块包括第一端和第二端。输出控制模块包括控制端、第一端和第二端。第一初始化模块的控制端与第一扫描信号端连接，第一端与第一电压端连接，第二端与第一存储模块的第二端连接。第二初始化模块的控制端与第三扫描信号端连接，第一端与第二电压端连接，第二端与第二存储模块的第二端连接。光电转换模块的第一端与第三电压端连接，第二端与光电转换控制模块的第一端连接。光电转换控制模块的控制端与第一扫描信号端连接，第二端与第二存储模块的第二端连接。输出信号产生模块的控制端与第一存储模块的第二端连接，第一端与第二存储模块的第二端连接，第二端与输出控制模块的第一端连接。第一存储模块的第一端与第二电压端连接。第二存储模块的第一端与第三电压端连接。输出控制模块的控制端与第四扫描信号端连接，第二端与信号输出端连接。
在本公开的实施例中，第一初始化模块包括第一晶体管。第一晶体管的控制端是第一初始化模块的控制端，第一晶体管的第一端是第一初始化模块的第一端，第一晶体管的第二端是第一初始化模块的第二端。
在本公开的实施例中，第二初始化模块包括第四晶体管。第四晶体管的控制端是第二初始化模块的控制端，第四晶体管的第一端是第二初始化模块的第一端，第四晶体管的第二端是第二初始化模块的第二端。
在本公开的实施例中，光电转换模块包括光电转换器件。光电转换器件的第一端是光电转换模块的第一端，光电转换器件的第二端是光电转换模块的第二端。
在本公开的实施例中，光电转换器件是光电二极管。
在本公开的实施例中，光电转换控制模块包括第五晶体管。第五晶体管的控制端是光电转换控制模块的控制端，第五晶体管的第一端是光电转换控制模块的第一端，第五晶体管的第二端是光电转换控制模块的第二端。
在本公开的实施例中，第一存储模块包括第一电容。第一电容的第一端是第一存储模块的第一端，第一电容的第二端是第一存储模块的第二端。
在本公开的实施例中，第二存储模块包括第二电容。第二电容的第一端是第二存储模块的第一端，第二电容的第二端是第二存储模块的第二端。
在本公开的实施例中，输出控制模块包括第六晶体管。第六晶体管的控制端是输出控制模块的控制端，第六晶体管的第一端是输出控制模块的第一端，第六晶体管的第二端是输出控制模块的第二端。
根据第二个方面，本公开的实施例提供了一种像素电路的驱动方法，用于驱动上述的像素电路，包括：初始化阶段，由初始化模块对于存储模块存储的电压进行初始化；光电转换阶段，在光电转换控制模块的控制下，由光电转换模块将入射光转换为电信号，并存储于存储模块；补偿阶段，由补偿模块获取输出信号产生模块的阈值电压，并存储于存储模块；输出阶段，在输出控制模块的控制下，由输出信号产生模块基于存储模块存储的电信号，产生像素电路的对应于入射光的输出信号，并且，由像素电路输出该输出信号。
在本公开的实施例中，存储模块包括：第一存储模块，以及第二存储模块。第一存储模块被配置为存储输出信号产生模块的阈值电压。第二存储模块被配置为存储存贮光电转换模块转换的电信号。初始化模块包括：第一初始化模块，以及第二初始化模块。第一初始化模块被配置为初始化第一存储模块。第二初始化模块被配置为初始化第二存储模块。并且，第一初始化模块包括控制端、第一端和第二端。第二初始化模块包括控制端、第一端和第二端。光电转换模块包括第一端和第二端。光电转换控制模块包括控制端、第一端和第二端。输出信号产生模块包括控制端、第一端和第二端。补偿模块包括控制端、第一端和第二端。第一存储模块包括第一端和第二端。第二存储模块包括第一端和第二端。输出控制模块包括控制端、第一端和第二端。第一初始化模块的控制端与第一扫描信号端连接，第一端与第一电压端连接，第二端与第一存储模块的第二端连接。第二初始化模块的控制端与第三扫描信号端连接，第一端与第二电压端连接，第 二端与第二存储模块的第二端连接。光电转换模块的第一端与第三电压端连接，第二端与光电转换控制模块的第一端连接。光电转换控制模块的控制端与第一扫描信号端连接，第二端与第二存储模块的第二端连接。输出信号产生模块的控制端与第一存储模块的第二端连接，第一端与第二存储模块的第二端连接，第二端与输出控制模块的第一端连接。补偿模块的控制端与第二扫描信号端连接，第一端与输出信号产生模块的控制端连接，第二端与输出信号产生模块的第二端连接。第一存储模块的第一端与第二电压端连接。第二存储模块的第一端与第三电压端连接。输出控制模块的控制端与第四扫描信号端连接，第二端与信号输出端连接。其中，第一电压端的电压是低电平，第二电压端的电压是高电平，第三电压端的电压是低电平。并且，在初始化阶段，第一扫描信号端的电压是有效电平，第二扫描信号端的电压是无效电平，第三扫描信号端的电压是有效电平，第四扫描信号端的电压是无效电平。在光电转换阶段，第一扫描信号端的电压是有效电平，第二扫描信号端的电压是无效电平，第三扫描信号端的电压是无效电平，第四扫描信号端的电压是无效电平。在补偿阶段，第一扫描信号端的电压是无效电平，第二扫描信号端的电压是有效电平，第三扫描信号端的电压是无效电平，第四扫描信号端的电压是无效电平。在输出阶段，第一扫描信号端的电压是无效电平，第二扫描信号端的电压是无效电平，第三扫描信号端的电压是有效电平，第四扫描信号端的电压是有效电平。
在本公开的实施例中，在光电转换阶段，第二存储模块的第二端的电压是Vdata，Vdata是由光电转换模块转换的电信号。在补偿阶段，第一存储模块的第二端的电压是Vdata-Vth，Vth是使得输出信号产生模块产生输出信号的阈值电压。在输出阶段，输出信号产生模块产生的输出信号为I＝K[Vvdd–(Vdata–Vth)–Vth]2＝K(Vvdd–Vdata)2，K是与输出信号产生模块结构相关的常值，Vvdd是第二电压端的电压。
根据第三个方面，本公开的实施例提供了一种图像传感器，包括上述的像素电路。
根据第四个方面，本公开的实施例提供了一种图像获取装置，包括上述的图像传感器。
根据本公开的实施例的像素电路及其驱动方法、图像传感器及图像获取装置，补偿模块可以对于输出信号产生模块的阈值电压的电压漂移进行补偿，使得对应于相同的入射光，不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路及其驱动方法、图像传感器及图像获取装置可以减轻或者消除获取的图像的失真。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是作为示例的像素电路图；
图2是根据本公开的第一实施例的像素电路的框图；
图3是图2所示的像素电路的示意性的电路图；
图4是图3所示的像素电路的驱动方法的流程图；
图5是图4所示的驱动方法对应的信号时序图；
图6是图3所示的像素电路在初始化阶段的状态示意图；
图7是图3所示的像素电路在光电转换阶段的状态示意图；
图8是图3所示的像素电路在补偿阶段的状态示意图；
图9是图3所示的像素电路在输出阶段的状态示意图。
具体实施方式
为了使本公开的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开保护的范围。
图1是作为示例的像素电路图。该像素电路被称为主动式像素结构或者有源式像素结构(Active Pixel Sensor，APS)。如图1所示，该像素电路包括三个晶体管和一个光电二极管PD，因此又称为3T APS。三个晶体管包括源极跟随器Tsf、选择开关晶体管Tsel以及重置开关晶体管Trst。在初始化阶段，通过重置信号开启重置开关晶体管Trst，以使用重置电压Vrst反向偏置光电二极管PD，重置电压Vrst对光电二极管PD的PN结电容充电。在光电转换阶段，当光电二极管PD的PN结上有入射光照射时，在PN结上产生电子空穴对，PN结电容上的电荷发生复合，PN结电容存储的电压发生变化。在输出阶段，选择开关晶体管Tsel导通，PN结电容存储的电压使得源极跟随器Tsf的栅极电势降低，源极跟随器Tsf产生输出信号。该输出信号最终被输出到列输出总线并且被读取电路读取。根据该输出信号，图像传感器获取最终的图像。
但是在实际制作过程中，像素电路中源极跟随器会存在器件上的差异，因此，对应于相同的入射光，不同的源极跟随器，或者不同时期的同一源极跟随器，可能产生不同的输出信号，从而使得图像失真。
图2是根据本公开的第一实施例的像素电路的框图。像素电路10包括：初始化模块1，光电转换模块2，光电转换控制模块3，输出信号产生模块4，补偿模块5，存储模块6，以及输出控制模块7。初始化模块1被配置为初始化像素电路10中的存储模块6存储的电压。光电转换模块2被配置为将入射光转换为电信号。光电转换控制模块3与光电转换模块2连接，被配置为控制光电转换模块2将入射光转换为电信号，并存储到存储模块6。输出信号产生模块4与光电转换控制模块3连接，被配置为根据光电转换模块2转换的电信号产生像素电路10的对应于入射光的输出信号。补偿模块5与输出信号产生模块4连接，被配置为获取输出信号产生模块4的阈值电压，并存储于存储模块6。存储模块6与光电转换控制模块3以及输出信号产生模块4连接，被配置为存贮光电转换模块2转换的电信号和输出信号产生模块4的阈值电压。输出控制模块7与输出信号产生模块4连接，被配置为控制像素电路的对应于入射光的输出信号的输出。
根据本公开的实施例的像素电路，补偿模块可以对于输出信号产生模块的阈值电压的电压漂移进行补偿，使得对应于相同的入射光，不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路可以减轻或者消除获取的图像的失真。
在本公开的实施例中，存储模块6包括：第一存储模块，以及第二存储模块。第一存储模块被配置为存储输出信号产生模块4的阈值电压。第二存储模块被配置为存储存贮光电转换模块2转换的电信号。初始化模块1包括：第一初始化模块，以及第二初始化模块。第一初始化模块被配置为初始化第一存储模块。第二初始化模块被配置为初始化第二存储模块。
图3是图2所示的像素电路的示意性的电路图。
第一初始化模块包括控制端、第一端和第二端。第一初始化模块包括第一晶体管M1。第一晶体管M1的控制端是第一初始化模块的控制端，第一晶体管M1的第一端是第一初始化模块的第一端，第一晶体管M1的第二端是第一初始化模块的第二端。
第二初始化模块包括控制端、第一端和第二端。第二初始化模块包括第四晶体管M4。第四晶体管M4的控制端是第二初始化模块的控制端，第四晶体管M4的第一端是第二初始化模块的第一端，第四晶体管M4的第二端是第二初始化模块的第二端。
光电转换模块2包括第一端和第二端。光电转换模块2包括光电转换器件。光电转换器件的第一端是光电转换模块2的第一端，光电转换器件的第二端是光电转换模块2的第二端。光电转换器件可以是光电二极管PD。
光电转换控制模块3包括控制端、第一端和第二端。光电转换控制模块3包括第五晶体管M5。第五晶体管M5的控制端是光电转换控制模块3的控制端，第五晶体管M5的第一端是光电转换控制模块3的第一端，第五晶体管M5的第二端是光电转换控制模块3的第二端。
输出信号产生模块4包括控制端、第一端和第二端。输出信号产生模块4包括第三晶体管M3。第三晶体管M3的控制端是输出信号产生模块4的控制端，第三晶体管M3的第一端是输出信号产生模块4的第一端，第 三晶体管M3的第二端是输出信号产生模块4的第二端。
补偿模块5包括控制端、第一端和第二端。补偿模块5包括第二晶体管M2。第二晶体管M2的控制端是补偿模块5的控制端，第二晶体管M2的第一端是补偿模块5的第一端，第二晶体管M2的第二端是补偿模块5的第二端。
第一存储模块包括第一端和第二端。第一存储模块包括第一电容C1。第一电容C1的第一端是第一存储模块的第一端，第一电容C1的第二端是第一存储模块的第二端。
第二存储模块包括第一端和第二端。第二存储模块包括第二电容C2。第二电容C2的第一端是第二存储模块的第一端，第二电容C2的第二端是第二存储模块的第二端。
输出控制模块7包括控制端、第一端和第二端。输出控制模块7包括第六晶体管M6。第六晶体管M6的控制端是输出控制模块7的控制端，第六晶体管M6的第一端是输出控制模块7的第一端，第六晶体管M6的第二端是输出控制模块7的第二端。
第一初始化模块的控制端与第一扫描信号端S1连接，第一端与第一电压端Vint连接，第二端与第一存储模块的第二端连接。第二初始化模块的控制端与第三扫描信号端RS连接，第一端与第二电压端Vdd连接，第二端与第二存储模块的第二端连接。光电转换模块2的第一端与第三电压端GND连接，第二端与光电转换控制模块3的第一端连接。光电转换控制模块3的控制端与第一扫描信号端S1连接，第二端与第二存储模块的第二端连接。输出信号产生模块4的控制端与第一存储模块的第二端连接，第一端与第二存储模块的第二端连接，第二端与输出控制模块3的第一端连接。补偿模块5的控制端与第二扫描信号端S2连接，第一端与输出信号产生模块4的控制端连接，第二端与输出信号产生模块4的第二端连接。第一存储模块的第一端与第二电压端Vdd连接。第二存储模块的第一端与第三电压端GND连接。输出控制模块7的控制端与第四扫描信号端EM连接，第二端与信号输出端OP连接。
根据本公开的实施例的像素电路，补偿模块的第二晶体管可以对于输出信号产生模块的第三晶体管的阈值电压的电压漂移进行补偿，使得对应于相同的入射光，不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路可以减轻或者消除获取的图像的失真。
图4是图3所示的像素电路的驱动方法的流程图。如图4所示，驱动方法包括：初始化阶段，由初始化模块对于像素电路进行初始化。光电转换阶段，在光电转换控制模块的控制下，由光电转换模块将入射光转换为电信号，并存储于存储模块。补偿阶段，由补偿模块获取输出信号产生模块的阈值电压，并存储于存储模块。输出阶段，在输出控制模块的控制下，由输出信号产生模块基于存储模块存储的电信号，产生像素电路的对应于入射光的输出信号，并且，由像素电路输出该输出信号。
根据本公开的实施例的像素电路的驱动方法，可以对于输出信号产生模块的阈值电压的电压漂移进行补偿，使得对应于相同的入射光，不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路的驱动方法可以减轻或者消除获取的图像的失真。
图5是图4所示的驱动方法对应的信号时序图。如图5所示，在本公开的实施例中，在初始化阶段，第一扫描信号端S1的电压是有效电平，第二扫描信号端S2的电压是无效电平，第三扫描信号端RS的电压是有效电平，第四扫描信号端EM的电压是无效电平。在光电转换阶段，第一扫描信号端S1的电压是有效电平，第二扫描信号端S2的电压是无效电平，第三扫描信号端RS的电压是无效电平，第四扫描信号端EM的电压是无效电平。在补偿阶段，第一扫描信号端S1的电压是无效电平，第二扫描信号端S2的电压是有效电平，第三扫描信号端RS的电压是无效电平，第四扫描信号端EM的电压是无效电平。在输出阶段，第一扫描信号端S1的电压是无效电平，第二扫描信号端S2的电压是无效电平，第三扫描信号端RS的电压是有效电平，第四扫描信号端EM的电压是有效电平。
按照本技术领域内的通常理解，电压是有效电平指该电压被施加到对应的模块时，该模块可以行使功能(例如，模块中的开关晶体管导通)。电压是无效电平指该电压被施加到对应的模块时，该模块可以不行使功能(例如，模块中的开关晶体管截止)。
在本公开的实施例中，第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6是开关晶体管，第三晶体管M3是驱动晶体管，作为源极跟随器工作。
以晶体管为P型为例进行说明，相应地，有效电平是低电平，无效电平是高电平。需要说明的是，高电平、低电平仅仅用于区分电压是否能够使得晶体管导通，并没有限制电压的值。例如，低电平可以是指接地的电平，也可以是负电平。此外，选择P型TFT晶体管进行示意性的说明，并不是对于晶体管类型的具体限制。根据本公开的原理，本领域技术人员能够在不付出创造性劳动的情况下，对于晶体管的类型做出适当的选择和调整，这些选择和调整也视为落入本公开的保护范围。
图6是图3所示的像素电路在初始化阶段的状态示意图。图7是图3所示的像素电路在光电转换阶段的状态示意图。图8是图3所示的像素电路在补偿阶段的状态示意图。图9是图3所示的像素电路在输出阶段的状态示意图。图中，“X”表示晶体管截止，箭头表示电流方向。
在本公开的实施例中，第一电压端Vint的电压是低电平，第二电压端Vdd的电压是高电平，第三电压端GND的电压是低电平。并且，第一电压端Vint的电压可以等于第三电压端GND的电压。进一步的，第一电压端Vint可以和第三电压端GND连接，这样可以进一步减少所需要的端口数量。
如图6所示，在初始化阶段，第一晶体管M1、第四晶体管M4、第五晶体管M5导通，第二晶体管M2、第三晶体管M3、第六晶体管M6截止。第一电容C1的第二端与第三晶体管M3的控制端连接的第一节点N1被连接到第一电压端Vint。第一节点N1的电压初始化为低电平，例如，可以为0V。第二电容C2的第二端与第三晶体管M3的第一端连接的第二节点 N2被连接到第二电压端Vdd。第二节点N2的电压初始化高电平，即，第二电压端Vdd的电压Vvdd。
如图7所示，在光电转换阶段，第五晶体管M5导通，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第六晶体管M6截止。光电转换器件，例如光电二极管PD接收入射光的照射，受光量子激发，在光电二极管PD的PN结产生电子空穴对，使PN结电容上的电荷发生复合，第二节点N2的电压降为Vdata，Vdata是由光电二极管PD转换的电信号。第二电容C2存储电压Vdata。
如图8所示，在补偿阶段，第二晶体管M2、第三晶体管M3导通，第一晶体管M1、第四晶体管M4、第五晶体管M5、第六晶体管M6截止。由于之前第一节点N1的电压是0V，所以第三晶体管M3导通，电压Vdata依次通过第五晶体管M5、第三晶体管M3、第二晶体管M2开始对第一节点N1(即，第一电容C1)进行充电，一直将第一节点N1的电压充电到Vdata–Vth为止，即满足第三晶体管M3第一极与控制极之间的压差为Vth，Vth是使得第三晶体管M3产生输出信号的阈值电压。当充电完毕以后，第一节点N1的电压(即，第一电容C1的第二端的电压)会一直维持在Vdata–Vth。
如图9所示，在输出阶段，第三晶体管M3、第四晶体管M4、第六晶体管M6导通，第一晶体管M1、第二晶体管M2、第五晶体管M5截止。第三晶体管M3的第一端连接到第二电压端Vdd，第三晶体管M3的第一端的电压是Vvdd。第三晶体管M3的控制极的电压是Vdata–Vth。因此，第三晶体管M3产生的输出信号是电流I＝K[Vvdd–(Vdata–Vth)–Vth]2＝K(Vvdd–Vdata)2，K是与第三晶体管M3结构相关的常值。电流I经信号输出端OP输出到信号读取线RL。
电流I只与Vdd和Vdata有关，与包含电压漂移的阈值电压Vth无关。Vvdd是常值，Vdata由光电二极管PD产生，与入射光相关。
根据本公开的实施例的像素电路的驱动方法，对于输出信号产生模块的第三晶体管的阈值电压的电压漂移进行补偿，使得对应于相同的入射光， 不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路的驱动方法可以减轻或者消除获取的图像的失真。
本公开的实施例还提供一种图像传感器，包括上述的像素电路。
本公开的实施例还提供了一种图像获取装置，包括上述的图像传感器。所述图像获取装置可以为：摄像头、相机、摄像机、手机、平板电脑等任何具有图像获取功能的产品或部件。
根据本公开的实施例的图像传感器及图像获取装置，补偿模块可以对于输出信号产生模块的电压漂移进行补偿，使得对应于相同的入射光，不同的像素电路，或者不同时期的同一像素电路，可以产生相同的输出信号。本公开的实施例的像素电路及其驱动方法、图像传感器及图像获取装置可以减轻或者消除获取的图像的失真。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种像素电路，包括：
    初始化模块，被配置为初始化存储模块存储的电压；
    光电转换模块，被配置为将入射光转换为电信号；
    光电转换控制模块，其与所述光电转换模块连接，被配置为控制所述光电转换模块将入射光转换为电信号，并存储到存储模块；
    输出信号产生模块，其与所述光电转换控制模块连接，被配置为根据所述光电转换模块转换的电信号产生所述像素电路的对应于入射光的输出信号；
    补偿模块，其与所述输出信号产生模块连接，被配置为获取所述输出信号产生模块的阈值电压，并存储于存储模块；
    存储模块，其与所述光电转换控制模块以及所述输出信号产生模块连接，被配置为存贮光电转换模块转换的电信号和输出信号产生模块的阈值电压；以及
    输出控制模块，其与所述输出信号产生模块连接，被配置为控制像素电路的对应于入射光的输出信号的输出。
  2. 根据权利要求1所述的像素电路，其中，
    所述输出信号产生模块包括控制端、第一端和第二端；
    所述补偿模块包括控制端、第一端和第二端；
    所述补偿模块的控制端与第二扫描信号端连接，第一端与所述输出信号产生模块的控制端连接，第二端与所述输出信号产生模块的第二端连接。
  3. 根据权利要求2所述的像素电路，其中，
    所述输出信号产生模块包括第三晶体管；所述第三晶体管的控制端是所述输出信号产生模块的控制端，所述第三晶体管的第一端是所述输出信号产生模块的第一端，所述第三晶体管的第二端是所述输出信号产生模块的第二端。
  4. 根据权利要求2所述的像素电路，其中，
    所述补偿模块包括第二晶体管；所述第二晶体管的控制端是所述补偿 模块的控制端，所述第二晶体管的第一端是所述补偿模块的第一端，所述第二晶体管的第二端是所述补偿模块的第二端。
  5. 根据权利要求2所述的像素电路，其中，
    所述存储模块包括：
    第一存储模块，其被配置为存储输出信号产生模块的阈值电压；
    第二存储模块，其被配置为存储存贮光电转换模块转换的电信号；
    所述初始化模块包括：
    第一初始化模块，其被配置为初始化第一存储模块；
    第二初始化模块，其被配置为初始化第二存储模块。
  6. 根据权利要求5所述的像素电路，其中，
    所述第一初始化模块包括控制端、第一端和第二端；
    所述第二初始化模块包括控制端、第一端和第二端；
    所述光电转换模块包括第一端和第二端；
    所述光电转换控制模块包括控制端、第一端和第二端；
    所述第一存储模块包括第一端和第二端；
    所述第二存储模块包括第一端和第二端；
    所述输出控制模块包括控制端、第一端和第二端；
    所述第一初始化模块的控制端与第一扫描信号端连接，第一端与第一电压端连接，第二端与所述第一存储模块的第二端连接；
    所述第二初始化模块的控制端与第三扫描信号端连接，第一端与第二电压端连接，第二端与所述第二存储模块的第二端连接；
    所述光电转换模块的第一端与第三电压端连接，第二端与所述光电转换控制模块的第一端连接；
    所述光电转换控制模块的控制端与第一扫描信号端连接，第二端与所述第二存储模块的第二端连接；
    所述输出信号产生模块的控制端与第一存储模块的第二端连接，第一端与所述第二存储模块的第二端连接，第二端与所述输出控制模块的第一端连接；
    所述第一存储模块的第一端与第二电压端连接；
    所述第二存储模块的第一端与第三电压端连接；
    所述输出控制模块的控制端与第四扫描信号端连接，第二端与信号输出端连接。
  7. 根据权利要求6所述的像素电路，其中，
    所述第一初始化模块包括第一晶体管；所述第一晶体管的控制端是所述第一初始化模块的控制端，所述第一晶体管的第一端是所述第一初始化模块的第一端，所述第一晶体管的第二端是所述第一初始化模块的第二端。
  8. 根据权利要求6所述的像素电路，其中，
    所述第二初始化模块包括第四晶体管；所述第四晶体管的控制端是所述第二初始化模块的控制端，所述第四晶体管的第一端是所述第二初始化模块的第一端，所述第四晶体管的第二端是所述第二初始化模块的第二端。
  9. 根据权利要求6所述的像素电路，其中，
    所述光电转换模块包括光电转换器件；所述光电转换器件的第一端是所述光电转换模块的第一端，所述光电转换器件的第二端是所述光电转换模块的第二端。
  10. 根据权利要求9所述的像素电路，其中，
    所述光电转换器件是光电二极管。
  11. 根据权利要求6所述的像素电路，其中，
    所述光电转换控制模块包括第五晶体管；所述第五晶体管的控制端是所述光电转换控制模块的控制端，所述第五晶体管的第一端是所述光电转换控制模块的第一端，所述第五晶体管的第二端是所述光电转换控制模块的第二端。
  12. 根据权利要求6所述的像素电路，其中，
    所述第一存储模块包括第一电容；所述第一电容的第一端是所述第一存储模块的第一端，所述第一电容的第二端是所述第一存储模块的第二端。
  13. 根据权利要求6所述的像素电路，其中，
    所述第二存储模块包括第二电容；所述第二电容的第一端是所述第二 存储模块的第一端，所述第二电容的第二端是所述第二存储模块的第二端。
  14. 根据权利要求6所述的像素电路，其中，
    所述输出控制模块包括第六晶体管；所述第六晶体管的控制端是所述输出控制模块的控制端，所述第六晶体管的第一端是所述输出控制模块的第一端，所述第六晶体管的第二端是所述输出控制模块的第二端。
  15. 一种像素电路的驱动方法，用于驱动根据权利要求1所述的像素电路，包括：
    初始化阶段，由初始化模块对于存储模块存储的电压进行初始化；
    光电转换阶段，在光电转换控制模块的控制下，由光电转换模块将入射光转换为电信号，并存储于存储模块；
    补偿阶段，由补偿模块获取输出信号产生模块的阈值电压，并存储于存储模块；
    输出阶段，在输出控制模块的控制下，由输出信号产生模块基于存储模块存储的电信号，产生像素电路的对应于入射光的输出信号；并且，由像素电路输出该输出信号。
  16. 根据权利要求15所述的像素电路的驱动方法，其中，
    所述存储模块包括：
    第一存储模块，其被配置为存储输出信号产生模块的阈值电压；
    第二存储模块，其被配置为存储存贮光电转换模块转换的电信号；
    所述初始化模块包括：
    第一初始化模块，其被配置为初始化第一存储模块；
    第二初始化模块，其被配置为初始化第二存储模块；
    并且，
    所述第一初始化模块包括控制端、第一端和第二端；
    所述第二初始化模块包括控制端、第一端和第二端；
    所述光电转换模块包括第一端和第二端；
    所述光电转换控制模块包括控制端、第一端和第二端；
    所述输出信号产生模块包括控制端、第一端和第二端；
    所述补偿模块包括控制端、第一端和第二端；
    所述第一存储模块包括第一端和第二端；
    所述第二存储模块包括第一端和第二端；
    所述输出控制模块包括控制端、第一端和第二端；
    所述第一初始化模块的控制端与第一扫描信号端连接，第一端与第一电压端连接，第二端与所述第一存储模块的第二端连接；
    所述第二初始化模块的控制端与第三扫描信号端连接，第一端与第二电压端连接，第二端与所述第二存储模块的第二端连接；
    所述光电转换模块的第一端与第三电压端连接，第二端与所述光电转换控制模块的第一端连接；
    所述光电转换控制模块的控制端与第一扫描信号端连接，第二端与所述第二存储模块的第二端连接；
    所述输出信号产生模块的控制端与第一存储模块的第二端连接，第一端与所述第二存储模块的第二端连接，第二端与所述输出控制模块的第一端连接；
    所述补偿模块的控制端与第二扫描信号端连接，第一端与所述输出信号产生模块的控制端连接，第二端与所述输出信号产生模块的第二端连接；
    所述第一存储模块的第一端与第二电压端连接；
    所述第二存储模块的第一端与第三电压端连接；
    所述输出控制模块的控制端与第四扫描信号端连接，第二端与信号输出端连接；
    其中，第一电压端的电压是低电平，第二电压端的电压是高电平，第三电压端的电压是低电平；
    并且，
    在所述初始化阶段，第一扫描信号端的电压是有效电平，第二扫描信号端的电压是无效电平，第三扫描信号端的电压是有效电平，第四扫描信号端的电压是无效电平；
    在所述光电转换阶段，第一扫描信号端的电压是有效电平，第二扫描 信号端的电压是无效电平，第三扫描信号端的电压是无效电平，第四扫描信号端的电压是无效电平；
    在所述补偿阶段，第一扫描信号端的电压是无效电平，第二扫描信号端的电压是有效电平，第三扫描信号端的电压是无效电平，第四扫描信号端的电压是无效电平；
    在所述输出阶段，第一扫描信号端的电压是无效电平，第二扫描信号端的电压是无效电平，第三扫描信号端的电压是有效电平，第四扫描信号端的电压是有效电平。
  17. 根据权利要求16所述的像素电路的驱动方法，其中，
    在所述光电转换阶段，所述第二存储模块的第二端的电压是Vdata，Vdata是由光电转换模块转换的电信号；
    在所述补偿阶段，所述第一存储模块的第二端的电压是Vdata-Vth，Vth是使得所述输出信号产生模块产生输出信号的阈值电压；
    在所述输出阶段，所述输出信号产生模块产生的输出信号为I＝K[Vvdd–(Vdata–Vth)–Vth]2＝K(Vvdd–Vdata)2，K是与所述输出信号产生模块结构相关的常值，Vvdd是第二电压端的电压。
  18. 一种图像传感器，包括根据权利要求1至14中任一项所述的像素电路。
  19. 一种图像获取装置，包括根据权利要求18所述的图像传感器。
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