WO2017197969A1 - 有源像素传感器电路、驱动方法和图像传感器 - Google Patents

有源像素传感器电路、驱动方法和图像传感器 Download PDF

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Publication number
WO2017197969A1
WO2017197969A1 PCT/CN2017/077083 CN2017077083W WO2017197969A1 WO 2017197969 A1 WO2017197969 A1 WO 2017197969A1 CN 2017077083 W CN2017077083 W CN 2017077083W WO 2017197969 A1 WO2017197969 A1 WO 2017197969A1
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Prior art keywords
transistor
reset
storage capacitor
control
source follower
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PCT/CN2017/077083
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English (en)
French (fr)
Inventor
杨盛际
董学
薛海林
陈小川
王海生
刘英明
赵卫杰
丁小梁
王春雷
李伟
孙泽斌
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/574,458 priority Critical patent/US10187597B2/en
Publication of WO2017197969A1 publication Critical patent/WO2017197969A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to the field of active pixel sensing technologies, and in particular, to an active pixel sensor circuit, a driving method, and an image sensor.
  • CMOS Complementary Metal-Oxide Semiconductor
  • the Active Pixel Sensor (APS) circuit is in the process of photoelectric conversion of the photosensitive device, due to the source-following TFT (Thin Film Transistor) process.
  • the difference causes its threshold voltage to be non-uniform, and the output current of the source follower TFT is affected by its own threshold voltage, so the output current of the source follower TFT is not uniform, resulting in distortion of the final picture.
  • a primary object of the present disclosure is to provide an active pixel sensor circuit, a driving method, and an image sensor that are capable of at least partially alleviating or eliminating the above-mentioned drawbacks of the prior art.
  • an active pixel sensor circuit including a photosensitive device, a first storage capacitor, a second storage capacitor, and a source follower transistor.
  • a first pole of the photosensitive device is connected to a first level line
  • a first end of the second storage capacitor is connected to a first level line
  • a source follows a gate of the transistor and the first storage capacitor The first end is connected, and the first pole of the source follower transistor is connected to the second level line.
  • the active pixel sensor circuit further includes a reset sub-circuit, a charge control sub-circuit, a compensation control sub-circuit, and a signal read control sub-circuit.
  • the reset sub-circuit is respectively connected to the first end of the first storage capacitor and the second end of the first storage capacitor, and is configured to control the first end and the first end of the first storage capacitor in a reset phase A reset voltage line connection and controlling the second end of the first storage capacitor to be connected to the second reset voltage line.
  • a charge control sub-circuit connected to a second electrode of the photosensitive device, a second end of the second storage capacitor, a gate of the source follower transistor, and a second electrode of the source follower transistor, respectively Controlling a second electrode of the photosensitive device to be coupled to a second end of the second storage capacitor during a reset phase and a charging phase, and controlling a gate of the source follower transistor and the source follower transistor during a charging phase
  • the second pole is connected.
  • the compensation control sub-circuit is respectively connected to the second end of the second storage capacitor and the second end of the first storage capacitor for controlling the second end of the second storage capacitor in the reset phase and the compensation phase
  • the second end of the first storage capacitor is connected.
  • a signal read control sub-circuit connected to the photocurrent signal read line and the second electrode of the source follower transistor, respectively, for controlling the photocurrent signal read line and the source follower transistor during a signal read phase
  • the second pole is connected.
  • the reset sub-circuit is further coupled to the reset control signal line for controlling the first end of the first storage capacitor and the first one under control of the reset control signal during the reset phase
  • the voltage line connection is reset, and the second end of the first storage capacitor is controlled to be connected to the second reset voltage line.
  • the charging control sub-circuit is further connected to the first charging control signal line and the second charging control signal line, respectively, for controlling the photosensitive device under the control of the first charging control signal in the reset phase and the charging phase
  • the diode is connected to the second end of the second storage capacitor, and controls the gate of the source follower transistor to be connected to the second pole of the source follower transistor under the control of the second charge control signal during the charging phase .
  • the compensation control sub-circuit is further connected to the compensation control signal line for controlling the second end of the second storage capacitor and the first storage capacitor under the control of the compensation control signal in the reset phase and the compensation phase Two-terminal connection.
  • the signal read control sub-circuit is further connected to the read control signal line for controlling the photocurrent signal read line and the second pole of the source follower transistor under the control of the read control signal during the signal read phase connection.
  • the reset subcircuit includes a first reset transistor and a second reset transistor.
  • a gate of the first reset transistor is connected to the reset control signal line, a first pole of the first reset transistor is connected to the first reset voltage line, and a second pole of the first reset transistor is opposite to the first A first end of a storage capacitor is connected.
  • a gate of the second reset transistor is connected to the reset control signal line, a first pole of the second reset transistor is connected to the second reset voltage line, and a second pole of the second reset transistor is opposite to the first A second end of the storage capacitor is connected.
  • the charge control subcircuit includes a first charge control transistor and a second charge control transistor.
  • a gate of the first charge control transistor is connected to the first charge control signal line, a first pole of the first charge control transistor is connected to a second pole of the photosensitive device, and a second pole of the first charge control transistor is The second end of the second storage capacitor is connected.
  • a gate of the second charge control transistor is connected to the second charge control signal line, a first pole of the second charge control transistor is connected to a gate of the source follower transistor, and a second pole of the second charge control transistor Connected to the second pole of the source follower transistor.
  • the compensation control sub-circuit includes: a compensation control transistor, wherein a gate of the compensation control transistor is coupled to the compensation control signal line, and compensates a first electrode of the control transistor and a second end of the first storage capacitor Connected, and the second pole of the compensation control transistor is coupled to the second end of the second storage capacitor.
  • the signal read control sub-circuit includes: a signal read control transistor, wherein a gate of the signal read control transistor is connected to the read control signal line, and the signal read control transistor has a first pole Connected to the second pole of the source follower transistor, and the second pole of the signal read control transistor is connected to the photocurrent signal read line.
  • the photosensitive device comprises a photodiode.
  • the source follower transistor, the first reset transistor, the second reset transistor, the first charge control transistor, the second charge control transistor, the compensation control transistor And the signal read control transistor is a p-type transistor, the second level is a high level, and the first level is a low level.
  • the present disclosure also provides a driving method of an active pixel sensor circuit for application to the above-described active pixel sensing circuit.
  • the driving method includes a resetting step, a charging step, a compensating step, and a signal reading step.
  • the reset sub-circuit controls the first reset voltage to be written to the first end of the first storage capacitor and controls the second reset voltage to be written to the first storage capacitor a second end; the compensation control sub-circuit controls the second reset voltage to be written to the second end of the second storage capacitor; the charge control sub-circuit controls the second reset voltage to be written to the second pole of the photosensitive device, such that The photosensitive device is reverse biased.
  • the charge control sub-circuit controls the second electrode of the photosensitive device to be connected to the second end of the second storage capacitor, and the photosensitive device is irradiated with incident light, thereby causing the The potential of the second end of the second storage capacitor becomes the photosensitive potential Vdata.
  • the light-receiving potential Vdata is stored in the second storage capacitor.
  • the charge control sub-circuit further controls a gate of the source follower transistor to be connected to a second electrode of the source follower transistor, wherein a gate potential of the source follower transistor is the first reset a voltage such that the source follower transistor is turned on until a potential of a gate of the source follower transistor is V2-
  • the compensation control sub-circuit controls the second end of the second storage capacitor to be connected to the second end of the first storage capacitor such that the photosensitive potential Vdata stored by the second storage capacitor is written Into the second end of the first storage capacitor.
  • An electric potential jump occurs at a potential of the first end of the first storage capacitor such that a gate potential of the source follower transistor jumps to V2-
  • the signal reading control sub-circuit controls the photo-current signal reading line and the second-pole connection of the source-following transistor, and the source-following transistor is turned on.
  • the gate-source voltage of the source follower transistor compensates a threshold voltage of the source follower transistor such that an operating current of the source follower transistor is independent of the threshold voltage, and is read by the photocurrent signal The line reads the operating current.
  • the present disclosure also provides a driving method of an active pixel sensor circuit for application to the above-described active pixel sensing circuit, the driving method including a resetting step, a charging step, a compensating step, and a signal reading step.
  • the reset control signal, the first charge control signal, and the compensation control signal are all low, and the first reset transistor, the second reset transistor, and the first charge control transistor And the compensation control transistor is turned on.
  • a first reset voltage is written to the first end of the first storage capacitor, and a second storage capacitor is coupled to the cathode of the photodiode such that the photodiode is reverse biased and the photodiode is paired by the second reset voltage
  • the PN junction capacitance of the diode is charged.
  • both the first charging control signal and the second charging control signal are at a low level, and both the first charging control transistor and the second charging control transistor are turned on, and the photodiode is illuminated by incident light.
  • the potential of the second end of the second storage capacitor to become the light-receiving potential Vdata, and storing the light-receiving potential Vdata in the second storage capacitor, wherein the gate potential of the source-following transistor is the a reset voltage such that the source follower transistor is turned on until the potential of the gate of the source follower transistor is Vdd-
  • the compensation control signal is at a low level, so the compensation control transistor is turned on, so that the photosensitive potential Vdata stored by the second storage capacitor is written to the second end of the first storage capacitor.
  • the potential of the first end of the first storage capacitor undergoes an isobaric jump such that the gate potential of the source follower transistor jumps to Vdd-
  • the read control signal is at a low level, and thus the signal read control transistor is turned on.
  • the gate potential of the source follower transistor is Vdd ⁇
  • the operating current is read by the photocurrent signal read line, where K is the current coefficient of the source follower transistor.
  • the resetting step further includes: in the reset phase, the second charging control signal and the read control signal are both high, and the second charging control transistor and the signal reading control transistor are both disconnected .
  • the charging step further includes: during the charging phase, the reset control signal, the compensation control signal, and the read control signal are both at a high level, and the first reset transistor, the second reset transistor, the compensation control transistor, and the signal read The control transistors are all turned off.
  • the compensating step further includes: in the compensation phase, the reset control signal, the first charging control signal, the second charging control signal, and the read control signal are all at a high level, and the first reset transistor and the second reset transistor The first charge control transistor, the second charge control transistor, and the signal read control transistor are all turned off.
  • the signal reading step further includes: in the signal reading phase, the reset control signal, the first charging control signal, the second charging control signal, and the compensation control signal are all at a high level, and the first reset transistor, the second The reset transistor, the first charge control transistor, the compensation control transistor, and the second charge control transistor are all turned off.
  • the present disclosure also provides an image sensor comprising the active pixel sensor circuit described above.
  • the active pixel sensor circuit, the driving method and the image sensor of the present disclosure adopt a reset sub-circuit, a charge control sub-circuit and a compensation sub-circuit, so that the method can be solved by voltage jump compensation.
  • the source follows the problem of inconsistent output current caused by the difference in the transistor itself, so that the output current is independent of the threshold voltage of the source follower transistor.
  • FIG. 1 is a block diagram of an active pixel sensor circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of an active pixel sensor circuit in accordance with another embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of an active pixel sensor circuit in accordance with an exemplary embodiment of the present disclosure
  • FIG. 4 is an operational timing diagram of the active pixel sensor circuit shown in FIG. 3;
  • 5A, 5B, 5C, and 5D are schematic diagrams showing current flow and transistor conduction in the T1, T2, T3, and T4 stages of FIG. 4, respectively, of the active pixel sensor circuit shown in FIG.
  • the active pixel sensor circuit of the embodiment of the present disclosure includes a photosensitive device 10, a first storage capacitor C1, a second storage capacitor C2, and a source follower transistor Tsf.
  • the first pole of the photosensitive device 10 is connected to a first level line, and the first level line outputs a first level V1.
  • the first end of the second storage capacitor C2 is connected to the first level line.
  • a gate of the source follower transistor Tsf is connected to a first end of the first storage capacitor C1, a first pole of the source follower transistor Tsf is connected to a second level line, and the second level The line outputs a second level V2.
  • the active pixel sensor circuit further includes a reset sub-circuit 21 and a charge control sub-circuit 22.
  • the reset sub-circuit 21 is respectively connected to the first end of the first storage capacitor C1 and the second end of the first storage capacitor C1 for controlling the first end of the first storage capacitor C1 in the reset phase Connected to the first reset voltage line, and controls the second end of the first storage capacitor C1 to be connected to the second reset voltage line.
  • the first reset voltage line outputs a first reset voltage Vinit
  • the second reset voltage line outputs a second reset voltage Vcom.
  • the charge control sub-circuit 22 is respectively connected to the second electrode of the photosensitive device 10, the second end of the second storage capacitor C2, the gate of the source follower transistor Tsf, and the second of the source follower transistor Tsf a pole connection for controlling a second pole of the photosensitive device 10 to be connected to a second end of the second storage capacitor C2 during a reset phase and a charging phase, and controlling a gate of the source follower transistor Tsf during a charging phase
  • the pole is connected to the second pole of the source follower transistor Tsf.
  • the compensation control sub-circuit 23 is respectively connected to the second end of the second storage capacitor C2 and the second end of the first storage capacitor C1 for controlling the second storage capacitor C2 in the reset phase and the compensation phase
  • the second end is connected to the second end of the first storage capacitor C1.
  • the signal reading control sub-circuit 24 is connected to the photocurrent signal reading line RL and the second electrode of the source follower transistor Tsf, respectively, for controlling the photocurrent signal reading line RL and the The source is connected to the second pole of the transistor Tsf.
  • Tsf is a p-type transistor, but in actual operation, Tsf can also be an n-type transistor.
  • the active pixel sensor circuit according to the embodiment of the present disclosure can make the output current of the source follower transistor and its threshold voltage by using voltage reset compensation by using a reset sub circuit, a charge control sub circuit, and a compensation sub circuit. Irrelevant, thus solving the problem of inconsistent output current due to the difference of the source follower transistors themselves.
  • the reset sub-circuit 21 is further connected with a reset control signal line Reset for use in the reset phase.
  • the first end of the first storage capacitor C1 is controlled to be connected to the first reset voltage line under the control of the reset control signal, and the second end of the first storage capacitor C1 is controlled to be connected to the second reset voltage line.
  • the charge control sub-circuit 22 is also connected to the first charge control signal line Scan2 and the second charge control signal line Scan3, respectively, for controlling the light-sensing under the control of the first charge control signal during the reset phase and the charge phase.
  • a second pole of device 10 and said second storage The second end of the capacitor C2 is connected, and the gate of the source follower transistor Tsf is controlled to be connected to the second pole of the source follower transistor Tsf under the control of the second charge control signal during the charging phase.
  • the compensation control sub-circuit 23 is further connected to the compensation control signal line Scan1 for controlling the second end of the second storage capacitor C2 and the first storage under the control of the compensation control signal in the reset phase and the compensation phase.
  • the second end of the capacitor C1 is connected.
  • the signal read control sub-circuit 24 is also connected to the read control signal line Scan4 for controlling the photo current signal read line RL and the source follower transistor Tsf under the control of the read control signal during the signal read phase.
  • the second pole is connected.
  • the reset sub-circuit is connected to the reset control signal line to perform a reset operation under the control of the reset control signal.
  • the charge control sub-circuit is respectively connected to the first charge control signal line and the second charge control signal line to perform a charging operation under the control of the first charge control signal and the second charge control signal.
  • the signal reading control sub-circuit is connected to the read control signal line to perform a signal reading operation under the control of the read control signal.
  • the reset sub-circuit may include a first reset transistor and a second reset transistor.
  • a gate of the first reset transistor is connected to the reset control signal line, a first pole of the first reset transistor is connected to the first reset voltage line, and a second pole of the first reset transistor is opposite to the first A first end of a storage capacitor is connected.
  • a gate of the second reset transistor is connected to the reset control signal line, a first pole of the second reset transistor is connected to the second reset voltage line, and a second pole of the second reset transistor is opposite to the first A second end of the storage capacitor is connected.
  • the charge control subcircuit includes a first charge control transistor and a second charge control transistor.
  • a gate of the first charge control transistor is connected to the first charge control signal line, a first pole of the first charge control transistor is connected to a second pole of the photosensitive device, and a second pole of the first charge control transistor is The second end of the second storage capacitor is connected.
  • a gate of the second charge control transistor is connected to the second charge control signal line, a first pole of the second charge control transistor is connected to a gate of the source follower transistor, and a second pole of the second charge control transistor Connected to the second pole of the source follower transistor.
  • the compensation control subcircuit includes a compensation control transistor, a gate of the middle compensation control transistor is connected to the compensation control signal line, a first pole of the compensation control transistor is connected to the second end of the first storage capacitor, and the second pole of the control transistor and the second storage capacitor are compensated The second end is connected.
  • the signal read control sub-circuit includes: a signal read control transistor, wherein a gate of the signal read control transistor is connected to the read control signal line, and the signal read control transistor has a first pole Connected to the second pole of the source follower transistor, and the second pole of the signal read control transistor is connected to the photocurrent signal read line.
  • the photosensitive device includes a photodiode.
  • the photosensitive device may also be other types of photosensitive devices, as long as the process of the photosensitive device can be combined with existing semiconductor processes.
  • the signal read control transistors may all be p-type transistors, in which case the second level is a high level and the first level is a low level.
  • the type of the above transistor may also be an n-type transistor, and the type of the transistor is not limited in the embodiment of the present disclosure.
  • the active pixel sensor circuit of the present disclosure is described below by way of exemplary embodiments.
  • the active pixel sensor circuit of the present disclosure includes a photodiode PD, a first storage capacitor C1, a second storage capacitor C2, a source follower transistor Tsf, a reset sub-circuit, a charge control sub-circuit, and compensation. Control subcircuit and signal read control subcircuit.
  • the anode of the photodiode PD is grounded, the first end of the second storage capacitor C2 is grounded, and the source follows the gate of the transistor Tsf and the first A first end of a storage capacitor C1 is connected, and a source of the source follower transistor Tsf is connected to a high level Vdd.
  • the reset subcircuit includes a first reset transistor TR1 and a second reset transistor TR2.
  • the gate of the first reset transistor TR1 is connected to the reset control signal line Reset, the source of the first reset transistor TR1 is connected to the first reset voltage Vinit, and the drain of the first reset transistor TR1 is opposite to the first A first end of a storage capacitor C1 is connected.
  • the gate of the second reset transistor TR2 is connected to the reset control signal line Reset, the source of the second reset transistor TR2 is connected to the second reset voltage Vcom, and the drain of the second reset transistor TR2 is The second end of the first storage capacitor C1 is connected.
  • the charge control subcircuit includes a first charge control transistor TC1 and a second charge control Transistor TC2.
  • the gate of the first charge control transistor TC1 is connected to the first charge control signal line Scan2, the source of the first charge control transistor TC1 is connected to the cathode of the photodiode PD, and the drain of the first charge control transistor TC1 Connected to the second end of the second storage capacitor C2.
  • the gate of the second charge control transistor TC2 is connected to the second charge control signal line Scan3, the source of the second charge control transistor TC2 is connected to the gate of the source follower transistor Tsf, and the second charge control transistor TC2 The drain is connected to the drain of the source follower transistor Tsf.
  • the compensation control sub-circuit includes a compensation control transistor Tcp, wherein a gate of the compensation control transistor Tcp is connected to the compensation control signal line Scan1, a source of the compensation control transistor Tcp is connected to a second end of the first storage capacitor C1, and The drain of the compensation control transistor Tcp is connected to the second end of the second storage capacitor C2.
  • the signal read control sub-circuit includes a signal read control transistor Tread, wherein a gate of the signal read control transistor Tread is connected to the read control signal line Scan4, and a source of the signal read control transistor Tread and the source follow The drain of the transistor Tsf is connected, and the drain of the signal read control transistor Tread is connected to the photocurrent signal read line RL.
  • the first node N1 is connected to the gate of the source follower transistor Tsf, and the second node N2 is connected to the second end of the second storage capacitor C2.
  • Figure 4 illustrates an operational timing diagram of the active pixel sensor circuit as shown in Figure 3.
  • Reset, Scan1, and Scan2 are both low, and both Scan3 and Scan4 are high.
  • TR1 is turned on, thereby resetting N1 to Vinit (Vinit is the initial low potential, Vinit can be 0 or negative voltage);
  • Tcp and TR2 are turned on, thereby resetting the potential of N2 to Vcom, and thus the previous The voltage signal is reset; and, since TC1 is turned on, the potential Vcom of N2 is written to the cathode of the PD through TC1 to control the PD reverse bias.
  • the effect of resetting during the reset phase is to eliminate the signal of the previous frame, thereby preventing the signal of the previous frame from affecting the detection of the next frame.
  • Reset, Scan1, and Scan4 are both high, and both Scan2 and Scan3 are low.
  • the PN junction of the PD is irradiated by the incident light
  • the PN junction is excited by the photon to generate an electron hole pair, thereby recombining the charges on the PN junction capacitor.
  • TC1 is turned on, the potential of N2 is lowered to Vdata (Vdata is the photosensitive potential generated after the PD is irradiated with incident light), and Vdata is stored at both ends of C2.
  • TC2 is turned on to control the gate of Tsf to connect to the drain of Tsf.
  • Tsf Since the gate potential of the source follower transistor Tsf is Vinit at this time, Tsf is turned on, and Vdd charges N1 through Tsf and TC2 until the potential of the gate of Tsf is Vdd-
  • Tread is turned on, the source of Tsf is connected to Vdd, and the drain of Tsf is connected to RL. Since the potential of N1 is Vdd-
  • K is the current coefficient of Tsf and V SG is the source gate voltage of Tsf.
  • I is not affected by the threshold voltage of the source follower transistor Tsf at this time, but only related to Vdata, and Vdata is directly generated by the PN junction of the photodiode PD, and is followed by the source.
  • the transistor Tsf is independent, so the problem of the threshold voltage shift caused by the process follow-up transistor Tsf due to the process process and long-time operation can be completely solved, and the accuracy of the photocurrent signal is ensured.
  • FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D are respectively a current flow direction and a transistor conduction diagram of the active pixel sensor circuit shown in FIG. 3A in stages T1, T2, T3, and T4 in FIG. .
  • the transistors framed by the broken lines are turned on.
  • Embodiments of the present disclosure also provide a driving method of an active pixel sensor circuit to be applied to the above-described active pixel sensing circuit.
  • the driving method includes a resetting step, a charging step, a compensating step, and a signal reading step.
  • the reset sub-circuit controls the first reset voltage to be written to the first end of the first storage capacitor and the second reset voltage to be written to the second end of the first storage capacitor.
  • the compensation control subcircuit controls the second reset voltage to be written to the second end of the second storage capacitor.
  • a charge control sub-circuit controlling the second reset voltage to be written to the second of the photosensitive device a pole so that the photosensitive device is reverse biased.
  • the charge control sub-circuit controls the second electrode of the photosensitive device to be connected to the second end of the second storage capacitor, and the photosensitive device is irradiated with incident light, thereby causing the The potential of the second end of the second storage capacitor becomes the photosensitive potential Vdata.
  • the light-receiving potential Vdata is stored in the second storage capacitor.
  • the charge control sub-circuit further controls a gate of the source follower transistor to be connected to a second electrode of the source follower transistor, wherein a gate potential of the source follower transistor is the first reset a voltage such that the source follower transistor is turned on until a potential of a gate of the source follower transistor is V2-
  • the compensation control sub-circuit controls the second end of the second storage capacitor to be connected to the second end of the first storage capacitor such that the photosensitive potential Vdata stored by the second storage capacitor is written Into the second end of the first storage capacitor.
  • An electric potential jump occurs at a potential of the first end of the first storage capacitor such that a gate potential of the source follower transistor jumps to V2-
  • the signal reading control sub-circuit controls the photo-current signal reading line and the second-pole connection of the source-following transistor, and the source-following transistor is turned on.
  • the gate-source voltage of the source-following transistor compensates a threshold voltage of the source-following transistor such that an operating current of the source-following transistor is independent of the threshold voltage, and the photo-current signal reading line Read the operating current.
  • the driving method of the active pixel sensor circuit may be such that a gate-source voltage of the source follower transistor compensates a threshold voltage of the source follower transistor during a signal reading phase, so that the source follows The operating current of the transistor is independent of the threshold voltage.
  • Embodiments of the present disclosure also provide a driving method of an active pixel sensor circuit for application to an active pixel sensing circuit as shown in FIG. 3A.
  • the driving method includes a resetting step, a charging step, a compensating step, and a signal reading step.
  • the reset control signal, the first charge control signal, and the compensation control signal are all low, and the first reset transistor, the second reset transistor, and the first charge control transistor And the compensation control transistor is turned on.
  • a first reset voltage is written to the first end of the first storage capacitor, and a second storage capacitor is coupled to the cathode of the photodiode such that the photodiode is reverse biased and The photodiode's PN junction capacitance is charged.
  • both the first charging control signal and the second charging control signal are at a low level, and both the first charging control transistor and the second charging control transistor are turned on, and the photodiode is illuminated by incident light.
  • the potential of the second end of the second storage capacitor is changed to the light-receiving potential Vdata, and the light-receiving potential Vdata is stored in the second storage capacitor.
  • the gate potential of the source follower transistor is the first reset voltage, such that the source follower transistor is turned on until the potential of the gate of the source follower transistor is Vdd ⁇
  • the compensation control signal is at a low level, so the compensation control transistor is turned on, so that the photosensitive potential Vdata stored by the second storage capacitor is written to the second end of the first storage capacitor.
  • the potential of the first end of the first storage capacitor undergoes an isobaric jump such that the gate potential of the source follower transistor jumps to Vdd-
  • the read control signal is at a low level, and thus the signal read control transistor is turned on.
  • the gate potential of the source follower transistor is Vdd ⁇
  • the operating current is read by the photocurrent signal read line, where K is the current coefficient of the source follower transistor.
  • the resetting step further includes: in the reset phase, both the second charging control signal and the read control signal are at a high level, and the second charging control transistor and the signal reading control transistor are both disconnected .
  • the charging step further includes: during the charging phase, the reset control signal, the compensation control signal, and the read control signal are both at a high level, and the first reset transistor, the second reset transistor, the compensation control transistor, and the signal read The control transistors are all turned off.
  • the compensating step further includes: in the compensation phase, the reset control signal, the first charging control signal, the second charging control signal, and the read control signal are all at a high level, and the first reset transistor and the second reset transistor The first charge control transistor, the second charge control transistor, and the signal read control transistor are all turned off.
  • the signal reading step further includes: in the signal reading phase, the reset control signal, the first charging control signal, the second charging control signal, and the compensation control signal are all at a high level, and the first reset transistor, the second Reset transistor, first charge control transistor, compensation control Both the transistor and the second charge control transistor are turned off.
  • Embodiments of the present disclosure also provide an image sensor including the active pixel sensor circuit described above.

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Abstract

提供一种有源像素传感器电路、驱动方法和图像传感器。有源像素传感器电路包括感光器件（10）、第一存储电容（C1）、第二存储电容（C2）和源极跟随晶体管（Tsf）。有源像素传感器电路还包括重置子电路（21）、充电控制子电路（22）、补偿控制子电路（23）和信号读取控制子电路（24）。充电控制子电路（22）在重置阶段和充电阶段控制感光器件（10）的第二极与第二存储电容（C2）的第二端连接，并且在充电阶段控制源极跟随晶体管（Tsf）的栅极与源极跟随晶体管（Tsf）的第二极连接。补偿控制子电路（23）在重置阶段和补偿阶段控制第二存储电容（C2）的第二端和第一存储电容（C1）的第二端连接。

Description

有源像素传感器电路、驱动方法和图像传感器
相关申请
本申请要求享有2016年5月20日提交的中国专利申请No.201610341437.0的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及有源像素传感技术领域，尤其涉及一种有源像素传感器电路、驱动方法和图像传感器。
背景技术
CMOS(Complementary Metal-Oxide Semiconductor，互补性金属氧化物半导体)图像传感器可以将纯粹逻辑运算的功能转换成接收外界光线后转变为电能并传递出去。
作为最常见的CMOS图像传感器的检测电路，有源式像素传感器(Active Pixel Sensor，简称APS)电路在感光器件进行光电转换的过程中，由于源极跟随TFT(Thin Film Transistor，薄膜晶体管)自身工艺差异导致其阈值电压不均一，并且源极跟随TFT的输出电流会受到其自身的阈值电压的影响，因此源极跟随TFT的输出电流不均一，使得最终的画面失真。
发明内容
本公开的主要目的在于提供一种有源像素传感器电路、驱动方法和图像传感器，其能够至少部分地缓解或消除以上提到的现有技术中的缺陷。
为了达到上述目的，本公开提供了一种有源像素传感器电路，包括感光器件、第一存储电容、第二存储电容和源极跟随晶体管。所述感光器件的第一极与第一电平线连接，所述第二存储电容的第一端与第一电平线连接，所述源极跟随晶体管的栅极与所述第一存储电容的第一端连接，并且所述源极跟随晶体管的第一极与第二电平线连接。
所述有源像素传感器电路还包括重置子电路、充电控制子电路、补偿控制子电路和信号读取控制子电路。
所述重置子电路分别与所述第一存储电容的第一端和所述第一存储电容的第二端连接，用于在重置阶段控制所述第一存储电容的第一端与第一重置电压线连接，并控制所述第一存储电容的第二端与第二重置电压线连接。
充电控制子电路分别与所述感光器件的第二极、所述第二存储电容的第二端、所述源极跟随晶体管的栅极和所述源极跟随晶体管的第二极连接，用于在重置阶段和充电阶段控制所述感光器件的第二极与所述第二存储电容的第二端连接，并在充电阶段控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接。
补偿控制子电路分别与所述第二存储电容的第二端和所述第一存储电容的第二端连接，用于在重置阶段和补偿阶段控制所述第二存储电容的第二端和所述第一存储电容的第二端连接。
信号读取控制子电路分别与光电流信号读取线和所述源极跟随晶体管的第二极连接，用于在信号读取阶段控制所述光电流信号读取线和所述源极跟随晶体管的第二极连接。
在一些实施例中，所述重置子电路还与重置控制信号线连接，以用于在重置阶段在重置控制信号的控制下控制所述第一存储电容的第一端与第一重置电压线连接，并控制所述第一存储电容的第二端与第二重置电压线连接。
所述充电控制子电路还分别与第一充电控制信号线和第二充电控制信号线连接，以用于在重置阶段和充电阶段在第一充电控制信号的控制下控制所述感光器件的第二极与所述第二存储电容的第二端连接，并在充电阶段在第二充电控制信号的控制下控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接。
所述补偿控制子电路还与补偿控制信号线连接，用于在重置阶段和补偿阶段在补偿控制信号的控制下控制所述第二存储电容的第二端和所述第一存储电容的第二端连接。
信号读取控制子电路还与读取控制信号线连接，用于在信号读取阶段在读取控制信号的控制下控制所述光电流信号读取线和所述源极跟随晶体管的第二极连接。
在一些实施例中，所述重置子电路包括第一重置晶体管和第二重置晶体管。
第一重置晶体管的栅极与所述重置控制信号线连接，第一重置晶体管的第一极与第一重置电压线连接，并且第一重置晶体管的第二极与所述第一存储电容的第一端连接。
第二重置晶体管的栅极与所述重置控制信号线连接，第二重置晶体管的第一极与第二重置电压线连接，并且第二重置晶体管的第二极与所述第一存储电容的第二端连接。
在一些实施例中，所述充电控制子电路包括第一充电控制晶体管和第二充电控制晶体管。
第一充电控制晶体管的栅极与所述第一充电控制信号线连接，第一充电控制晶体管的第一极与所述感光器件的第二极连接，并且第一充电控制晶体管的第二极与所述第二存储电容的第二端连接。
第二充电控制晶体管的栅极与所述第二充电控制信号线连接，第二充电控制晶体管的第一极与所述源极跟随晶体管的栅极连接，并且第二充电控制晶体管的第二极与所述源极跟随晶体管的第二极连接。
在一些实施例中，所述补偿控制子电路包括：补偿控制晶体管，其中补偿控制晶体管的栅极与补偿控制信号线连接，补偿控制晶体管的第一极与所述第一存储电容的第二端连接，并且补偿控制晶体管的第二极与所述第二存储电容的第二端连接。
在一些实施例中，所述信号读取控制子电路包括：信号读取控制晶体管，其中信号读取控制晶体管的栅极与所述读取控制信号线连接，信号读取控制晶体管的第一极与所述源极跟随晶体管的第二极连接，并且信号读取控制晶体管的第二极与所述光电流信号读取线连接。
在一些实施例中，所述感光器件包括光电二极管。
在一些实施例中，所述源极跟随晶体管、所述第一重置晶体管、所述第二重置晶体管、所述第一充电控制晶体管、所述第二充电控制晶体管、所述补偿控制晶体管和所述信号读取控制晶体管都为p型晶体管，第二电平为高电平，并且第一电平为低电平。
本公开还提供了一种有源像素传感器电路的驱动方法，以应用于上述的有源像素传感电路。所述驱动方法包括重置步骤、充电步骤、补偿步骤和信号读取步骤。
在重置步骤中，在重置阶段期间，重置子电路控制第一重置电压写入第一存储电容的第一端并控制第二重置电压写入第一存储电容的 第二端；补偿控制子电路控制所述第二重置电压写入第二存储电容的第二端；充电控制子电路控制所述第二重置电压写入感光器件的第二极，以使得所述感光器件反向偏置。
在充电步骤中，在充电阶段期间，充电控制子电路控制所述感光器件的第二极与所述第二存储电容的第二端连接，并且所述感光器件受到入射光照射，从而使得所述第二存储电容的第二端的电位变为感光电位Vdata。将该感光电位Vdata存储于所述第二存储电容。所述充电控制子电路还控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接，由于此时所述源极跟随晶体管的栅极电位为所述第一重置电压，使得所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为V2-|Vth|，其中V2为第二电平，Vth为所述源极跟随晶体管的阈值电压。
在补偿步骤中，在补偿阶段期间，补偿控制子电路控制所述第二存储电容的第二端和所述第一存储电容的第二端连接，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端。所述第一存储电容的第一端的电位发生等压跳变，使得所述源极跟随晶体管的栅极电位跳变为V2-|Vth|+Vdata。
在信号读取步骤中，在信号读取阶段期间，信号读取控制子电路控制光电流信号读取线和所述源极跟随晶体管的第二极连接，并且所述源极跟随晶体管导通。此时，所述源极跟随晶体管的栅源电压补偿所述源极跟随晶体管的阈值电压，以使得所述源极跟随晶体管的工作电流与该阈值电压无关，并且通过所述光电流信号读取线读取该工作电流。
本公开还提供了一种有源像素传感器电路的驱动方法，以应用于上述的有源像素传感电路，所述驱动方法包括重置步骤、充电步骤、补偿步骤和信号读取步骤。
在重置步骤中，在重置阶段期间，重置控制信号、第一充电控制信号和补偿控制信号都为低电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管和补偿控制晶体管都导通。第一重置电压写入第一存储电容的第一端，并且第二存储电容连接到光电二极管的阴极，以使得所述光电二极管反向偏置，并通过第二重置电压对所述光电二极管的PN结电容充电。
在充电步骤中，在充电阶段期间，第一充电控制信号和第二充电控制信号都为低电平，第一充电控制晶体管和第二充电控制晶体管都导通，所述光电二极管被入射光照射而使得所述第二存储电容的第二端的电位变为感光电位Vdata，并将该感光电位Vdata存储于所述第二存储电容，此时所述源极跟随晶体管的栅极电位为所述第一重置电压，使得所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为Vdd-|Vth|，其中Vdd为所述源极跟随晶体管的第一极接入的高电平，并且Vth为所述源极跟随晶体管的阈值电压。
在补偿步骤中，在补偿阶段期间，补偿控制信号为低电平，因此补偿控制晶体管导通，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端。所述第一存储电容的第一端的电位发生等压跳变，使得所述源极跟随晶体管的栅极电位跳变为Vdd-|Vth|+Vdata。
在信号读取步骤中，在信号读取阶段期间，读取控制信号为低电平，因此信号读取控制晶体管导通。此时源极跟随晶体管的栅极电位为Vdd-|Vth|+Vdata，所述源极跟随晶体管导通，并且该源极跟随晶体管的工作电流为K×Vdata2。通过所述光电流信号读取线读取该工作电流，其中K为所述源极跟随晶体管的电流系数。
在一些实施例中，所述重置步骤还包括：在重置阶段，第二充电控制信号和读取控制信号都为高电平，并且第二充电控制晶体管和信号读取控制晶体管都断开。
所述充电步骤还包括：在充电阶段，重置控制信号、补偿控制信号和读取控制信号都为高电平，并且第一重置晶体管，第二重置晶体管、补偿控制晶体管和信号读取控制晶体管都断开。
所述补偿步骤还包括：在补偿阶段，重置控制信号、第一充电控制信号、第二充电控制信号和读取控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、第二充电控制晶体管和信号读取控制晶体管都断开。
所述信号读取步骤还包括：在信号读取阶段，重置控制信号、第一充电控制信号、第二充电控制信号和补偿控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、补偿控制晶体管和第二充电控制晶体管都断开。
本公开还提供了一种图像传感器，包括上述的有源像素传感器电路。
与现有技术相比，本公开所述的有源像素传感器电路、驱动方法和图像传感器采用重置子电路、充电控制子电路和补偿子电路，使得可以通过电压跳变补偿的方式，解决由于源极跟随晶体管自身差异所导致的输出电流不一致的问题，使得该输出电流与所述源极跟随晶体管的阈值电压无关。
附图说明
图1是根据本公开实施例的有源像素传感器电路的结构图；
图2是根据本公开另一实施例的有源像素传感器电路的结构图；
图3是根据本公开的示例性实施例的有源像素传感器电路的电路图；
图4是如图3所示的有源像素传感器电路的工作时序图；以及
图5A、图5B、图5C和图5D分别是图3所示的有源像素传感器电路在图4中的T1、T2、T3、T4阶段中的电流流向和晶体管导通示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的有源像素传感器电路，包括感光器件10、第一存储电容C1、第二存储电容C2和源极跟随晶体管Tsf。所述感光器件10的第一极与第一电平线连接，并且所述第一电平线输出第一电平V1。所述第二存储电容C2的第一端与第一电平线连接。所述源极跟随晶体管Tsf的栅极与所述第一存储电容C1的第一端连接，所述源极跟随晶体管Tsf的第一极与第二电平线连接，并且所述第二电平线输出第二电平V2。
所述有源像素传感器电路还包括重置子电路21、充电控制子电路 22、补偿控制子电路23和信号读取控制子电路24。
重置子电路21分别与所述第一存储电容C1的第一端和所述第一存储电容C1的第二端连接，用于在重置阶段控制所述第一存储电容C1的第一端与第一重置电压线连接，并且控制所述第一存储电容C1的第二端与第二重置电压线连接。所述第一重置电压线输出第一重置电压Vinit，并且所述第二重置电压线输出第二重置电压Vcom。
充电控制子电路22分别与所述感光器件10的第二极、所述第二存储电容C2的第二端、所述源极跟随晶体管Tsf的栅极和所述源极跟随晶体管Tsf的第二极连接，用于在重置阶段和充电阶段控制所述感光器件10的第二极与所述第二存储电容C2的第二端连接，并在充电阶段控制所述源极跟随晶体管Tsf的栅极与所述源极跟随晶体管Tsf的第二极连接。
补偿控制子电路23分别与所述第二存储电容C2的第二端和所述第一存储电容C1的第二端连接，用于在重置阶段和补偿阶段控制所述第二存储电容C2的第二端和所述第一存储电容C1的第二端连接。
信号读取控制子电路24分别与光电流信号读取线RL和所述源极跟随晶体管Tsf的第二极连接，用于在信号读取阶段控制所述光电流信号读取线RL和所述源极跟随晶体管Tsf的第二极连接。
在图1中，Tsf为p型晶体管，但是实际操作时，Tsf也可以为n型晶体管。
本公开实施例所述的有源像素传感器电路通过采用重置子电路、充电控制子电路和补偿子电路，可以通过电压跳变补偿的方式，使得所述源极跟随晶体管的输出电流与其阈值电压无关，从而解决由于源极跟随晶体管自身差异所导致的输出电流不一致的问题。
具体的，如图2所示，在本公开所述的有源像素传感器电路的实施例中，所述重置子电路21还与重置控制信号线Reset连接，以用于在重置阶段在重置控制信号的控制下控制所述第一存储电容C1的第一端与第一重置电压线连接，并控制所述第一存储电容C1的第二端与第二重置电压线连接。
所述充电控制子电路22还分别与第一充电控制信号线Scan2和第二充电控制信号线Scan3连接，以用于在重置阶段和充电阶段在第一充电控制信号的控制下控制所述感光器件10的第二极与所述第二存储 电容C2的第二端连接，并在充电阶段在第二充电控制信号的控制下控制所述源极跟随晶体管Tsf的栅极与所述源极跟随晶体管Tsf的第二极连接。
所述补偿控制子电路23还与补偿控制信号线Scan1连接，用于在重置阶段和补偿阶段在补偿控制信号的控制下控制所述第二存储电容C2的第二端和所述第一存储电容C1的第二端连接。
信号读取控制子电路24还与读取控制信号线Scan4连接，用于在信号读取阶段在读取控制信号的控制下控制所述光电流信号读取线RL和所述源极跟随晶体管Tsf的第二极连接。
在以上的实施例中，重置子电路与重置控制信号线连接，以便在重置控制信号的控制下进行重置操作。充电控制子电路分别与第一充电控制信号线和第二充电控制信号线连接，以便在第一充电控制信号和第二充电控制信号的控制下进行充电操作。信号读取控制子电路与读取控制信号线连接，以便在读取控制信号的控制下进行信号读取操作。
在示例实施例中，所述重置子电路可以包括第一重置晶体管和第二重置晶体管。
第一重置晶体管的栅极与所述重置控制信号线连接，第一重置晶体管的第一极与第一重置电压线连接，并且第一重置晶体管的第二极与所述第一存储电容的第一端连接。
第二重置晶体管的栅极与所述重置控制信号线连接，第二重置晶体管的第一极与第二重置电压线连接，并且第二重置晶体管的第二极与所述第一存储电容的第二端连接。
在示例实施例中，所述充电控制子电路包括第一充电控制晶体管和第二充电控制晶体管。
第一充电控制晶体管的栅极与所述第一充电控制信号线连接，第一充电控制晶体管的第一极与所述感光器件的第二极连接，并且第一充电控制晶体管的第二极与所述第二存储电容的第二端连接。
第二充电控制晶体管的栅极与所述第二充电控制信号线连接，第二充电控制晶体管的第一极与所述源极跟随晶体管的栅极连接，并且第二充电控制晶体管的第二极与所述源极跟随晶体管的第二极连接。
在示例实施例中，所述补偿控制子电路包括补偿控制晶体管，其 中补偿控制晶体管的栅极与补偿控制信号线连接，补偿控制晶体管的第一极与所述第一存储电容的第二端连接，并且补偿控制晶体管的第二极与所述第二存储电容的第二端连接。
在示例实施例中，所述信号读取控制子电路包括：信号读取控制晶体管，其中信号读取控制晶体管的栅极与所述读取控制信号线连接，信号读取控制晶体管的第一极与所述源极跟随晶体管的第二极连接，并且信号读取控制晶体管的第二极与所述光电流信号读取线连接。
在示例实施例中，所述感光器件包括光电二极管。
在实际操作时，所述感光器件也可以为其他类型的光敏器件，只要该光敏器件的工艺制程可以和现有的半导体制程相结合即可。
在实际操作时，所述源极跟随晶体管、所述第一重置晶体管、所述第二重置晶体管、所述第一充电控制晶体管、所述第二充电控制晶体管、所述补偿控制晶体管和所述信号读取控制晶体管可以都为p型晶体管，此时第二电平为高电平，第一电平为低电平。但是在实际操作时，上述晶体管的类型也可以是n型晶体管，本公开实施例对晶体管的类型不作限定。
下面通过示例性实施例来说明本公开所述的有源像素传感器电路。
如图3所示，本公开所述的有源像素传感器电路包括光电二极管PD、第一存储电容C1、第二存储电容C2、源极跟随晶体管Tsf、重置子电路、充电控制子电路、补偿控制子电路和信号读取控制子电路。
在图3中所示的示例性实施例中，所述光电二极管PD的阳极接地，所述第二存储电容C2的第一端接地，并且所述源极跟随晶体管Tsf的栅极与所述第一存储电容C1的第一端连接，并且所述源极跟随晶体管Tsf的源极接入高电平Vdd。
所述重置子电路包括第一重置晶体管TR1和第二重置晶体管TR2。
第一重置晶体管TR1的栅极与重置控制信号线Reset连接，第一重置晶体管TR1的源极接入第一重置电压Vinit，并且第一重置晶体管TR1的漏极与所述第一存储电容C1的第一端连接。
第二重置晶体管TR2的栅极与所述重置控制信号线Reset连接，第二重置晶体管TR2的源极接入第二重置电压Vcom，并且第二重置晶体管TR2的漏极与所述第一存储电容C1的第二端连接。
所述充电控制子电路包括第一充电控制晶体管TC1和第二充电控 制晶体管TC2。
第一充电控制晶体管TC1的栅极与所述第一充电控制信号线Scan2连接，第一充电控制晶体管TC1的源极与所述光电二极管PD的阴极连接，并且第一充电控制晶体管TC1的漏极与所述第二存储电容C2的第二端连接。
第二充电控制晶体管TC2的栅极与所述第二充电控制信号线Scan3连接，第二充电控制晶体管TC2的源极与所述源极跟随晶体管Tsf的栅极连接，并且第二充电控制晶体管TC2的漏极与所述源极跟随晶体管Tsf的漏极连接。
所述补偿控制子电路包括补偿控制晶体管Tcp，其中补偿控制晶体管Tcp的栅极与补偿控制信号线Scan1连接，补偿控制晶体管Tcp的源极与所述第一存储电容C1的第二端连接，并且补偿控制晶体管Tcp的漏极与所述第二存储电容C2的第二端连接。
所述信号读取控制子电路包括信号读取控制晶体管Tread，其中信号读取控制晶体管Tread的栅极与读取控制信号线Scan4连接，信号读取控制晶体管Tread的源极与所述源极跟随晶体管Tsf的漏极连接，并且信号读取控制晶体管Tread的漏极与所述光电流信号读取线RL连接。
在图3中，第一节点N1与所述源极跟随晶体管Tsf的栅极连接，并且第二节点N2与第二存储电容C2的第二端连接。
图4图示了是如图3所示的有源像素传感器电路的工作时序图。
如图4所示，在重置阶段T1(如图5A所示)，Reset、Scan1、Scan2都为低电平，并且Scan3和Scan4都为高电平。此时，TR1导通，从而将N1重置为Vinit(Vinit为初始低电位，Vinit可以为0或负电压)；Tcp和TR2导通，从而将N2的电位重置为Vcom，进而将之前的电压信号进行重置；并且，由于TC1导通，因此N2的电位Vcom经过TC1写入PD的阴极，以控制PD反向偏置。在重置阶段进行重置的作用是消除上一帧的信号，从而防止上一帧的信号对下一帧的检测产生影响。
在充电阶段T2(如图5B所示)，Reset、Scan1和Scan4都为高电平，Scan2和Scan3都为低电平。此时，当PD的PN结被入射光照射时，PN结受光量子激发而产生电子空穴对，从而使PN结电容上的电荷发生复合。由于TC1导通，因此使N2的电位降为Vdata(Vdata是PD被入射光照射后产生的感光电位)，并将Vdata存储在C2两端。 同时，TC2导通，以控制Tsf的栅极与Tsf的漏极连接。由于此时所述源极跟随晶体管Tsf的栅极电位为Vinit，Tsf导通，并且Vdd通过Tsf和TC2对N1进行充电，直至Tsf的栅极的电位为Vdd-|Vth|，其中Vth为Tsf的阈值电压。
在补偿阶段T3(如图5C所示)，Reset、Scan2、Scan3和Scan4都为高电平，并且Scan1为低电平。此时，Tcp导通，使得C1的第二端的电位为N2的电位Vdata。进一步地，由于此时TR2、TC2、Tsf、TC1和TR1均断开，因此C1没有充放电路径。在C1的第一端电位为Vdata的情况下，由于C1要保持两端电位差(即Vdd-|Vth|)不变，因此N1的电位会发生等压跳变，使得N1的电位跳变为Vdd-|Vth|+Vdata。
在信号读取阶段T4(如图5D所示)，Reset、Scan1、Scan2和Scan3都为高电平，Scan4为低电平。此时，Tread导通，Tsf的源极接入Vdd，并且Tsf的漏极与RL连接。由于N1的电位为Vdd-|Vth|+Vdata，因此Tsf的导通电流I(即光电流信号)通过Tsf和Tread被RL读取：
I＝K(VSG-|Vth|)2＝K[Vdd-(Vdd-|Vth|+Vdata)-|Vth|]2＝K(Vdata)2
其中，K为Tsf的电流系数，并且VSG为Tsf的源栅电压。
由上式可看出，此时I已经不受源极跟随晶体管Tsf的阈值电压的影响，而只与Vdata有关，而Vdata直接由光电二极管PD的PN结受光照而产生，而与源极跟随晶体管Tsf无关，因此可以彻底解决源极跟随晶体管Tsf由于工艺制程及长时间的操作而导致的阈值电压偏移的问题，保证光电流信号的准确性。
需要说明的是，图5A、图5B、图5C、图5D分别是图3A所示的有源像素传感器电路在图4中的阶段T1、T2、T3、T4中的电流流向和晶体管导通示意图。在图5A、图5B、图5C、图5D中，虚线框起来的晶体管是导通的。
本公开实施例还提供了一种有源像素传感器电路的驱动方法，以应用于上述的有源像素传感电路。所述驱动方法包括重置步骤、充电步骤、补偿步骤和信号读取步骤。
在重置步骤中，在重置阶段期间，重置子电路控制第一重置电压写入第一存储电容的第一端并控制第二重置电压写入第一存储电容的第二端。补偿控制子电路控制所述第二重置电压写入第二存储电容的第二端。充电控制子电路控制所述第二重置电压写入感光器件的第二 极，以使得所述感光器件反向偏置。
在充电步骤中，在充电阶段期间，充电控制子电路控制所述感光器件的第二极与所述第二存储电容的第二端连接，并且所述感光器件受到入射光照射，从而使得所述第二存储电容的第二端的电位变为感光电位Vdata。将该感光电位Vdata存储于所述第二存储电容。所述充电控制子电路还控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接，由于此时所述源极跟随晶体管的栅极电位为所述第一重置电压，使得所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为V2-|Vth|，其中V2为第二电平，Vth为所述源极跟随晶体管的阈值电压。
在补偿步骤中，在补偿阶段期间，补偿控制子电路控制所述第二存储电容的第二端和所述第一存储电容的第二端连接，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端。所述第一存储电容的第一端的电位发生等压跳变，使得所述源极跟随晶体管的栅极电位跳变为V2-|Vth|+Vdata。
在信号读取步骤中，在信号读取阶段期间，信号读取控制子电路控制光电流信号读取线和所述源极跟随晶体管的第二极连接，并且所述源极跟随晶体管导通。此时，所述源极跟随晶体管的栅源电压补偿所述源极跟随晶体管的阈值电压，以使得所述源极跟随晶体管的工作电流与该阈值电压无关，并所述光电流信号读取线读取该工作电流。
本公开实施例所述的有源像素传感器电路的驱动方法可以使得在信号读取阶段所述源极跟随晶体管的栅源电压补偿所述源极跟随晶体管的阈值电压，以使得所述源极跟随晶体管的工作电流与该阈值电压无关。
本公开实施例还提供了一种有源像素传感器电路的驱动方法，以应用于如图3A所示的有源像素传感电路。所述驱动方法包括重置步骤、充电步骤、补偿步骤和信号读取步骤。
在重置步骤中，在重置阶段期间，重置控制信号、第一充电控制信号和补偿控制信号都为低电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管和补偿控制晶体管都导通。第一重置电压写入第一存储电容的第一端，并且第二存储电容连接到光电二极管的阴极，以使得所述光电二极管反向偏置，并通过第二重置电压对所述 光电二极管的PN结电容充电。
在充电步骤中，在充电阶段期间，第一充电控制信号和第二充电控制信号都为低电平，第一充电控制晶体管和第二充电控制晶体管都导通，所述光电二极管被入射光照射而使得所述第二存储电容的第二端的电位变为感光电位Vdata，并将该感光电位Vdata存储于所述第二存储电容。此时所述源极跟随晶体管的栅极电位为所述第一重置电压，使得所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为Vdd-|Vth|，其中Vdd为所述源极跟随晶体管的第一极接入的高电平，并且Vth为所述源极跟随晶体管的阈值电压。
在补偿步骤中，在补偿阶段期间，补偿控制信号为低电平，因此补偿控制晶体管导通，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端。所述第一存储电容的第一端的电位发生等压跳变，使得所述源极跟随晶体管的栅极电位跳变为Vdd-|Vth|+Vdata。
在信号读取步骤中，在信号读取阶段期间，读取控制信号为低电平，因此信号读取控制晶体管导通。此时源极跟随晶体管的栅极电位为Vdd-|Vth|+Vdata，所述源极跟随晶体管导通，并且该源极跟随晶体管的工作电流为K×Vdata2。通过所述光电流信号读取线读取该工作电流，其中K为所述源极跟随晶体管的电流系数。
在示例实施例中，所述重置步骤还包括：在重置阶段，第二充电控制信号和读取控制信号都为高电平，并且第二充电控制晶体管和信号读取控制晶体管都断开。
所述充电步骤还包括：在充电阶段，重置控制信号、补偿控制信号和读取控制信号都为高电平，并且第一重置晶体管，第二重置晶体管、补偿控制晶体管和信号读取控制晶体管都断开。
所述补偿步骤还包括：在补偿阶段，重置控制信号、第一充电控制信号、第二充电控制信号和读取控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、第二充电控制晶体管和信号读取控制晶体管都断开。
所述信号读取步骤还包括：在信号读取阶段，重置控制信号、第一充电控制信号、第二充电控制信号和补偿控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、补偿控 制晶体管和第二充电控制晶体管都断开。
本公开实施例还提供了一种图像传感器，包括上述的有源像素传感器电路。
以上所述是本公开的示例实施方式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (12)

  1. 一种有源像素传感器电路，包括感光器件、第一存储电容、第二存储电容、源极跟随晶体管、重置子电路、充电控制子电路、补偿控制子电路和信号读取控制子电路，其中
    所述感光器件的第一极与第一电平线连接；
    所述第二存储电容的第一端与第一电平线连接；
    所述源极跟随晶体管的栅极与所述第一存储电容的第一端连接，并且所述源极跟随晶体管的第一极与第二电平线连接；
    所述重置子电路分别与所述第一存储电容的第一端和所述第一存储电容的第二端连接，用于在重置阶段控制所述第一存储电容的第一端与第一重置电压线连接，并控制所述第一存储电容的第二端与第二重置电压线连接；
    所述充电控制子电路分别与所述感光器件的第二极、所述第二存储电容的第二端、所述源极跟随晶体管的栅极和所述源极跟随晶体管的第二极连接，用于在重置阶段和充电阶段控制所述感光器件的第二极与所述第二存储电容的第二端连接，并在充电阶段控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接；
    所述补偿控制子电路分别与所述第二存储电容的第二端和所述第一存储电容的第二端连接，用于在重置阶段和补偿阶段控制所述第二存储电容的第二端和所述第一存储电容的第二端连接；并且
    所述信号读取控制子电路分别与光电流信号读取线和所述源极跟随晶体管的第二极连接，用于在信号读取阶段控制所述光电流信号读取线和所述源极跟随晶体管的第二极连接。
  2. 如权利要求1所述的有源像素传感器电路，其中，
    所述重置子电路还与重置控制信号线连接，以用于在重置阶段在重置控制信号的控制下控制所述第一存储电容的第一端与第一重置电压线连接，并控制所述第一存储电容的第二端与第二重置电压线连接；
    所述充电控制子电路还分别与第一充电控制信号线和第二充电控制信号线连接，以用于在重置阶段和充电阶段在第一充电控制信号的控制下控制所述感光器件的第二极与所述第二存储电容的第二端连接，并在充电阶段在第二充电控制信号的控制下控制所述源极跟随晶体管 的栅极与所述源极跟随晶体管的第二极连接；
    所述补偿控制子电路还与补偿控制信号线连接，以用于在重置阶段和补偿阶段在补偿控制信号的控制下控制所述第二存储电容的第二端和所述第一存储电容的第二端连接；并且
    信号读取控制子电路还与读取控制信号线连接，以用于在信号读取阶段在读取控制信号的控制下控制所述光电流信号读取线和所述源极跟随晶体管的第二极连接。
  3. 如权利要求2所述的有源像素传感器电路，其中，所述重置子电路包括：
    第一重置晶体管，其中所述第一重置晶体管的栅极与所述重置控制信号线连接，所述第一重置晶体管的第一极与第一重置电压线连接，并且所述第一重置晶体管的第二极与所述第一存储电容的第一端连接；以及，
    第二重置晶体管，其中所述第二重置晶体管的栅极与所述重置控制信号线连接，所述第二重置晶体管的第一极与第二重置电压线连接，并且所述第二重置晶体管的第二极与所述第一存储电容的第二端连接。
  4. 如权利要求2所述的有源像素传感器电路，其中，所述充电控制子电路包括：
    第一充电控制晶体管，其中所述第一充电控制晶体管的栅极与所述第一充电控制信号线连接，所述第一充电控制晶体管的第一极与所述感光器件的第二极连接，并且所述第一充电控制晶体管的第二极与所述第二存储电容的第二端连接；以及，
    第二充电控制晶体管，其中所述第二充电控制晶体管的栅极与所述第二充电控制信号线连接，所述第二充电控制晶体管的第一极与所述源极跟随晶体管的栅极连接，并且所述第二充电控制晶体管的第二极与所述源极跟随晶体管的第二极连接。
  5. 如权利要求2所述的有源像素传感器电路，其中，所述补偿控制子电路包括补偿控制晶体管，其中所述补偿控制晶体管的栅极与补偿控制信号线连接，所述补偿控制晶体管的第一极与所述第一存储电容的第二端连接，并且所述补偿控制晶体管的第二极与所述第二存储电容的第二端连接。
  6. 如权利要求2所述的有源像素传感器电路，其中，所述信号读 取控制子电路包括信号读取控制晶体管，其中所述信号读取控制晶体管的栅极与所述读取控制信号线连接，所述信号读取控制晶体管的第一极与所述源极跟随晶体管的第二极连接，并且所述信号读取控制晶体管的第二极与所述光电流信号读取线连接。
  7. 如权利要求1至6中任一权利要求所述的有源像素传感器电路，其中，所述感光器件包括光电二极管。
  8. 如权利要求1至7中任一权利要求所述的有源像素传感器电路，其中，所述源极跟随晶体管、所述第一重置晶体管、所述第二重置晶体管、所述第一充电控制晶体管、所述第二充电控制晶体管、所述补偿控制晶体管和所述信号读取控制晶体管都为p型晶体管，第二电平为高电平，并且第一电平为低电平。
  9. 一种有源像素传感器电路的驱动方法，以应用于如权利要求1至8中任一权利要求所述的有源像素传感电路，所述驱动方法包括：
    重置步骤：在重置阶段，重置子电路控制第一重置电压写入第一存储电容的第一端并控制第二重置电压写入第一存储电容的第二端；补偿控制子电路控制所述第二重置电压写入第二存储电容的第二端；充电控制子电路控制所述第二重置电压写入感光器件的第二极，以使得所述感光器件反向偏置；
    充电步骤：在充电阶段，充电控制子电路控制所述感光器件的第二极与所述第二存储电容的第二端连接；所述感光器件受到入射光照射从而使得所述第二存储电容的第二端的电位变为感光电位Vdata；将该感光电位Vdata存储于所述第二存储电容；所述充电控制子电路还控制所述源极跟随晶体管的栅极与所述源极跟随晶体管的第二极连接，使得所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为V2-|Vth|，其中V2为第二电平，并且Vth为所述源极跟随晶体管的阈值电压；
    补偿步骤：在补偿阶段，补偿控制子电路控制所述第二存储电容的第二端和所述第一存储电容的第二端连接，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端，并且所述源极跟随晶体管的栅极电位跳变为V2-|Vth|+Vdata；
    信号读取步骤：在信号读取阶段，信号读取控制子电路控制光电流信号读取线和所述源极跟随晶体管的第二极连接；所述源极跟随晶 体管导通，使得所述源极跟随晶体管的工作电流与所述源极跟随晶体管的阈值电压无关，并且通过所述光电流信号读取线读取该工作电流。
  10. 一种有源像素传感器电路的驱动方法，以应用于如权利要求8所述的有源像素传感电路，所述驱动方法包括：
    重置步骤：在重置阶段，重置控制信号、第一充电控制信号和补偿控制信号都为低电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管和补偿控制晶体管都导通；第一重置电压写入第一存储电容的第一端，并且第二存储电容连接到光电二极管的阴极，以使得所述光电二极管反向偏置，并通过第二重置电压对所述光电二极管的PN结电容充电；
    充电步骤：在充电阶段，第一充电控制信号和第二充电控制信号都为低电平，并且第一充电控制晶体管和第二充电控制晶体管都导通；所述光电二极管被入射光照射而使得所述第二存储电容的第二端的电位变为感光电位Vdata，并将该感光电位Vdata存储于所述第二存储电容；所述源极跟随晶体管导通，直至所述源极跟随晶体管的栅极的电位为Vdd-|Vth|，其中Vdd为所述源极跟随晶体管的第一极接入的高电平，并且Vth为所述源极跟随晶体管的阈值电压；
    补偿步骤：在补偿阶段，补偿控制信号为低电平，并且补偿控制晶体管导通，使得由第二存储电容存储的感光电位Vdata写入所述第一存储电容的第二端；所述第一存储电容的第一端的电位发生等压跳变，使得所述源极跟随晶体管的栅极电位跳变为Vdd-|Vth|+Vdata；
    信号读取步骤：在信号读取阶段，读取控制信号为低电平，信号读取控制晶体管导通，并且此时源极跟随晶体管的栅极电位为Vdd-|Vth|+Vdata；所述源极跟随晶体管导通，该源极跟随晶体管的工作电流为K×Vdata2，并且通过所述光电流信号读取线读取该工作电流，其中K为所述源极跟随晶体管的电流系数。
  11. 如权利要求10所述的有源像素传感器电路的驱动方法，其中，所述重置步骤还包括：在重置阶段，第二充电控制信号和读取控制信号都为高电平，并且第二充电控制晶体管和信号读取控制晶体管都断开；
    所述充电步骤还包括：在充电阶段，重置控制信号、补偿控制信号和读取控制信号都为高电平，并且第一重置晶体管，第二重置晶体 管、补偿控制晶体管和信号读取控制晶体管都断开；
    所述补偿步骤还包括：在补偿阶段，重置控制信号、第一充电控制信号、第二充电控制信号和读取控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、第二充电控制晶体管和信号读取控制晶体管都断开；
    所述信号读取步骤还包括：在信号读取阶段，重置控制信号、第一充电控制信号、第二充电控制信号和补偿控制信号都为高电平，并且第一重置晶体管、第二重置晶体管、第一充电控制晶体管、补偿控制晶体管和第二充电控制晶体管都断开。
  12. 一种图像传感器，包括如权利要求1至8中任一权利要求所述的有源像素传感器电路。
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