WO2016197508A1 - 一种像素电路及其驱动方法以及探测器 - Google Patents

一种像素电路及其驱动方法以及探测器 Download PDF

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Publication number
WO2016197508A1
WO2016197508A1 PCT/CN2015/092282 CN2015092282W WO2016197508A1 WO 2016197508 A1 WO2016197508 A1 WO 2016197508A1 CN 2015092282 W CN2015092282 W CN 2015092282W WO 2016197508 A1 WO2016197508 A1 WO 2016197508A1
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WIPO (PCT)
Prior art keywords
unit
transistor
terminal
input
pixel circuit
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PCT/CN2015/092282
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English (en)
French (fr)
Inventor
段立业
李重君
江峰
周莉
王龙
钟杰兴
Original Assignee
京东方科技集团股份有限公司
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Priority to EP15892058.7A priority Critical patent/EP3309773B1/en
Priority to US15/103,979 priority patent/US9681074B2/en
Publication of WO2016197508A1 publication Critical patent/WO2016197508A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/24—Measuring radiation intensity with semiconductor detectors
    • G01T1/247—Detector read-out circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/66—Transforming electric information into light information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/32—Transforming X-rays

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, and a detector including the pixel circuit.
  • the X-ray flat panel detector is an X-ray image detector with a photodiode array as its core. Under the illumination of X-rays, the scintillator or phosphor layer of the detector converts the X-ray photons into visible light. The visible light is then converted to an image electrical signal by an array having the function of a photodiode. The image electrical signal is read out through the peripheral circuit and subjected to analog/digital conversion to obtain a digitized image.
  • the electric charge accumulated by the photodiode can be converted into a voltage and amplified, thereby greatly improving the signal-to-noise ratio of the image signal, and further improving the anti-interference ability of the image signal during transmission.
  • the existing pixel circuit does not compensate the threshold voltage Vth of the amplifying transistor, it may cause a drop in image quality.
  • embodiments of the present invention provide a pixel circuit, a driving method thereof, and a detector for compensating for a threshold voltage Vth of an amplifying transistor in a pixel circuit to improve image quality.
  • a pixel circuit including a photoelectric conversion unit, an amplification unit, a reset unit, a compensation unit, a charging unit, and a reading unit.
  • the photoelectric conversion unit is connected to the first voltage terminal and the amplification unit for converting the optical signal into an electrical signal.
  • Amplification unit and The photoelectric conversion unit, the charging unit, and the readout unit are connected for amplifying an output signal from the photoelectric conversion unit.
  • the reset unit is connected to the reset end, the first voltage end and the amplifying unit, and is configured to reset the amplifying unit according to the input signal of the reset end and the input signal of the first voltage end.
  • the charging unit is connected to the first control terminal, the second voltage terminal and the amplifying unit for controlling the voltage at one end of the amplifying unit according to the input signal of the first control terminal and the input signal of the second voltage terminal.
  • the compensation unit is connected to the second control terminal, the reset unit and the amplification unit for controlling the voltage at the other end of the amplification unit according to the input signal of the second control terminal.
  • the reading unit is connected to the third control end and the amplifying unit for controlling the output signal according to the input signal of the third control end.
  • the photoelectric conversion unit may include a photodiode.
  • a photodiode can be connected between the amplifying unit and the first voltage terminal.
  • the amplification unit comprises an amplification transistor.
  • the gate of the amplifying transistor is connected to the photoelectric conversion unit, the first pole is connected to the charging unit, and the second pole is connected to the reading unit.
  • the reset unit comprises a first transistor.
  • the gate of the first transistor is connected to the reset terminal, the first pole is connected to the amplification unit, and the second pole is connected to the first voltage terminal.
  • the charging unit comprises a third transistor.
  • the gate of the third transistor is connected to the first control terminal, the first pole is connected to the second voltage terminal, and the second pole is connected to the amplification unit.
  • the compensation unit comprises a second transistor.
  • the gate of the second transistor is connected to the second control terminal, the first pole is connected to the reset unit, and the second pole is connected to the amplification unit.
  • the readout unit comprises a fourth transistor.
  • the gate of the fourth transistor is connected to the third control terminal, the first pole is connected to the amplification unit, and the second pole outputs an output signal.
  • the pixel circuit may further include a first capacitance.
  • the first capacitor can be connected between the second voltage terminal and the input of the amplification unit.
  • the first capacitor may be connected between the first voltage terminal and the input of the amplification unit.
  • the pixel circuit may further include a first capacitor and a second capacitor.
  • the first capacitor is connected between the second voltage terminal and the input of the amplifying unit, and the second capacitor is connected between the first voltage terminal and the input of the amplifying unit.
  • all of the transistors are P-type transistors.
  • all of the transistors are N-type transistors.
  • a detector is provided that includes any of the pixel circuits described above.
  • a driving method of a pixel circuit wherein a first voltage terminal is supplied with an input signal of a low level, and a second voltage terminal is supplied with an input signal of a high level.
  • a low level is input at the reset terminal
  • a high level is input at the first control terminal
  • a high level is input at the second control terminal
  • a high level is input at the third control terminal.
  • a high level is input at the reset terminal
  • a low level is input at the first control terminal
  • a low level is input at the second control terminal
  • a high level is input at the third control terminal.
  • a high level is input at the reset terminal, a low level is input at the first control terminal, a high level is input at the second control terminal, and a high level is input at the third control terminal.
  • a high level is input at the reset terminal, a low level is input at the first control terminal, a high level is input at the second control terminal, and a low level is input at the third control terminal.
  • a driving method of a pixel circuit wherein a first voltage terminal is supplied with an input signal of a high level, and a second voltage terminal is supplied with an input signal of a low level.
  • the driving method comprises: inputting a high level at the reset end, inputting a low level at the first control end, inputting a low level at the second control end, and inputting a low level at the third control end.
  • the driving method further includes: inputting a low level at the reset end, inputting a high level at the first control end, inputting a high level at the second control end, and inputting a low level at the third control end.
  • the driving method further comprises: inputting a low level at the reset end, inputting a high level at the first control end, inputting a low level at the second control end, and inputting a low level at the third control end.
  • the driving method further comprises: inputting a low level at the reset end, inputting a high level at the first control end, inputting a low level at the second control end, and inputting a high level at the third control end.
  • the compensation unit can compensate the threshold voltage Vth of the amplification unit, it is possible to avoid the output voltage signal due to the drift of the threshold voltage Vth Unstable, which significantly improves image quality.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural diagram of a pixel circuit according to Embodiment 4 of the present invention.
  • FIG. 5 is an operational timing diagram of a pixel circuit employing a P-type transistor, in accordance with an embodiment of the present invention
  • FIG. 6 is an operational timing diagram of a pixel circuit employing an N-type transistor, in accordance with an embodiment of the present invention.
  • Fig. 1 schematically shows the structure of a pixel circuit according to a first embodiment of the present invention.
  • the pixel circuit includes a photoelectric conversion unit 101, an amplification unit 102, a reset unit 103, a compensation unit 104, a charging unit 105, and a reading unit 106.
  • the photoelectric conversion unit 101 is connected to the first voltage terminal and the first node n1.
  • the photoelectric conversion unit 101 can convert an optical signal that illuminates the pixel circuit into an electrical signal.
  • the photoelectric conversion unit 101 may include a photodiode PD.
  • the cathode of the photodiode PD is connected to the first node n1, and the anode is connected to the first voltage terminal.
  • the amplifying unit 102 is connected to the first node n1, the second node n2, and the third node n3, and performs amplification processing on the input signal at the first node n1.
  • the input signal at the first node n1 to be subjected to the amplification processing is the output signal of the photoelectric conversion unit 101.
  • the amplification unit 102 may include an amplification transistor Ta. Amplifying transistor The gate of Ta is connected to the first node n1, the first pole of the amplification transistor Ta is connected to the second node n2, and the second pole of the amplification transistor Ta is connected to the third node n3.
  • the reset unit 103 is connected to the reset terminal RST, the first voltage terminal, and the first node n1.
  • the reset unit 103 can control the voltage at the first node n1 according to the input signal of the reset terminal RST and the input signal of the first voltage terminal to reset the amplification unit 102.
  • the reset unit 103 may include a first transistor T1.
  • the gate of the first transistor T1 is connected to the reset terminal RST, the first pole of the first transistor T1 is connected to the first node n1, and the second pole of the first transistor T1 is connected to the first voltage terminal.
  • the charging unit 105 is connected to the first control terminal S1, the second node n2, and the second voltage terminal.
  • the charging unit 105 can control the voltage at the second node n2 according to the input signal of the first control terminal S1 and the input signal of the second voltage terminal.
  • the charging unit 105 may include a third transistor T3.
  • the gate of the third transistor T3 is connected to the first control terminal S1, the first electrode of the third transistor T3 is connected to the second voltage terminal, and the second electrode of the third transistor T3 is connected to the second node n2.
  • the compensation unit 104 is connected to the second control terminal S2, the first node n1, and the third node n3.
  • the compensation unit 104 can control the voltage at the third node n3 according to the input signal of the second control terminal S2.
  • the compensation unit 104 may include a second transistor T2.
  • the gate of the second transistor T2 is connected to the second control terminal S2, the first pole of the second transistor T2 is connected to the first node n1, and the second pole of the second transistor T2 is connected to the third node n3.
  • the read unit 106 is connected to the third control terminal RD and the third node n3.
  • the reading unit 106 can control the output signal OUT according to the input signal of the third control terminal RD.
  • the readout unit 106 can include a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the third control terminal RD, the first electrode of the fourth transistor T4 is connected to the third node n3, and the second electrode of the fourth transistor T4 is used as an output terminal to output the final output signal OUT.
  • the pixel circuit may further include a first capacitor Cst.
  • the first capacitor Cst is connectable between the second voltage terminal and the first node n1.
  • the amplifying transistor, the first, second, third, and fourth transistors are each a P-type transistor. Therefore, the first voltage terminal is supplied with an input signal of a low level VSS, and the second voltage terminal An input signal that is supplied with a high level of VDD.
  • the first node n1, the second node n2, and the third node n3 are merely points defined for convenience of explanation, and do not represent actual nodes.
  • a photoelectric conversion unit 101, an amplification unit 102, a reset unit 103, and a compensation unit 104 are connected at a first node n1
  • an amplification unit 102 and a charging unit 105 are connected at a second node n2.
  • An amplifying unit 102, a compensating unit 104, and a reading unit 106 are connected to the third node n3.
  • the compensation unit 104 can compensate the threshold voltage Vth of the amplification unit 102, thereby avoiding the influence on the output voltage signal due to the drift of the threshold voltage Vth, and can significantly improve the image quality. .
  • the pixel circuit includes a photoelectric conversion unit 101, an amplification unit 102, a reset unit 103, a compensation unit 104, a charging unit 105, and a reading unit 106.
  • the photoelectric conversion unit 101 is connected to the first voltage terminal and the first node n1.
  • the photoelectric conversion unit 101 can convert an optical signal that illuminates the pixel circuit into an electrical signal.
  • the amplification unit 102 is connected to the first node n1, the second node n2, and the third node n3.
  • the amplifying unit 102 can perform an amplification process on the input signal at the first node n1.
  • the input signal at the first node n1 to be subjected to the amplification processing is the output signal of the photoelectric conversion unit 101.
  • the reset unit 103 is connected to the reset terminal RST, the first voltage terminal, and the first node n1.
  • the reset unit 103 can control the voltage at the first node n1 according to the input signal of the reset terminal RST and the input signal of the first voltage terminal.
  • the compensation unit 104 is connected to the second control terminal S2, the first node n1, and the third node n3.
  • the compensation unit 104 can control the voltage at the third node n3 according to the input signal of the second control terminal S2.
  • the charging unit 105 is connected to the first control terminal S1, the second node n2, and the second voltage terminal.
  • the charging unit 105 can be based on an input signal of the first control terminal S1 and an input signal of the second voltage terminal.
  • the voltage at the second node n2 is controlled.
  • the read unit 106 is connected to the third control terminal RD and the third node n3.
  • the reading unit 106 can control the output signal OUT according to the input signal of the third control terminal RD.
  • the pixel circuit may further include a first capacitor Cst.
  • the first capacitor Cst can be connected between the first voltage terminal and the first node n1.
  • the pixel circuit may further include both the first capacitor and the second capacitor.
  • the first capacitor can be connected between the second voltage terminal and the first node n1
  • the second capacitor is connected between the first voltage terminal and the first node n1.
  • the first capacitor or the second capacitor may also be a parasitic capacitance of the photodiode PD or other parasitic capacitance connected to the first node n1, and thus may not be separately fabricated.
  • the amplifying transistor, the first, second, third, and fourth transistors are each a P-type transistor. Therefore, the first voltage terminal is supplied with an input signal of a low level VSS, and the second voltage terminal is supplied with an input signal of a high level VDD.
  • the compensation unit 104 can compensate the threshold voltage Vth of the amplification unit 102, thereby avoiding the influence on the output voltage signal due to the drift of the threshold voltage Vth, and can significantly improve the image quality. .
  • the pixel circuit includes a photoelectric conversion unit 101, an amplification unit 102, a reset unit 103, a compensation unit 104, a charging unit 105, and a reading unit 106.
  • the photoelectric conversion unit 101 is connected to the first voltage terminal and the first node n1.
  • the photoelectric conversion unit 101 can convert an optical signal that illuminates the pixel circuit into an electrical signal.
  • the photoelectric conversion unit 101 may include a photodiode PD.
  • the anode of the photodiode PD is connected to the first node n1, and the cathode of the photodiode PD is connected to the first voltage terminal.
  • the amplification unit 102 is connected to the first node n1, the second node n2, and the third node n3.
  • the amplifying unit 102 can perform an amplification process on the input signal at the first node n1.
  • the amplification unit 102 may include an amplification transistor Ta.
  • the gate of the amplification transistor Ta is connected to the first node n1, and the first pole of the amplification transistor Ta is connected to the second node n2 to amplify the crystal
  • the second pole of the body tube Ta is connected to the third node n3.
  • the reset unit 103 is connected to the reset terminal RST, the first voltage terminal, and the first node n1.
  • the reset unit 103 can control the voltage at the first node n1 according to the input signal of the reset terminal RST and the input signal of the first voltage terminal to reset the amplification unit 102.
  • the reset unit 103 may include a first transistor T1.
  • the gate of the first transistor T1 is connected to the reset terminal RST, the first pole of the first transistor T1 is connected to the first node n1, and the second pole of the first transistor T1 is connected to the first voltage terminal.
  • the charging unit 105 is connected to the first control terminal S1, the second node n2, and the second voltage terminal.
  • the charging unit 105 can control the voltage at the second node n2 according to the input signals of the first control terminal S1 and the second voltage terminal.
  • the charging unit 105 may include a third transistor T3.
  • the gate of the third transistor T3 is connected to the first control terminal S1, the first electrode of the third transistor T3 is connected to the second voltage terminal, and the second electrode of the third transistor T3 is connected to the second node n2.
  • the compensation unit 104 is connected to the second control terminal S2, the first node n1, and the third node n3.
  • the compensation unit 104 can control the voltage at the third node n3 according to the input signal of the second control terminal S2.
  • the compensation unit 104 may include a second transistor T2.
  • the gate of the second transistor T2 is connected to the second control terminal S2, the first pole of the second transistor T2 is connected to the first node n1, and the second pole of the second transistor T2 is connected to the third node n3.
  • the read unit 106 is connected to the third control terminal RD and the third node n3.
  • the reading unit 106 can control the output signal OUT according to the input signal of the third control terminal RD.
  • the readout unit 106 can include a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the third control terminal RD, the first electrode of the fourth transistor T4 is connected to the third node n3, and the second electrode of the fourth transistor T4 is used as an output terminal to output the signal OUT.
  • the pixel circuit may further include a first capacitor Cst.
  • the first capacitor Cst is connectable between the second voltage terminal and the first node n1.
  • the amplifying transistor, the first, second, third, and fourth transistors are N-type transistors. Therefore, the first voltage terminal is supplied with an input signal of a high level VDD, and the second voltage terminal is supplied with an input signal of a low level VSS.
  • the compensation unit 104 can be applied to the amplification unit 102
  • the threshold voltage Vth is compensated to avoid instability of the output voltage signal due to the drift of the threshold voltage Vth, and the image quality can be remarkably improved.
  • the pixel circuit includes a photoelectric conversion unit 101, an amplification unit 102, a reset unit 103, a compensation unit 104, a charging unit 105, and a reading unit 106.
  • the photoelectric conversion unit 101 is connected to the first voltage terminal and the first node n1.
  • the photoelectric conversion unit 101 can convert an optical signal that illuminates the pixel circuit into an electrical signal.
  • the amplification unit 102 is connected to the first node n1, the second node n2, and the third node n3.
  • the amplifying unit 102 can perform an amplification process on the input signal at the first node n1.
  • the reset unit 103 is connected to the reset terminal RST, the first voltage terminal, and the first node n1.
  • the reset unit 103 can control the voltage at the first node n1 according to the input signal of the reset terminal RST and the input signal of the first voltage terminal.
  • the compensation unit 104 is connected to the second control terminal S2, the first node n1, and the third node n3.
  • the compensation unit 104 can control the voltage at the third node n3 according to the input signal of the second control terminal S2.
  • the charging unit 105 is connected to the first control terminal S1, the second node n2, and the second voltage terminal.
  • the charging unit 105 can control the voltage at the second node n2 according to the input signal of the first control terminal S1 and the input signal of the second voltage terminal.
  • the read unit 106 is connected to the third control terminal RD and the third node n3.
  • the reading unit 106 can control the output signal OUT according to the input signal of the third control terminal RD.
  • the pixel circuit may further include a first capacitor Cst.
  • the first capacitor Cst can be connected between the first voltage terminal and the first node n1.
  • the pixel circuit may further include both the first capacitor and the second capacitor.
  • the first capacitor can be connected between the second voltage terminal and the first node n1
  • the second capacitor is connected between the first voltage terminal and the first node n1.
  • the first capacitor or the second capacitor may also be a parasitic capacitance of the photodiode PD or other parasitic capacitance connected to the first node n1, and thus may not be fabricated separately.
  • the amplifying transistor, the first, second, third, and fourth transistors are each an N-type transistor. Therefore, the first voltage terminal is supplied with an input signal of a high level VDD, and the second voltage terminal is supplied with an input signal of a low level VSS.
  • the compensation unit 104 can compensate the threshold voltage Vth of the amplification unit 102, thereby avoiding the influence on the output voltage signal due to the drift of the threshold voltage Vth, and can significantly improve the image quality. .
  • This embodiment provides a detector including the pixel circuit as described in the first embodiment, the second embodiment, the third embodiment, or the fourth embodiment. Since the pixel circuit has been described in detail in the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, the details are not described herein.
  • the compensation unit in the pixel circuit can compensate the threshold voltage Vth of the amplification unit, such a detector can avoid the output voltage signal due to the drift of the threshold voltage Vth Unstable, which can significantly improve image quality.
  • the present embodiment provides a driving method of a pixel circuit including the pixel circuit of the first embodiment or the second embodiment as described above.
  • all of the transistors are P-type transistors. Therefore, the first voltage terminal is supplied with an input signal of a low level VSS, and the second voltage terminal is supplied with an input signal of a high level VDD.
  • the driving method of this embodiment will be described below by taking the pixel circuit shown in FIG. 1 as an example.
  • Fig. 5 is a timing chart showing the operation of the pixel circuit of the embodiment shown in Fig. 1.
  • step 1001 the reset terminal is input with a low level, the first control terminal is input with a high level, the second control terminal is input with a high level, and the third control terminal is input with a high level.
  • This step can be considered as a reset phase.
  • a low level is input to the reset terminal RST, so that the first transistor T1 is turned on.
  • the third transistor T3 is turned off.
  • the second transistor T2 is turned off.
  • the third control terminal RD inputs a high level, the fourth thin film transistor T4 is turned off.
  • VSS low voltage
  • Vn1 VSS at the first node n1. This voltage can be held on the first capacitor Cst.
  • step 1002 the reset terminal is input with a high level, the first control terminal is input with a low level, the second control terminal is input with a low level, and the third control terminal is input with a high level.
  • This step can be considered as a compensation phase.
  • a high level is input to the reset terminal RST, so that the first transistor T1 becomes off.
  • a low level is input at the first control terminal S1, so that the third transistor T3 becomes conductive.
  • a low level is input to the second control terminal S2 so that the second transistor T2 is also turned on.
  • step 1003 the reset terminal is input with a high level, the first control terminal is input with a low level, the second control terminal is input with a high level, and the third control terminal is input with a high level.
  • This step can be considered as the charging phase.
  • the input RST continues to input a high level, and the first transistor T1 is still turned off.
  • the input low level continues, and the third transistor T3 continues to be turned on.
  • a high level is input at the second control terminal S2 such that the second transistor T2 becomes off.
  • the third control terminal RD the input of the high level continues, and the fourth transistor T4 is still turned off.
  • the current path through the first node n1 is only the photodiode PD, and the magnitude of the current passing through the first node n1 is related to the illumination intensity of the pixel circuit. Assuming that the average value of the current passing through the first node n1 is represented by I, the voltage at the first node n1 is lowered after the elapse of time t.
  • step 1004 the reset terminal is input with a high level, the first control terminal is input with a low level, the second control terminal is input with a high level, and the third control terminal is input with a low level.
  • This step can be considered as the readout phase.
  • the input terminal RST continues to input a high level, and the first transistor T1 is still turned off.
  • the input low level continues, and the third transistor T3 continues to be turned on.
  • the second control terminal S2 continues to input a high level, and the second transistor T2 is still turned off.
  • a low level is input to the third control terminal RD, so that the fourth transistor T4 is turned on.
  • the amplification transistor Ta is in the saturation region, and the current of the amplification transistor Ta can be calculated as
  • ⁇ n represents a carrier mobility
  • Cox represents a gate insulating layer capacitance value per unit area
  • W/L represents a width to length ratio of the amplification transistor Ta.
  • the magnitude of the variable I can be analyzed to obtain information on the illumination intensity of the pixel circuit.
  • the compensation unit can compensate the threshold voltage Vth of the amplifying unit, it is possible to avoid instability of the output voltage signal due to the drift of the threshold voltage Vth, thereby being remarkable Improve image quality.
  • the present embodiment provides a driving method of a pixel circuit including the pixel circuit of the third embodiment or the fourth embodiment as described above.
  • all transistors are N-type transistors. Therefore, the first voltage terminal is supplied with an input signal of a high level VDD, and the second voltage terminal is supplied with an input signal of a low level VSS.
  • the driving method of this embodiment will be described below by taking the pixel circuit shown in FIG. 3 as an example.
  • Fig. 6 is a timing chart showing the operation of the pixel circuit of the embodiment shown in Fig. 3.
  • step 2001 the reset terminal is input with a high level, the first control terminal is input with a low level, the second control terminal is input with a low level, and the third control terminal is input with a low level.
  • This step can be considered as a reset phase.
  • a high level is input to the reset terminal RST, so that the first transistor T1 is turned on.
  • the third transistor T3 is turned off.
  • the second transistor T2 is turned off.
  • the fourth thin film transistor T4 is turned off.
  • the electricity can be maintained on the first capacitor Cst.
  • step 2002 the reset terminal is input with a low level, the first control terminal is input with a high level, the second control terminal is input with a high level, and the third control terminal is input with a low level.
  • This step can be considered as a compensation phase.
  • a low level is input to the reset terminal RST, so that the first transistor T1 becomes off.
  • a high level is input at the first control terminal S1 so that the third transistor T3 becomes conductive.
  • a high level is input to the second control terminal S2 so that the second transistor T2 is also turned on.
  • the input low level is continued, and the fourth transistor T4 is still in the off state.
  • step 2003 the reset terminal is input with a low level, the first control terminal is input with a high level, the second control terminal is input with a low level, and the third control terminal is input with a low level.
  • This step can be considered as the charging phase.
  • the input RST continues to input a low level, and the first transistor T1 is still turned off.
  • the input of the high level continues, and the third transistor T3 continues to be turned on.
  • a low level is input to the second control terminal S2 such that the second transistor T2 becomes off.
  • the input low level continues, and the fourth transistor T4 is still turned off.
  • the current path through the first node n1 is only the photodiode PD, and the magnitude of the current passing through the first node n1 is related to the illumination intensity of the pixel circuit. Assuming that the average value of the current passing through the first node n1 is represented by I, the voltage at the first node n1 is raised after the elapse of time t.
  • step 2004 the reset terminal is input with a low level, the first control terminal is input with a high level, the second control terminal is input with a low level, and the third control terminal is input with a high level.
  • This step can be considered as the readout phase.
  • the input terminal RST continues to input a low level, and the first transistor T1 is still turned off.
  • the input of the high level continues, and the third transistor T3 continues to be turned on.
  • the input low level is continued, and the second transistor T2 is still turned off.
  • the RD input is high, causing the fourth transistor T4 to be turned on.
  • the amplification transistor Ta is in the saturation region, and the current of the amplification transistor Ta can be calculated as
  • ⁇ n represents a carrier mobility
  • Cox represents a gate insulating layer capacitance value per unit area
  • W/L represents a width to length ratio of the amplification transistor Ta.
  • the magnitude of the variable I can be analyzed to obtain information on the illumination intensity of the pixel circuit.
  • the compensation unit can compensate the threshold voltage Vth of the amplifying unit, it is possible to avoid instability of the output voltage signal due to the drift of the threshold voltage Vth, thereby being remarkable Improve image quality.

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Abstract

一种像素电路及其驱动方法以及探测器，像素电路包括光电转换单元（101）、放大单元（102）、复位单元（103）、补偿单元（104）、充电单元（105）以及读出单元（106）。其中，补偿单元（104）能够对放大单元（102）的阈值电压进行补偿，以避免由于阈值电压的漂移而造成的输出的电压信号不稳定，从而可以显著提高图像质量。

Description

一种像素电路及其驱动方法以及探测器
本申请要求2015年6月12日递交的中国专利申请No.201510324511.3的优先权，并在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及一种像素电路及其驱动方法以及包括该像素电路的探测器。
背景技术
X射线平板探测器是一种以光电二极管阵列为核心的X射线影像探测器。在X射线的照射下，探测器的闪烁体或荧光体层将X射线光子转换为可见光。而后，该可见光由具有光电二极管作用的阵列转化为图像电信号。图像电信号通过外围电路读出，并进行模拟/数字转换，从而获得数字化图像。
通过在像素电路中增加放大晶体管，可以将光电二极管所积累的电荷转换成电压并进行放大，从而大大提高图像信号的信噪比，并进而提高图像信号在传输过程中抗干扰的能力。然而，由于现有的像素电路没有对放大晶体管的阈值电压Vth进行补偿，因此，可能造成图像质量的下降。
发明内容
因此，本发明的实施例提供了一种像素电路及其驱动方法以及探测器，以对像素电路中的放大晶体管的阈值电压Vth进行补偿，提高图像质量。
根据本发明的一个方面，提供了一种像素电路，其包括光电转换单元、放大单元、复位单元、补偿单元、充电单元以及读出单元。光电转换单元与第一电压端和放大单元连接，用于将光信号转化为电信号。放大单元与 光电转换单元、充电单元以及读出单元连接，用于放大来自光电转换单元的输出信号。复位单元与复位端、第一电压端以及放大单元连接，用于根据复位端的输入信号和第一电压端的输入信号，对放大单元进行复位。充电单元与第一控制端、第二电压端和放大单元连接，用于根据第一控制端的输入信号和第二电压端的输入信号，控制在放大单元的一端处的电压。补偿单元与第二控制端、复位单元以及放大单元连接，用于根据第二控制端的输入信号，控制在放大单元的另一端处的电压。读出单元与第三控制端和放大单元连接，用于根据第三控制端的输入信号，控制输出信号。
在本发明的实施例中，光电转换单元可包括光电二极管。光电二极管可连接在放大单元与第一电压端之间。
在本发明的实施例中，放大单元包括放大晶体管。放大晶体管的栅极与光电转换单元连接，第一极与充电单元连接，第二极与读出单元连接。
在本发明的实施例中，复位单元包括第一晶体管。第一晶体管的栅极与复位端连接，第一极与放大单元连接，第二极与第一电压端连接。
在本发明的实施例中，充电单元包括第三晶体管。第三晶体管的栅极与第一控制端连接，第一极与第二电压端连接，第二极与放大单元连接。
在本发明的实施例中，补偿单元包括第二晶体管。第二晶体管的栅极与第二控制端连接，第一极与复位单元连接，第二极与放大单元连接。
在本发明的实施例中，读出单元包括第四晶体管。第四晶体管的栅极与第三控制端连接，第一极与放大单元连接，第二极输出输出信号。
在本发明的实施例中，像素电路还可包括第一电容。第一电容可连接在第二电压端与放大单元的输入之间。可选地，第一电容可连接在第一电压端与放大单元的输入之间。
在本发明的实施例中，像素电路还可包括第一电容和第二电容。第一电容连接在第二电压端与放大单元的输入之间，第二电容连接在第一电压端与放大单元的输入之间。
在本发明的实施例中，所有的晶体管是P型晶体管。
在本发明的实施例中，所有的晶体管是N型晶体管。
根据本发明的另一个方面，提供了一种探测器，其包括上述任一像素电路。
根据本发明的再一个方面，提供了一种像素电路的驱动方法，其中，第一电压端被提供低电平的输入信号，第二电压端被提供高电平的输入信号。在该驱动方法中，首先，在复位端输入低电平，在第一控制端输入高电平，在第二控制端输入高电平，在第三控制端输入高电平。然后，在复位端输入高电平，在第一控制端输入低电平，在第二控制端输入低电平，在第三控制端输入高电平。然后，在复位端输入高电平，在第一控制端输入低电平，在第二控制端输入高电平，并在第三控制端输入高电平。接着，在复位端输入高电平，在第一控制端输入低电平，在第二控制端输入高电平，并在第三控制端输入低电平。
根据本发明的再一个方面，提供了一种像素电路的驱动方法，其中，第一电压端被提供高电平的输入信号，第二电压端被提供低电平的输入信号。该驱动方法包括：在复位端输入高电平，在第一控制端输入低电平，在第二控制端输入低电平，在第三控制端输入低电平。该驱动方法还包括：在复位端输入低电平，在第一控制端输入高电平，在第二控制端输入高电平，在第三控制端输入低电平。该驱动方法还包括：在复位端输入低电平，在第一控制端输入高电平，在第二控制端输入低电平，在第三控制端输入低电平。该驱动方法还包括：在复位端输入低电平，在第一控制端输入高电平，在第二控制端输入低电平，在第三控制端输入高电平。
采用根据本发明的实施例的像素电路及其驱动方法以及探测器，由于补偿单元能够对放大单元的阈值电压Vth进行补偿，因此，能够避免由于阈值电压Vth的漂移而导致的输出的电压信号的不稳定，从而显著地提高图像质量。
附图说明
为了更清楚地说明本发明的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本发明的一些实施 例，而非对本发明的限制，其中：
图1是根据本发明的实施例一的像素电路的结构示意图；
图2是根据本发明的实施例二的像素电路的结构示意图；
图3是根据本发明的实施例三的像素电路的结构示意图；
图4是根据本发明的实施例四的像素电路的结构示意图；
图5是根据本发明的实施例的采用P型晶体管的像素电路的工作时序图；
图6是根据本发明的实施例的采用N型晶体管的像素电路的工作时序图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本发明保护的范围。
实施例一
图1示意性地示出了根据本发明的实施例一的像素电路的结构。如图1所示，像素电路包括光电转换单元101、放大单元102、复位单元103、补偿单元104、充电单元105以及读出单元106。
光电转换单元101与第一电压端和第一节点n1连接。光电转换单元101可将照射像素电路的光信号转化为电信号。在本发明的实施例中，光电转换单元101可包括光电二极管PD。光电二极管PD的负极与第一节点n1连接，正极与第一电压端连接。
放大单元102与第一节点n1、第二节点n2以及第三节点n3连接，并对在第一节点n1处的输入信号进行放大处理。在本实施例中，将要进行放大处理的在第一节点n1处的输入信号是光电转换单元101的输出信号。在本发明的实施例中，放大单元102可包括放大晶体管Ta。放大晶体管 Ta的栅极与第一节点n1连接，放大晶体管Ta的第一极与第二节点n2连接，放大晶体管Ta的第二极与第三节点n3连接。复位单元103与复位端RST、第一电压端以及第一节点n1连接。复位单元103可根据复位端RST的输入信号和第一电压端的输入信号，控制在第一节点n1处的电压，以便对放大单元102进行复位。在本发明的实施例中，复位单元103可包括第一晶体管T1。第一晶体管T1的栅极与复位端RST连接，第一晶体管T1的第一极与第一节点n1连接，第一晶体管T1的第二极与第一电压端连接。
充电单元105与第一控制端S1、第二节点n2以及第二电压端连接。充电单元105可根据第一控制端S1的输入信号和第二电压端的输入信号，控制在第二节点n2处的电压。在本发明的实施例中，充电单元105可包括第三晶体管T3。第三晶体管T3的栅极与第一控制端S1连接，第三晶体管T3的第一极与第二电压端连接，第三晶体管T3的第二极与第二节点n2连接。
补偿单元104与第二控制端S2、第一节点n1以及第三节点n3连接。补偿单元104可根据第二控制端S2的输入信号，控制在第三节点n3处的电压。在本发明的实施例中，补偿单元104可包括第二晶体管T2。第二晶体管T2的栅极与第二控制端S2连接，第二晶体管T2的第一极与第一节点n1连接，第二晶体管T2的第二极与第三节点n3连接。
读出单元106与第三控制端RD和第三节点n3连接。读出单元106可根据第三控制端RD的输入信号，控制输出信号OUT。在本发明的实施例中，读出单元106可包括第四晶体管T4。第四晶体管T4的栅极与第三控制端RD连接，第四晶体管T4的第一极与第三节点n3连接，第四晶体管T4的第二极作为输出端以输出最终的输出信号OUT。
进一步地，像素电路还可包括第一电容Cst。第一电容Cst可连接在第二电压端与第一节点n1之间。
在本实施例中，放大晶体管、第一、第二、第三和第四晶体管均是P型晶体管。因此，第一电压端被提供低电平VSS的输入信号，第二电压端 被提供高电平VDD的输入信号。
需要注意，在本发明的各种实施例中，第一节点n1、第二节点n2和第三节点n3仅仅是为了方便说明而定义的点，而并不代表实际的节点。在图1所示的实施例中，在第一节点n1处连接有光电转换单元101、放大单元102、复位单元103和补偿单元104，在第二节点n2处连接有放大单元102和充电单元105，在第三节点n3处连接有放大单元102、补偿单元104、读出单元106。
在根据本实施例的像素电路中，补偿单元104能够对放大单元102的阈值电压Vth进行补偿，从而避免由于阈值电压Vth的漂移而对输出的电压信号带来的影响，可以显著地提高图像质量。
实施例二
图2是根据本发明的实施例二的像素电路的结构示意图。如图2所示，像素电路包括光电转换单元101、放大单元102、复位单元103、补偿单元104、充电单元105以及读出单元106。
光电转换单元101与第一电压端和第一节点n1连接。光电转换单元101可将照射像素电路的光信号转化为电信号。
放大单元102与第一节点n1、第二节点n2以及第三节点n3连接。放大单元102可对在第一节点n1处的输入信号进行放大处理。在本实施例中，将要进行放大处理的在第一节点n1处的输入信号是光电转换单元101的输出信号。
复位单元103与复位端RST、第一电压端以及第一节点n1连接。复位单元103可根据复位端RST的输入信号和第一电压端的输入信号，控制在第一节点n1处的电压。
补偿单元104与第二控制端S2、第一节点n1以及第三节点n3连接。补偿单元104可根据第二控制端S2的输入信号，控制在第三节点n3处的电压。
充电单元105与第一控制端S1、第二节点n2以及第二电压端连接。充电单元105可根据第一控制端S1的输入信号和第二电压端的输入信号， 控制在第二节点n2处的电压。
读出单元106与第三控制端RD和第三节点n3连接。读出单元106可根据第三控制端RD的输入信号，控制输出信号OUT。
进一步地，像素电路还可包括第一电容Cst。与实施例一不同，在本实施例中，第一电容Cst可连接在第一电压端与第一节点n1之间。
另外，在本发明的实施例中，像素电路还可以包括第一电容和第二电容两者。在这种实施例中，第一电容可连接在第二电压端与第一节点n1之间，而第二电容连接在第一电压端与第一节点n1之间。本领域的技术人应当知道，第一电容或第二电容也可以是光电二极管PD的寄生电容，或者是与第一节点n1连接的其它寄生电容，因此可以不单独制作。
在本实施例中，放大晶体管、第一、第二、第三和第四晶体管均是P型晶体管。因此，第一电压端被提供低电平VSS的输入信号，第二电压端被提供高电平VDD的输入信号。
在根据本实施例的像素电路中，补偿单元104能够对放大单元102的阈值电压Vth进行补偿，从而避免由于阈值电压Vth的漂移而对输出的电压信号带来的影响，可以显著地提高图像质量。
实施例三
图3是根据本发明的实施例三的像素电路的结构示意图。如图3所示，像素电路包括光电转换单元101、放大单元102、复位单元103、补偿单元104、充电单元105以及读出单元106。
光电转换单元101与第一电压端和第一节点n1连接。光电转换单元101可将照射像素电路的光信号转化为电信号。在本发明的实施例中，光电转换单元101可包括光电二极管PD。光电二极管PD的正极与第一节点n1连接，而光电二极管PD的负极与第一电压端连接。
放大单元102与第一节点n1、第二节点n2以及第三节点n3连接。放大单元102可对在第一节点n1处的输入信号进行放大处理。在本发明的实施例中，放大单元102可包括放大晶体管Ta。放大晶体管Ta的栅极与第一节点n1连接，放大晶体管Ta的第一极与第二节点n2连接，放大晶 体管Ta的第二极与第三节点n3连接。
复位单元103与复位端RST、第一电压端以及第一节点n1连接。复位单元103可根据复位端RST的输入信号和第一电压端的输入信号，控制在第一节点n1处的电压，以便对放大单元102进行复位。在本发明的实施例中，复位单元103可包括第一晶体管T1。第一晶体管T1的栅极与复位端RST连接，第一晶体管T1的第一极与第一节点n1连接，第一晶体管T1的第二极与第一电压端连接。
充电单元105与第一控制端S1、第二节点n2以及第二电压端连接。充电单元105可根据第一控制端S1和第二电压端的输入信号，控制在第二节点n2处的电压。在本发明的实施例中，充电单元105可包括第三晶体管T3。第三晶体管T3的栅极与第一控制端S1连接，第三晶体管T3的第一极与第二电压端连接，第三晶体管T3的第二极与第二节点n2连接。
补偿单元104与第二控制端S2、第一节点n1以及第三节点n3连接。补偿单元104可根据第二控制端S2的输入信号，控制在第三节点n3处的电压。在本发明的实施例中，补偿单元104可包括第二晶体管T2。第二晶体管T2的栅极与第二控制端S2连接，第二晶体管T2的第一极与第一节点n1连接，第二晶体管T2的第二极与第三节点n3连接。
读出单元106与第三控制端RD和第三节点n3连接。读出单元106可根据第三控制端RD的输入信号，控制输出信号OUT。在本发明的实施例中，读出单元106可包括第四晶体管T4。第四晶体管T4的栅极与第三控制端RD连接，第四晶体管T4的第一极与第三节点n3连接，第四晶体管T4的第二极作为输出端以输出信号OUT。
进一步地，像素电路还可包括第一电容Cst。第一电容Cst可连接在第二电压端与第一节点n1之间。
在本实施例中，放大晶体管、第一、第二、第三和第四晶体管是N型晶体管。因此，第一电压端被提供高电平VDD的输入信号，而第二电压端被提供低电平VSS的输入信号。
在根据本实施例的像素电路中，补偿单元104能够对放大单元102的 阈值电压Vth进行补偿，从而避免由于阈值电压Vth的漂移而造成的输出的电压信号的不稳定，可以显著地提高图像质量。
实施例四
图4是根据本发明的实施例四的像素电路的结构示意图。如图4所示，像素电路包括光电转换单元101、放大单元102、复位单元103、补偿单元104、充电单元105以及读出单元106。
光电转换单元101与第一电压端和第一节点n1连接。光电转换单元101可将照射像素电路的光信号转化为电信号。
放大单元102与第一节点n1、第二节点n2以及第三节点n3连接。放大单元102可对在第一节点n1处的输入信号进行放大处理。
复位单元103与复位端RST、第一电压端以及第一节点n1连接。复位单元103可根据复位端RST的输入信号和第一电压端的输入信号，控制在第一节点n1处的电压。
补偿单元104与第二控制端S2、第一节点n1以及第三节点n3连接。补偿单元104可根据第二控制端S2的输入信号，控制在第三节点n3处的电压。
充电单元105与第一控制端S1、第二节点n2以及第二电压端连接。充电单元105可根据第一控制端S1的输入信号和第二电压端的输入信号，控制在第二节点n2处的电压。
读出单元106与第三控制端RD和第三节点n3连接。读出单元106可根据第三控制端RD的输入信号，控制输出信号OUT。
进一步地，像素电路还可包括第一电容Cst。与实施例三不同，第一电容Cst可连接在第一电压端与第一节点n1之间。
另外，在本发明的实施例中，像素电路还可以包括第一电容和第二电容两者。在这种实施例中，第一电容可连接在第二电压端与第一节点n1之间，而第二电容连接在第一电压端与第一节点n1之间。本领域的技术人员应当知道，第一电容或第二电容也可以是光电二极管PD的寄生电容，或者是与第一节点n1连接的其它寄生电容，因此可以不单独制作。
在本实施例中，放大晶体管、第一、第二、第三和第四晶体管均是N型晶体管。因此，第一电压端被提供高电平VDD的输入信号，第二电压端被提供低电平VSS的输入信号。
在根据本实施例的像素电路中，补偿单元104能够对放大单元102的阈值电压Vth进行补偿，从而避免由于阈值电压Vth的漂移而对输出的电压信号带来的影响，可以显著地提高图像质量。
实施例五
本实施例提供了一种探测器，其包括如上述实施例一、实施例二、实施例三或实施例四所述的像素电路。由于已经在上述的实施例一、实施例二、实施例三、实施例四中对像素电路进行了详细描述，因此，在此处不再赘述。
在根据本实施例的探测器中，由于像素电路中的补偿单元能够对放大单元的阈值电压Vth进行补偿，因此，这样的探测器能够避免由于阈值电压Vth的漂移而造成的输出的电压信号的不稳定，从而可以显著地提高图像质量。
实施例六
本实施例提供了包括如上述的实施例一或实施例二的像素电路的像素电路的驱动方法。在这样的像素电路中，所有的晶体管均是P型晶体管。因此，第一电压端被提供低电平VSS的输入信号，第二电压端被提供高电平VDD的输入信号。下面以图1所示的像素电路为例说明本实施例的驱动方法。图5是图1所示的实施例的像素电路的工作时序图。
在步骤1001中，复位端被输入低电平，第一控制端被输入高电平，第二控制端被输入高电平，第三控制端被输入高电平。该步骤可被认为是复位阶段。
参见图5，在复位阶段，在复位端RST输入低电平，使得第一晶体管T1导通。在第一控制端S1输入高电平，则第三晶体管T3截止。在第二控制端S2输入高电平，则第二晶体管T2截止。在第三控制端RD输入高电平，，则第四薄膜晶体管T4截止。在这种情况下，在第一节点n1处的 电压被复位至低电压VSS，即在第一节点n1处的电压Vn1＝VSS。该电压可被保持在第一电容Cst上。
在步骤1002，复位端被输入高电平，第一控制端被输入低电平，第二控制端被输入低电平，第三控制端被输入高电平。该步骤可被认为是补偿阶段。
参见图5，在补偿阶段，在复位端RST输入高电平，使得第一晶体管T1变为截止。在第一控制端S1输入低电平，使得第三晶体管T3变得导通。在第二控制端S2输入低电平，使得第二晶体管T2也导通。在第三控制端RD继续输入高电平，第四晶体管T4仍然处于截止状态。在这种情况下，放大晶体管Ta成为二极管连接状态，此时在第一节点n1处的电压Vn1＝Vn3＝VDD-︱Vth︱，其中Vn3是在第三节点n3处的电压，Vth是放大晶体管Ta的阈值电压。
在步骤1003，复位端被输入高电平，第一控制端被输入低电平，第二控制端被输入高电平，第三控制端输入高电平。该步骤可被认为是充电阶段。
在充电阶段，在复位端RST继续输入高电平，第一晶体管T1仍然截止。在第一控制端S1继续输入低电平，第三晶体管T3继续处于导通。在第二控制端S2输入高电平，使得第二晶体管T2变成截止。在第三控制端RD继续输入高电平，第四晶体管T4仍然处于截止。在这种情况下，经过第一节点n1的电流通路只有光电二极管PD，则经过第一节点n1的电流的大小与像素电路的光照强度有关。假设经过第一节点n1的电流平均值用I表示，那么在经过时间t后，在第一节点n1处的电压被降低了
Figure PCTCN2015092282-appb-000001
则此时在第一节点n1处的电压为
Figure PCTCN2015092282-appb-000002
在步骤1004，复位端被输入高电平，第一控制端被输入低电平，第二控制端被输入高电平，第三控制端被输入低电平。该步骤可被认为是读出阶段。
在读出阶段，在复位端RST继续输入高电平，第一晶体管T1仍然截止。在第一控制端S1继续输入低电平，第三晶体管T3继续处于导通。在 第二控制端S2继续输入高电平，第二晶体管T2仍然截止。在第三控制端RD输入低电平，使得第四晶体管T4导通。在这种情况下，放大晶体管Ta处于饱和区，则放大晶体管Ta的电流可被计算为
Figure PCTCN2015092282-appb-000003
其中，μn表示载流子迁移率，Cox表示单位面积的栅绝缘层电容值，W/L表示放大晶体管Ta的宽长比。
将
Figure PCTCN2015092282-appb-000004
代入上述公式，可以得出：
Figure PCTCN2015092282-appb-000005
这样，在读出电流Id后，可以分析变量I的大小，从而得到像素电路的光照强度的信息。
采用根据本实施例的像素电路的驱动方法，由于补偿单元能够对放大单元的阈值电压Vth进行补偿，因此，能够避免由于阈值电压Vth的漂移而造成的输出的电压信号的不稳定，从而可以显著地提高图像质量。
实施例七
本实施例提供了包括如上述的实施例三或实施例四的像素电路的像素电路的驱动方法。在这样的像素电路中，所有晶体管均是N型晶体管。因此，第一电压端被提供高电平VDD的输入信号，第二电压端被提供低电平VSS的输入信号。下面以图3所示的像素电路为例说明本实施例的驱动方法。图6是图3所示的实施例的像素电路的工作时序图。
在步骤2001，复位端被输入高电平，第一控制端被输入低电平，第二控制端被输入低电平，第三控制端被输入低电平。该步骤可被认为是复位阶段。
参见图6，在复位阶段，在复位端RST输入高电平，使得第一晶体管T1导通。在第一控制端S1输入低电平，则第三晶体管T3截止。在第二控制端S2输入低电平，则第二晶体管T2截止。在第三控制端RD输入低电平，则第四薄膜晶体管T4截止。在这种情况下，在第一节点n1处的电压被复位至高电压VDD，即，在第一节点n1处的电压Vn1＝VDD。该电 压可被保持在第一电容Cst上。
在步骤2002，复位端被输入低电平，第一控制端被输入高电平，第二控制端被输入高电平，第三控制端被输入低电平。该步骤可被认为是补偿阶段。
在补偿阶段，在复位端RST输入低电平，使得第一晶体管T1变为截止。在第一控制端S1输入高电平，使得第三晶体管T3变为导通。在第二控制端S2输入高电平，使得第二晶体管T2也导通。在第三控制端RD继续输入低电平，第四晶体管T4仍然处于截止状态。在这种情况下，放大晶体管Ta成为二极管连接状态，此时在第一节点n1处的电压Vn1＝Vn3＝VSS+Vth，其中Vn3是在第三节点n3处的电压，Vth是放大晶体管Ta的阈值电压。
在步骤2003，复位端被输入低电平，第一控制端被输入高电平，第二控制端被输入低电平，第三控制端被输入低电平。该步骤可被认为是充电阶段。
在充电阶段，在复位端RST继续输入低电平，第一晶体管T1仍然处于截止。在第一控制端S1继续输入高电平，第三晶体管T3继续处于导通。在第二控制端S2输入低电平，使得第二晶体管T2变成截止。在第三控制端RD继续输入低电平，第四晶体管T4仍然处于截止。在这种情况下，经过第一节点n1的电流通路只有光电二极管PD，则经过第一节点n1的电流的大小与像素电路的光照强度有关。假设经过第一节点n1的电流平均值用I表示，那么在经过时间t后，在第一节点n1处的电压被升高了
Figure PCTCN2015092282-appb-000006
则此时在第一节点n1处的电压为
Figure PCTCN2015092282-appb-000007
在步骤2004，复位端被输入低电平，第一控制端被输入高电平，第二控制端被输入低电平，第三控制端被输入高电平。该步骤可被认为是读出阶段。
在读出阶段，在复位端RST继续输入低电平，第一晶体管T1仍然截止。在第一控制端S1继续输入高电平，第三晶体管T3继续处于导通。在第二控制端S2继续输入低电平，第二晶体管T2仍然截止。在第三控制端 RD输入高电平，使得第四晶体管T4导通。在这种情况下，放大晶体管Ta处于饱和区，则放大晶体管Ta的电流可被计算为
Figure PCTCN2015092282-appb-000008
其中，μn表示载流子迁移率，Cox表示单位面积的栅绝缘层电容值，W/L表示放大晶体管Ta的宽长比。
将
Figure PCTCN2015092282-appb-000009
代入上述公式，可以得出：
Figure PCTCN2015092282-appb-000010
这样，在读出电流Id后，可以分析变量I的大小，从而得到像素电路的光照强度的信息。
采用根据本实施例的像素电路的驱动方法，由于补偿单元能够对放大单元的阈值电压Vth进行补偿，因此，能够避免由于阈值电压Vth的漂移而造成的输出的电压信号的不稳定，从而可以显著地提高图像质量。
以上对本发明的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本发明的精神和范围的情况下对本发明的实施例进行各种修改和变型。本发明的保护范围由所附的权利要求限定。

Claims (15)

  1. 一种像素电路，包括：光电转换单元、放大单元、复位单元、补偿单元、充电单元以及读出单元；
    其中，所述光电转换单元与第一电压端、和所述放大单元连接，用于将光信号转化为电信号；
    所述放大单元与所述光电转换单元、所述充电单元以及所述读出单元连接，用于放大来自所述光电转换单元的输出信号；
    所述复位单元与复位端、所述第一电压端以及所述放大单元连接，用于根据所述复位端的输入信号和所述第一电压端的输入信号，对所述放大单元进行复位；
    所述充电单元与第一控制端、第二电压端和所述放大单元连接，用于根据所述第一控制端的输入信号和所述第二电压端的输入信号，控制在所述放大单元的一端处的电压；
    所述补偿单元与第二控制端、所述复位单元以及所述放大单元连接，用于根据所述第二控制端的输入信号，控制在所述放大单元的另一端处的电压；
    所述读出单元与第三控制端和所述放大单元连接，用于根据所述第三控制端的输入信号，控制输出信号。
  2. 根据权利要求1所述的像素电路，其中，所述光电转换单元包括光电二极管，所述光电二极管连接在所述放大单元和所述第一电压端之间。
  3. 根据权利要求1或2所述的像素电路，其中，所述放大单元包括放大晶体管，所述放大晶体管的栅极与所述光电转换单元连接，所述放大晶体管的第一极与所述充电单元连接，所述放大晶体管的第二极与所述读出单元连接。
  4. 根据权利要求1至3任意一项所述的像素电路，其中，所述复位单元包括第一晶体管，所述第一晶体管的栅极与所述复位端连接，所述第一晶体管的第一极与所述放大单元连接，所述第一晶体管的第二极与所述第一电压端连接。
  5. 根据权利要求1至4任意一项所述的像素电路，其中，所述充电单元包括第三晶体管，所述第三晶体管的栅极与所述第一控制端连接，所述第三晶体管的第一极与所述第二电压端连接，所述第三晶体管的第二极与所述放大单元连接。
  6. 根据权利要求1至5任意一项所述的像素电路，其中，所述补偿单元包括第二晶体管，所述第二晶体管的栅极与所述第二控制端连接，所述第二晶体管的第一极与所述复位单元连接，所述第二晶体管的第二极与所述放大单元连接。
  7. 根据权利要求1至6任意一项所述的像素电路，其中，所述读出单元包括第四晶体管，所述第四晶体管的栅极与所述第三控制端连接，所述第四晶体管的第一极与所述放大单元连接，所述第四晶体管的第二极输出所述输出信号。
  8. 根据权利要求1至7任意一项所述的像素电路，还包括：第一电容，其中，所述第一电容连接于所述第二电压端与所述放大单元的输入之间。
  9. 根据权利要求1至7任意一项所述的像素电路，还包括：第一电容，其中，所述第一电容连接于所述第一电压端与所述放大单元的输入之间。
  10. 根据权利要求1至7任意一项所述的像素电路，还包括：第一电容和第二电容，其中，所述第一电容连接于所述第二电压端与所述放大单元的输入之间，所述第二电容连接于所述第一电压端与所述放大单元的输入之间。
  11. 根据权利要求2至7任意一项所述的像素电路，其中，所述晶体管是P型晶体管。
  12. 根据权利要求2至7任意一项所述的像素电路，其中，所述晶体管是N型晶体管。
  13. 一种探测器，包括：权利要求1-12任一所述的像素电路。
  14. 一种像素电路的驱动方法，其中，所述像素电路包括权利要求11所述的像素电路，第一电压端被提供低电平的输入信号，第二电压端被提供高电平的输入信号，所述驱动方法包括：
    在所述复位端输入低电平，在所述第一控制端输入高电平，在所述第二控制端输入高电平，在所述第三控制端输入高电平；
    在所述复位端输入高电平，在所述第一控制端输入低电平，在所述第二控制端输入低电平，在所述第三控制端输入高电平；
    在所述复位端输入高电平，在所述第一控制端输入低电平，在所述第二控制端输入高电平，在所述第三控制端输入高电平；以及
    在所述复位端输入高电平，在所述第一控制端输入低电平，在所述第二控制端输入高电平，在所述第三控制端输入低电平。
  15. 一种像素电路的驱动方法，其中，所述像素电路包括权利要求12所述的像素电路，第一电压端被提供高电平的输入信号，第二电压端被提供低电平的输入信号，所述驱动方法包括：
    在所述复位端输入高电平，在所述第一控制端输入低电平，在所述第二控制端输入低电平，在所述第三控制端输入低电平；
    在所述复位端输入低电平，在所述第一控制端输入高电平，在所述第二控制端输入高电平，在所述第三控制端输入低电平；
    在所述复位端输入低电平，在所述第一控制端输入高电平，在所述第二控制端输入低电平，在所述第三控制端输入低电平；以及
    在所述复位端输入低电平，在所述第一控制端输入高电平，在所述第二控制端输入低电平，在所述第三控制端输入高电平。
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