WO2018000481A1 - 阵列基板及其制造方法、液晶显示面板 - Google Patents

阵列基板及其制造方法、液晶显示面板 Download PDF

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Publication number
WO2018000481A1
WO2018000481A1 PCT/CN2016/090609 CN2016090609W WO2018000481A1 WO 2018000481 A1 WO2018000481 A1 WO 2018000481A1 CN 2016090609 W CN2016090609 W CN 2016090609W WO 2018000481 A1 WO2018000481 A1 WO 2018000481A1
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Prior art keywords
layer
insulating layer
forming
common electrode
transparent electrode
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Ceased
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PCT/CN2016/090609
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English (en)
French (fr)
Inventor
林碧芬
甘启明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/125,193 priority Critical patent/US10139690B2/en
Publication of WO2018000481A1 publication Critical patent/WO2018000481A1/zh
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    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a liquid crystal display panel.
  • LTPS-LCD LowTemperature Poly-Silicon Liquid Crystal Display
  • the liquid crystal display panel generally includes an array substrate and a color filter substrate, and the array substrate and the color filter substrate pair form a liquid crystal panel.
  • the gate substrate is provided with a gate line, that is, a scan line, a data line, and a common line.
  • the gate line layer and the common electrode layer are laid by the same metal layer, and the gate line layer and the common electrode layer are formed by etching or the like. However, since the distance between the two is relatively close, the short circuit forming line defect is easily caused.
  • An object of the present invention is to provide an array substrate and a method of manufacturing the same, which can effectively improve the abnormality of the open circuit of the gate line layer and the common electrode layer, and improve the stability of the liquid crystal display panel.
  • Another object of the present invention is to provide a liquid crystal display panel using the above array substrate.
  • the present invention provides an array substrate comprising: a substrate, a common electrode layer, an isolation layer, a gate layer, a first insulating layer, a data line layer, a second insulating layer, a first transparent electrode, and a third insulating layer which are sequentially stacked.
  • the isolation layer is provided with a first via hole
  • the first insulating layer is provided with a second via hole
  • the second insulating layer is provided with a third via hole and the second via hole a fourth via that communicates with the via
  • the first transparent electrode being connected to the public via the first via, the second via, and the fourth via a common electrode layer
  • the third insulating layer is provided with a fifth via hole communicating with the third via hole
  • the second transparent electrode passes through the fifth via hole and the third via hole and the data Line layer connection.
  • the isolation layer includes a buffer layer, a polysilicon layer, and a gate insulating layer which are sequentially stacked, and the buffer layer covers the common electrode layer.
  • the first insulating layer is further provided with a sixth via hole
  • the gate insulating layer is provided with a seventh via hole communicating with the sixth via hole
  • the data line layer passes through the sixth A via and the seventh via are connected to the polysilicon layer.
  • the buffer layer comprises a composite material of SiNx or SiO2 or both.
  • the gate layer comprises a conductive block
  • the conductive block is connected to the common electrode layer via the first via, the first transparent electrode passing through the second via and the fourth via Connected to the conductive block.
  • the present invention provides a liquid crystal display panel, comprising: a substrate, a common electrode layer, an isolation layer, a gate layer, a first insulating layer, a data line layer, a second insulating layer, a first transparent electrode, and a first layer.
  • the isolation layer is provided with a first via hole
  • the first insulating layer is provided with a second via hole
  • the second insulating layer is provided with a third via hole and a a fourth via that communicates with the second via, the first transparent via being connected to the common electrode layer via the first via, the second via, and the fourth via
  • the third insulating layer is provided with a fifth via communicating with the third via
  • the second transparent electrode is connected to the data line layer via the fifth via and the third via.
  • the isolation layer includes a buffer layer, a polysilicon layer, and a gate insulating layer which are sequentially stacked, and the buffer layer covers the common electrode layer.
  • the first insulating layer is further provided with a sixth via hole
  • the gate insulating layer is provided with a seventh via hole communicating with the sixth via hole
  • the data line layer passes through the sixth A via and the seventh via are connected to the polysilicon layer.
  • the buffer layer comprises a composite material of SiNx or SiO2 or both.
  • the gate layer comprises a conductive block
  • the conductive block is connected to the common electrode layer via the first via, the first transparent electrode passing through the second via and the fourth via Connected to the conductive block.
  • the present invention provides a method of fabricating an array substrate, comprising: forming a common electrode layer on the substrate; forming an isolation layer covering the common electrode layer on the substrate; forming a first pass on the isolation layer a hole; a gate line layer formed on the isolation layer; a first insulation formed on the gate line layer Forming a data line layer on the first insulating layer; forming a second insulating layer on the data line layer; forming a first long via in communication with the first via hole in the second insulating layer Forming a first transparent electrode on the second insulating layer, the first transparent electrode being connected to the common electrode layer via the first via, the first long via; in the first transparent Forming a third insulating layer on the electrode; forming a second long via connected to the data line layer in the third insulating layer; forming a second transparent electrode on the third insulating layer, the second transparent electrode Connecting to the data line layer via the second long via.
  • the step of forming a gate line layer on the isolation layer includes: forming a conductive block connecting the common electrode layer via the first via hole on the gate layer.
  • the step of forming an isolation layer covering the common electrode layer on the substrate includes: sequentially forming a buffer layer, a polysilicon layer, and a gate insulating layer, wherein the buffer layer covers the common electrode layer on.
  • the step of forming a first insulating layer on the gate line layer includes forming a third long via connected to the polysilicon layer on the first insulating layer.
  • the gate line layer and the common electrode layer are disposed in different conductive layers, and the gate line layer and the common electrode layer are separated by an isolation layer, thereby avoiding a short circuit caused by the distance between the two Forming line defects is abnormal, which improves the stability of the array substrate and the liquid crystal display panel.
  • the present invention also provides a method of manufacturing the above array substrate.
  • FIG. 1 is a schematic cross-sectional view of an array substrate of the present invention.
  • FIG. 2 is a schematic view showing the structure of a capacitor having the array substrate of FIG. 1.
  • the present invention provides an array substrate 100 including: a substrate 110 , a common electrode layer 120 , an isolation layer 130 , a gate line layer (not numbered), a first insulating layer 150 , and a data line layer (not shown).
  • the common electrode layer 120 is disposed above the substrate 110; the isolation layer 130 is disposed on the Above the substrate 110 and covering the common electrode layer 120, the isolation layer 130 is provided with a first via 131; the gate line layer is disposed above the isolation layer 130, and the gate line layer comprises a plurality of a gate line 140 is disposed at intervals; a first insulating layer 150 is disposed over the gate line layer, a second via 152 is disposed on the first insulating layer 150; and a data line layer is disposed on the first insulating layer Above the 150, the data line layer includes a plurality of spaced-apart data lines 160; the second insulating layer 170 covers the data line layer, and the second insulating layer 170 is provided with a third via 173 and a fourth via 174 communicating with the second via 152; disposed above the second insulating layer 170 a first
  • the gate line layer and the common electrode layer are disposed in different conductive layers, and the gate line layer and the common electrode layer are separated by an isolation layer, thereby avoiding a short circuit caused by the distance between the two Forming a line defect is abnormal, which improves the stability of the liquid crystal display panel.
  • the isolation layer 130 includes a buffer layer 132 and a polysilicon layer 133 which are sequentially stacked. And a gate insulating layer 134 overlying the common electrode layer 120, the polysilicon layer 133 being covered between the buffer layer 132 and the gate insulating layer 134.
  • the first insulating layer 150 is further provided with a sixth via 156
  • the gate insulating layer is provided with a seventh via 137 communicating with the sixth via 156, the data line
  • the layer 160 is connected to the polysilicon layer 133 via the sixth via 156 and the seventh via 137. It can be understood that the sixth via 156 and the seventh via 137 can be simultaneously obtained in one etching (ie, the third long via below). Similarly, the fifth via 195 and the third via 173 can also be obtained at one time (ie, the second long via below).
  • a first storage capacitor Cs1 is formed between the first transparent electrode 180 and the second transparent electrode 182 in the present invention.
  • a second storage capacitor Cs2 is formed between the polysilicon layer 133 and the common electrode layer 120.
  • the polysilicon layer 133 constitutes one substrate of the second storage capacitor Cs2, the buffer layer 132 constitutes an insulating layer of the storage capacitor Cs2, and the common electrode layer 120 constitutes another substrate. Equivalent to an equivalent storage capacitor in parallel with the original base (first storage capacitor Cs1). The capacitance value of the storage capacitor is increased without changing the pixel aperture ratio.
  • the material of the third insulating layer 190 and the buffer layer 132 is SiNx, SiO2 or a composite material of any combination between the two.
  • the gate layer further includes a conductive block 141.
  • the conductive block 141 is a metal conductive block.
  • the conductive block 141 is connected to the common electrode layer 120 via the first via 131, and the first transparent electrode 180 passes through the second via 152 and the fourth via 174 and the conductive block 141 connection. It can be understood that the second via 152 and the fourth via 174 can be simultaneously formed in one etching.
  • the purpose of connecting the first transparent electrode 180 to the common electrode layer 120 through the first metal block 141 is to avoid a via hole composed of the second via hole 152 and the fourth via hole 174 (ie, The first long via in the text is too deep, causing a fault when the first transparent electrode 180 is connected to the common electrode layer 120.
  • the common electrode layer 120 may be a molybdenum aluminum alloy, a chrome metal, a molybdenum metal or other materials having both a light shielding function and an electrical conductivity.
  • the separator has a thickness of 0.2 mm to 0.35 mm.
  • the present invention also provides a liquid crystal using the above array substrate 100. Display panel.
  • the present invention also provides a method of manufacturing the above array substrate. It mainly includes the following steps:
  • the substrate is a glass substrate
  • the common electrode layer is formed on the substrate by a film forming, photolithography, and etching process.
  • the buffer layer and the polysilicon layer are sequentially formed on the common electrode layer by using a film forming process, and the buffer layer includes a composite material of SiNx or SiO2 or both, and the order of the buffer layer thickness and the polysilicon layer is not limited thereto. Then, an amorphous silicon crystallization process is performed, and then an active layer pattern is formed by photolithography and etching processes, and a gate insulating layer is covered.
  • the first via hole is etched on the gate insulating layer and the underlying buffer layer and the polysilicon layer by a dry etching process.
  • the gate layer is formed by a film forming and photolithography process, and the formed gate layer includes a gate trace and a conductive block, so that the common electrode layer and the conductive block layer are connected through the first via hole, so as to avoid the via hole. Deep, causing a fault when the upper first transparent electrode and the common electrode layer are connected.
  • a third long via connected to the polysilicon layer is formed on the first insulating layer by a film forming and photolithography process.
  • a data line layer is formed on the first insulating layer by a film forming process.
  • the first long via passes through the first insulating layer and the second insulating layer.
  • a third insulating layer is formed by a film forming and photolithography process, and a second long via is etched on the third insulating layer, and the second long via passes through the three insulating layers and the A second insulating layer is described and connected to the data line layer.

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Abstract

一种阵列基板（100）及其制造方法，该阵列基板（100）包括：依次层叠设置的基板（110）、公共电极层（120）、隔离层（130）、栅极线层、第一绝缘层（150）、数据线层、第二绝缘层（170）、第一透明电极（180）、第三绝缘层（190）和第二透明电极（182），第一透明电极（180）连接至公共电极层（120），第二透明电极（182）与数据线层连接。由于将栅极线层和公共电极层（120）设置在不同的导电层中，避免了由于两者距离过近造成的短路形成线类不良异常，提升了液晶显示面板的稳定性。

Description

阵列基板及其制造方法、液晶显示面板
本发明要求2016年6月29日递交的发明名称为“阵列基板及其制造方法、液晶显示面板”的申请号201610493244.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，具体而言涉及一种阵列基板及其制造方法、液晶显示面板。
背景技术
LTPS-LCD(LowTemperature Poly-Silicon Liquid Crystal Display，低温多晶硅液晶显示面板)具有高分辨率、反应速度快、高亮度、高开口率等优点，因此在当前的平板显示器市场占据了主导地位。
液晶显示面板通常包括阵列基板和彩膜基板，阵列基板和彩膜基板对盒形成液晶面板(Panel)。其中，一般情况下，阵列基板上设置有栅极线层(Gate line)即扫描线、数据线层(Data line)以及公共电极层(Common line)。栅极线层和公共电极层采用同一层金属层铺设，通过刻蚀等加工工艺形成栅极线层和公共电极层，但是由于两者距离较近，极易造成短路形成线类不良异常。
发明内容
本发明的目的在于提供阵列基板及其制造方法，能够有效改善栅极线层和公共电极层的断路异常，提升液晶显示面板的稳定性。
本发明的另一目的在于提供采用上述阵列基板的液晶显示面板。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明提供一种阵列基板，包括：依次层叠设置的基板、公共电极层、隔离层、栅极层、第一绝缘层、数据线层、第二绝缘层、第一透明电极、第三绝缘层和第二透明电极，所述隔离层上设有第一过孔，所述第一绝缘层上设有第二过孔，所述第二绝缘层设有第三过孔和与所述第二过孔连通的第四过孔，所述第一透明电极经所述第一过孔、所述第二过孔和所述第四过孔连接至所述公 共电极层，所述第三绝缘层设有与所述第三过孔连通的第五过孔，所述第二透明电极经所述第五过孔和所述第三过孔与所述数据线层连接。
其中，所述隔离层包括依次层叠设置的缓冲层、多晶硅层和栅极绝缘层，所述缓冲层覆盖在所述公共电极层上。
其中，所述第一绝缘层上还设有第六过孔，所述栅极绝缘层上设有与所述第六过孔连通的第七过孔，所述数据线层经所述第六过孔和所述第七过孔连接至所述多晶硅层。
其中，所述缓冲层包括SiNx或SiO2或者两者的复合材料。
其中，所述栅极层包括导电块，所述导电块经所述第一过孔与所述公共电极层连接，所述第一透明电极经所述第二过孔和所述第四过孔与所述导电块连接。
本发明提供一种液晶显示面板，其中，包括：依次层叠设置的基板、公共电极层、隔离层、栅极层、第一绝缘层、数据线层、第二绝缘层、第一透明电极、第三绝缘层和第二透明电极，所述隔离层上设有第一过孔，所述第一绝缘层上设有第二过孔，所述第二绝缘层设有第三过孔和与所述第二过孔连通的第四过孔，所述第一透明电极经所述第一过孔、所述第二过孔和所述第四过孔连接至所述公共电极层，所述第三绝缘层设有与所述第三过孔连通的第五过孔，所述第二透明电极经所述第五过孔和所述第三过孔与所述数据线层连接。
其中，所述隔离层包括依次层叠设置的缓冲层、多晶硅层和栅极绝缘层，所述缓冲层覆盖在所述公共电极层上。
其中，所述第一绝缘层上还设有第六过孔，所述栅极绝缘层上设有与所述第六过孔连通的第七过孔，所述数据线层经所述第六过孔和所述第七过孔连接至所述多晶硅层。
其中，所述缓冲层包括SiNx或SiO2或者两者的复合材料。
其中，所述栅极层包括导电块，所述导电块经所述第一过孔与所述公共电极层连接，所述第一透明电极经所述第二过孔和所述第四过孔与所述导电块连接。
本发明提供一种阵列基板的制造方法，其中，包括：在所述基板上形成公共电极层；在所述基板上形成覆盖所述公共电极层的隔离层；在所述隔离层形成第一过孔；在所述隔离层上形成栅极线层；在所述栅极线层上形成第一绝缘 层；在所述第一绝缘层上形成数据线层；在所述数据线层上形成第二绝缘层；在所述第二绝缘层形成与所述第一过孔连通的第一长过孔；在所述第二绝缘层上形成第一透明电极，所述第一透明电极经所述第一过孔、所述第一长过孔与所述公共电极层连接；在所述第一透明电极上形成第三绝缘层；在所述第三绝缘层形成连通至所述数据线层的第二长过孔；在所述第三绝缘层上形成第二透明电极，所述第二透明电极经所述第二长过孔与所述数据线层连接。
其中，在所述隔离层上形成栅极线层步骤中包括：在栅极层上形成经所述第一过孔连接所述公共电极层的导电块。
其中，所述在所述基板上形成覆盖所述公共电极层的隔离层步骤中，包括：依次形成缓冲层、多晶硅层和栅极绝缘层，其中，所述缓冲层覆盖在所述公共电极层上。
其中，所述在所述栅极线层上形成第一绝缘层步骤中，包括在所述第一绝缘层上形成连通至所述多晶硅层的第三长过孔。
本发明实施例具有如下优点或有益效果：
本发明中将栅极线层和公共电极层设置在不同的导电层中，并通过隔离层隔开所述栅极线层和所述公共电极层，避免了由于两者距离过近造成的短路形成线类不良异常，提升了阵列基板和液晶显示面板的稳定性。本发明还提供一种上述阵列基板的制造方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明阵列基板的剖面结构示意图。
图2是具有图1所述阵列基板的电容结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的用相同的标号表示。
请参与图1，本发明提供一种阵列基板100，包括：基板110、公共电极层120、隔离层130、栅极线层(图未编号)、第一绝缘层150、数据线层(图未编号)、第二绝缘层170、第一透明电极180、第三绝缘层190和第二透明电极182；所述公共电极层120设置于所述基板110上方；所述隔离层130设置于所述基板110上方且覆盖所述公共电极层120，所述隔离层130上设有第一过孔131；所述栅极线层设置于所述隔离层130上方，所述栅极线层包括多条间隔设置的栅极线140；第一绝缘层150覆盖于所述栅极线层上方，所述第一绝缘层150上设有第二过孔152；数据线层设置于所述第一绝缘层150上方，所述数据线层包括多条间隔设置的数据线160；所述第二绝缘层170覆盖在所述数据线层上方，所述第二绝缘层170上设有第三过孔173和与所述第二过孔152连通的第四过孔174；所述第二绝缘层170上方设置有第一透明电极180，所述第一透明电极180经所述第一过孔131、所述第二过孔152和所述第四过孔174与所述公共电极层120连接；第三绝缘层190设置于所述第一透明电极180上方，所述第三绝缘层190设有与所述第三过孔173连通的第五过孔195；第二透明电极182设置于所述第三绝缘层190上方，所述第二透明电极182经所述第三过孔173和所述第五过孔195与所述栅极线层上的栅极线140连接。
本发明中将栅极线层和公共电极层设置在不同的导电层中，并通过隔离层隔开所述栅极线层和所述公共电极层，避免了由于两者距离过近造成的短路形成线类不良异常，提升了液晶显示面板的稳定性。
具体的，所述隔离层130包括依次层叠设置的缓冲层132、多晶硅层133 和栅极绝缘层134，所述缓冲层132覆盖在所述公共电极层120上，所述多晶硅层133覆盖介于所述缓冲层132和所述栅极绝缘层134之间。
进一步具体的，所述第一绝缘层150上还设有第六过孔156，所述栅极绝缘层上设有与所述第六过孔156连通的第七过孔137，所述数据线层160经所述第六过孔156和所述第七过孔137连接至所述多晶硅层133。可以理解的是，所述第六过孔156和所述第七过孔137可以在一次蚀刻中同时得到(即下文中的第三长过孔)。同理，所述第五过孔195和所述第三过孔173也可以一次得到(即下文中的第二长过孔)。
请结合参阅图2，本发明中所述第一透明电极180与所述第二透明电极182之间形成第一存储电容Cs1。所述多晶硅层133与所述公共电极层120之间形成第二存储电容Cs2。所述多晶硅层133构成第二存储电容Cs2的一个基板，所述缓冲层132构成存储电容Cs2的绝缘层，所述公共电极层120构成另一个基板。相当于在原有的基础(第一存储电容Cs1)上并联一个等效存储电容。在不改变像素开口率的情况下，增大了存储电容的电容值。
优选的，所述第三绝缘层190和所述缓冲层132的材料为SiNx、SiO2或者两者之间任意组合的复合材料。
优选的，所述栅极层还包括导电块141。进一步的所述导电块141为金属导电块。所述导电块141经所述第一过孔131与所述公共电极层120连接，所述第一透明电极180经所述第二过孔152和所述第四过孔174与所述导电块141连接。可以理解的是，所述第二过孔152和所述第四过孔174可以在一次蚀刻中同时形成。
通过第一金属块141使得所述第一透明电极180与所述公共电极层120连接的目的在于：避免由于所述第二过孔152和所述第四过孔174组成的过孔(即下文中的第一长过孔)过深，导致所述第一透明电极180与所述公共电极层120连接时出现断层。
进一步的，为达到良好的遮光效果，公共电极层120可采用钼铝合金、铬金属、钼金属或者其它既具有遮光功能又具有导电性能的材料。
优选的，所述隔离层的厚度为0.2mm～0.35mm。
基于上述阵列基板100，本发明还提供一种采用上述阵列基板100的液晶 显示面板。
本发明还提供一种上述阵列基板的制造方法。主要包括如下步骤：
S001：在所述基板上形成公共电极层。
具体的，所述基板为玻璃基板，通过成膜、光刻及刻蚀工艺在所述基板上形成所述公共电极层。
S002：在所述基板上形成覆盖所述公共电极层的隔离层。
具体的，包括利用成膜工艺在所述公共电极层上依次形成缓冲层和多晶硅层，所述缓冲层包括SiNx或SiO2或者两者的复合材料，缓冲层厚度和多晶硅层的顺序不限于此。然后进行非晶硅结晶工艺，然后利用光刻和刻蚀工艺制作有源层图案，并覆盖一层栅极绝缘层。
S003：在所述隔离层形成第一过孔。
具体的，利用干刻工艺在栅绝缘层和下方的缓冲层、多晶硅层上刻蚀所述第一过孔。
S004：在所述隔离层上形成栅极线层。
具体的，利用成膜和光刻工艺制作栅极层，所形成的栅极层包括栅描线和导电块，使公共电极层和导电块层经第一过孔连接，目的是避免过孔过深，造成上方的第一透明电极和公共电极层联通时出现断层。
S004：在所述栅极线层上形成第一绝缘层。
具体的，包括在所述第一绝缘层上利用成膜和光刻工艺形成连通至所述多晶硅层的第三长过孔。
S005：在所述第一绝缘层上形成数据线层。
具体的，利用成膜工艺在所述第一绝缘层上制作数据线层。
S006：在所述数据线层上形成第二绝缘层。
S007：在所述第二绝缘层形成与所述第一过孔连通的第一长过孔。
具体的，所述第一长过孔穿过所述第一绝缘层和所述第二绝缘层。
S008：在所述第二绝缘层上形成第一透明电极，所述第一透明电极经所述第一过孔、所述第一长过孔与所述公共电极层连接。
S009：在所述第一透明电极上形成第三绝缘层。
S010：在所述第三绝缘层形成连通至所述数据线层的第二长过孔。
具体的，利用成膜、光刻工艺制作第三绝缘层，并在所述第三绝缘层上蚀刻处第二长过孔，所述第二长过孔穿过所述一三绝缘层和所述第二绝缘层，并连通至所述数据线层。
S011：在所述第三绝缘层上形成第二透明电极，所述第二透明电极经所述第二长过孔与所述数据线层连接。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (14)

  1. 一种阵列基板，其中，包括：依次层叠设置的基板、公共电极层、隔离层、栅极层、第一绝缘层、数据线层、第二绝缘层、第一透明电极、第三绝缘层和第二透明电极，所述隔离层上设有第一过孔，所述第一绝缘层上设有第二过孔，所述第二绝缘层设有第三过孔和与所述第二过孔连通的第四过孔，所述第一透明电极经所述第一过孔、所述第二过孔和所述第四过孔连接至所述公共电极层，所述第三绝缘层设有与所述第三过孔连通的第五过孔，所述第二透明电极经所述第五过孔和所述第三过孔与所述数据线层连接。
  2. 如权利要求1所述的阵列基板，其中，所述隔离层包括依次层叠设置的缓冲层、多晶硅层和栅极绝缘层，所述缓冲层覆盖在所述公共电极层上。
  3. 如权利要求2所述的阵列基板，其中，所述第一绝缘层上还设有第六过孔，所述栅极绝缘层上设有与所述第六过孔连通的第七过孔，所述数据线层经所述第六过孔和所述第七过孔连接至所述多晶硅层。
  4. 如权利要求2所述的阵列基板，其中，所述缓冲层包括SiNx或SiO2或者两者的复合材料。
  5. 如权利要求1所述的阵列基板，其中，所述栅极层包括导电块，所述导电块经所述第一过孔与所述公共电极层连接，所述第一透明电极经所述第二过孔和所述第四过孔与所述导电块连接。
  6. 一种液晶显示面板，其中，包括阵列基板，所述阵列基板包括：依次层叠设置的基板、公共电极层、隔离层、栅极层、第一绝缘层、数据线层、第二绝缘层、第一透明电极、第三绝缘层和第二透明电极，所述隔离层上设有第一过孔，所述第一绝缘层上设有第二过孔，所述第二绝缘层设有第三过孔和与所述第二过孔连通的第四过孔，所述第一透明电极经所述第一过孔、所述第二过孔和所述第四过孔连接至所述公共电极层，所述第三绝缘层设有与所述第三过 孔连通的第五过孔，所述第二透明电极经所述第五过孔和所述第三过孔与所述数据线层连接。
  7. 如权利要求6所述的液晶显示面板，其中，所述隔离层包括依次层叠设置的缓冲层、多晶硅层和栅极绝缘层，所述缓冲层覆盖在所述公共电极层上。
  8. 如权利要求7所述的液晶显示面板，其中，所述第一绝缘层上还设有第六过孔，所述栅极绝缘层上设有与所述第六过孔连通的第七过孔，所述数据线层经所述第六过孔和所述第七过孔连接至所述多晶硅层。
  9. 如权利要求7所述的液晶显示面板，其中，所述缓冲层包括SiNx或SiO2或者两者的复合材料。
  10. 如权利要求6所述的液晶显示面板，其中，所述栅极层包括导电块，所述导电块经所述第一过孔与所述公共电极层连接，所述第一透明电极经所述第二过孔和所述第四过孔与所述导电块连接。
  11. 一种阵列基板的制造方法，其中，包括：在所述基板上形成公共电极层；在所述基板上形成覆盖所述公共电极层的隔离层；在所述隔离层形成第一过孔；在所述隔离层上形成栅极线层；在所述栅极线层上形成第一绝缘层；在所述第一绝缘层上形成数据线层；在所述数据线层上形成第二绝缘层；在所述第二绝缘层形成与所述第一过孔连通的第一长过孔；在所述第二绝缘层上形成第一透明电极，所述第一透明电极经所述第一过孔、所述第一长过孔与所述公共电极层连接；在所述第一透明电极上形成第三绝缘层；在所述第三绝缘层形成连通至所述数据线层的第二长过孔；在所述第三绝缘层上形成第二透明电极，所述第二透明电极经所述第二长过孔与所述数据线层连接。
  12. 如权利要求11所述的阵列基板的制造方法，其中，在所述隔离层上形成栅极线层步骤中包括：在栅极层上形成经所述第一过孔连接所述公共电极层的导电块。
  13. 如权利要求11所述的阵列基板的制造方法，其中，所述在所述基板上形成覆盖所述公共电极层的隔离层步骤中，包括：依次形成缓冲层、多晶硅层和栅极绝缘层，其中，所述缓冲层覆盖在所述公共电极层上。
  14. 如权利要求13所述的阵列基板的制造方法，其中，所述在所述栅极线层上形成第一绝缘层步骤中，包括在所述第一绝缘层上形成连通至所述多晶硅层的第三长过孔。
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