WO2017219422A1 - 薄膜晶体管及其制造方法、液晶显示面板 - Google Patents

薄膜晶体管及其制造方法、液晶显示面板 Download PDF

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WO2017219422A1
WO2017219422A1 PCT/CN2016/090589 CN2016090589W WO2017219422A1 WO 2017219422 A1 WO2017219422 A1 WO 2017219422A1 CN 2016090589 W CN2016090589 W CN 2016090589W WO 2017219422 A1 WO2017219422 A1 WO 2017219422A1
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pattern
transition
doping
source
drain
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French (fr)
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吕晓文
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a thin film transistor, a method of fabricating the same, and a liquid crystal display panel having the same.
  • amorphous silicon is a material sensitive to light and is susceptible to backlight illumination to affect the electrical stability of the TFT. Sex.
  • the current TFT designs usually Conlanar (co-planar) structure, as shown, TFT 10 is a portion of the active pattern 11 is shown on the gate pattern G 1, are provided in another portion of the source pattern On the S 1 and the drain pattern D 1 , the backlight pattern is blocked by the gate pattern G 1 of the metal material, the source pattern S 1 and the drain pattern D 1 , thereby preventing the amorphous silicon in the active pattern 11 from being illuminated.
  • a hole layer (Hole Current, also referred to as a hole current layer) is formed in the active pattern 11, due to the active pattern 11 and the source pattern S 1 and the drain pattern D 1
  • the side walls are in direct contact to facilitate conduction of hole current, and thus the leakage current (Ioff) of the TFT 10 is large.
  • the source pattern S 1 and the drain pattern D 1 are formed by etching, a metal Under cut phenomenon occurs in the sidewalls of the source pattern S 1 and the drain pattern D 1 adjacent to the active pattern 11 .
  • the undercut angle is formed, resulting in a high contact resistance between the active pattern 11 and the source pattern S 1 and the drain pattern D 1 , which tends to cause insufficient charging of the TFT 10 .
  • the present invention provides a thin film transistor, a method of fabricating the same, and a liquid crystal display panel, which can reduce leakage current of the TFT, reduce contact resistance between the active pattern and the source pattern and the drain pattern, and avoid the problem of insufficient charging of the TFT.
  • a thin film transistor provided by the present invention includes a substrate, a source pattern and a drain pattern spaced apart on the substrate, a first doping pattern and a second doping pattern respectively covering the source pattern and the drain pattern, and respectively An active pattern in which the first doping pattern and the second doping pattern are electrically contacted, wherein between the source pattern and the first doping pattern and between the drain pattern and the second doping pattern respectively a first transition pattern and a second transition pattern are disposed, and the first transition pattern and the second transition pattern respectively cover sidewalls of the source pattern and the drain pattern, thereby isolating sidewalls of the source pattern and the drain pattern Direct contact of the source pattern.
  • first transition pattern and the second transition pattern are metal or metal oxide.
  • the first transition pattern and the second transition pattern have a thickness of 100-500 angstroms.
  • the thin film transistor further includes a gate pattern disposed between the source pattern and the drain pattern and the substrate and corresponding to the active pattern, and the gate insulating layer is used for electrically isolating the gate
  • the pattern is opposite to the source pattern and the drain pattern; or the gate pattern is disposed above the active pattern, and the gate insulating layer is used to electrically isolate the gate pattern from the active pattern.
  • a liquid crystal display panel provided by the present invention includes a thin film transistor including a substrate, a source pattern and a drain pattern spaced apart on the substrate, and a first doping pattern covering the source pattern and the drain pattern, respectively And an active pattern electrically contacting the first doped pattern and the second doped pattern, respectively, wherein the source pattern and the first doped pattern and the drain pattern and the second doping
  • a first transition pattern and a second transition pattern are respectively disposed between the patterns, and the first transition pattern and the second transition pattern respectively cover sidewalls of the source pattern and the drain pattern, thereby isolating the source pattern and the drain pattern Direct contact of the sidewalls with the active pattern.
  • first transition pattern and the second transition pattern are metal or metal oxide.
  • the first transition pattern and the second transition pattern have a thickness of 100-500 angstroms.
  • the thin film transistor further includes a gate pattern disposed between the source pattern and the drain pattern and the substrate and corresponding to the active pattern, and the gate insulating layer is used for electrically isolating the gate
  • the pattern is opposite to the source pattern and the drain pattern; or the gate pattern is disposed above the active pattern, and the gate insulating layer is used to electrically isolate the gate pattern from the active pattern.
  • the invention provides a method for manufacturing a thin film transistor, comprising: providing a substrate; forming a source/drain electrode layer on the substrate and performing a patterning process to form a spaced source and drain patterns; forming sequentially on the substrate The transition layer and the doping layer are patterned to form a first transition pattern and a first doping pattern covering the source pattern and a second transition pattern and a second doping pattern covering the drain pattern, the first transition pattern And a second transition pattern respectively covering the sidewalls of the source pattern and the drain pattern; forming an active layer on the substrate and performing a patterning process to form electrical contact with the first doping pattern and the second doping pattern, respectively Active pattern.
  • the step of sequentially forming a transition layer and a doping layer on the substrate and performing patterning processing includes: patterning the transition layer and the doping layer by using the same mask.
  • the step of patterning the transition layer and the doped layer by using the same mask comprises: sequentially etching the doped layer and the transition layer by using the same mask, or performing the doping layer first by using the same mask. Dry etching, and then the transition layer is wet etched.
  • the step of sequentially forming a transition layer and a doped layer on the substrate and performing a patterning process includes sequentially forming a transition layer having a thickness of 100-500 angstroms and a doping layer having a thickness of 300-500 angstroms on the substrate.
  • a thin film transistor and a method of fabricating the same, and a liquid crystal display panel according to an embodiment of the present invention by providing a transition pattern between a doping pattern and a source pattern and a drain pattern, and the transition pattern respectively covers the source pattern and the drain pattern a sidewall, thereby being capable of isolating the direct contact of the active pattern with the sidewalls of the source pattern and the drain pattern, reducing leakage current of the TFT; in addition, the transition pattern is covered by the doped pattern adjacent to both sides of the active pattern, The contact resistance between the active pattern and the source pattern and the drain pattern is lowered to avoid the problem of insufficient charging of the TFT.
  • FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the prior art
  • FIG. 2 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing the structure of a thin film transistor according to another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of an embodiment of a method for fabricating a thin film transistor of the present invention
  • Fig. 5 is a cross-sectional view showing the structure of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor 20 is a bottom gate structure including a substrate 21 and a gate pattern G 2 and a gate insulating layer 22 disposed on the substrate 21 .
  • the gate pattern G 2 is disposed between the source pattern S 2 and the drain pattern D 2 and the substrate 21 and corresponding to the active pattern 27, specifically corresponding to being located below the active pattern 27; the source pattern S 2 and The drain pattern D 2 is disposed on the substrate 21 , and the gate insulating layer 22 is used for isolating the electrical contact between the gate pattern G 2 and the source pattern S 2 and the drain pattern D 2 ; the first transition pattern 23 is located at the source Between the pattern S 2 and the first doping pattern 25 , the second transition pattern 24 is located between the drain pattern D 2 and the second doping pattern 23 such that the first doping pattern 25 covers the source pattern S 2 . The second doping pattern 26 covers the drain pattern D 2 .
  • the material of the active pattern 27 is a-Si, which is the semiconductor layer of the thin film transistor 20; the material of the first doping pattern 25 and the second doping pattern 26 is doped a-Si, which is the ohmic of the thin film transistor 20. Contact layer.
  • the first transition pattern 23 and the second transition pattern 24 are electrically stable metal or metal oxides, such as Mo (Molybdenum, molybdenum), Ti (Titanium, titanium), ITO (Indium tin oxide, indium tin oxide)
  • the first doping pattern 25 may be in electrical contact with the source pattern S 2 through the first transition pattern 23
  • the second doping pattern 26 may be in electrical contact with the drain pattern D 2 through the second transition pattern 24 .
  • the difference from the prior art thin film transistor 10 shown in FIG. 1 is that in the structure of the thin film transistor 20 of the embodiment of the present invention, between the source pattern S 2 and the first doping pattern 25 and the drain pattern A first transition pattern 23 and a second transition pattern 24 are respectively disposed between the D 2 and the second doping pattern 26, and the first transition pattern 23 covers the sidewall of the source pattern S 2 and the second transition pattern 24 is covered.
  • the sidewalls of the drain pattern D 2 are capable of isolating the direct contact of the active pattern 27 with the sidewalls of the source pattern S 2 and the drain pattern D 2 .
  • first doping pattern 25 and the second doping pattern 26 respectively cover the first transition pattern 23 and the second transition pattern 24, it is possible to suppress the hole current transfer in the active pattern 27 to the source pattern. S 2 and the drain pattern D 2 , thereby reducing the leakage current of the thin film transistor 20.
  • the first transition pattern 23 and the second transition pattern 24 formed by etching form an undercut angle adjacent to the sidewall of the active pattern 11, the first doping pattern 25 and the second doping pattern 26 are also formed. Covering separately, and since the first transition pattern 23 and the second transition pattern 24 are in good contact with the source pattern S 2 and the drain pattern D 2 , respectively, the active pattern 27 and the source pattern S due to the undercut angle can be solved. 2 and the problem that the contact resistance of the drain pattern D 2 is high, thereby preventing the phenomenon that the thin film transistor 20 is insufficiently charged.
  • the embodiment of the present invention may set the thickness of the first transition pattern 23 and the second transition pattern 24 to be thin, for example, 100-500 angstroms, based on the cover protection of the first doping pattern 25 and the second doping pattern 26.
  • the first doping pattern 25 and the second doping pattern 26 have a thickness of 300-500 angstroms.
  • the present embodiment may further set the sum of the thicknesses of the first doping pattern 25 and the first transition pattern 23 and the sum of the thicknesses of the second doping pattern 26 and the second transition pattern 24 to be equal to the existing one shown in FIG.
  • the thickness of the doping pattern 12 is such that the thickness of the thin film transistor 20 of the embodiment of the present invention is not increased, which facilitates a thin-sized design.
  • the thin film transistor 30 is a top gate structure including a substrate 31 and a source pattern S 3 and a drain pattern D 3 and a first transition pattern disposed on the substrate 31. 33 and the second transition pattern 34, pattern 35 and the first doped second doping pattern 36, the active pattern 37, gate insulating layer 32, the gate pattern G 3.
  • the arrangement of each doping pattern and each transition pattern is the same as that of the embodiment shown in FIG. 2, and details are not described herein again.
  • the gate pattern G 3 of the embodiment is correspondingly located above the active pattern 37, and the gate insulating layer 32 is used for electrically isolating the gate pattern G 3 from the active pattern 37; in addition, in order to avoid backlight illumination
  • the active pattern 37 is provided between the substrate 31 and the source/drain electrode layer with a light shielding metal layer M and an insulating layer 38 for isolating the light shielding metal layer M and the source pattern S 2 and the drain pattern. Electrical contact of D 2 .
  • the first transition pattern 33 and the second are respectively disposed between the source pattern S 3 and the first doping pattern 35 and between the drain pattern D 3 and the second doping pattern 36
  • the transition pattern 34, and the first transition pattern 33 covers the sidewall of the source pattern S 3
  • the second transition pattern 34 covers the sidewall of the drain pattern D 3 , so that the active pattern 37 and the source pattern S 3 can be isolated. and a drain electrode in direct contact with the side wall of the pattern D 3.
  • the first doping pattern 35 and the second doping pattern 36 respectively cover the first transition pattern 33 and the second transition pattern 34, it is possible to suppress the hole current in the active pattern 37 from being transmitted to the source pattern. S 3 and the drain pattern D 3 , thereby reducing the leakage current of the thin film transistor 30.
  • FIG. 4 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention. As shown in FIG. 4, the manufacturing method of this embodiment includes:
  • the substrate includes, but is not limited to, a glass substrate.
  • S42 forming a source/drain electrode layer on the substrate and performing a patterning process to form a source pattern and a drain pattern which are disposed at intervals;
  • a source/drain electrode layer may be formed on the substrate by any method such as chemical vapor deposition (CVD) or magnetron sputtering (Sputter).
  • CVD chemical vapor deposition
  • Sputter magnetron sputtering
  • S43 sequentially forming a transition layer and a doping layer on the substrate and performing a patterning process to form a first transition pattern covering the source pattern and the first doping pattern and a second transition pattern and a second doping covering the drain pattern a dummy pattern, the first transition pattern and the second transition pattern respectively covering sidewalls of the source pattern and the drain pattern;
  • a transition layer having a thickness of 100-500 angstroms and a doped layer having a thickness of 300-500 angstroms are sequentially formed on the substrate.
  • the transition layer and the doped layer are patterned by using the same mask.
  • the doping layer and the transition layer may be dry etched sequentially by using the same mask, or the same mask may be used for first doping. The layer is dry etched and the transition layer is wet etched.
  • S44 forming an active layer on the substrate and performing a patterning process to form an active pattern respectively in electrical contact with the first doping pattern and the second doping pattern.
  • the manner in which the above-described patterning process is performed in this embodiment includes, but is not limited to, etching.
  • the present invention also provides a liquid crystal display panel of an embodiment.
  • the liquid crystal display panel 50 includes an array substrate (Array Substrate, also known as a Thin Film Transistor Substrate) 51 and a color filter substrate (Color Filter, CF substrate or color).
  • the array substrate 51 includes the thin film transistor of any of the above embodiments, and thus has the same advantageous effects.

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Abstract

提供了一种薄膜晶体管及其制造方法、液晶显示面板，通过在掺杂图案(25,26)与源极图案(S 2)和漏极图案(D 2)之间设置过渡图案(23,24)，且过渡图案(23,24)分别包覆源极图案(S 2)和漏极图案(D 2)的侧壁，隔离有源图案(27)与源极图案(S 2)和漏极图案(D 2)的侧壁的直接接触，从而能够降低TFT的漏电流；另外，过渡图案(23,24)邻近于有源图案(27)的两侧被掺杂图案(25,26)覆盖，能够降低有源图案(27)与源极图案(S 2)和漏极图案(D 2)的接触阻抗，避免TFT充电不足的问题。

Description

薄膜晶体管及其制造方法、液晶显示面板 【技术领域】
本发明涉及液晶显示技术领域，具体涉及一种薄膜晶体管及其制造方法以及具有该薄膜晶体管的液晶显示面板。
【背景技术】
在采用非晶硅(a-Si)形成有源图案的TFT(Thin Film Transistor，薄膜晶体管)设计中，非晶硅作为一种对光照十分敏感的材料，容易受到背光照射而影响TFT的电学稳定性。为了解决该问题，当前的TFT设计通常采用Conlanar(共平面)结构，如图1所示，TFT 10的有源图案11的一部分设置于栅极图案G1上、另一部分分别设置于源极图案S1和漏极图案D1上，利用金属材质的栅极图案G1、源极图案S1和漏极图案D1遮挡背光，从而避免有源图案11中的非晶硅受到光照。
对于上述结构，在TFT 10通电时，有源图案11中会形成空穴层(Hole Current，又称空穴电流层)，由于有源图案11与源极图案S1和漏极图案D1的侧壁直接接触，便于空穴电流的传导，因此会导致TFT 10的漏电流(Ioff)较大。另外，在蚀刻形成源极图案S1和漏极图案D1时，源极图案S1和漏极图案D1的邻近于有源图案11的侧壁会发生金属Under Cut(倒切)现象，形成倒切角，从而导致有源图案11与源极图案S1和漏极图案D1的接触阻抗较高，容易导致TFT 10充电不足。
【发明内容】
有鉴于此，本发明提供一种薄膜晶体管及其制造方法、液晶显示面板，能够降低TFT的漏电流，降低有源图案与源极图案和漏极图案的接触阻抗，避免TFT充电不足的问题。
本发明提供的一种薄膜晶体管，包括基板、间隔设置于基板上的源极图案和漏极图案、分别覆盖源极图案和漏极图案的第一掺杂图案和第二掺杂图案以及分别与第一掺杂图案和第二掺杂图案电性接触的有源图案，其中在源极图案与第一掺杂图案之间以及漏极图案与第二掺杂图案之间分别 设置有第一过渡图案和第二过渡图案，且第一过渡图案和第二过渡图案分别包覆源极图案和漏极图案的侧壁，进而隔离源极图案和漏极图案的侧壁与有源图案的直接接触。
其中，第一过渡图案和第二过渡图案为金属或金属氧化物。
其中，第一过渡图案和第二过渡图案的厚度为100-500埃。
其中，薄膜晶体管进一步包括栅极图案和栅极绝缘层，栅极图案设置于源极图案和漏极图案与基板之间且对应于有源图案设置，栅极绝缘层用于电性隔离栅极图案与源极图案和漏极图案；或者栅极图案对应设置于有源图案的上方，栅极绝缘层用于电性隔离栅极图案与有源图案。
本发明提供的一种液晶显示面板，包括薄膜晶体管，所述薄膜晶体管包括基板、间隔设置于基板上的源极图案和漏极图案、分别覆盖源极图案和漏极图案的第一掺杂图案和第二掺杂图案以及分别与第一掺杂图案和第二掺杂图案电性接触的有源图案，其中在源极图案与第一掺杂图案之间以及漏极图案与第二掺杂图案之间分别设置有第一过渡图案和第二过渡图案，且第一过渡图案和第二过渡图案分别包覆源极图案和漏极图案的侧壁，进而隔离源极图案和漏极图案的侧壁与有源图案的直接接触。
其中，第一过渡图案和第二过渡图案为金属或金属氧化物。
其中，第一过渡图案和第二过渡图案的厚度为100-500埃。
其中，薄膜晶体管进一步包括栅极图案和栅极绝缘层，栅极图案设置于源极图案和漏极图案与基板之间且对应于有源图案设置，栅极绝缘层用于电性隔离栅极图案与源极图案和漏极图案；或者栅极图案对应设置于有源图案的上方，栅极绝缘层用于电性隔离栅极图案与有源图案。
本发明提供的一种薄膜晶体管的制造方法，包括：提供一基板；在基板上形成源漏电极层并进行图案化处理，以形成间隔设置的源极图案和漏极图案；在基板上依次形成过渡层和掺杂层并进行图案化处理，以形成覆盖源极图案的第一过渡图案和第一掺杂图案以及覆盖漏极图案的第二过渡图案和第二掺杂图案，第一过渡图案和第二过渡图案分别包覆源极图案和漏极图案的侧壁；在基板上形成有源层并进行图案化处理，以形成分别与第一掺杂图案和第二掺杂图案电性接触的有源图案。
其中，所述在基板上依次形成过渡层和掺杂层并进行图案化处理的步 骤包括：利用同一光罩对过渡层和掺杂层进行图案化处理。
其中，所述利用同一光罩对过渡层和掺杂层进行图案化处理的步骤包括：利用同一光罩依次对掺杂层和过渡层进行干蚀刻，或者利用同一光罩先对掺杂层进行干蚀刻，再对过渡层进行湿蚀刻。
其中，所述在基板上依次形成过渡层和掺杂层并进行图案化处理的步骤包括：在基板上依次形成厚度为100-500埃的过渡层和厚度为300-500埃的掺杂层。
本发明实施例的薄膜晶体管及其制造方法、液晶显示面板，通过在掺杂图案与源极图案和漏极图案之间设置过渡图案，且该过渡图案分别包覆源极图案和漏极图案的侧壁，从而能够隔离有源图案与源极图案和漏极图案的侧壁的直接接触，降低TFT的漏电流；另外，该过渡图案邻近于有源图案的两侧被掺杂图案覆盖，能够降低有源图案与源极图案和漏极图案的接触阻抗，避免TFT充电不足的问题。
【附图说明】
图1是现有技术一实施例的薄膜晶体管的结构剖视图；
图2是本发明一实施例的薄膜晶体管的结构剖视图；
图3是本发明另一实施例的薄膜晶体管的结构剖视图；
图4是本发明的薄膜晶体管的制造方法一实施例的流程示意图；
图5是本发明一实施例的液晶显示面板的结构剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
如图2所示，本发明一实施例的薄膜晶体管的结构剖视图，所述薄膜晶体管20为底栅结构，包括基板21以及设置于基板21上的栅极图案G2和栅极绝缘层22、源极图案S2和漏极图案D2、第一过渡图案23和第二过渡图案24、第一掺杂图案25和第二掺杂图案26、有源图案27。其中，栅极图案G2设置于源极图案S2和漏极图案D2与基板21之间且对应于有源图案27设置，具体对应位于有源图案27的下方；源极图案S2和漏极图案D2 间隔设置于基板21上，栅极绝缘层22用于隔离栅极图案G2与源极图案S2和漏极图案D2的电性接触；第一过渡图案23位于源极图案S2与第一掺杂图案25之间，第二过渡图案24位于漏极图案D2与第二掺杂图案之间23之间，从而使得第一掺杂图案25覆盖源极图案S2、第二掺杂图案26覆盖漏极图案D2。
其中，有源图案27的材质为a-Si，作为薄膜晶体管20的半导体层；第一掺杂图案25和第二掺杂图案26的材质为掺杂的a-Si，作为薄膜晶体管20的欧姆接触层。基于此，当第一过渡图案23和第二过渡图案24为电学性能稳定的金属或金属氧化物，例如Mo(Molybdenum，钼)、Ti(Titanium，钛)、ITO(Indium tin oxide，氧化铟锡)时，第一掺杂图案25可通过第一过渡图案23与源极图案S2电性接触，第二掺杂图案26可通过第二过渡图案24与漏极图案D2电性接触。
与图1所示现有技术的薄膜晶体管10的不同之处在于，在本发明实施例的薄膜晶体管20的结构中，在源极图案S2与第一掺杂图案25之间以及漏极图案D2与第二掺杂图案26之间分别设置有第一过渡图案23和第二过渡图案24，并且第一过渡图案23包覆源极图案S2的侧壁、第二过渡图案24包覆漏极图案D2的侧壁，从而能够隔离有源图案27与源极图案S2和漏极图案D2的侧壁的直接接触。进一步地，由于第一掺杂图案25和第二掺杂图案26分别覆盖于第一过渡图案23和第二过渡图案24上，因此能够抑制有源图案27中的空穴电流传递至源极图案S2和漏极图案D2，从而降低薄膜晶体管20的漏电流。
另外，即使刻蚀形成的第一过渡图案23和第二过渡图案24会在邻近于有源图案11的侧壁形成倒切角，也会被第一掺杂图案25和第二掺杂图案26分别覆盖，并且由于第一过渡图案23和第二过渡图案24分别与源极图案S2和漏极图案D2接触良好，因此能够解决因倒切角导致的有源图案27与源极图案S2和漏极图案D2的接触阻抗较高的问题，进而避免薄膜晶体管20充电不足的现象发生。
基于前述第一掺杂图案25和第二掺杂图案26的覆盖保护，本发明实施例可以设置第一过渡图案23和第二过渡图案24的厚度较薄，例如为100-500埃
Figure PCTCN2016090589-appb-000001
第一掺杂图案25和第二掺杂图案26的厚度为300-500埃。 进一步地，本实施还可以设置第一掺杂图案25与第一过渡图案23的厚度之和以及第二掺杂图案26与第二过渡图案24的厚度之和均等于图1所示现有的掺杂图案12的厚度，使得本发明实施例的薄膜晶体管20的厚度不会增加，利于薄尺寸设计。
图3是本发明另一实施例的薄膜晶体管的结构剖视图，薄膜晶体管30为顶栅结构，包括基板31以及设置于基板31上的源极图案S3和漏极图案D3、第一过渡图案33和第二过渡图案34、第一掺杂图案35和第二掺杂图案36、有源图案37、栅极绝缘层32、栅极图案G3。其中，各个掺杂图案和各个过渡图案的设置与图2所示实施例相同，此处不再赘述。不同的是，本实施例的栅极图案G3对应位于有源图案37的上方，栅极绝缘层32用于电性隔离栅极图案G3与有源图案37；另外，为了避免背光照射到有源图案37，本实施例在基板31和源漏电极层之间设置有遮光金属层M以及绝缘层38，该绝缘层38用于隔离遮光金属层M与源极图案S2和漏极图案D2的电性接触。
在本实施例的结构设计中，在源极图案S3与第一掺杂图案35之间以及漏极图案D3与第二掺杂图案36之间分别设置有第一过渡图案33和第二过渡图案34，并且第一过渡图案33包覆源极图案S3的侧壁、第二过渡图案34包覆漏极图案D3的侧壁，从而能够隔离有源图案37与源极图案S3和漏极图案D3的侧壁的直接接触。进一步地，由于第一掺杂图案35和第二掺杂图案36分别覆盖于第一过渡图案33和第二过渡图案34上，因此能够抑制有源图案37中的空穴电流传递至源极图案S3和漏极图案D3，从而降低薄膜晶体管30的漏电流。
图4是本发明一实施例的薄膜晶体管的制造方法的流程示意图。如图4所示，本实施例的制造方法包括：
S41：提供一基板；
所述基板包括但不限于玻璃基板。
S42：在基板上形成源漏电极层并进行图案化处理，以形成间隔设置的源极图案和漏极图案；
本实施例可以采用化学气相沉积(Chemical vapor deposition，CVD)、磁控溅射(Sputter)等任意方式在基板上形成源漏电极层。
S43：在基板上依次形成过渡层和掺杂层并进行图案化处理，以形成覆盖源极图案的第一过渡图案和第一掺杂图案以及覆盖漏极图案的第二过渡图案和第二掺杂图案，第一过渡图案和第二过渡图案分别包覆源极图案和漏极图案的侧壁；
可选地，在基板上依次形成厚度为100-500埃的过渡层和厚度为300-500埃的掺杂层。进一步可选地，利用同一光罩对过渡层和掺杂层进行图案化处理，具体地，可以利用同一光罩依次对掺杂层和过渡层进行干蚀刻，或者利用同一光罩先对掺杂层进行干蚀刻，再对过渡层进行湿蚀刻。
S44：在基板上形成有源层并进行图案化处理，以形成分别与第一掺杂图案和第二掺杂图案电性接触的有源图案。
本实施例进行上述图案化处理的方式包括但不限于刻蚀。
本发明还提供一实施例的液晶显示面板。如图5所示，所述液晶显示面板50包括相对间隔设置的阵列基板(Array Substrate，又称Thin Film Transistor Substrate，TFT基板或薄膜晶体管基板)51和彩膜基板(Color Filter，CF基板或彩色滤光片基板)52，以及夹持于两者之间的液晶(液晶分子)53，其中，液晶53位于阵列基板51和彩膜基板52叠加组合成的液晶盒内。所述阵列基板51包括上述任一实施例的薄膜晶体管，因此具有与其相同的有益效果。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括基板、间隔设置于所述基板上的源极图案和漏极图案、分别覆盖所述源极图案和所述漏极图案的第一掺杂图案和第二掺杂图案以及分别与所述第一掺杂图案和所述第二掺杂图案电性接触的有源图案，其中在所述源极图案与所述第一掺杂图案之间以及所述漏极图案与所述第二掺杂图案之间分别设置有第一过渡图案和第二过渡图案，所述第一过渡图案和所述第二过渡图案分别包覆所述源极图案和漏极图案的侧壁，进而隔离所述有源图案与所述源极图案和漏极图案的侧壁的直接接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一过渡图案和所述第二过渡图案为金属或金属氧化物。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一过渡图案和所述第二过渡图案的厚度为100-500埃。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管进一步包括栅极图案和栅极绝缘层，其中所述栅极图案设置于所述源极图案和漏极图案与所述基板之间且对应于所述有源图案设置，所述栅极绝缘层用于电性隔离所述栅极图案与所述源极图案和漏极图案；或者所述栅极图案对应设置于所述有源图案的上方，所述栅极绝缘层用于电性隔离所述栅极图案与所述有源图案。
  5. 一种液晶显示面板，其中，所述液晶显示面板包括薄膜晶体管，所述薄膜晶体管包括基板、间隔设置于所述基板上的源极图案和漏极图案、分别覆盖所述源极图案和所述漏极图案的第一掺杂图案和第二掺杂图案以及分别与所述第一掺杂图案和所述第二掺杂图案电性接触的有源图案，其中在所述源极图案与所述第一掺杂图案之间以及所述漏极图案与所述第二掺杂图案之间分别设置有第一过渡图案和第二过渡图案，所述第一过渡图案和所述第二过渡图案分别包覆所述源极图案和漏极图案的侧壁，进而隔离所述有源图案与所述源极图案和漏极图案的侧壁的直接接触。
  6. 根据权利要求5所述的液晶显示面板，其中，所述第一过渡图案和所述第二过渡图案为金属或金属氧化物。
  7. 根据权利要求5所述的液晶显示面板，其中，所述第一过渡图案和所述第二过渡图案的厚度为100-500埃。
  8. 根据权利要求5所述的液晶显示面板，其中，所述薄膜晶体管进一步包括栅极图案和栅极绝缘层，其中所述栅极图案设置于所述源极图案和漏极图案与所述基板之间且对应于所述有源图案设置，所述栅极绝缘层用于电性隔离所述栅极图案与所述源极图案和漏极图案；或者所述栅极图案对应设置于所述有源图案的上方，所述栅极绝缘层用于电性隔离所述栅极图案与所述有源图案。
  9. 一种薄膜晶体管的制造方法，其中，所述制造方法包括：
    提供一基板；
    在所述基板上形成源漏电极层并进行图案化处理，以形成间隔设置的源极图案和漏极图案；
    在所述基板上依次形成过渡层和掺杂层并进行图案化处理，以形成覆盖所述源极图案的第一过渡图案和第一掺杂图案以及覆盖所述漏极图案的第二过渡图案和第二掺杂图案，且所述第一过渡图案和所述第二过渡图案分别包覆所述源极图案和漏极图案的侧壁；
    在所述基板上形成有源层并进行图案化处理，以形成分别与所述第一掺杂图案和所述第二掺杂图案电性接触的有源图案。
  10. 根据权利要求9所述的制造方法，其中，所述在所述基板上依次形成过渡层和掺杂层并进行图案化处理的步骤包括：
    利用同一光罩对所述过渡层和掺杂层进行图案化处理。
  11. 根据权利要求10所述的制造方法，其中，所述利用同一光罩对所述过渡层和掺杂层进行图案化处理的步骤包括：
    利用同一光罩依次对所述掺杂层和过渡层进行干蚀刻，或者利用所述同一光罩先对所述掺杂层进行干蚀刻，再对所述过渡层进行湿蚀刻。
  12. 根据权利要求10所述的制造方法，其中，所述在所述基板上依次形成过渡层和掺杂层并进行图案化处理的步骤包括：
    在所述基板上依次形成厚度为100-500埃的所述过渡层和厚度为300-500埃的掺杂层。
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