WO2017214955A1 - 流水线模数转换器的误差补偿校正装置 - Google Patents

流水线模数转换器的误差补偿校正装置 Download PDF

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WO2017214955A1
WO2017214955A1 PCT/CN2016/086097 CN2016086097W WO2017214955A1 WO 2017214955 A1 WO2017214955 A1 WO 2017214955A1 CN 2016086097 W CN2016086097 W CN 2016086097W WO 2017214955 A1 WO2017214955 A1 WO 2017214955A1
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comparator
output signal
correction
level
signal
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PCT/CN2016/086097
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English (en)
French (fr)
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蒲杰
胡刚毅
付东兵
陈玺
黄兴发
王育新
陈光炳
李儒章
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中国电子科技集团公司第二十四研究所
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Priority to US16/475,120 priority Critical patent/US10735014B2/en
Publication of WO2017214955A1 publication Critical patent/WO2017214955A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1071—Measuring or testing
    • H03M1/1076—Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages

Definitions

  • the invention belongs to the field of integrated circuits, and in particular relates to an error compensation correction device for a pipeline analog-to-digital converter.
  • the circuit structure of A/D (Analog/Digital) analog-to-digital converter mainly includes successive comparison structure, integral structure, full-parallel (flash) structure, hierarchical structure, pipeline structure and ⁇ - ⁇ oversampling structure.
  • the main circuit structure involved in the high-speed high-precision A/D converter circuit is a pipeline structure.
  • the pipeline-to-Digital Converter (ADC) is cascaded by the same pipeline stages operating under two-phase non-overlapping clocks. Except for the last stage, each pipeline stage is based on an operational amplifier.
  • OPAMP and switched capacitor circuit composed of MDAC (Multiplying Digital to Analog Converter) and comparator-based sub-ADC, and the flow level has various non-ideal characteristics and mismatch errors, which lead to the transmission curve.
  • the error compensation correction method of the pipeline analog-to-digital converter usually needs to interrupt the normal operation of the ADC and input the known test signal to obtain the correction information. Even so, the error information extracted during the test and the error information of the actual work may have a certain deviation. At the same time, it is impossible to track the non-ideal characteristics of the device and the mismatch error factors with time and external environment (such as temperature changes, component aging, voltage changes, etc.); at the same time, it is impossible to avoid the test process interrupting the normal operation of the ADC, and the error measurement results are deviated. , different from the normal working state of the ADC.
  • the invention provides an error compensation correction device for a pipeline analog-to-digital converter to solve the problem that the pipeline analog-to-digital converter needs to be interrupted and the correction accuracy is low when the error compensation correction of the pipeline analog-to-digital converter is performed.
  • an error compensation correcting apparatus for a pipelined analog-to-digital converter, comprising: a corrected flow level and a normal flow level, and corresponding to each of the corrected flow levels An error estimation circuit, a level edge detection circuit, a random level generation circuit, and a MUX circuit, wherein the level edge detection circuit is configured to detect whether the output signal of the comparator in the correction flow level is stably outputted within a preset time;
  • the MUX circuit is configured to select, as a result of the detecting, an output signal of the comparator or an output signal of the random level generating circuit as an actual output signal of the comparator;
  • the error estimating circuit is configured to: according to the actual output signal, the encoded signal of the subsequent stage water level when the output signal of the comparator is not stably outputted within a preset time
  • the correction signal value is used to estimate the correction value of the correction flow level.
  • the error estimating circuit is configured to: for each comparator in the corrected pipeline stage that the output signal is not stably outputted within a preset time, according to the actual output signal of the comparator, The coded signal of the stage flow level and the correction value signal determine the error amount of the current comparator; the correction value corresponding to the output signal of the comparator is calculated according to the determined error amount; and the calibration flow level is counted in the calibration After the correction values corresponding to the output signals of the respective comparators, the correction values of the correction flow level are determined according to the correction values corresponding to the output signals of the respective comparators in the correction flow level.
  • the error estimation circuit is configured to determine an error amount of the comparator according to the following formula:
  • err(i,mux i ) on the left side of the equation indicates the error amount determined by the i-th comparator at the time when the actual output signal of the i-th comparator in the nth correction stream is mux i ;
  • the right side of the equation Err(i,mux i ) represents the error amount determined by the i-th comparator when the actual output signal of the i-th comparator in the nth correction stream is mux i ;
  • a n+1 to a L indicates n coded signals of the subsequent stage water level after the correction of the water level;
  • b n+1 to b L represent weight values corresponding to the coded signals of the respective subsequent stage water levels;
  • cal n+1 to cal N represent the stage flow level Correction values for each calibration flow level.
  • the error estimation circuit is configured to calculate a correction value of the comparator according to the following formula:
  • Calc(i) avg(err(i,0))-avg(err(i,1)), where calc(i) represents the nth corrected flow
  • the correction value corresponding to the output signal of the i-th comparator in the stage, avg(err(i, 0)) indicates that the actual output signal of the i-th comparator in the n-th corrected pipeline stage is 0, the determined each
  • the average of the error amounts of the i comparators; avg(err(i,1)) indicates the ith comparator determined each time when the actual output signal of the i-th comparator in the nth corrected pipeline stage is 1. The average of the amount of error.
  • the error estimation circuit is configured to determine a correction value of the correction flow level according to the following formula:
  • cal n represents the correction value of the nth corrected flow level
  • C n represents the number of comparators in the nth corrected flow level
  • calc(i) represents the i-th comparator output signal in the nth corrected flow level
  • mux i represents the actual output signal of the ith comparator in the nth corrected pipeline stage.
  • the MUX circuit is configured to select an output signal of the comparator as the comparator when the output signal of the comparator in the calibration pipeline stage is stably outputted within a preset time.
  • the actual output signal otherwise, the output signal of the random level generating circuit is selected as the actual output signal of the comparator.
  • the level edge detection circuit is configured to: when detecting that the output signal of the comparator in the correction pipeline stage is not stably outputting within a preset time, set the corresponding flag signal Bit, when detecting that the output signal of the comparator in the correction flow level is stably outputted within a preset time, resetting the corresponding flag signal;
  • the MUX circuit is configured to select, when the flag signal is set, an output signal corresponding to the random level generating circuit as an actual output signal of the comparator, in the flag When the signal is reset, the output signal corresponding to the comparator is selected as the actual output signal of the comparator;
  • the error estimating circuit is configured to determine, for each comparator corresponding to the flag signal in the correction pipeline stage, the comparator based on the actual output signal of the comparator, the encoded signal of the subsequent stage water level, and the correction value signal.
  • the error amount; the correction value corresponding to the output signal of the comparator is calculated according to each determined error amount; and after the correction value corresponding to each comparator output signal in the correction flow level is counted, according to the correction flow level
  • the correction value corresponding to each comparator output signal determines the correction value of the correction flow level.
  • the error estimating circuit is configured to: for each comparator that sets the flag signal in the correction pipeline stage, according to the actual output signal of the comparator, the encoded signal of the subsequent stage water level And the correction value signal, determining the error amount of the current output of the comparator, adding 1 to the set number of the flag signal corresponding to the comparator, determining whether the set number of the corresponding flag signal of the comparator is equal to a preset number of times threshold, If yes, the correction value corresponding to the output signal of the comparator is calculated according to the determined error amount.
  • the apparatus further includes a correction value storage circuit for storing a correction value of each of the correction flow levels.
  • the corrected output value of the pipelined analog to digital converter is:
  • cal 1 ⁇ Cal N represents the correction value of each of the corrected flow levels in the pipelined analog-to-digital converter.
  • the non-ideal characteristics of the calibration device and the mismatch error with time and external environment can not be tracked in real time, and the error information extracted from the measurement may be deviated from the actual working error information.
  • the present invention can track the correction non-real time in real time.
  • FIG. 1 is a circuit diagram showing an embodiment of an error compensation correcting apparatus of a pipelined analog-to-digital converter of the present invention
  • Figure 2 is a circuit diagram of an embodiment of the corrected flow level of Figure 1;
  • 3 is a schematic diagram showing the connection of each comparator of the corrected pipeline stage neutron ADC and the level edge detection circuit, the random level generation circuit, and the MUX circuit;
  • FIG. 5 is a schematic diagram of static performance simulation before and after calibration of the pipelined analog-to-digital converter of the present invention.
  • FIG. 6 is a schematic diagram of dynamic performance simulation before and after calibration of the pipelined analog-to-digital converter of the present invention.
  • connection should be understood broadly, and may be, for example, a mechanical connection or an electrical connection, or may be internal to the two elements, or may be The direct connection may also be indirectly connected through an intermediate medium.
  • connection should be understood broadly, and may be, for example, a mechanical connection or an electrical connection, or may be internal to the two elements, or may be The direct connection may also be indirectly connected through an intermediate medium.
  • specific meanings of the above terms may be understood according to specific situations.
  • the error compensation correction means of the pipelined analog-to-digital converter may include a correction pipeline stage 110 and a conventional pipeline stage 120. As shown in FIG. 2, for each correction stream stage 110, a corresponding error estimation circuit 130 and level edge detection are provided.
  • the circuit 140, the random level generating circuit 150 and the MUX (multiplexer) circuit 160 wherein the level edge detecting circuit 140 can detect whether the output signal of the comparator in the corrected water level 110 is within a preset time Stabilizing the output; the MUX circuit 160 may select the comparison according to the result of the detection
  • the output signal of the device or the output signal of the random level generating circuit 150 serves as an actual output signal of the comparator; the error estimating circuit 130 may be configured when the output signal of the comparator is not stably outputted within a preset time.
  • a correction value of the corrected flow level 110 is estimated based on the actual output signal, the encoded signal of the subsequent stage water level, and the correction value signal.
  • the pipelined analog-to-digital converter includes a plurality of flow stages, wherein the first N flow stages can be used as the corrected flow stage, and the remaining flow stages can be used as the conventional flow stage.
  • Each of the correction stream stages may output an encoded signal D i and a corrected value signal cal i
  • each of the conventional pipeline stages may output an encoded signal D i .
  • each of the conventional pipeline stages in the pipelined analog-to-digital converter can include a sub-ADC and an MDAC, and each correction pipeline stage is provided with a corresponding error estimate in addition to a sub-ADC and an MDAC.
  • the comparator compares two levels, if the difference between the two levels is small, the output speed is slower. If the two levels are different, the output speed is faster, so
  • the i-th comparator of the n-th correction pipeline stage neutron ADC is taken as an example, and the comparison is performed.
  • the device 111 can compare the input signal with the reference level, and when the level edge detecting circuit 140 detects that the output signal of the comparator 111 is not stably outputted within a preset time, the comparator 111 is indicated.
  • the input signal has a small difference from the reference level.
  • the MUX circuit 160 can use the output signal of the random level generating circuit 150 as the actual output signal of the comparator 111.
  • the level edge detecting circuit 140 detects that the output signal of the comparator 111 is stably outputted within a preset time, it indicates that the input signal of the comparator 111 is different from the reference level, and the MUX circuit 160 can compare the comparison.
  • the output signal of the converter 111 serves as the actual output signal of the comparator 111. It should be noted that the stable output of the comparator 111 may refer to a signal whose output signal is constant.
  • the error estimation circuit 130 is enabled to operate when the level edge detection circuit 140 detects that the output signal of at least one of the comparators in the corresponding correction pipeline stage 110 has not been stably outputted for a preset time. For each comparator 111 corresponding to the output of the correction pipeline stage 110 that is not stably outputted within a preset time, the error estimation circuit 130 may firstly be based on the actual output signal of the comparator, the encoded signal of the subsequent stage, and the correction.
  • the error estimation circuit 130 may determine the correction value of the correction flow level according to the correction value corresponding to each comparator output signal in the correction flow level.
  • the error amount of the corresponding comparator in the correction flow level 110 can be separately calculated according to the following formula:
  • err(i,mux i ) on the left side of the equation indicates the error amount of the i-th comparator determined this time when the actual output signal of the i-th comparator in the n-th correction stream is mux i ;
  • the err(i,mux i ) on the right indicates the error amount of the i-th comparator determined last time when the actual output signal of the i-th comparator in the nth correction pipeline is mux i ;
  • a n+1 to a L represents the coded signal of the subsequent stage of the water level after the nth corrected flow level;
  • b n+1 to b L represent the weight values corresponding to the coded signals of the respective subsequent stage water levels;
  • cal n+1 to cal N represent the latter stage Correction value for each corrected flow level in the flow level.
  • the error estimation circuit 130 may separately calculate the correction values corresponding to the output signals of the respective comparators according to the following formula:
  • calc(i) represents the correction value of the ith comparator in the nth corrected flow level
  • avg(err(i, 0)) represents the actual output signal of the ith comparator in the nth corrected flow level.
  • the average value of the error amount of the i-th comparator determined each time; avg(err(i, 1)) indicates that the actual output signal of the i-th comparator in the n-th corrected stream level is 1, each The average of the error amounts of the i-th comparator determined in the second time.
  • the correction value of the correction flow level may be determined according to the following formula:
  • cal n represents the correction value of the nth corrected flow level
  • C n represents the number of comparators in the nth corrected flow level
  • calc(i) represents the i-th comparator output signal in the nth corrected flow level
  • mux i represents the actual output signal of the ith comparator in the nth corrected pipeline stage.
  • the corrected output value of the pipeline analog-to-digital converter can be:
  • a 1 to a L represent coded signals of respective pipeline stages in the pipelined analog-to-digital converter
  • b 1 to b L represent weight values corresponding to coded signals of respective pipeline stages in the pipelined analog-to-digital converter
  • cal 1 ⁇ cal N represents the correction value of each correction flow level in the pipelined analog-to-digital converter.
  • the non-ideal characteristics of the correcting device and the mismatch error with time and the external environment cannot be tracked in real time compared with the conventional correction mode, and the error information extracted from the measurement may be deviated from the actual working error information.
  • the invention can track and correct the non-ideal characteristics and the mismatch error in real time with the external environment change, without interrupting the normal operation of the pipeline ADC, correcting the discontinuous points in the transmission curve, and the correction value is closer to the real situation, only need to add a small amount in the original circuit.
  • the digital circuit makes full use of the convenience brought by the current CMOS process advancement and the shrinking feature size, realizes low complexity, and can be flexibly designed according to the redundant coding structure of the pipeline ADC, and does not depend on the specific operation of the op amp and the comparator in the sub-ADC.
  • the structure is implemented to effectively improve the performance and accuracy of the pipelined ADC.
  • each comparator of each calibration flow level in the pipeline analog-to-digital converter corresponding flag signals may be respectively set, and each flag signal is correspondingly set. There are set times, where the initial value of the set number of times can be zero.
  • the error amount of each comparator of the correction flow level neutron ADC, the correction value, and the initial value of the correction value of each correction flow level may both be zero.
  • the comparator 111 can compare the input signal with the reference level when When the level edge detecting circuit 140 detects that the output signal of the comparator 111 is not stably outputted within a preset time, it indicates that the input signal of the comparator 111 is different from the reference level, and the corresponding flag signal sig can be i is set, wherein sig i represents a flag signal corresponding to the i-th comparator in the nth corrected pipeline stage; when the level edge detection circuit 140 detects that the output signal of the comparator 111 is stably outputted within a preset time , indicating that the input signal of the comparator 111 is different from the reference level, and the corresponding flag signal sig i can be reset at this time.
  • the MUX circuit 160 can use the output signal of the random level generating circuit 150 as the actual output signal of the comparator 111; when the flag signal sig i of the comparator 111 is reset At this time, the MUX circuit 160 can use the output signal of the comparator 111 as the actual output signal of the comparator 111.
  • the error estimation circuit 130 is enabled when the level edge detection circuit 140 detects that the flag signal of at least one of the corresponding correction pipeline stages 110 is set. For each comparator 111 in which the flag signal is set in the correction pipeline stage 110, the error estimation circuit 130 may first determine the error amount of the current output of the comparator according to formula (1) as shown in FIG. 4, and The set number of the flag signal corresponding to the comparator is incremented by 1, and then it is determined whether the set number of the corresponding flag signal of the comparator is equal to the preset The threshold of the number of times, if yes, the correction value corresponding to the output signal of the comparator is calculated according to formula (2), otherwise, the above steps are continued.
  • the error estimation circuit 130 may determine the correction value of the correction flow level according to formula (3), update the correction value of the correction flow level, and store the correction value. . Thereafter, the set number of times of the flag signals corresponding to the respective comparators is cleared, and the error amount of each of the comparators stored in the storage circuit is cleared to repeat the correction value update process of the above-described correction flow level. It should be noted that each of the above pipeline stages may output a coded signal by means of redundant coding.
  • a 14-bit 250 MHz sampling rate pipeline ADC is taken as an example, and the redundancy coding mode is 3.5-2.5-1.5-1.5-1.5-1.5-4 bit, including 8 pipeline levels, setting The first two stages of the flow level are the corrected flow level, and the background non-ideal parameters are estimated and corrected. The remaining flow levels are the regular flow level, and the last stage is the 4-bit flash ADC.
  • the performance of the pipeline of the pipeline is improved obviously.
  • the boost is about 3.5LSB
  • the effective bit (ENOB) is improved by 0.9LSB
  • the dynamic performance is increased by about 15dB after the SFDR correction.

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Abstract

本发明提供一种流水线模数转换器的误差补偿校正装置，包括校正流水级和常规流水级，针对每个校正流水级，设置有对应的误差估计电路、电平边沿检测电路、随机电平发生电路和MUX电路，其中电平边沿检测电路检测该校正流水级中比较器的输出信号是否在预设的时间内稳定输出；MUX电路用于根据检测的结果，选择将该比较器的输出信号或所述随机电平发生电路的输出信号作为该比较器的实际输出信号；误差估计电路在该比较器的输出信号未在预设的时间内稳定输出时，根据实际输出信号、后级流水级的编码信号和校正值信号，估计该校正流水级的校正值。本发明能够实时跟踪校正非理想特性和失配误差随时间外界环境变化，不打断流水线ADC正常工作，校正值更接近真实情况。

Description

流水线模数转换器的误差补偿校正装置 技术领域
本发明属于集成电路领域，具体涉及一种流水线模数转换器的误差补偿校正装置。
背景技术
A/D(Analog/Digital，模数)模数转换器的电路结构主要有逐次比较结构、积分型结构、全并行(flash)结构、分级结构、流水线结构和Δ－∑过采样结构等。高速高精度A/D转换器电路涉及的主要电路结构为流水线结构。流水线ADC(Analog-to-Digital Converter，模数转换器)由工作在双相不交叠时钟下的结构相同的流水级级联而成，除最末级外，各流水级都由基于运算放大器OPAMP和开关电容电路构成的MDAC(Multiplying Digital to Analog Converter，乘法数模转换器)以及基于比较器的子ADC构成，而流水级存在各种非理想特性和失配误差等因素，导致传输曲线中出现非连续跳变点，并且随着工艺特征尺寸的逐年缩小越来越成为限制流水线ADC转换精度的主要因素，严重制约了高速高精度流水线ADC的性能提升。要解决这些误差对流水线ADC的性能影响，使用切实有效的校正技术对误差进行补偿和纠正非常重要。
目前流水线模数转换器的误差补偿校正方法通常需要打断ADC正常工作，输入已知测试信号来获取校正信息，即便如此，测试时提取的误差信息和实际工作的误差信息也可能有一定偏差，同时无法跟踪器件非理想特性和失配误差因素随时间、外界环境的变化(比如温度变化、元器件老化、电压变化等)；同时也无法避免测试过程打断ADC正常工作，误差测量结果发生偏差，与ADC正常工作状态不同的影响。
发明内容
本发明提供一种流水线模数转换器的误差补偿校正装置，以解决目前在进行流水线模数转换器的误差补偿校正时需要打断流水线模数转换器正常工作且校正准确度较低的问题。
根据本发明实施例的第一方面，提供一种流水线模数转换器的误差补偿校正装置，其特征在于，包括校正流水级和常规流水级，针对每个所述校正流水级，设置有对应的误差估计电路、电平边沿检测电路、随机电平发生电路和MUX电路，其中所述电平边沿检测电路用于检测该校正流水级中比较器的输出信号是否在预设的时间内稳定输出；所述MUX电路用于根据所述检测的结果，选择将该比较器的输出信号或所述随机电平发生电路的输出信号作为该比较器的实际输出信号；
所述误差估计电路用于在该比较器的输出信号未在预设的时间内稳定输出时，根据所述实际输出信号、后级流水级的编码信 号和校正值信号，估计该校正流水级的校正值。
在一种可选的实现方式中，所述误差估计电路用于针对该校正流水级中输出信号未在预设的时间内稳定输出的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次的误差量；根据各次确定的误差量统计出该比较器输出信号所对应的校正值；并在统计出该校正流水级中各个比较器输出信号所对应的校正值后，根据该校正流水级中各个比较器输出信号所对应的校正值确定该校正流水级的校正值。
在另一种可选的实现方式中，所述误差估计电路用于根据以下公式确定该比较器的误差量：
Figure PCTCN2016086097-appb-000001
其中等式左边的err(i，muxi)表示第n个校正流水级中第i个比较器的实际输出信号为muxi时，第i个比较器本次确定的误差量；等式右边的err(i，muxi)表示第n个校正流水级中第i个比较器的实际输出信号为muxi时，第i个比较器上次确定的误差量；an+1～aL表示第n个校正流水级之后的后级流水级的编码信号；bn+1～bL表示与各个后级流水级的编码信号对应的权重值；caln+1～calN表示后级流水级中各个校正流水级的校正值。
在另一种可选的实现方式中，所述误差估计电路用于根据以下公式统计出该比较器的校正值：
calc(i)＝avg(err(i,0))-avg(err(i,1))，其中calc(i)表示第n个校正流水 级中第i个比较器输出信号所对应的校正值，avg(err(i,0))表示第n个校正流水级中第i个比较器的实际输出信号为0时，各次确定的第i个比较器的误差量的平均值；avg(err(i,1))表示第n个校正流水级中第i个比较器的实际输出信号为1时，各次确定的第i个比较器的误差量的平均值。
在另一种可选的实现方式中，所述误差估计电路用于根据以下公式确定该校正流水级的校正值：
Figure PCTCN2016086097-appb-000002
其中caln表示第n个校正流水级的校正值，Cn表示第n个校正流水级中比较器的个数，calc(i)表示第n个校正流水级中第i个比较器输出信号所对应的校正值，muxi表示第n个校正流水级中第i个比较器的实际输出信号。
在另一种可选的实现方式中，所述MUX电路用于在该校正流水级中比较器的输出信号在预设的时间内稳定输出时，选择将该比较器的输出信号作为该比较器的实际输出信号，否则，选择将该随机电平发生电路的输出信号作为该比较器的实际输出信号。
在另一种可选的实现方式中，所述电平边沿检测电路用于在检测到该校正流水级中比较器的输出信号未在预设的时间内稳定输出时，将对应的标志信号置位，在检测到该校正流水级中比较器的输出信号在预设的时间内稳定输出时，将对应的标志信号复位；
所述MUX电路用于在该标志信号置位时，选择将对应随机电平发生电路的输出信号作为该比较器的实际输出信号，在该标志 信号复位时，选择将对应比较器的输出信号作为该比较器的实际输出信号；
所述误差估计电路用于针对该校正流水级中标志信号置位的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次的误差量；根据各次确定的误差量统计出该比较器输出信号所对应的校正值；并在统计出该校正流水级中各个比较器输出信号所对应的校正值后，根据该校正流水级中各个比较器输出信号所对应的校正值确定该校正流水级的校正值。
在另一种可选的实现方式中，所述误差估计电路用于针对该校正流水级中标志信号置位的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次输出的误差量，将该比较器对应的标志信号的置位次数加1，判断该比较器对应标志信号的置位次数是否等于预设的次数阈值，若是，则根据各次确定的误差量统计出该比较器输出信号所对应的校正值。
在另一种可选的实现方式中，所述装置还包括校正值存储电路，所述校正值存储电路用于存储各个校正流水级的校正值。
在另一种可选的实现方式中，流水线模数转换器校正后的输出值为：
Figure PCTCN2016086097-appb-000003
其中a1～aL表示所述流水线模数转换器中各个流水级的编码信号，b1～bL表示所述流水线模数转换器中各个 流水级的编码信号对应的权重值，cal1～calN表示所述流水线模数转换器中各个校正流水级的校正值。
本发明的有益效果是：
相比于传统的校正方式不能实时跟踪校正器件非理想特性和失配误差随时间、外界环境的变化，且测量提取得误差信息与实际工作误差信息可能有一定偏差，本发明能够实时跟踪校正非理想特性和失配误差随时间外界环境变化，不打断流水线ADC正常工作，校正传输曲线中的非连续点，校正值更接近真实情况，仅仅只需要在原电路中添加少量数字电路，充分利用了当前CMOS工艺进步和特征尺寸不断缩小带来的便利，实现复杂度低，并且可根据流水线ADC冗余编码结构灵活设计，不依赖于子ADC中运放和比较器的具体实现结构，从而能够有效提高流水线ADC的性能和精度。
附图说明
图1是本发明流水线模数转换器的误差补偿校正装置的一个实施例电路示意图；
图2是图1中校正流水级的一个实施例电路示意图；
图3是图1中校正流水级中子ADC的各个比较器与电平边沿检测电路、随机电平发生电路和MUX电路的连接示意图；
图4是误差估计电路对校正流水级的校正值进行更新的流程图；
图5是本发明流水线模数转换器校正前后的静态性能仿真示意 图；
图6是本发明流水线模数转换器校正前后的动态性能仿真示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明实施例中的技术方案，并使本发明实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明实施例中技术方案作进一步详细的说明。
在本发明的描述中，除非另有规定和限定，需要说明的是，术语“连接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
参见图1，为本发明流水线模数转换器的误差补偿校正装置的一个实施例电路示意图。该流水线模数转换器的误差补偿校正装置可以包括校正流水级110和常规流水级120，结合图2所示，针对每个校正流水级110，设置有对应的误差估计电路130、电平边沿检测电路140、随机电平发生电路150和MUX(multiplexer，数据选择器)电路160，其中所述电平边沿检测电路140可以检测该校正流水级110中比较器的输出信号是否在预设的时间内稳定输出；所述MUX电路160可以根据所述检测的结果，选择将该比较 器的输出信号或所述随机电平发生电路150的输出信号作为该比较器的实际输出信号；所述误差估计电路130可以在该比较器的输出信号未在预设的时间内稳定输出时，根据所述实际输出信号、后级流水级的编码信号和校正值信号，估计该校正流水级110的校正值。
本实施例中，流水线模数转换器包括多个流水级，其中前面的N个流水级可以作为校正流水级，后面剩余的流水级可以作为常规流水级。每一校正流水级可以输出编码信号Di和校正值信号cali，每一常规流水级可以输出编码信号Di。参见图2所示，流水线模数转换器中每个常规流水级都可以包括一个子ADC和一个MDAC，并且每个校正流水级除包括一个子ADC和一个MDAC外，还设置有对应的误差估计电路130、电平边沿检测电路140、随机电平发生电路150和MUX电路160，其中随机电平发生电路150可以在对应校正流水级110采样时钟的控制下随机生成对应的“0”或“1”两个数字电平。
经研究发现，比较器在对两个电平进行比较时若这两个电平相差较小，则输出速度较慢，若两个电平相差较大，则输出速度较快，因此在一种可选的实现方式中，参见图3所示，针对各个校正流水级110中子ADC的每个比较器111，以第n个校正流水级中子ADC的第i个比较器为例，该比较器111可以将输入信号与参考电平进行比较，当电平边沿检测电路140检测到该比较器111的输出信号未在预设的时间内稳定输出时，表示该比较器111 的输入信号与参考电平相差较小，此时MUX电路160可以将该随机电平发生电路150的输出信号作为该比较器111的实际输出信号。当电平边沿检测电路140检测到该比较器111的输出信号在预设的时间内稳定输出时，表示比较器111的输入信号与参考电平相差较大，此时MUX电路160可以将该比较器111的输出信号作为该比较器111的实际输出信号。需要注意的是：该比较器111稳定输出可以是指其输出的信号为不变的信号。
当电平边沿检测电路140检测到对应校正流水级110中至少有一个比较器111的输出信号未在预设的时间内稳定输出时，该误差估计电路130使能工作。针对对应校正流水级110中输出信号未在预设的时间内稳定输出的每个比较器111，该误差估计电路130可以首先根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器输出的对应的误差量，然后根据各次确定的误差量统计出该比较器输出信号所对应的校正值；在统计出该校正流水级中各个比较器输出信号所对应的校正值后，误差估计电路130可以根据该校正流水级中各个比较器输出信号所对应的校正值确定该校正流水级的校正值。
当误差估计电路130使能工作时，可以根据以下公式分别计算出该校正流水级110中对应比较器的误差量：
Figure PCTCN2016086097-appb-000004
其中，等式左边的err(i，muxi)表示第n个校正流水级中第i个 比较器的实际输出信号为muxi时，本次确定的第i个比较器的误差量；等式右边的err(i，muxi)表示第n个校正流水级中第i个比较器的实际输出信号为muxi时，上次确定的第i个比较器的误差量；an+1～aL表示第n个校正流水级之后的后级流水级的编码信号；bn+1～bL表示与各个后级流水级的编码信号对应的权重值；caln+1～calN表示后级流水级中各个校正流水级的校正值。
误差估计电路130在计算出各个比较器预设次数的误差量后，可以根据以下公式分别统计出各个比较器输出信号所对应的校正值：
calc(i)＝avg(err(i,0))-avg(err(i,1))          ，(2)
其中，calc(i)表示第n个校正流水级中第i个比较器的校正值，avg(err(i,0))表示第n个校正流水级中第i个比较器的实际输出信号为0时，各次确定的第i个比较器的误差量的平均值；avg(err(i,1))表示第n个校正流水级中第i个比较器的实际输出信号为1时，各次确定的第i个比较器的误差量的平均值。
误差估计电路130在统计出对应比较器输出信号所对应的校正值后，可以根据以下公式确定该校正流水级的校正值：
Figure PCTCN2016086097-appb-000005
其中caln表示第n个校正流水级的校正值，Cn表示第n个校正流水级中比较器的个数，calc(i)表示第n个校正流水级中第i个比 较器输出信号所对应的校正值，muxi表示第n个校正流水级中第i个比较器的实际输出信号。
在确定各个校正流水级的校正值后，流水线模数转换器校正后的输出值可以为：
Figure PCTCN2016086097-appb-000006
其中，a1～aL表示所述流水线模数转换器中各个流水级的编码信号，b1～bL表示所述流水线模数转换器中各个流水级的编码信号对应的权重值，cal1～calN表示所述流水线模数转换器中各个校正流水级的校正值。
由上述实施例可见，相比于传统的校正方式不能实时跟踪校正器件非理想特性和失配误差随时间、外界环境的变化，且测量提取得误差信息与实际工作误差信息可能有一定偏差，本发明能够实时跟踪校正非理想特性和失配误差随时间外界环境变化，不打断流水线ADC正常工作，校正传输曲线中的非连续点，校正值更接近真实情况，仅仅只需要在原电路中添加少量数字电路，充分利用了当前CMOS工艺进步和特征尺寸不断缩小带来的便利，实现复杂度低，并且可根据流水线ADC冗余编码结构灵活设计，不依赖于子ADC中运放和比较器的具体实现结构，从而能够有效提高流水线ADC的性能和精度。
另外，针对流水线模数转换器中每个校正流水级的各个比较器，可以分别设置有对应的标志信号，且每个标志信号对应设置 有置位次数，其中置位次数的初始值可以为0。该校正流水级中子ADC的各个比较器的误差量、校正值以及各个校正流水级的校正值的初始值都可以为0。
针对校正流水级110中子ADC的每个比较器111，以第n个校正流水级中子ADC的第i个比较器为例，该比较器111可以将输入信号与参考电平进行比较，当电平边沿检测电路140检测到该比较器111的输出信号未在预设的时间内稳定输出时，表示比较器111的输入信号与参考电平相差较小，此时可以将对应的标志信号sigi置位，其中sigi表示第n个校正流水级中第i个比较器对应的标志信号；当电平边沿检测电路140检测到该比较器111的输出信号在预设的时间内稳定输出时，表示比较器111的输入信号与参考电平相差较大，此时可以将对应的标志信号sigi复位。当该比较器111的标志信号sigi置位时，MUX电路160可以将该随机电平发生电路150的输出信号作为该比较器111的实际输出信号；当该比较器111的标志信号sigi复位时，MUX电路160可以将该比较器111的输出信号作为该比较器111的实际输出信号。
当电平边沿检测电路140检测到对应校正流水级110中至少有一个比较器的标志信号置位时，该误差估计电路130使能工作。针对该校正流水级110中标志信号置位的每个比较器111，该误差估计电路130可以如图4所示，首先根据公式(1)确定该比较器本次输出的误差量，并将该比较器对应的标志信号的置位次数加1，然后判断该比较器对应的标志信号的置位次数是否等于预设的 次数阈值，若是，则根据公式(2)统计出该比较器输出信号所对应的校正值，否则，继续执行上述步骤。在统计出该校正流水级中各个比较器输出信号所对应的校正值后，误差估计电路130可以根据公式(3)确定该校正流水级的校正值，更新该校正流水级的校正值并进行存储。此后，将各个比较器对应的标志信号的置位次数清零，并将存储电路中存储的各个比较器的误差量清零，以重复上述校正流水级的校正值更新过程。需要注意的是：上述各个流水级可以采用冗余编码的方式输出编码信号。
在一种可选的实现方式中，以14比特250MHZ采样率流水线ADC为例，冗余编码方式为3.5-2.5-1.5-1.5-1.5-1.5-1.5-4bit，包含8个流水级，设定前两级流水级为校正流水级，进行后台非理想参数的估计校正，其余流水级为常规流水级，其中最后一级流水级为4bit flash ADC，相关参数具体值如下，L＝8，N＝2，C1＝14，C2＝6，标志信号置位次数设定值为64k，添加非理想参数，输入正弦信号，按照上述方式进行实时校正，仿真结果如图所示，如图5和6可见，校正后流水级线ADC性能提升明显，INL校正后比校正前提升约3.5LSB，有效位(ENOB)校正后提高0.9LSB，动态性能SFDR校正后提高约15dB。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本发明的其它实施方案。本申请旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公 知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

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  1. 一种流水线模数转换器的误差补偿校正装置，其特征在于，包括校正流水级和常规流水级，针对每个所述校正流水级，设置有对应的误差估计电路、电平边沿检测电路、随机电平发生电路和MUX电路，其中所述电平边沿检测电路用于检测该校正流水级中比较器的输出信号是否在预设的时间内稳定输出；所述MUX电路用于根据所述检测的结果，选择将该比较器的输出信号或所述随机电平发生电路的输出信号作为该比较器的实际输出信号；
    所述误差估计电路用于在该比较器的输出信号未在预设的时间内稳定输出时，根据所述实际输出信号、后级流水级的编码信号和校正值信号，估计该校正流水级的校正值。
  2. 根据权利要求1所述的装置，其特征在于，所述误差估计电路用于针对该校正流水级中输出信号未在预设的时间内稳定输出的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次输出的误差量；根据各次确定的误差量统计出该比较器输出信号所对应的校正值；并在统计出该校正流水级中各个比较器输出信号所对应的校正值后，根据该校正流水级中各个比较器输出信号所对应的校正值确定该校正流水级的校正值。
  3. 根据权利要求2所述的装置，其特征在于，所述误差估计 电路用于根据以下公式确定该比较器的误差量：
    Figure PCTCN2016086097-appb-100001
    其中等式左边的err(i，muxi)表示第n个校正流水级中第i个比较器的实际输出信号为muxi时，第i个比较器本次确定的误差量；等式右边的err(i，muxi)表示第n个校正流水级中第i个比较器的实际输出信号为muxi时，第i个比较器上次确定的误差量；an+1～aL表示第n个校正流水级之后的后级流水级的编码信号；bn+1～bL表示与各个后级流水级的编码信号对应的权重值；caln+1～calN表示后级流水级中各个校正流水级的校正值。
  4. 根据权利要求2所述的装置，其特征在于，所述误差估计电路用于根据以下公式统计出该比较器的校正值：
    calc(i)＝avg(err(i,0))-avg(err(i,1))，其中calc(i)表示第n个校正流水级中第i个比较器输出信号所对应的校正值，avg(err(i,0))表示第n个校正流水级中第i个比较器的实际输出信号为0时，各次确定的第i个比较器的误差量的平均值；avg(err(i,1))表示第n个校正流水级中第i个比较器的实际输出信号为1时，各次确定的第i个比较器的误差量的平均值。
  5. 根据权利要求2所述的装置，其特征在于，所述误差估计电路用于根据以下公式确定该校正流水级的校正值：
    Figure PCTCN2016086097-appb-100002
    其中caln表示第n个校正流水级的校正值，Cn表示第n个校正流水级中比较器的个数，calc(i)表示第n个校正 流水级中第i个比较器输出信号所对应的校正值，muxi表示第n个校正流水级中第i个比较器的实际输出信号。
  6. 根据权利要求1所述的装置，其特征在于，所述MUX电路用于在该校正流水级中比较器的输出信号在预设的时间内稳定输出时，选择将该比较器的输出信号作为该比较器的实际输出信号，否则，选择将该随机电平发生电路的输出信号作为该比较器的实际输出信号。
  7. 根据权利要求2所述的装置，其特征在于，所述电平边沿检测电路用于在检测到该校正流水级中比较器的输出信号未在预设的时间内稳定输出时，将对应的标志信号置位，在检测到该校正流水级中比较器的输出信号在预设的时间内稳定输出时，将对应的标志信号复位；
    所述MUX电路用于在该标志信号置位时，选择将对应随机电平发生电路的输出信号作为该比较器的实际输出信号，在该标志信号复位时，选择将对应比较器的输出信号作为该比较器的实际输出信号；
    所述误差估计电路用于针对该校正流水级中标志信号置位的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次的误差量；根据各次确定的误差量统计出该比较器输出信号所对应的校正值；并在统计出该校正流水级中各个比较器输出信号所对应的校正值后，根据该校正流水级中各个比较器输出信号所对应的校正值确定该校正流 水级的校正值。
  8. 根据权利要求7所述的装置，其特征在于，所述误差估计电路用于针对该校正流水级中标志信号置位的每个比较器，根据该比较器的实际输出信号、后级流水级的编码信号和校正值信号，确定该比较器本次的误差量，将该比较器对应的标志信号的置位次数加1，判断该比较器对应标志信号的置位次数是否等于预设的次数阈值，若是，则根据各次确定的误差量统计出该比较器输出信号所对应的校正值。
  9. 根据权利要求1所述的装置，其特征在于，所述装置还包括校正值存储电路，所述校正值存储电路用于存储各个校正流水级的校正值。
  10. 根据权利要求1所述的装置，其特征在于，流水线模数转换器校正后的输出值为：
    Figure PCTCN2016086097-appb-100003
    其中a1～aL表示所述流水线模数转换器中各个流水级的编码信号，b1～bL表示所述流水线模数转换器中各个流水级的编码信号对应的权重值，cal1～calN表示所述流水线模数转换器中各个校正流水级的校正值。
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