WO2017196109A1 - Support de dispositif à semi-conducteur, son procédé de fabrication, et dispositif de manipulation de dispositif comprenant celui-ci - Google Patents

Support de dispositif à semi-conducteur, son procédé de fabrication, et dispositif de manipulation de dispositif comprenant celui-ci Download PDF

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Publication number
WO2017196109A1
WO2017196109A1 PCT/KR2017/004898 KR2017004898W WO2017196109A1 WO 2017196109 A1 WO2017196109 A1 WO 2017196109A1 KR 2017004898 W KR2017004898 W KR 2017004898W WO 2017196109 A1 WO2017196109 A1 WO 2017196109A1
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Prior art keywords
semiconductor device
base member
hole
carrier
semiconductor
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PCT/KR2017/004898
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English (en)
Korean (ko)
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유홍준
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(주)제이티
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Publication of WO2017196109A1 publication Critical patent/WO2017196109A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67386—Closed carriers characterised by the construction of the closed carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to an EMI shielding process, and more particularly, to an EMI shielding process of forming an EMI shielding layer on the top and side surfaces of a semiconductor device having a plurality of projecting terminals formed on a bottom thereof.
  • noise electromagnetic noise
  • the device Because of the circuitry to block noise, the device becomes thicker and smaller, and it becomes a barrier to thin film, so it is necessary to develop EMI shielding technology to solve this problem.
  • semiconductor chip EMI shielding is achieved by adding an ultra thin metal coating process on the packaging surface.
  • the semiconductor chip according to a surface mounter technology (SMT) method, that is, a method mounted on a printed circuit board (PCB), a flat flat package (QFP), a land grid array (LGA), a ball grid array (BGA) and the like.
  • SMT surface mounter technology
  • PCB printed circuit board
  • QFP flat flat package
  • LGA land grid array
  • BGA ball grid array
  • SOP Small out-line package
  • a BGA chip in which a ball-shaped electrode is formed at a lower portion thereof has a lot of gaps in a lower portion thereof, and thus a gap is formed in a lower empty space, thereby making it difficult to completely shield EMI.
  • the through hole is formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to form a shield layer in the terminal or the like during the EMI shielding process It is to provide a semiconductor device carrier that can be prevented.
  • Another object of the present invention is to provide a base member having rigidity in order to prevent stiffness deterioration due to formation of a through hole of a corresponding size in a terminal area formed on a bottom surface of a semiconductor element in loading a plurality of semiconductor elements to form an EMI shield. And an adhesion layer to which the bottom of the semiconductor device is attached, thereby providing a semiconductor device carrier on which semi-element devices can be stably loaded.
  • Still another object of the present invention is to provide an element handler for loading elements from a tray on which a plurality of elements are loaded to an EMI shield tray to form an EMI shield.
  • the present invention is an EMI shield for forming an EMI shield layer 13 on the top and side surfaces of a semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface
  • the plurality of semiconductor devices having a predetermined rigidity and a size corresponding to the terminal area in which the protruding terminals 12 of each semiconductor device are formed are formed.
  • a semiconductor device carrier comprising a.
  • the semiconductor device carrier may further include a frame 300 coupled to an upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed upward. have.
  • the base member 100 may have a disk-shaped wafer shape, or various shapes such as a rectangle and an octagon.
  • the adhesion layer 200 may be formed by a double-sided tape attached to an upper surface of the base member 100.
  • the double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or less than the first through-hole 101 at the same position as the first through-hole 101. Can be.
  • the attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101) ) May be formed.
  • the present invention a plurality of the semiconductor device to perform the process of forming the EMI shield layer 13 to form the EMI shield layer 13 on the upper and side surfaces of the semiconductor device having a plurality of projecting terminals 12 formed on the bottom surface
  • a method of manufacturing a semiconductor device carrier to be attached the plate-shaped base member 100 having a predetermined rigidity and having a plurality of first through holes 101 formed in a size corresponding to a terminal area in which a protruding terminal 12 of each semiconductor device is formed.
  • a base member providing step of providing; The attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100.
  • Forming an adhesion layer After the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100, the second through hole with the same or smaller size as the first through hole 101 at the same position as the first through hole 101.
  • a method for manufacturing a semiconductor device carrier comprising the step of forming a second through hole forming a 201.
  • the adhesion layer 200 is a double-sided tape attached to the upper surface of the base member 100, the second through-hole forming step, the laser drilling to drill the same position as the first through-hole 101 using a laser It may include a step.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step, may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
  • a device handler comprising at least one transfer tool attached to the semiconductor device carrier.
  • the carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
  • the transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
  • the device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device picked up by the transfer tool 400, wherein the image Analyzing the image of the bottom surface obtained by the acquisition unit 30 by the movement of at least one of the XY movement and the horizontal rotation movement so that the semiconductor device is positioned in a predetermined loading position on the semiconductor device carrier by the carrier table 700 ) Can be moved.
  • through holes are formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to prevent the shield layer from being formed during the EMI shielding process. There is this.
  • the semiconductor device carrier according to the present invention the base having a rigidity in order to prevent the degradation of the rigidity caused by the formation of the through-holes of the corresponding size of the terminal region formed on the bottom surface of the semiconductor device in the plurality of stacks to form the EMI shield Since the bottom surface of the member and the semiconductor device is composed of an adhesion layer, there is an advantage in that the semi-elements can be loaded and transported stably.
  • the device handler according to the present invention is made of an adhesion layer to which the semiconductor device is attached and a base member made of a material having a rigidity greater than that of the adhesion layer, for example, a metal material, a synthetic resin material, etc.
  • a base member made of a material having a rigidity greater than that of the adhesion layer, for example, a metal material, a synthetic resin material, etc.
  • the device handler in loading a semiconductor device in the EMI shield semiconductor device carrier having the above configuration from a tray on which a plurality of semiconductor devices are loaded, the carrier table on both sides of the carrier table based on the transfer direction of the tray
  • the carrier table By installing a pair and installing a pair of transfer tools corresponding to each of the pair of carrier tables, it is possible to greatly improve the transfer efficiency of semiconductor elements that pick up the semiconductor elements from the tray and attach them to the carriers loaded on the carrier table. have.
  • FIG. 1 is a plan view showing a semiconductor device carrier according to the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II ′ of the semiconductor device carrier of FIG. 1.
  • FIG. 3 is an enlarged view illustrating an enlarged portion A of FIG. 2.
  • FIG. 4 is a perspective view illustrating a base member constituting the semiconductor device carrier of FIG. 1.
  • FIG. 5 is a plan view showing a device handler according to the present invention.
  • FIG. 6 is a sectional view taken along the line II-II 'of the device handler of FIG.
  • FIG. 7 is a cross-sectional view illustrating a vertical cross section of the device handler of FIG. 5.
  • FIG. 8 is a bottom view illustrating an example of a device seated on a semiconductor device carrier according to the present invention.
  • the semiconductor device carrier according to the present invention is configured to be loaded for performing an EMI shielding process for forming an EMI shield for shielding electromagnetic waves on a surface of a semiconductor device such as a system semiconductor.
  • the EMI shielding process includes loading a semiconductor device into a semiconductor device carrier for EMI shielding, and forming an EMI shield layer to form an EMI shield layer on upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier. It includes.
  • the loading step may be performed by various methods as the step of loading the semiconductor device in the semiconductor device carrier for EMI shield.
  • the semiconductor device carrier for device loading before the loading step is supplied to the device handler for device loading through a semiconductor device carrier manufacturing method to be described later.
  • the EMI shield layer forming step may be performed by various methods as a step of forming an EMI shield layer on the upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier through a deposition process such as sputtering or spraying.
  • the EMI shielding process is completed after a dry process and the like, and a process of unloading from the semiconductor device carrier may be performed for performing or shipping the subsequent process.
  • the semiconductor device carrier for the EMI shield needs to have a semiconductor device loaded thereon except for a bottom on which terminals are formed, that is, an EMI shield layer may be formed on the top and side surfaces of the semiconductor devices.
  • the semiconductor device 10 is an element forming an IC chip such as a display drive IC (DDI) such as a chip on glass (COG) or a chip on film (COF), an LED element, or the like, and a wafer is a so-called semiconductor. It may correspond to a device that has completed a process and a cutting process (also a test process and a classification process).
  • a display drive IC such as a chip on glass (COG) or a chip on film (COF), an LED element, or the like
  • a wafer is a so-called semiconductor. It may correspond to a device that has completed a process and a cutting process (also a test process and a classification process).
  • the semiconductor device 10 is a ball grid array package device, in which a hemispherical solder terminal is arranged in a two-dimensional array on a rear surface of a printed circuit board (PCB). It may correspond to a semiconductor package instead of.
  • PCB printed circuit board
  • the semiconductor device 10 may have a plurality of hemispherical protrusion terminals 12 formed on a bottom surface thereof.
  • the semiconductor device 10 may be loaded on the tray 20 and transported, as shown in FIGS. 5 to 6.
  • the process of forming the EMI shield layer 13 is a process of forming the EMI shield layer 13 on the top and side surfaces of the semiconductor device 10 having the plurality of protruding terminals 12 formed on the bottom thereof.
  • the EMI shield layer 13 may be formed by spraying or depositing a metal material on the top and side surfaces of the semiconductor device 10.
  • the device handler is configured to load the semiconductor device 10 from the tray 20 on which the plurality of semiconductor devices 10 are loaded to the semiconductor device carrier.
  • the device handler is configured to load the semiconductor device 10 from the tray 20 on which the plurality of semiconductor devices 10 are loaded to the semiconductor device carrier.
  • Various configurations are possible.
  • the device handler may include: a loading unit in which trays 20 in which a plurality of semiconductor devices are loaded are loaded; At least one carrier table 700 positioned on at least one side of the loading unit based on a transport direction of the tray 20 and horizontally moving a carrier for loading of semiconductor devices; The semiconductor device is picked up from the tray 20 in the loading unit, and the terminal area is exposed to the lower side of the first through hole 101 on the carriers loaded on the carrier tables 700, and the edges of the terminal areas are exposed to the semiconductor device carrier. It may include one or more transfer tool 400 to attach.
  • the loading unit may be configured in a variety of configurations in which the trays 20 in which the plurality of semiconductor devices are loaded are loaded to the device withdrawal positions.
  • the loading unit transfers the tray 20 loaded with the semiconductor elements 10 to be loaded from the loading position to the extraction position, and transfers the tray 20 from which the device is completed to the unloading position. It may include a tray transfer unit 600 to.
  • the loading unit may include a tray loading part 630 in which a tray on which the device 10 is seated in the unloading position is loaded.
  • the tray transfer part 600 may include a guide rail 610 which is installed to face each other around the element extraction position so that the tray 20 drawn out of the tray loading part 630 moves horizontally. .
  • the loading unit may be driven in the vertical direction to recover the tray 20, the device withdrawal is completed.
  • the carrier table 700 is located on at least one side of the loading unit with respect to the conveying direction of the tray 20 and is configured in various configurations to horizontally move the semiconductor device carrier to load the semiconductor devices 10 in the semiconductor device carrier. This is possible.
  • the carrier table 700 receives the semiconductor device carrier from the carrier loading unit 900 so that the transfer device 400 can load the device 10 picked up from the tray 20.
  • the configuration for moving in the horizontal direction various configurations such as an XY table and an XY- ⁇ table are possible.
  • the carrier loading unit 900 is configured to move the semiconductor device carrier to the carrier table 700 in sequence and can be configured in various ways.
  • the carrier loading unit 900 may include a carrier loading unit in which a plurality of carriers are loaded.
  • the carrier table 700 may be moved in the vertical direction, that is, the Z axis direction.
  • the carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
  • the carrier table 700 may include a carrier transfer unit (not shown) which transfers the semiconductor device carrier from which the device 10 is loaded from the tray 20 to the carrier unloading unit 800 by the transfer tool 400. Can be.
  • the semiconductor device carrier may be conveyed to the EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process after the semiconductor device 10 is loaded.
  • the transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
  • the transfer tool 400 may be combined with a guide 500 for linear movement of the transfer tool 400.
  • the transfer tool 400 may be coupled to both sides of the guide 500 or to the same side.
  • the transfer tool 400 may include a first transfer tool 410 corresponding to the first semiconductor device carrier table 700 located on one side of the loading unit and a second semiconductor device carrier table 700 located on the other side of the loading unit.
  • the second transfer tool 420 corresponding to and may be installed in pairs.
  • the first transfer tool 410 transfers the semiconductor device 10 to the first semiconductor device carrier along the first path
  • the second transfer tool 420 may be formed of the first transfer tool 420.
  • Various configurations are possible by transferring the semiconductor device 10 to the second semiconductor device carrier along the two paths ().
  • first transfer tool 410 and the second transfer tool 420 may be configured to alternately transfer the elements so as not to interfere with each other when the semiconductor element 10 is drawn out from the withdrawal position.
  • the transfer tool 400 is a configuration for transferring the element 10 from the tray 20 to the semiconductor element carrier, and can be configured in various ways according to the pick-up method. It may be configured to include an adsorption head (not shown) for generating the adsorption to pick up the element 10.
  • the device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device 10 picked up by the transfer tool 400. can do.
  • the image obtained by the image acquisition unit 30 may perform a vision inspection on the bottom surface of the semiconductor device 10 adsorbed on the adsorption pad of the transfer tool 400.
  • the image obtained by the image acquisition unit 30, the semiconductor device (suitable for a suitable mounting position on the semiconductor device carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201) It can be utilized to check the horizontal state of the semiconductor device 10 picked up by the transfer tool 400 so that 10) can be loaded.
  • the device handler analyzes an image of the bottom surface obtained by the image acquisition unit 30 to move the semiconductor device to at least one of an XY movement and a horizontal rotational movement so that the semiconductor device is positioned at a preset loading position on the semiconductor device carrier.
  • the carrier table 700 may be moved.
  • the transfer tool 400 picking up the semiconductor element 10 is rotated so as to be suitable for the proper seating position on the semiconductor element carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201.
  • the semiconductor device 10 can be loaded.
  • the semiconductor device carrier on which the semiconductor device 10 is loaded by the device handler may move to the carrier unloading unit 900 and be transferred to an EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process. have.
  • the device handler having the above configuration may be configured as part of an inline system that is inlined from the above-described device loading to the unloading after EMI shielding.
  • the bottom surface of the semiconductor device 10 is not closely adhered to the semiconductor device carrier due to the influence of the protruding terminal 12 formed on the bottom surface of the semiconductor device 10.
  • the formation of the EMI shield layer 13 is not completely made.
  • the conventional semiconductor device carrier has a problem in that the shape of the support surface is not stably maintained during the carrier transfer process by attaching the semiconductor device 10 to a support surface formed of a thin and flexible material such as a tape.
  • the semiconductor device carrier according to the present invention, EMI shield layer 13 to form an EMI shield layer 13 on the upper surface and the side of the semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface
  • the semiconductor device carrier has a predetermined rigidity and has a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device is formed.
  • Plate-shaped base member 100 is formed; An attachment layer 200 formed on an upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region is attached to the base member 100; The frame 300 is coupled to the upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed to the upper portion.
  • the base member 100 is a plate-shaped member having a predetermined rigidity, and a plurality of first through holes 101 are formed to have a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device 10 is formed. Can be.
  • the first through hole 101 may have a size smaller than that of the semiconductor device 10 and larger than a terminal region in which the protruding terminal 12 is formed.
  • the first through hole 101 may have various shapes in such a manner as to support an edge at which the protruding terminal 12 of the bottom surface of the semiconductor device 10 is not formed.
  • the first through hole 101 may have a shape corresponding to a planar shape of the semiconductor device 10, for example, a rectangular shape, the boundary of which the protruding terminal 12 of the bottom surface of the semiconductor device 10 may be formed. It may be formed to be located between the terminal area and the edge.
  • the first through hole 101 is larger in size than the terminal area w in which the protruding terminal 12 is formed, and is larger than the bottom surface of the semiconductor device 10. It may be formed to be small so as to contact an edge outside the terminal region w of the semiconductor device 10.
  • the first through hole 101 is preferably located in the circumferential region d1 + d2 excluding the terminal region of the semiconductor device 10.
  • the base member 100, the base member 100 may have a variety of shapes, such as a disk-shaped wafer shape or octagonal, rectangular, but is not limited thereto.
  • the base member 100 may have various materials as long as it is a material capable of supporting the semiconductor device 10 loaded with predetermined rigidity without shaking.
  • the base member 100 may have a material that is harder than the material of the metal and the adhesion layer 200 described later.
  • the attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region can be attached to the base member 100.
  • Various configurations are possible.
  • the adhesion layer 200 may be formed by an adhesive tape having an adhesive attached to the upper surface of the base member 100, for example, the adhesive tape may correspond to a double-sided tape. have.
  • the double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or smaller in size with the first through-hole 101. Can be.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It may include an adhesive material bonded to the upper surface of the film.
  • the attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101). Can be formed.
  • the frame 300 is configured to be coupled to the upper surface of the base member 100 so that the region in which the first through holes 101 are formed in the base member 100 is exposed to the top.
  • the frame 300 may be configured as a coupling ring coupled to an edge of the adhesive layer 200 so that the region where the first through holes 101 are formed is exposed upward.
  • the frame 300 may have various shapes such as a circle and a rectangle.
  • the frame 300 is not an essential configuration, it corresponds to a configuration that can be selectively adopted.
  • a method of manufacturing a semiconductor device carrier to which a plurality of semiconductor devices are attached to perform a method comprising: a plurality of first through holes 101 having a predetermined rigidity and corresponding to a terminal area in which protrusion terminals 12 of each semiconductor device are formed; A base member providing step of providing a plate-shaped base member 100 formed thereon; Attachment layer forming step of forming the attachment layer 200 on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100.
  • the second through hole 201 is formed in the same position as or less than the first through hole 101 at the same position as the first through hole 101. It can be produced by a semiconductor device carrier manufacturing method comprising a second through-hole forming step to form.
  • the adhesion layer 200 is a double-sided tape is attached to the upper surface of the base member 100, the second through-hole forming step, drilling the same position as the first through-hole 101 using a laser It may include a laser drilling step.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
  • the semiconductor device carrier manufacturing method the first through-hole (at the same position as the first through-hole 101 in the attachment layer 200 before the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100 ( The second through-hole forming step of forming the second through-hole 201 with the same or smaller size than that of 101 is performed, and the attachment layer 200 having the second through-hole 201 is formed on the base member 100.
  • An adhesive layer forming step of attaching the first through hole 101 and the second through hole 201 to correspond to each other may be performed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

La présente invention concerne un procédé de protection contre les interférences électromagnétiques (EMI) et, plus spécifiquement, un procédé de protection contre les interférences électromagnétiques conçu pour former des couches de protection contre les interférences électromagnétiques sur une surface supérieure et une surface latérale d'un dispositif à semi-conducteur ayant une pluralité de bornes saillantes formées sur une surface inférieure de celui-ci. L'invention concerne en outre un support de dispositif à semi-conducteur sur lequel une pluralité de dispositifs à semi-conducteur est fixée afin d'effectuer un processus de formation de couches de protection contre les interférences électromagnétiques (13) pour former des couches de protection contre les interférences électromagnétiques (13) sur une surface supérieure et sur une surface latérale d'un dispositif à semi-conducteur ayant une pluralité de bornes saillantes (12) formée sur une surface inférieure de celui-ci, le support comprenant : un élément de base en forme de plaque (100) présentant une rigidité prédéterminée et ayant une pluralité de premiers trous traversants (101) formés en une dimension correspondant à des zones de borne dans lesquelles les bornes saillantes (12) des dispositifs à semi-conducteur respectifs sont formées; et une couche de fixation (200) formée sur une surface supérieure de l'élément de base (100) de sorte que les zones de borne sont exposées sur le côté inférieur des premiers trous traversants (101) et les bords des zones de borne puissent être fixées à l'élément de base (100).
PCT/KR2017/004898 2016-05-11 2017-05-11 Support de dispositif à semi-conducteur, son procédé de fabrication, et dispositif de manipulation de dispositif comprenant celui-ci WO2017196109A1 (fr)

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KR10-2016-0057833 2016-05-11
KR1020160057833A KR20170127324A (ko) 2016-05-11 2016-05-11 반도체소자 캐리어, 이의 제조방법 및 이를 포함하는 소자핸들러

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Publication number Priority date Publication date Assignee Title
SG10201901908XA (en) * 2019-03-04 2020-10-29 Rokko Systems Pte Ltd Improved sputtering processing and apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003040389A (ja) * 2001-08-01 2003-02-13 Ricoh Co Ltd 半導体集積回路装置用トレイ
KR100748482B1 (ko) * 2006-01-23 2007-08-10 미래산업 주식회사 반도체 소자 테스트 핸들러
KR20110002496A (ko) * 2008-05-02 2011-01-07 이뮤노베이티브 테라피스, 엘티디. 백신 조성물 및 방법
KR101501735B1 (ko) * 2014-09-23 2015-03-12 제너셈(주) 반도체패키지의 ｅｍｉ 쉴드 처리공법
KR101604582B1 (ko) * 2015-08-24 2016-03-17 (주) 에스에스피 반도체 패키지 코팅 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910010A (en) * 1994-04-26 1999-06-08 Hitachi, Ltd. Semiconductor integrated circuit device, and process and apparatus for manufacturing the same
CN101969053B (zh) * 2008-05-16 2012-12-26 精材科技股份有限公司 半导体装置及其制造方法
US8508103B2 (en) * 2009-03-23 2013-08-13 Sonavation, Inc. Piezoelectric identification device and applications thereof
US9362196B2 (en) * 2010-07-15 2016-06-07 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
JP2015115558A (ja) * 2013-12-13 2015-06-22 株式会社東芝 半導体装置
JP6219155B2 (ja) * 2013-12-13 2017-10-25 東芝メモリ株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003040389A (ja) * 2001-08-01 2003-02-13 Ricoh Co Ltd 半導体集積回路装置用トレイ
KR100748482B1 (ko) * 2006-01-23 2007-08-10 미래산업 주식회사 반도체 소자 테스트 핸들러
KR20110002496A (ko) * 2008-05-02 2011-01-07 이뮤노베이티브 테라피스, 엘티디. 백신 조성물 및 방법
KR101501735B1 (ko) * 2014-09-23 2015-03-12 제너셈(주) 반도체패키지의 ｅｍｉ 쉴드 처리공법
KR101604582B1 (ko) * 2015-08-24 2016-03-17 (주) 에스에스피 반도체 패키지 코팅 장치

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KR20170127324A (ko) 2017-11-21
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