WO2017196109A1 - Semiconductor device carrier, manufacturing method therefor, and device handler including same - Google Patents

Semiconductor device carrier, manufacturing method therefor, and device handler including same Download PDF

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Publication number
WO2017196109A1
WO2017196109A1 PCT/KR2017/004898 KR2017004898W WO2017196109A1 WO 2017196109 A1 WO2017196109 A1 WO 2017196109A1 KR 2017004898 W KR2017004898 W KR 2017004898W WO 2017196109 A1 WO2017196109 A1 WO 2017196109A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
base member
hole
carrier
semiconductor
Prior art date
Application number
PCT/KR2017/004898
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French (fr)
Korean (ko)
Inventor
유홍준
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(주)제이티
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Publication date
Application filed by (주)제이티 filed Critical (주)제이티
Publication of WO2017196109A1 publication Critical patent/WO2017196109A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67386Closed carriers characterised by the construction of the closed carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67132Apparatus for placing on an insulating substrate, e.g. tape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Definitions

  • the present invention relates to an EMI shielding process, and more particularly, to an EMI shielding process of forming an EMI shielding layer on the top and side surfaces of a semiconductor device having a plurality of projecting terminals formed on a bottom thereof.
  • noise electromagnetic noise
  • the device Because of the circuitry to block noise, the device becomes thicker and smaller, and it becomes a barrier to thin film, so it is necessary to develop EMI shielding technology to solve this problem.
  • semiconductor chip EMI shielding is achieved by adding an ultra thin metal coating process on the packaging surface.
  • the semiconductor chip according to a surface mounter technology (SMT) method, that is, a method mounted on a printed circuit board (PCB), a flat flat package (QFP), a land grid array (LGA), a ball grid array (BGA) and the like.
  • SMT surface mounter technology
  • PCB printed circuit board
  • QFP flat flat package
  • LGA land grid array
  • BGA ball grid array
  • SOP Small out-line package
  • a BGA chip in which a ball-shaped electrode is formed at a lower portion thereof has a lot of gaps in a lower portion thereof, and thus a gap is formed in a lower empty space, thereby making it difficult to completely shield EMI.
  • the through hole is formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to form a shield layer in the terminal or the like during the EMI shielding process It is to provide a semiconductor device carrier that can be prevented.
  • Another object of the present invention is to provide a base member having rigidity in order to prevent stiffness deterioration due to formation of a through hole of a corresponding size in a terminal area formed on a bottom surface of a semiconductor element in loading a plurality of semiconductor elements to form an EMI shield. And an adhesion layer to which the bottom of the semiconductor device is attached, thereby providing a semiconductor device carrier on which semi-element devices can be stably loaded.
  • Still another object of the present invention is to provide an element handler for loading elements from a tray on which a plurality of elements are loaded to an EMI shield tray to form an EMI shield.
  • the present invention is an EMI shield for forming an EMI shield layer 13 on the top and side surfaces of a semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface
  • the plurality of semiconductor devices having a predetermined rigidity and a size corresponding to the terminal area in which the protruding terminals 12 of each semiconductor device are formed are formed.
  • a semiconductor device carrier comprising a.
  • the semiconductor device carrier may further include a frame 300 coupled to an upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed upward. have.
  • the base member 100 may have a disk-shaped wafer shape, or various shapes such as a rectangle and an octagon.
  • the adhesion layer 200 may be formed by a double-sided tape attached to an upper surface of the base member 100.
  • the double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or less than the first through-hole 101 at the same position as the first through-hole 101. Can be.
  • the attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101) ) May be formed.
  • the present invention a plurality of the semiconductor device to perform the process of forming the EMI shield layer 13 to form the EMI shield layer 13 on the upper and side surfaces of the semiconductor device having a plurality of projecting terminals 12 formed on the bottom surface
  • a method of manufacturing a semiconductor device carrier to be attached the plate-shaped base member 100 having a predetermined rigidity and having a plurality of first through holes 101 formed in a size corresponding to a terminal area in which a protruding terminal 12 of each semiconductor device is formed.
  • a base member providing step of providing; The attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100.
  • Forming an adhesion layer After the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100, the second through hole with the same or smaller size as the first through hole 101 at the same position as the first through hole 101.
  • a method for manufacturing a semiconductor device carrier comprising the step of forming a second through hole forming a 201.
  • the adhesion layer 200 is a double-sided tape attached to the upper surface of the base member 100, the second through-hole forming step, the laser drilling to drill the same position as the first through-hole 101 using a laser It may include a step.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step, may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
  • a device handler comprising at least one transfer tool attached to the semiconductor device carrier.
  • the carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
  • the transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
  • the device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device picked up by the transfer tool 400, wherein the image Analyzing the image of the bottom surface obtained by the acquisition unit 30 by the movement of at least one of the XY movement and the horizontal rotation movement so that the semiconductor device is positioned in a predetermined loading position on the semiconductor device carrier by the carrier table 700 ) Can be moved.
  • through holes are formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to prevent the shield layer from being formed during the EMI shielding process. There is this.
  • the semiconductor device carrier according to the present invention the base having a rigidity in order to prevent the degradation of the rigidity caused by the formation of the through-holes of the corresponding size of the terminal region formed on the bottom surface of the semiconductor device in the plurality of stacks to form the EMI shield Since the bottom surface of the member and the semiconductor device is composed of an adhesion layer, there is an advantage in that the semi-elements can be loaded and transported stably.
  • the device handler according to the present invention is made of an adhesion layer to which the semiconductor device is attached and a base member made of a material having a rigidity greater than that of the adhesion layer, for example, a metal material, a synthetic resin material, etc.
  • a base member made of a material having a rigidity greater than that of the adhesion layer, for example, a metal material, a synthetic resin material, etc.
  • the device handler in loading a semiconductor device in the EMI shield semiconductor device carrier having the above configuration from a tray on which a plurality of semiconductor devices are loaded, the carrier table on both sides of the carrier table based on the transfer direction of the tray
  • the carrier table By installing a pair and installing a pair of transfer tools corresponding to each of the pair of carrier tables, it is possible to greatly improve the transfer efficiency of semiconductor elements that pick up the semiconductor elements from the tray and attach them to the carriers loaded on the carrier table. have.
  • FIG. 1 is a plan view showing a semiconductor device carrier according to the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II ′ of the semiconductor device carrier of FIG. 1.
  • FIG. 3 is an enlarged view illustrating an enlarged portion A of FIG. 2.
  • FIG. 4 is a perspective view illustrating a base member constituting the semiconductor device carrier of FIG. 1.
  • FIG. 5 is a plan view showing a device handler according to the present invention.
  • FIG. 6 is a sectional view taken along the line II-II 'of the device handler of FIG.
  • FIG. 7 is a cross-sectional view illustrating a vertical cross section of the device handler of FIG. 5.
  • FIG. 8 is a bottom view illustrating an example of a device seated on a semiconductor device carrier according to the present invention.
  • the semiconductor device carrier according to the present invention is configured to be loaded for performing an EMI shielding process for forming an EMI shield for shielding electromagnetic waves on a surface of a semiconductor device such as a system semiconductor.
  • the EMI shielding process includes loading a semiconductor device into a semiconductor device carrier for EMI shielding, and forming an EMI shield layer to form an EMI shield layer on upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier. It includes.
  • the loading step may be performed by various methods as the step of loading the semiconductor device in the semiconductor device carrier for EMI shield.
  • the semiconductor device carrier for device loading before the loading step is supplied to the device handler for device loading through a semiconductor device carrier manufacturing method to be described later.
  • the EMI shield layer forming step may be performed by various methods as a step of forming an EMI shield layer on the upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier through a deposition process such as sputtering or spraying.
  • the EMI shielding process is completed after a dry process and the like, and a process of unloading from the semiconductor device carrier may be performed for performing or shipping the subsequent process.
  • the semiconductor device carrier for the EMI shield needs to have a semiconductor device loaded thereon except for a bottom on which terminals are formed, that is, an EMI shield layer may be formed on the top and side surfaces of the semiconductor devices.
  • the semiconductor device 10 is an element forming an IC chip such as a display drive IC (DDI) such as a chip on glass (COG) or a chip on film (COF), an LED element, or the like, and a wafer is a so-called semiconductor. It may correspond to a device that has completed a process and a cutting process (also a test process and a classification process).
  • a display drive IC such as a chip on glass (COG) or a chip on film (COF), an LED element, or the like
  • a wafer is a so-called semiconductor. It may correspond to a device that has completed a process and a cutting process (also a test process and a classification process).
  • the semiconductor device 10 is a ball grid array package device, in which a hemispherical solder terminal is arranged in a two-dimensional array on a rear surface of a printed circuit board (PCB). It may correspond to a semiconductor package instead of.
  • PCB printed circuit board
  • the semiconductor device 10 may have a plurality of hemispherical protrusion terminals 12 formed on a bottom surface thereof.
  • the semiconductor device 10 may be loaded on the tray 20 and transported, as shown in FIGS. 5 to 6.
  • the process of forming the EMI shield layer 13 is a process of forming the EMI shield layer 13 on the top and side surfaces of the semiconductor device 10 having the plurality of protruding terminals 12 formed on the bottom thereof.
  • the EMI shield layer 13 may be formed by spraying or depositing a metal material on the top and side surfaces of the semiconductor device 10.
  • the device handler is configured to load the semiconductor device 10 from the tray 20 on which the plurality of semiconductor devices 10 are loaded to the semiconductor device carrier.
  • the device handler is configured to load the semiconductor device 10 from the tray 20 on which the plurality of semiconductor devices 10 are loaded to the semiconductor device carrier.
  • Various configurations are possible.
  • the device handler may include: a loading unit in which trays 20 in which a plurality of semiconductor devices are loaded are loaded; At least one carrier table 700 positioned on at least one side of the loading unit based on a transport direction of the tray 20 and horizontally moving a carrier for loading of semiconductor devices; The semiconductor device is picked up from the tray 20 in the loading unit, and the terminal area is exposed to the lower side of the first through hole 101 on the carriers loaded on the carrier tables 700, and the edges of the terminal areas are exposed to the semiconductor device carrier. It may include one or more transfer tool 400 to attach.
  • the loading unit may be configured in a variety of configurations in which the trays 20 in which the plurality of semiconductor devices are loaded are loaded to the device withdrawal positions.
  • the loading unit transfers the tray 20 loaded with the semiconductor elements 10 to be loaded from the loading position to the extraction position, and transfers the tray 20 from which the device is completed to the unloading position. It may include a tray transfer unit 600 to.
  • the loading unit may include a tray loading part 630 in which a tray on which the device 10 is seated in the unloading position is loaded.
  • the tray transfer part 600 may include a guide rail 610 which is installed to face each other around the element extraction position so that the tray 20 drawn out of the tray loading part 630 moves horizontally. .
  • the loading unit may be driven in the vertical direction to recover the tray 20, the device withdrawal is completed.
  • the carrier table 700 is located on at least one side of the loading unit with respect to the conveying direction of the tray 20 and is configured in various configurations to horizontally move the semiconductor device carrier to load the semiconductor devices 10 in the semiconductor device carrier. This is possible.
  • the carrier table 700 receives the semiconductor device carrier from the carrier loading unit 900 so that the transfer device 400 can load the device 10 picked up from the tray 20.
  • the configuration for moving in the horizontal direction various configurations such as an XY table and an XY- ⁇ table are possible.
  • the carrier loading unit 900 is configured to move the semiconductor device carrier to the carrier table 700 in sequence and can be configured in various ways.
  • the carrier loading unit 900 may include a carrier loading unit in which a plurality of carriers are loaded.
  • the carrier table 700 may be moved in the vertical direction, that is, the Z axis direction.
  • the carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
  • the carrier table 700 may include a carrier transfer unit (not shown) which transfers the semiconductor device carrier from which the device 10 is loaded from the tray 20 to the carrier unloading unit 800 by the transfer tool 400. Can be.
  • the semiconductor device carrier may be conveyed to the EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process after the semiconductor device 10 is loaded.
  • the transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
  • the transfer tool 400 may be combined with a guide 500 for linear movement of the transfer tool 400.
  • the transfer tool 400 may be coupled to both sides of the guide 500 or to the same side.
  • the transfer tool 400 may include a first transfer tool 410 corresponding to the first semiconductor device carrier table 700 located on one side of the loading unit and a second semiconductor device carrier table 700 located on the other side of the loading unit.
  • the second transfer tool 420 corresponding to and may be installed in pairs.
  • the first transfer tool 410 transfers the semiconductor device 10 to the first semiconductor device carrier along the first path
  • the second transfer tool 420 may be formed of the first transfer tool 420.
  • Various configurations are possible by transferring the semiconductor device 10 to the second semiconductor device carrier along the two paths ().
  • first transfer tool 410 and the second transfer tool 420 may be configured to alternately transfer the elements so as not to interfere with each other when the semiconductor element 10 is drawn out from the withdrawal position.
  • the transfer tool 400 is a configuration for transferring the element 10 from the tray 20 to the semiconductor element carrier, and can be configured in various ways according to the pick-up method. It may be configured to include an adsorption head (not shown) for generating the adsorption to pick up the element 10.
  • the device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device 10 picked up by the transfer tool 400. can do.
  • the image obtained by the image acquisition unit 30 may perform a vision inspection on the bottom surface of the semiconductor device 10 adsorbed on the adsorption pad of the transfer tool 400.
  • the image obtained by the image acquisition unit 30, the semiconductor device (suitable for a suitable mounting position on the semiconductor device carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201) It can be utilized to check the horizontal state of the semiconductor device 10 picked up by the transfer tool 400 so that 10) can be loaded.
  • the device handler analyzes an image of the bottom surface obtained by the image acquisition unit 30 to move the semiconductor device to at least one of an XY movement and a horizontal rotational movement so that the semiconductor device is positioned at a preset loading position on the semiconductor device carrier.
  • the carrier table 700 may be moved.
  • the transfer tool 400 picking up the semiconductor element 10 is rotated so as to be suitable for the proper seating position on the semiconductor element carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201.
  • the semiconductor device 10 can be loaded.
  • the semiconductor device carrier on which the semiconductor device 10 is loaded by the device handler may move to the carrier unloading unit 900 and be transferred to an EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process. have.
  • the device handler having the above configuration may be configured as part of an inline system that is inlined from the above-described device loading to the unloading after EMI shielding.
  • the bottom surface of the semiconductor device 10 is not closely adhered to the semiconductor device carrier due to the influence of the protruding terminal 12 formed on the bottom surface of the semiconductor device 10.
  • the formation of the EMI shield layer 13 is not completely made.
  • the conventional semiconductor device carrier has a problem in that the shape of the support surface is not stably maintained during the carrier transfer process by attaching the semiconductor device 10 to a support surface formed of a thin and flexible material such as a tape.
  • the semiconductor device carrier according to the present invention, EMI shield layer 13 to form an EMI shield layer 13 on the upper surface and the side of the semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface
  • the semiconductor device carrier has a predetermined rigidity and has a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device is formed.
  • Plate-shaped base member 100 is formed; An attachment layer 200 formed on an upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region is attached to the base member 100; The frame 300 is coupled to the upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed to the upper portion.
  • the base member 100 is a plate-shaped member having a predetermined rigidity, and a plurality of first through holes 101 are formed to have a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device 10 is formed. Can be.
  • the first through hole 101 may have a size smaller than that of the semiconductor device 10 and larger than a terminal region in which the protruding terminal 12 is formed.
  • the first through hole 101 may have various shapes in such a manner as to support an edge at which the protruding terminal 12 of the bottom surface of the semiconductor device 10 is not formed.
  • the first through hole 101 may have a shape corresponding to a planar shape of the semiconductor device 10, for example, a rectangular shape, the boundary of which the protruding terminal 12 of the bottom surface of the semiconductor device 10 may be formed. It may be formed to be located between the terminal area and the edge.
  • the first through hole 101 is larger in size than the terminal area w in which the protruding terminal 12 is formed, and is larger than the bottom surface of the semiconductor device 10. It may be formed to be small so as to contact an edge outside the terminal region w of the semiconductor device 10.
  • the first through hole 101 is preferably located in the circumferential region d1 + d2 excluding the terminal region of the semiconductor device 10.
  • the base member 100, the base member 100 may have a variety of shapes, such as a disk-shaped wafer shape or octagonal, rectangular, but is not limited thereto.
  • the base member 100 may have various materials as long as it is a material capable of supporting the semiconductor device 10 loaded with predetermined rigidity without shaking.
  • the base member 100 may have a material that is harder than the material of the metal and the adhesion layer 200 described later.
  • the attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region can be attached to the base member 100.
  • Various configurations are possible.
  • the adhesion layer 200 may be formed by an adhesive tape having an adhesive attached to the upper surface of the base member 100, for example, the adhesive tape may correspond to a double-sided tape. have.
  • the double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or smaller in size with the first through-hole 101. Can be.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It may include an adhesive material bonded to the upper surface of the film.
  • the attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101). Can be formed.
  • the frame 300 is configured to be coupled to the upper surface of the base member 100 so that the region in which the first through holes 101 are formed in the base member 100 is exposed to the top.
  • the frame 300 may be configured as a coupling ring coupled to an edge of the adhesive layer 200 so that the region where the first through holes 101 are formed is exposed upward.
  • the frame 300 may have various shapes such as a circle and a rectangle.
  • the frame 300 is not an essential configuration, it corresponds to a configuration that can be selectively adopted.
  • a method of manufacturing a semiconductor device carrier to which a plurality of semiconductor devices are attached to perform a method comprising: a plurality of first through holes 101 having a predetermined rigidity and corresponding to a terminal area in which protrusion terminals 12 of each semiconductor device are formed; A base member providing step of providing a plate-shaped base member 100 formed thereon; Attachment layer forming step of forming the attachment layer 200 on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100.
  • the second through hole 201 is formed in the same position as or less than the first through hole 101 at the same position as the first through hole 101. It can be produced by a semiconductor device carrier manufacturing method comprising a second through-hole forming step to form.
  • the adhesion layer 200 is a double-sided tape is attached to the upper surface of the base member 100, the second through-hole forming step, drilling the same position as the first through-hole 101 using a laser It may include a laser drilling step.
  • the adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
  • the semiconductor device carrier manufacturing method the first through-hole (at the same position as the first through-hole 101 in the attachment layer 200 before the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100 ( The second through-hole forming step of forming the second through-hole 201 with the same or smaller size than that of 101 is performed, and the attachment layer 200 having the second through-hole 201 is formed on the base member 100.
  • An adhesive layer forming step of attaching the first through hole 101 and the second through hole 201 to correspond to each other may be performed.

Abstract

The present invention relates to an EMI shield process and, more specifically, to an EMI shield process for forming EMI shield layers on an upper surface and a lateral surface of a semiconductor device having a plurality of protruding terminals formed on a lower surface thereof. Disclosed is a semiconductor device carrier to which a plurality of semiconductor devices is attached in order to perform an EMI shield layer (13) formation process for forming EMI shield layers (13) on an upper surface and a lateral surface of a semiconductor device having a plurality of protruding terminals (12) formed on a lower surface thereof, the carrier comprising: a plate-shaped base member (100) having a preset rigidity and having a plurality of first through-holes (101) formed in a size corresponding to terminal areas in which the protruding terminals (12) of the respective semiconductor devices are formed; and an attachment layer (200) formed on an upper surface of the base member (100) such that the terminal areas are exposed to the lower side of the first through-holes (101) and edges of the terminal areas can be attached to the base member (100).

Description

반도체소자 캐리어, 이의 제조방법 및 이를 포함하는 소자핸들러Semiconductor device carrier, manufacturing method thereof and device handler comprising same
본 발명은 EMI 실드 공정에 관한 것으로서, 보다 상세하게는 저면에 복수의 돌출단자들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층을 형성하는 EMI 실드 공정에 관한 것이다.The present invention relates to an EMI shielding process, and more particularly, to an EMI shielding process of forming an EMI shielding layer on the top and side surfaces of a semiconductor device having a plurality of projecting terminals formed on a bottom thereof.
최근의 휴대전화와 스마트폰은 국제화 시대에 대응하고 기능을 향상하기 위해서 기기에 탑재하는 무선시스템의 수가 늘고 있다.In recent years, mobile phones and smartphones are increasing in number of wireless systems installed in devices in order to cope with internationalization and improve their functions.
한편 내장회로의 클럭(clock) 주파수와 데이터 전송속도는 빨라져서 무선시스템에서 사용하는 전자기 잡음(이하 잡음으로 약기)이 발생하기 쉽다. 이 잡음이 무선시스템에 간섭하여 수신감도가 나빠지는데 이 현상을 "자가중독" 현상이라고 부른다.On the other hand, the clock frequency and data transmission speed of embedded circuits are increased, and electromagnetic noise (hereinafter, abbreviated as noise) used in a wireless system is likely to occur. This noise interferes with the wireless system, resulting in poor reception. This phenomenon is called "self-adding".
잡음을 차단하기 위한 회로 때문에 기기가 두꺼워져서 소형화하고, 박형화(thin film)하는데 장애가 되므로, 이것을 해결하기 위한 EMI 차폐기술 개발이 필요하게 되었다.Because of the circuitry to block noise, the device becomes thicker and smaller, and it becomes a barrier to thin film, so it is necessary to develop EMI shielding technology to solve this problem.
일반적으로, 반도체 칩 EMI 차폐는 패키징 표면에 초박 금속을 씌우는 공정을 추가함으로써 이뤄진다. In general, semiconductor chip EMI shielding is achieved by adding an ultra thin metal coating process on the packaging surface.
한편, 반도체 칩은, SMT(Surface mounter technology) 방식, 즉, PCB(Printed circuit board)에 실장되는 방식에 따라, QFP(Quard flat package), LGA(Land grid array), BGA(Ball grid array) 및 SOP(Small out-line package) 등으로 분류될 수 있다.On the other hand, the semiconductor chip, according to a surface mounter technology (SMT) method, that is, a method mounted on a printed circuit board (PCB), a flat flat package (QFP), a land grid array (LGA), a ball grid array (BGA) and the like. SOP (Small out-line package) and the like.
이 중 하부에 볼 형태 전극이 형성되는 BGA 칩은, 아래쪽에 빈틈이 많아 하부 빈 공간에 틈이 형성되어 완벽한 EMI 차폐가 어렵다는 문제점이 있다.Among these, a BGA chip in which a ball-shaped electrode is formed at a lower portion thereof has a lot of gaps in a lower portion thereof, and thus a gap is formed in a lower empty space, thereby making it difficult to completely shield EMI.
본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여, EMI 실드를 형성함에 있어서, 반도체소자의 저면에 형성된 단자영역 대응되는 크기로 관통공이 형성됨으로써 EMI 실드 공정 수행시 단자 등에 실드층이 형성되는 것을 방지할 수 있는 반도체소자 캐리어를 제공하는 데 있다.An object of the present invention, in order to solve the above problems, in forming the EMI shield, the through hole is formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to form a shield layer in the terminal or the like during the EMI shielding process It is to provide a semiconductor device carrier that can be prevented.
본 발명의 다른 목적은, EMI 실드를 형성하기 위하여 복수의 반도체소자들을 적재함에 있어서 반도체소자의 저면에 형성된 단자영역 대응되는 크기의 관통공의 형성에 의한 강성 저하를 방지하기 위하여 강성을 가지는 베이스부재 및 반도체소자의 저면이 부착되는 부착층으로 구성됨으로써 반소체소자들이 안정적으로 적재될 수 있는 반도체소자 캐리어를 제공하는데 있다.Another object of the present invention is to provide a base member having rigidity in order to prevent stiffness deterioration due to formation of a through hole of a corresponding size in a terminal area formed on a bottom surface of a semiconductor element in loading a plurality of semiconductor elements to form an EMI shield. And an adhesion layer to which the bottom of the semiconductor device is attached, thereby providing a semiconductor device carrier on which semi-element devices can be stably loaded.
또한, 본 발명의 또 다른 목적은, EMI 실드를 형성하기 위하여 다수의 소자들이 적재된 트레이로부터 EMI 실드용 트레이로 소자들을 적재하는 소자핸들러를 제공하는 데 있다.Still another object of the present invention is to provide an element handler for loading elements from a tray on which a plurality of elements are loaded to an EMI shield tray to form an EMI shield.
본 발명은 상기와 같은 본 발명의 목적을 달성하기 위하여 창출된 것으로서 , 본 발명은 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 상기 반도체소자들이 부착되는 반도체소자 캐리어에 있어서, 미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)와; 상기 단자영역이 상기 제1관통구(101)의 하측으로 노출되고 상기 단자영역의 가장자리가 상기 베이스부재(100)에 부착될 수 있도록 상기 베이스부재(100)의 상면에 형성된 부착층(200)를 포함하는 것을 특징으로 하는 반도체소자 캐리어를 개시한다.The present invention was created in order to achieve the object of the present invention as described above , the present invention is an EMI shield for forming an EMI shield layer 13 on the top and side surfaces of a semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface In the semiconductor device carrier to which the plurality of semiconductor devices are attached to perform the process of forming the layer 13, the plurality of semiconductor devices having a predetermined rigidity and a size corresponding to the terminal area in which the protruding terminals 12 of each semiconductor device are formed are formed. A plate-shaped base member 100 in which one through holes 101 are formed; Attaching layer 200 formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area can be attached to the base member 100 Disclosed is a semiconductor device carrier comprising a.
상기 반도체소자 캐리어는, 상기 베이스부재(100) 중 상기 제1관통구(101)들이 형성된 영역이 상부로 노출되도록 상기 베이스부재(100)의 상면에 결합되는 프레임(300)을 추가로 포함할 수 있다.The semiconductor device carrier may further include a frame 300 coupled to an upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed upward. have.
상기 베이스부재(100)는, 원판 형상의 웨이퍼 형상, 또는 직사각형, 팔각형 등 다양한 형상을 가질 수 있다.The base member 100 may have a disk-shaped wafer shape, or various shapes such as a rectangle and an octagon.
상기 부착층(200)은, 상기 베이스부재(100)의 상면에 부착되는 양면테이프에 의하여 형성될 수 있다.The adhesion layer 200 may be formed by a double-sided tape attached to an upper surface of the base member 100.
상기 양면테이프는, 상기 베이스부재(100)에 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성될 수 있다.The double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or less than the first through-hole 101 at the same position as the first through-hole 101. Can be.
상기 부착층(200)은, 상기 베이스부재(100)의 상면에 형성되는 필름과; 상기 필름의 상면에 접합되는 접착물질을 포함할 수 있다.The adhesion layer 200, the film formed on the upper surface of the base member 100; It may include an adhesive material bonded to the upper surface of the film.
상기 부착층(200)은, 상기 베이스부재(100)에 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성될 수 있다.The attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101) ) May be formed.
또한 본 발명은, 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 상기 반도체소자들이 부착되는 반도체소자 캐리어 제조방법으로서, 미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)를 제공하는 베이스부재 제공단계와; 상기 단자영역이 상기 제1관통구(101)의 하측으로 노출되고 상기 단자영역의 가장자리가 상기 베이스부재(100)에 부착될 수 있도록 상기 베이스부재(100)의 상면에 부착층(200)을 형성하는 부착층 형성단계와; 상기 판상형의 베이스부재(100) 상면에 상기 부착층(200)이 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)를 형성하는 제2관통구 형성단계를 포함하는 것을 특징으로 하는 반도체소자 캐리어 제조방법을 개시한다.In addition, the present invention, a plurality of the semiconductor device to perform the process of forming the EMI shield layer 13 to form the EMI shield layer 13 on the upper and side surfaces of the semiconductor device having a plurality of projecting terminals 12 formed on the bottom surface A method of manufacturing a semiconductor device carrier to be attached, the plate-shaped base member 100 having a predetermined rigidity and having a plurality of first through holes 101 formed in a size corresponding to a terminal area in which a protruding terminal 12 of each semiconductor device is formed. A base member providing step of providing; The attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100. Forming an adhesion layer; After the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100, the second through hole with the same or smaller size as the first through hole 101 at the same position as the first through hole 101. Disclosed is a method for manufacturing a semiconductor device carrier comprising the step of forming a second through hole forming a 201.
상기 부착층(200)은, 상기 베이스부재(100)의 상면에 부착되는 양면테이프이며, 제2관통구 형성단계는, 상기 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함할 수 있다.The adhesion layer 200 is a double-sided tape attached to the upper surface of the base member 100, the second through-hole forming step, the laser drilling to drill the same position as the first through-hole 101 using a laser It may include a step.
상기 부착층(200)은, 상기 베이스부재(100)의 상면에 형성되는 필름과; 상기 필름의 상면에 접합되는 접착물질을 포함하며, 제2관통구 형성단계는, 상기 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함할 수 있다.The adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step, may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
또한 본 발명은, 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여, 다수의 반도체소자들이 적재된 트레이(20)로부터 청구항 제1항에 따른 반도체소자 캐리어에 적재하는 소자핸들러로서, 다수의 반도체소자들이 적재된 트레이(20)들이 로딩되는 로딩부와; 상기 로딩부에서 트레이(20)의 이송방향을 기준으로 적어도 일측에 위치되며 반도체소자들의 적재를 위하여 상기 캐리어를 수평이동시키는 하나 이상의 캐리어테이블(700)과; 상기 로딩부에서의 트레이(20)로부터 반도체소자를 픽업하여 각 캐리어테이블(700)에 적재된 캐리어 상에 상기 단자영역을 상기 제1관통구(101)의 하측으로 노출시키고 상기 단자영역의 가장자리를 상기 반도체소자 캐리어에 부착시키는 하나 이상의 이송툴을 포함하는 소자핸들러를 개시한다.In addition, in order to perform the EMI shield layer 13 forming process of forming the EMI shield layer 13 on the top and side surfaces of the semiconductor device having a plurality of protruding terminals 12 formed on the bottom thereof, An element handler for loading a semiconductor device carrier according to claim 1 from a stacked tray 20, comprising: a loading unit in which trays 20 on which a plurality of semiconductor elements are loaded are loaded; At least one carrier table 700 positioned on at least one side of the loading unit based on a transfer direction of the tray 20 and horizontally moving the carrier for loading of semiconductor devices; The semiconductor device is picked up from the tray 20 in the loading unit to expose the terminal area to the lower side of the first through hole 101 on a carrier loaded in each carrier table 700, and the edge of the terminal area is exposed. Disclosed is a device handler comprising at least one transfer tool attached to the semiconductor device carrier.
상기 캐리어테이블(700)은, 상기 로딩부에서 트레이(20)의 이송방향을 기준으로 양측에 한 쌍으로 설치될 수 있다.The carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
상기 이송툴(400)은, 상기 한 쌍의 캐리어테이블(700) 각각에 대응되어 한 쌍으로 설치될 수 있다.The transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
상기 소자핸들러는, 상기 이송툴(400)에 의한 반도체소자의 이송경로에 설치되며 이송툴(400)에 픽업된 반도체소자의 저면을 촬영하는 이미지획득부(30)를 추가로 포함하며, 상기 이미지획득부(30)에 의하여 획득된 저면의 이미지를 분석하여 반도체소자가 상기 반도체소자 캐리어 상에 미리 설정된 적재위치에 위치되도록 X-Y 이동 및 수평회전이동 중 적어도 어느 하나의 이동에 의하여 상기 캐리어테이블(700)을 이동시킬 수 있다.The device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device picked up by the transfer tool 400, wherein the image Analyzing the image of the bottom surface obtained by the acquisition unit 30 by the movement of at least one of the XY movement and the horizontal rotation movement so that the semiconductor device is positioned in a predetermined loading position on the semiconductor device carrier by the carrier table 700 ) Can be moved.
본 발명에 따른 반도체소자 캐리어는, EMI 실드를 형성함에 있어서, 반도체소자의 저면에 형성된 단자영역 대응되는 크기로 관통공이 형성됨으로써 EMI 실드 공정 수행시 단자 등에 실드층이 형성되는 것을 방지할 수 있는 이점이 있다.In the semiconductor device carrier according to the present invention, through holes are formed in a size corresponding to the terminal area formed on the bottom surface of the semiconductor device to prevent the shield layer from being formed during the EMI shielding process. There is this.
또한, 본 발명에 따른 반도체소자 캐리어는, EMI 실드를 형성하기 위하여 복수들을 적재함에 있어서 반도체소자의 저면에 형성된 단자영역 대응되는 크기의 관통공의 형성에 의한 강성 저하를 방지하기 위하여 강성을 가지는 베이스부재 및 반도체소자의 저면이 부착되는 부착층으로 구성됨으로써 반소체소자들을 안정적인 적재 및 이송이 가능한 이점이 있다.In addition, the semiconductor device carrier according to the present invention, the base having a rigidity in order to prevent the degradation of the rigidity caused by the formation of the through-holes of the corresponding size of the terminal region formed on the bottom surface of the semiconductor device in the plurality of stacks to form the EMI shield Since the bottom surface of the member and the semiconductor device is composed of an adhesion layer, there is an advantage in that the semi-elements can be loaded and transported stably.
구체적으로, 본 발명에 따른 소자 핸들러는, 반도체소자가 부착되는 부착층 및 부착층보다 강성이 큰 재질, 예를 들면 금속재질, 합성수지재질 등으로 이루어진 베이스부재로 이루어짐으로써 반도체소자의 적재 및 이송 등 핸들링이 용이한데 이점이 있다.Specifically, the device handler according to the present invention is made of an adhesion layer to which the semiconductor device is attached and a base member made of a material having a rigidity greater than that of the adhesion layer, for example, a metal material, a synthetic resin material, etc. There is an advantage in being easy to handle.
또한, 본 발명에 따른 소자 핸들러는, 다수의 반도체소자들이 적재된 트레이로부터 상기와 같은 구성을 가지는 EMI 실드용 반도체 소자 캐리어에 반도체소자를 적재함에 있어서 트레이의 이송방향을 기준으로 캐리어테이블을 양측에 쌍으로 설치하고 한 쌍의 캐리어테이블 각각에 대응되는 한 쌍의 이송툴을 설치함으로써, 트레이로부터 반도체소자를 픽업하여 캐리어테이블에 적재된 캐리어에 부착시키는 반도체소자 이송 효율을 크게 향상시킬 수 있는 이점이 있다.In addition, the device handler according to the present invention, in loading a semiconductor device in the EMI shield semiconductor device carrier having the above configuration from a tray on which a plurality of semiconductor devices are loaded, the carrier table on both sides of the carrier table based on the transfer direction of the tray By installing a pair and installing a pair of transfer tools corresponding to each of the pair of carrier tables, it is possible to greatly improve the transfer efficiency of semiconductor elements that pick up the semiconductor elements from the tray and attach them to the carriers loaded on the carrier table. have.
도 1은, 본 발명에 따른 반도체소자 캐리어를 보여주는 평면도이다.1 is a plan view showing a semiconductor device carrier according to the present invention.
도 2는, 도 1의 반도체소자 캐리어의 Ⅰ-Ⅰ'방향 단면도이다.FIG. 2 is a cross-sectional view taken along the line II ′ of the semiconductor device carrier of FIG. 1.
도 3은, 도 2의 A부분을 확대하여 보여주는 확대도이다.3 is an enlarged view illustrating an enlarged portion A of FIG. 2.
도 4는, 도 1의 반도체소자 캐리어를 구성하는 베이스부재를 보여주는 사시도이다.4 is a perspective view illustrating a base member constituting the semiconductor device carrier of FIG. 1.
도 5는, 본 발명에 따른 소자핸들러를 보여주는 평면도이다.5 is a plan view showing a device handler according to the present invention.
도 6은, 도 5의 소자핸들러의 Ⅱ-Ⅱ'방향 단면도이다.FIG. 6 is a sectional view taken along the line II-II 'of the device handler of FIG.
도 7은, 도 5의 소자핸들러의 수직단면을 보여주는 단면도이다.FIG. 7 is a cross-sectional view illustrating a vertical cross section of the device handler of FIG. 5.
도 8은, 본 발명에 따른 반도체 소자 캐리어에 안착되는 소자의 일 예를 보여주는 저면도이다.8 is a bottom view illustrating an example of a device seated on a semiconductor device carrier according to the present invention.
이하 본 발명에 따른 반도체소자 캐리어 및 소자핸들러에 관하여 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a semiconductor device carrier and a device handler according to the present invention will be described with reference to the accompanying drawings.
먼저 본 발명에 따른 반도체소자 캐리어는, 시스템 반도체 등 반도체 소자의 표면에 전자파 차폐를 위한 EMI 실드를 형성하는 EMI 실드 공정 수행을 위하여 적재되는 구성이다.First, the semiconductor device carrier according to the present invention is configured to be loaded for performing an EMI shielding process for forming an EMI shield for shielding electromagnetic waves on a surface of a semiconductor device such as a system semiconductor.
여기서 EMI 실드 공정은, 반도체 소자를 EMI 실드용 반도체 소자 캐리어에 반도체소자를 적재하는 적재단계와, 반도체 소자 캐리어에 적재된 반도체소자들의 상면 및 측면들에 EMI 실드층을 형성하는 EMI실드층 형성단계를 포함한다.The EMI shielding process includes loading a semiconductor device into a semiconductor device carrier for EMI shielding, and forming an EMI shield layer to form an EMI shield layer on upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier. It includes.
상기 적재단계는, 반도체 소자를 EMI 실드용 반도체 소자 캐리어에 반도체소자를 적재하는 단계로서 다양한 방법에 의하여 수행될 수 있다.The loading step may be performed by various methods as the step of loading the semiconductor device in the semiconductor device carrier for EMI shield.
여기서 상기 적재단계 전에 소자 적재를 위한 반도체 소자 캐리어는 후술하는 반도체소자 캐리어 제조방법을 거쳐 소자 적재를 위한 소자핸들러로 공급된다.Here, the semiconductor device carrier for device loading before the loading step is supplied to the device handler for device loading through a semiconductor device carrier manufacturing method to be described later.
상기 EMI실드층 형성단계는, 반도체 소자 캐리어에 적재된 반도체소자들의 상면 및 측면들에 스퍼터링, 스프레이 등의 증착공정 등을 통하여 EMI 실드층을 형성하는 단계로서 다양한 방법에 의하여 수행될 수 있다.The EMI shield layer forming step may be performed by various methods as a step of forming an EMI shield layer on the upper and side surfaces of the semiconductor devices loaded on the semiconductor device carrier through a deposition process such as sputtering or spraying.
그리고 상기 EMI실드층 형성단계 후에는 드라이 공정 등을 거친 후에 EMI실드공정이 완료되며 후속공정의 수행 또는 출하 등을 위하여 반도체 소자 캐리어로부터 언로딩하는 공정이 수행될 수 있다. After the EMI shielding layer forming step, the EMI shielding process is completed after a dry process and the like, and a process of unloading from the semiconductor device carrier may be performed for performing or shipping the subsequent process.
한편 상기 EMI 실드용 반도체 소자 캐리어는, 단자들이 형성된 저면을 제외, 즉 반도체소자들의 상면 및 측면들에 EMI 실드층가 형성될 수 있도록 반도체 소자가 적재될 필요가 있다.Meanwhile, the semiconductor device carrier for the EMI shield needs to have a semiconductor device loaded thereon except for a bottom on which terminals are formed, that is, an EMI shield layer may be formed on the top and side surfaces of the semiconductor devices.
먼저 반도체 소자를 EMI 실드용 반도체 소자 캐리어에 반도체소자를 적재하는 적재단계를 수행하는 소자핸들러에 관하여 설명한다.First, a description will be given of a device handler performing a loading step of loading a semiconductor device into a semiconductor device carrier for an EMI shield.
상기 반도체소자(10)는, COG(Chip On Glass), COF(Chip On Film)와 같은 디스플레이 구동칩인 DDI(Display Drive IC) 등의 IC칩, LED 소자 등을 이루는 소자로서, 웨이퍼가 소위 반도체 공정 및 절단 공정(또한 테스트공정 및 분류공정)을 마친 소자에 해당될 수 있다.The semiconductor device 10 is an element forming an IC chip such as a display drive IC (DDI) such as a chip on glass (COG) or a chip on film (COF), an LED element, or the like, and a wafer is a so-called semiconductor. It may correspond to a device that has completed a process and a cutting process (also a test process and a classification process).
예로서, 상기 반도체소자(10)는, 도 7에 도시된 바와 같이, 볼 그리드 어레이 패키지 소자로, 인쇄 회로 기판(PCB)의 뒷면에 반구형의 납땜 단자를 2차원 어레이상으로 줄지어 배열해 리드를 대신하는 반도체 패키지에 해당될 수 있다.For example, as shown in FIG. 7, the semiconductor device 10 is a ball grid array package device, in which a hemispherical solder terminal is arranged in a two-dimensional array on a rear surface of a printed circuit board (PCB). It may correspond to a semiconductor package instead of.
이때, 상기 반도체소자(10)는, 저면에 반구형의 복수의 돌출단자(12)들이 형성될 수 있다.In this case, the semiconductor device 10 may have a plurality of hemispherical protrusion terminals 12 formed on a bottom surface thereof.
그리고 상기 반도체소자(10)는, 도 5 내지 도 6에 도시된 바와 같이, 트레이(20)에 적재되어 이송될 수 있다.The semiconductor device 10 may be loaded on the tray 20 and transported, as shown in FIGS. 5 to 6.
본 발명에서 EMI 실드층(13) 형성 공정은, 저면에 복수의 돌출단자(12)들이 형성된 반도체소자(10)의 상면 및 측면에 EMI 실드층(13)을 형성하는 공정이다.In the present invention, the process of forming the EMI shield layer 13 is a process of forming the EMI shield layer 13 on the top and side surfaces of the semiconductor device 10 having the plurality of protruding terminals 12 formed on the bottom thereof.
상기 EMI 실드층(13)은, 반도체소자(10)의 상면 및 측면에 금속물질이 스프레이 되거나 증착되어 형성될 수 있다.The EMI shield layer 13 may be formed by spraying or depositing a metal material on the top and side surfaces of the semiconductor device 10.
상기 소자핸들러는, 반도체소자(10)에 EMI 실드층(13)을 형성하기 위하여, 반도체소자(10)를 다수의 반도체소자(10)들이 적재된 트레이(20)로부터 반도체소자 캐리어에 적재하는 구성으로 다양한 구성이 가능하다.In order to form the EMI shield layer 13 on the semiconductor device 10, the device handler is configured to load the semiconductor device 10 from the tray 20 on which the plurality of semiconductor devices 10 are loaded to the semiconductor device carrier. Various configurations are possible.
예로서, 상기 소자핸들러는, 다수의 반도체소자들이 적재된 트레이(20)들이 로딩되는 로딩부와; 로딩부에서 트레이(20)의 이송방향을 기준으로 적어도 일측에 위치되며 반도체소자들의 적재를 위하여 캐리어를 수평이동시키는 하나 이상의 캐리어테이블(700)과; 로딩부에서의 트레이(20)로부터 반도체소자를 픽업하여 각 캐리어테이블(700)에 적재된 캐리어 상에 단자영역을 제1관통구(101)의 하측으로 노출시키고 단자영역의 가장자리를 반도체소자 캐리어에 부착시키는 하나 이상의 이송툴(400)를 포함할 수 있다.For example, the device handler may include: a loading unit in which trays 20 in which a plurality of semiconductor devices are loaded are loaded; At least one carrier table 700 positioned on at least one side of the loading unit based on a transport direction of the tray 20 and horizontally moving a carrier for loading of semiconductor devices; The semiconductor device is picked up from the tray 20 in the loading unit, and the terminal area is exposed to the lower side of the first through hole 101 on the carriers loaded on the carrier tables 700, and the edges of the terminal areas are exposed to the semiconductor device carrier. It may include one or more transfer tool 400 to attach.
상기 로딩부는, 다수의 반도체소자들이 적재된 트레이(20)들이 소자 인출위치로 로딩되는 구성으로 다양한 구성이 가능하다.The loading unit may be configured in a variety of configurations in which the trays 20 in which the plurality of semiconductor devices are loaded are loaded to the device withdrawal positions.
예로서, 상기 로딩부는, 로딩위치에서 로딩된 인출될 반도체소자(10)들이 적재된 트레이(20)를 인출위치까지 이송하고, 소자 인출이 완료된 트레이(20)를 인출위치에서 언로딩위치까지 이송하는 트레이이송부(600)를 포함할 수 있다.For example, the loading unit transfers the tray 20 loaded with the semiconductor elements 10 to be loaded from the loading position to the extraction position, and transfers the tray 20 from which the device is completed to the unloading position. It may include a tray transfer unit 600 to.
이때, 상기 로딩부는, 언로딩위치에서 소자(10)가 안착된 트레이가 적재되는 트레이적재부(630)를 포함할 수 있다.In this case, the loading unit may include a tray loading part 630 in which a tray on which the device 10 is seated in the unloading position is loaded.
또한, 상기 트레이이송부(600)는, 상기 트레이적재부(630)에서 인출된 트레이(20)가 수평으로 이동하도록 소자 인출위치를 중심으로 서로 대향되게 설치되는 가이드레일(610)을 포함할 수 있다.In addition, the tray transfer part 600 may include a guide rail 610 which is installed to face each other around the element extraction position so that the tray 20 drawn out of the tray loading part 630 moves horizontally. .
이때, 상기 로딩부는, 도 7에 도시된 바와 같이, 소자 인출이 완료된 트레이(20)를 회수하기 위하여 상하방향으로 구동될 수 있다.In this case, as shown in Figure 7, the loading unit may be driven in the vertical direction to recover the tray 20, the device withdrawal is completed.
상기 캐리어테이블(700)은, 로딩부에서 트레이(20)의 이송방향을 기준으로 적어도 일측에 위치되며 반도체소자 캐리어에 반도체소자(10)들을 적재하기 위하여 반도체소자 캐리어를 수평이동시키는 구성으로 다양한 구성이 가능하다.The carrier table 700 is located on at least one side of the loading unit with respect to the conveying direction of the tray 20 and is configured in various configurations to horizontally move the semiconductor device carrier to load the semiconductor devices 10 in the semiconductor device carrier. This is possible.
예로서, 상기 캐리어테이블(700)은, 캐리어로딩부(900)로부터 반도체소자 캐리어를 전달받아 이송툴(400)이 트레이(20)에서 픽업한 소자(10)를 적재할 수 있도록 반도체소자 캐리어를 수평방향으로 이동시키는 구성으로서, X-Y테이블, X-Y-Θ테이블 등 다양한 구성이 가능하다.For example, the carrier table 700 receives the semiconductor device carrier from the carrier loading unit 900 so that the transfer device 400 can load the device 10 picked up from the tray 20. As the configuration for moving in the horizontal direction, various configurations such as an XY table and an XY-Θ table are possible.
여기서, 상기 캐리어로딩부(900)는, 반도체 소자 캐리어를 순차적으로 캐리어테이블(700)로 이동시키는 구성으로 다양한 구성이 가능하다. 예로서, 상기 캐리어로딩부(900)는, 복수의 캐리어들이 적재되는 캐리어적재부를 포함할 수 있다.In this case, the carrier loading unit 900 is configured to move the semiconductor device carrier to the carrier table 700 in sequence and can be configured in various ways. For example, the carrier loading unit 900 may include a carrier loading unit in which a plurality of carriers are loaded.
또한 상기 캐리어테이블(700)은, 상하방향 즉, Z축방향으로 이동될 수도 있다.In addition, the carrier table 700 may be moved in the vertical direction, that is, the Z axis direction.
상기 캐리어테이블(700)은, 로딩부에서 트레이(20)의 이송방향을 기준으로 양측에 한 쌍으로 설치될 수 있다.The carrier table 700 may be installed in pairs on both sides of the loading unit based on the transport direction of the tray 20.
상기 캐리어테이블(700)은, 이송툴(400)에 의해 트레이(20)로부터 소자(10) 적재가 완료된 반도체 소자 캐리어를 캐리어언로딩부(800)로 전달하는 캐리어이송부(미도시)를 포함할 수 있다.The carrier table 700 may include a carrier transfer unit (not shown) which transfers the semiconductor device carrier from which the device 10 is loaded from the tray 20 to the carrier unloading unit 800 by the transfer tool 400. Can be.
이때, 상기 반도체 소자 캐리어는, 반도체 소자(10) 적재 완료 후 EMI 실드층(13) 형성 공정을 위한 EMI 실드 형성장치(미도시)로 반송될 수 있다.In this case, the semiconductor device carrier may be conveyed to the EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process after the semiconductor device 10 is loaded.
상기 이송툴(400)은, 한 쌍의 캐리어테이블(700) 각각에 대응되어 한 쌍으로 설치될 수 있다.The transfer tool 400 may be installed in pairs corresponding to each of the pair of carrier tables 700.
상기 이송툴(400)은, 도 6에 도시된 바와 같이, 이송툴(400)을 직선운동 시키는 가이드(500)와 결합될 수 있다.The transfer tool 400, as shown in Figure 6, may be combined with a guide 500 for linear movement of the transfer tool 400.
이때, 상기 이송툴(400)은, 가이드(500)의 양 측에 결합되거나 또는 같은 측에 결합될 수 있다.In this case, the transfer tool 400 may be coupled to both sides of the guide 500 or to the same side.
예로서, 상기 이송툴(400)은, 로딩부의 일측에 위치한 제1반도체소자 캐리어테이블(700)과 대응되는 제1이송툴(410) 및 로딩부의 타측에 위치한 제2반도체소자 캐리어테이블(700)과 대응되는 제2이송툴(420)로 한 쌍으로 설치될 수 있다.For example, the transfer tool 400 may include a first transfer tool 410 corresponding to the first semiconductor device carrier table 700 located on one side of the loading unit and a second semiconductor device carrier table 700 located on the other side of the loading unit. The second transfer tool 420 corresponding to and may be installed in pairs.
상기 제1이송툴(410)은, 도 6에 도시된 바와 같이, 제1경로()를 따라 반도체소자(10)를 제1반도체소자 캐리어로 이송하고, 제2이송툴(420)은, 제2경로()를 따라 반도체소자(10)를 제2반도체소자 캐리어로 이송하는 구성으로 다양한 구성이 가능하다.As illustrated in FIG. 6, the first transfer tool 410 transfers the semiconductor device 10 to the first semiconductor device carrier along the first path), and the second transfer tool 420 may be formed of the first transfer tool 420. Various configurations are possible by transferring the semiconductor device 10 to the second semiconductor device carrier along the two paths ().
예로서, 상기 제1이송툴(410) 및 제2이송툴(420)은, 인출위치에서 반도체소자(10) 인출시 상호 방해되지 않도록 교대로 소자를 이송하도록 구성될 수 있다.For example, the first transfer tool 410 and the second transfer tool 420 may be configured to alternately transfer the elements so as not to interfere with each other when the semiconductor element 10 is drawn out from the withdrawal position.
한편 상기 이송툴(400)은, 소자(10)를 트레이(20)로부터 반도체소자 캐리어까지 이송하기 위한 구성으로서, 픽업방식에 따라서 다양한 구성이 가능하며, 상하이동(Z방향 이동)과 함께 진공압을 발생시켜 소자(10)를 흡착하여 픽업하는 흡착헤드(미도시)를 포함하여 구성될 수 있다.On the other hand, the transfer tool 400 is a configuration for transferring the element 10 from the tray 20 to the semiconductor element carrier, and can be configured in various ways according to the pick-up method. It may be configured to include an adsorption head (not shown) for generating the adsorption to pick up the element 10.
한편, 상기 소자핸들러는, 이송툴(400)에 의한 반도체소자의 이송경로에 설치되며 이송툴(400)에 픽업된 반도체소자(10)의 저면을 촬영하는 이미지획득부(30)를 추가로 포함할 수 있다.Meanwhile, the device handler further includes an image acquisition unit 30 installed on the transfer path of the semiconductor device by the transfer tool 400 and photographing the bottom surface of the semiconductor device 10 picked up by the transfer tool 400. can do.
여기서, 상기 이미지획득부(30)에 의하여 획득된 이미지는, 이송툴(400)의 흡착패드에 흡착된 반도체소자(10)의 저면에 대한 비전검사를 수행할 수 있다.Here, the image obtained by the image acquisition unit 30 may perform a vision inspection on the bottom surface of the semiconductor device 10 adsorbed on the adsorption pad of the transfer tool 400.
또한 상기 이미지획득부(30)에 의하여 획득된 이미지는, 캐리어테이블(700) 상의 반도체 소자 캐리어 상의 적절한 안착위치, 즉 제1관통구(101) 및 제2관통구(201)에 알맞게 반도체소자(10)가 적재될 수 있도록 이송툴(400)에 의하여 픽업된 반도체소자(10)의 수평상태를 확인하는데 활용될 수 있다.In addition, the image obtained by the image acquisition unit 30, the semiconductor device (suitable for a suitable mounting position on the semiconductor device carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201) It can be utilized to check the horizontal state of the semiconductor device 10 picked up by the transfer tool 400 so that 10) can be loaded.
상기 소자핸들러는, 이미지획득부(30)에 의하여 획득된 저면의 이미지를 분석하여 반도체소자가 반도체소자 캐리어 상에 미리 설정된 적재위치에 위치되도록 X-Y 이동 및 수평회전이동 중 적어도 어느 하나의 이동에 의하여 캐리어테이블(700)을 이동시킬 수 있다.The device handler analyzes an image of the bottom surface obtained by the image acquisition unit 30 to move the semiconductor device to at least one of an XY movement and a horizontal rotational movement so that the semiconductor device is positioned at a preset loading position on the semiconductor device carrier. The carrier table 700 may be moved.
여기서 물론 반도체소자(10)를 픽업하는 이송툴(400)을 회전시켜 캐리어테이블(700) 상의 반도체 소자 캐리어 상의 적절한 안착위치, 즉 제1관통구(101) 및 제2관통구(201)에 알맞게 반도체소자(10)가 적재되도록 할 수 있음은 물론이다.Here, of course, the transfer tool 400 picking up the semiconductor element 10 is rotated so as to be suitable for the proper seating position on the semiconductor element carrier on the carrier table 700, that is, the first through hole 101 and the second through hole 201. Of course, the semiconductor device 10 can be loaded.
상기 소자핸들러에 의해 반도체소자(10)가 적재된 반도체소자 캐리어는, 캐리어언로딩부(900)로 이동하여 EMI 실드층(13) 형성 공정을 위한 EMI 실드 형성장치(미도시)로 반송될 수 있다.The semiconductor device carrier on which the semiconductor device 10 is loaded by the device handler may move to the carrier unloading unit 900 and be transferred to an EMI shield forming apparatus (not shown) for the EMI shield layer 13 forming process. have.
한편 상기와 같은 구성을 가지는 소자핸들러는, 앞서 설명한 소자의 로딩부터 EMI실드 후의 언로딩까지 인라인으로 이루어지는 인라인시스템의 일부로서 구성될 수 있다.Meanwhile, the device handler having the above configuration may be configured as part of an inline system that is inlined from the above-described device loading to the unloading after EMI shielding.
한편, 종래의 반도체소자 캐리어는, 반도체소자(10)의 저면에 형성된 돌출단자(12)의 영향으로, 반도체소자(10)의 저면이 반도체소자 캐리어에 빈틈없이 밀착되지 않아 저면을 제외한 상면 및 측면에 대한 EMI 실드층(13) 형성이 완전히 이루어지지 않는 문제점이 있다.Meanwhile, in the conventional semiconductor device carrier, the bottom surface of the semiconductor device 10 is not closely adhered to the semiconductor device carrier due to the influence of the protruding terminal 12 formed on the bottom surface of the semiconductor device 10. There is a problem that the formation of the EMI shield layer 13 is not completely made.
또한, 종래의 반도체소자 캐리어는, 테이프 등과 같은 얇고 플렉서블한 소재로 형성된 지지면에 반도체소자(10)를 부착시킴으로써 캐리어 이송 과정에서 지지면의 형상이 안정적으로 유지되지 않는 문제점이 있다.In addition, the conventional semiconductor device carrier has a problem in that the shape of the support surface is not stably maintained during the carrier transfer process by attaching the semiconductor device 10 to a support surface formed of a thin and flexible material such as a tape.
상기와 같은 문제점을 해결하기 위하여, 본 발명에 따른 반도체소자 캐리어는, 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 반도체소자들이 부착되는 반도체소자 캐리어로서, 미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)와; 단자영역이 제1관통구(101)의 하측으로 노출되고 단자영역의 가장자리가 베이스부재(100)에 부착될 수 있도록 베이스부재(100)의 상면에 형성된 부착층(200)과; 베이스부재(100) 중 제1관통구(101)들이 형성된 영역이 상부로 노출되도록 베이스부재(100)의 상면에 결합되는 프레임(300)을 포함한다.In order to solve the above problems, the semiconductor device carrier according to the present invention, EMI shield layer 13 to form an EMI shield layer 13 on the upper surface and the side of the semiconductor device formed with a plurality of protruding terminals 12 on the bottom surface A semiconductor device carrier to which a plurality of semiconductor devices are attached to perform a forming process. The semiconductor device carrier has a predetermined rigidity and has a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device is formed. Plate-shaped base member 100 is formed; An attachment layer 200 formed on an upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region is attached to the base member 100; The frame 300 is coupled to the upper surface of the base member 100 so that the region where the first through holes 101 are formed in the base member 100 is exposed to the upper portion.
상기 베이스부재(100)는, 미리 설정된 강성을 가지는 판상형의 부재로, 각 반도체소자(10)의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성될 수 있다.The base member 100 is a plate-shaped member having a predetermined rigidity, and a plurality of first through holes 101 are formed to have a size corresponding to a terminal area in which the protruding terminal 12 of each semiconductor device 10 is formed. Can be.
상기 제1관통구(101)는, 도 1 내지 도 3에 도시된 바와 같이, 그 크기가 반도체소자(10)의 크기보다는 작고 돌출단자(12)가 형성된 단자영역보다는 크게 형성됨이 바람직하다.As shown in FIGS. 1 to 3, the first through hole 101 may have a size smaller than that of the semiconductor device 10 and larger than a terminal region in which the protruding terminal 12 is formed.
상기 제1관통구(101)는, 반도체소자(10) 저면의 돌출단자(12)가 형성되지 않은 가장자리를 지지하는 형상으로 다양한 형상이 가능하다.The first through hole 101 may have various shapes in such a manner as to support an edge at which the protruding terminal 12 of the bottom surface of the semiconductor device 10 is not formed.
예로서, 상기 제1관통구(101)는, 반도체 소자(10)의 평면형상과 대응되는 형상, 예를 들면 직사각형 형상으로, 그 경계가 반도체소자(10) 저면의 돌출단자(12)가 형성된 단자영역과 가장자리 사이에 위치하도록 형성될 수 있다.For example, the first through hole 101 may have a shape corresponding to a planar shape of the semiconductor device 10, for example, a rectangular shape, the boundary of which the protruding terminal 12 of the bottom surface of the semiconductor device 10 may be formed. It may be formed to be located between the terminal area and the edge.
보다 구체적으로, 상기 제1관통구(101)는, 도 3에 도시된 바와 같이, 돌출단자(12)가 형성된 단자영역(w) 보다는 그 크기가 크고, 반도체 소자(10) 저면 보다는 그 크기가 작게 형성되어 반도체 소자(10)의 단자영역(w) 밖의 가장자리와 접하도록 형성될 수 있다.More specifically, as illustrated in FIG. 3, the first through hole 101 is larger in size than the terminal area w in which the protruding terminal 12 is formed, and is larger than the bottom surface of the semiconductor device 10. It may be formed to be small so as to contact an edge outside the terminal region w of the semiconductor device 10.
즉, 상기 제1관통구(101)는, 도 3에 도시된 바와 같이, 그 경계가 반도체소자(10) 단자영역을 제외한 둘레영역(d1+d2)에 위치함이 바람직하다.That is, as shown in FIG. 3, the first through hole 101 is preferably located in the circumferential region d1 + d2 excluding the terminal region of the semiconductor device 10.
상기 베이스부재(100)는, 베이스부재(100)는, 원판 형상의 웨이퍼 형상 또는 팔각형, 직사각형 등 다양한 형상을 가질 수 있으나, 이에 한정되는 것은 아니다.The base member 100, the base member 100 may have a variety of shapes, such as a disk-shaped wafer shape or octagonal, rectangular, but is not limited thereto.
상기 베이스부재(100)는, 기 설정된 강성을 가져 적재된 반도체소자(10)를 흔들림 없이 지지할 수 있는 재질이면 다양한 재질을 가질 수 있다.The base member 100 may have various materials as long as it is a material capable of supporting the semiconductor device 10 loaded with predetermined rigidity without shaking.
예로서, 상기 베이스부재(100)는, 금속재질, 후술하는 부착층(200)의 재질보다 경질의 재질을 가질 수 있다.For example, the base member 100 may have a material that is harder than the material of the metal and the adhesion layer 200 described later.
상기 부착층(200)은, 단자영역이 제1관통구(101)의 하측으로 노출되고 단자영역의 가장자리가 베이스부재(100)에 부착될 수 있도록 베이스부재(100)의 상면에 형성되는 구성으로 다양한 구성이 가능하다.The attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal region is exposed to the lower side of the first through hole 101 and the edge of the terminal region can be attached to the base member 100. Various configurations are possible.
일 실시예에서, 상기 부착층(200)은, 베이스부재(100)의 상면에 부착되는 접착성을 가지는 접착테이프에 의하여 형성될 수 있다, 예로서, 상기 접착테이프는, 양면테이프에 해당할 수 있다.In one embodiment, the adhesion layer 200 may be formed by an adhesive tape having an adhesive attached to the upper surface of the base member 100, for example, the adhesive tape may correspond to a double-sided tape. have.
이때, 상기 양면테이프는, 베이스부재(100)에 부착된 후 제1관통구(101)와 동일한 위치에 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성될 수 있다.In this case, the double-sided tape is attached to the base member 100, the second through-hole 201 is formed in the same position as the first through-hole 101 or smaller in size with the first through-hole 101. Can be.
다른 일 실시예에서, 상기 부착층(200)은, 베이스부재(100)의 상면에 형성되는 필름과; 필름의 상면에 접합되는 접착물질을 포함할 수 있다.In another embodiment, the adhesion layer 200, the film formed on the upper surface of the base member 100; It may include an adhesive material bonded to the upper surface of the film.
이때, 상기 부착층(200)은, 베이스부재(100)에 부착된 후 제1관통구(101)와 동일한 위치에 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성될 수 있다.At this time, the attachment layer 200 is attached to the base member 100, the second through-hole 201 in the same position or smaller than the first through-hole 101 at the same position as the first through-hole (101). Can be formed.
상기 프레임(300)은, 베이스부재(100) 중 제1관통구(101)들이 형성된 영역이 상부로 노출되도록 베이스부재(100)의 상면에 결합되는 구성으로 다양한 구성이 가능하다.The frame 300 is configured to be coupled to the upper surface of the base member 100 so that the region in which the first through holes 101 are formed in the base member 100 is exposed to the top.
예로서, 상기 프레임(300)은, 제1관통구(101)들이 형성된 영역이 상부로 노출되도록 접착층(200)의 가장자리와 결합되는 결합링으로 구성될 수 있다.For example, the frame 300 may be configured as a coupling ring coupled to an edge of the adhesive layer 200 so that the region where the first through holes 101 are formed is exposed upward.
상기 프레임(300)은, 원형, 사각형 등 다양한 형상을 가질 수 있다.The frame 300 may have various shapes such as a circle and a rectangle.
한편, 상기 프레임(300)은, 필수적인 구성은 아닌 것으로, 선택적으로 채택될 수 있는 구성에 해당한다.On the other hand, the frame 300 is not an essential configuration, it corresponds to a configuration that can be selectively adopted.
상기와 같은 구성을 가지는 본 발명에 따른 반도체소자 캐리어는, 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 반도체소자들이 부착되는 반도체소자 캐리어 제조방법으로서, 미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)를 제공하는 베이스부재 제공단계와; 단자영역이 제1관통구(101)의 하측으로 노출되고 단자영역의 가장자리가 베이스부재(100)에 부착될 수 있도록 베이스부재(100)의 상면에 부착층(200)을 형성하는 부착층 형성단계와; 판상형의 베이스부재(100) 상면에 부착층(200)이 부착된 후 제1관통구(101)와 동일한 위치에 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)를 형성하는 제2관통구 형성단계를 포함하는 반도체소자 캐리어 제조방법에 의해 제조될 수 있다.In the semiconductor device carrier according to the present invention having the above-described configuration, an EMI shield layer 13 forming process of forming an EMI shield layer 13 on the top and side surfaces of a semiconductor device having a plurality of protruding terminals 12 formed on a bottom surface thereof. A method of manufacturing a semiconductor device carrier to which a plurality of semiconductor devices are attached to perform a method, comprising: a plurality of first through holes 101 having a predetermined rigidity and corresponding to a terminal area in which protrusion terminals 12 of each semiconductor device are formed; A base member providing step of providing a plate-shaped base member 100 formed thereon; Attachment layer forming step of forming the attachment layer 200 on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100. Wow; After the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100, the second through hole 201 is formed in the same position as or less than the first through hole 101 at the same position as the first through hole 101. It can be produced by a semiconductor device carrier manufacturing method comprising a second through-hole forming step to form.
일 실시예에서, 상기 부착층(200)은, 베이스부재(100)의 상면에 부착되는 양면테이프이며, 제2관통구 형성단계는, 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함할 수 있다.In one embodiment, the adhesion layer 200 is a double-sided tape is attached to the upper surface of the base member 100, the second through-hole forming step, drilling the same position as the first through-hole 101 using a laser It may include a laser drilling step.
다른 일 실시예에서, 상기 부착층(200)은, 베이스부재(100)의 상면에 형성되는 필름과; 필름의 상면에 접합되는 접착물질을 포함하며, 제2관통구 형성단계는, 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함할 수 있다.In another embodiment, the adhesion layer 200, the film formed on the upper surface of the base member 100; It includes an adhesive material bonded to the upper surface of the film, the second through-hole forming step may include a laser drilling step of drilling the same position as the first through-hole 101 using a laser.
한편, 상기 반도체소자 캐리어 제조방법은, 판상형의 베이스부재(100) 상면에 부착층(200)이 부착되기 전 부착층(200)에 제1관통구(101)와 동일한 위치에 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)를 형성하는 제2관통구 형성단계를 수행하고, 제2관통구(201)가 형성된 부착층(200)을 베이스부재(100)에 제1관통구(101)와 제2관통구(201)가 상호 대응되도록 부착하는 부착층 형성단계를 수행할 수 있다.On the other hand, the semiconductor device carrier manufacturing method, the first through-hole (at the same position as the first through-hole 101 in the attachment layer 200 before the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100 ( The second through-hole forming step of forming the second through-hole 201 with the same or smaller size than that of 101 is performed, and the attachment layer 200 having the second through-hole 201 is formed on the base member 100. An adhesive layer forming step of attaching the first through hole 101 and the second through hole 201 to correspond to each other may be performed.
이상은 본 발명에 의해 구현될 수 있는 바람직한 실시예의 일부에 관하여 설명한 것에 불과하므로, 주지된 바와 같이 본 발명의 범위는 위의 실시예에 한정되어 해석되어서는 안 될 것이며, 위에서 설명된 본 발명의 기술적 사상과 그 근본을 함께하는 기술적 사상은 모두 본 발명의 범위에 포함된다고 할 것이다.Since the above has been described only with respect to some of the preferred embodiments that can be implemented by the present invention, the scope of the present invention, as is well known, should not be construed as limited to the above embodiments, the present invention described above It will be said that both the technical idea and the technical idea which together with the base are included in the scope of the present invention.

Claims (11)

  1. 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 상기 반도체소자들이 부착되는 반도체소자 캐리어에 있어서,Semiconductor device carrier to which the plurality of semiconductor devices are attached to perform the process of forming the EMI shield layer 13 to form the EMI shield layer 13 on the top and side surfaces of the semiconductor device having the plurality of protruding terminals 12 formed on the bottom surface thereof. To
    미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)와;A plate-shaped base member 100 having a predetermined rigidity and having a plurality of first through holes 101 formed in a size corresponding to a terminal region in which the protruding terminals 12 of each semiconductor element are formed;
    상기 단자영역이 상기 제1관통구(101)의 하측으로 노출되고 상기 단자영역의 가장자리가 상기 베이스부재(100)에 부착될 수 있도록 상기 베이스부재(100)의 상면에 형성된 부착층(200)를 포함하는 것을 특징으로 하는 반도체소자 캐리어.Attaching layer 200 formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area can be attached to the base member 100 A semiconductor device carrier comprising a.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 베이스부재(100) 중 상기 제1관통구(101)들이 형성된 영역이 상부로 노출되도록 상기 베이스부재(100)의 상면에 결합되는 프레임(300)을 추가로 포함하는 것을 특징으로 하는 반도체소자 캐리어.The semiconductor device carrier further comprises a frame 300 coupled to the upper surface of the base member 100 so that the region in which the first through holes 101 are formed in the base member 100 is exposed to the upper portion. .
  3. 청구항 1에 있어서,The method according to claim 1,
    상기 베이스부재(100)는,The base member 100,
    원판 형상의 웨이퍼 형상 또는 다각형 형상을 가지는 것을 특징으로 하는 반도체소자 캐리어.A semiconductor device carrier having a disk shape wafer shape or a polygonal shape.
  4. 청구항 1에 있어서,The method according to claim 1,
    상기 부착층(200)은, The adhesion layer 200,
    상기 베이스부재(100)의 상면에 부착되는 양면테이프에 의하여 형성되며,It is formed by a double-sided tape attached to the upper surface of the base member 100,
    상기 양면테이프는, The double-sided tape,
    상기 베이스부재(100)에 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성된 것을 특징으로 하는 반도체소자 캐리어.The semiconductor is characterized in that the second through-hole 201 is formed in the same position or smaller than the first through-hole 101 at the same position as the first through-hole 101 after being attached to the base member 100 Device carrier.
  5. 청구항 1에 있어서,The method according to claim 1,
    상기 부착층(200)은,The adhesion layer 200,
    상기 베이스부재(100)의 상면에 형성되는 필름과;A film formed on an upper surface of the base member 100;
    상기 필름의 상면에 접합되는 접착물질을 포함하며,It includes an adhesive material bonded to the upper surface of the film,
    상기 베이스부재(100)에 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)가 형성된 것을 특징으로 하는 반도체소자 캐리어.The semiconductor is characterized in that the second through-hole 201 is formed in the same position or smaller than the first through-hole 101 at the same position as the first through-hole 101 after being attached to the base member 100 Device carrier.
  6. 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여 복수의 상기 반도체소자들이 부착되는 반도체소자 캐리어 제조방법으로서,Semiconductor device carrier to which the plurality of semiconductor devices are attached to perform the process of forming the EMI shield layer 13 to form the EMI shield layer 13 on the top and side surfaces of the semiconductor device having the plurality of protruding terminals 12 formed on the bottom surface thereof. As a manufacturing method,
    미리 설정된 강성을 가지며 각 반도체소자의 돌출단자(12)가 형성된 단자영역에 대응되는 크기로 복수의 제1관통구(101)들이 형성된 판상형의 베이스부재(100)를 제공하는 베이스부재 제공단계와;A base member providing step of providing a plate-shaped base member 100 having a predetermined rigidity and having a plurality of first through holes 101 formed in a size corresponding to a terminal region in which the protruding terminals 12 of each semiconductor element are formed;
    상기 단자영역이 상기 제1관통구(101)의 하측으로 노출되고 상기 단자영역의 가장자리가 상기 베이스부재(100)에 부착될 수 있도록 상기 베이스부재(100)의 상면에 부착층(200)을 형성하는 부착층 형성단계와;The attachment layer 200 is formed on the upper surface of the base member 100 so that the terminal area is exposed to the lower side of the first through hole 101 and the edge of the terminal area is attached to the base member 100. Forming an adhesion layer;
    상기 판상형의 베이스부재(100) 상면에 상기 부착층(200)이 부착된 후 상기 제1관통구(101)와 동일한 위치에 상기 제1관통구(101)와 동일하거나 작은 크기로 제2관통구(201)를 형성하는 제2관통구 형성단계를 포함하는 것을 특징으로 하는 반도체소자 캐리어 제조방법.After the attachment layer 200 is attached to the upper surface of the plate-shaped base member 100, the second through hole with the same or smaller size as the first through hole 101 at the same position as the first through hole 101. And a second through hole forming step of forming a 201.
  7. 청구항 6에 있어서,The method according to claim 6,
    상기 부착층(200)은,The adhesion layer 200,
    상기 베이스부재(100)의 상면에 부착되는 양면테이프이며,Is a double-sided tape attached to the upper surface of the base member 100,
    제2관통구 형성단계는,The second through-hole forming step,
    상기 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함하는 것을 특징으로 하는 반도체소자 캐리어 제조방법.And a laser drilling step of drilling the same position as the first through hole 101 using a laser.
  8. 청구항 6에 있어서,The method according to claim 6,
    상기 부착층(200)은,The adhesion layer 200,
    상기 베이스부재(100)의 상면에 형성되는 필름과;A film formed on an upper surface of the base member 100;
    상기 필름의 상면에 접합되는 접착물질을 포함하며,It includes an adhesive material bonded to the upper surface of the film,
    제2관통구 형성단계는,The second through-hole forming step,
    상기 제1관통구(101)와 동일한 위치를 레이저를 이용해 천공하는 레이저 천공단계를 포함하는 것을 특징으로 하는 반도체소자 캐리어 제조방법.And a laser drilling step of drilling the same position as the first through hole 101 using a laser.
  9. 저면에 복수의 돌출단자(12)들이 형성된 반도체소자의 상면 및 측면에 EMI 실드층(13)을 형성하는 EMI 실드층(13) 형성 공정을 수행하기 위하여, 다수의 반도체소자들이 적재된 트레이(20)로부터 청구항 제1항에 따른 반도체소자 캐리어에 적재하는 소자핸들러로서,In order to perform the process of forming the EMI shield layer 13, which forms the EMI shield layer 13 on the top and side surfaces of the semiconductor device having the plurality of protruding terminals 12 formed on the bottom thereof, a tray 20 in which a plurality of semiconductor devices are stacked. A device handler mounted on a semiconductor device carrier according to claim 1 from
    다수의 반도체소자들이 적재된 트레이(20)들이 로딩되는 로딩부와;A loading unit in which trays 20 in which a plurality of semiconductor devices are loaded are loaded;
    상기 로딩부에서 트레이(20)의 이송방향을 기준으로 적어도 일측에 위치되며 반도체소자들의 적재를 위하여 상기 캐리어를 수평이동시키는 하나 이상의 캐리어테이블(700)과;At least one carrier table 700 positioned on at least one side of the loading unit based on a transfer direction of the tray 20 and horizontally moving the carrier for loading of semiconductor devices;
    상기 로딩부에서의 트레이(20)로부터 반도체소자를 픽업하여 각 캐리어테이블(700)에 적재된 캐리어 상에 상기 단자영역을 상기 제1관통구(101)의 하측으로 노출시키고 상기 단자영역의 가장자리를 상기 반도체소자 캐리어에 부착시키는 하나 이상의 이송툴(400)을 포함하는 소자핸들러.The semiconductor device is picked up from the tray 20 in the loading unit to expose the terminal area to the lower side of the first through hole 101 on a carrier loaded in each carrier table 700, and the edge of the terminal area is exposed. And at least one transfer tool (400) attached to the semiconductor device carrier.
  10. 청구항 9에 있어서,The method according to claim 9,
    상기 캐리어테이블(700)은, The carrier table 700,
    상기 로딩부에서 트레이(20)의 이송방향을 기준으로 양측에 한 쌍으로 설치되고,In the loading unit is installed in pairs on both sides based on the conveying direction of the tray 20,
    상기 이송툴(400)은, The transfer tool 400,
    상기 한 쌍의 캐리어테이블(700) 각각에 대응되어 한 쌍으로 설치된 것을 특징으로 하는 소자핸들러.A device handler, characterized in that installed in pairs corresponding to each of the pair of carrier table (700).
  11. 청구항 10에 있어서,The method according to claim 10,
    상기 이송툴(400)에 의한 반도체소자의 이송경로에 설치되며 이송툴(400)에 픽업된 반도체소자의 저면을 촬영하는 이미지획득부(30)를 추가로 포함하며,It is installed on the transfer path of the semiconductor device by the transfer tool 400 and further comprises an image acquisition unit 30 for photographing the bottom surface of the semiconductor element picked up by the transfer tool 400,
    상기 이미지획득부(30)에 의하여 획득된 저면의 이미지를 분석하여 반도체소자가 상기 반도체소자 캐리어 상에 미리 설정된 적재위치에 위치되도록 X-Y 이동 및 수평회전이동 중 적어도 어느 하나의 이동에 의하여 상기 캐리어테이블(700)을 이동시키는 것을 특징으로 하는 소자핸들러.Analyzing the image of the bottom surface obtained by the image acquisition unit 30 and the carrier table by the movement of at least one of XY movement and horizontal rotational movement so that the semiconductor device is positioned in a predetermined loading position on the semiconductor device carrier A device handler, characterized in that for moving (700).
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