WO2017193775A1 - 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2017193775A1
WO2017193775A1 PCT/CN2017/081023 CN2017081023W WO2017193775A1 WO 2017193775 A1 WO2017193775 A1 WO 2017193775A1 CN 2017081023 W CN2017081023 W CN 2017081023W WO 2017193775 A1 WO2017193775 A1 WO 2017193775A1
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Prior art keywords
transistor
node
pull
voltage
unit
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PCT/CN2017/081023
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English (en)
French (fr)
Inventor
韩龙
刘利宾
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/574,465 priority Critical patent/US20180144811A1/en
Publication of WO2017193775A1 publication Critical patent/WO2017193775A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, a driving method thereof, and a display device.
  • the display device is generally provided with a GOA (Gate Driver on Array) circuit, the GOA circuit includes a plurality of shift register units, and the output terminal of each stage of the shift register unit is connected to a row of gate lines for The gate line outputs a gate scan signal to effect progressive scan of the gate line.
  • GOA Gate Driver on Array
  • the output of the remaining shift register units needs to be connected to the input of the shift register unit of the next stage.
  • a shift register unit including: a first control unit, a first control unit connecting a signal input end, a first clock signal end, and a first node, Outputting a voltage of the signal input terminal to the first node under control of a clock signal terminal;
  • the second control unit is connected to the first clock signal terminal, the first voltage terminal, the first node, and a second node, configured to output the voltage of the first voltage terminal to the second node under the control of the first clock signal end, and/or to the first clock signal end under the control of the first node a voltage is output to the second node;
  • a first pull-up unit, the first pull-up unit is connected to the second node, a second voltage terminal, and a first signal output terminal, for controlling at the second node And outputting the voltage of the second voltage terminal to the first signal output end;
  • the second pull-up unit, the second pull-up unit is connected to the second node, the second voltage terminal, a second signal output terminal, configured
  • the first control unit includes a first transistor, a gate of the first transistor is connected to the first clock signal end, a first pole is connected to the signal input end, and a second pole is connected to the first node connection.
  • the second control unit includes a second transistor and a third transistor; a gate of the second transistor is connected to the first node, a first pole is connected to the first clock signal terminal, and a second pole is connected to the first pole The second node is connected; the gate of the third transistor is connected to the first clock signal end, the first pole is connected to the first voltage end, and the second pole is connected to the second node.
  • the first pull-up unit includes a fourth transistor and a first capacitor; a gate of the fourth transistor is connected to the second node, a first pole is connected to the second voltage terminal, and a second pole is connected to the second pole The first signal output terminal is connected; one end of the first capacitor is connected to the first pole of the fourth transistor, and the other end is connected to the gate of the fourth transistor.
  • the second pull-up unit includes a fifth transistor and a second capacitor; a gate of the fifth transistor is connected to the second node, a first pole is connected to the second voltage terminal, and a second pole is connected to the second pole The second signal output terminal is connected; one end of the second capacitor is connected to the first pole of the fifth transistor, and the other end is connected to the gate of the fifth transistor.
  • the first pull-up unit includes a fourth transistor and the second pull-up unit includes a fifth transistor; a channel width-to-length ratio of the fourth transistor is greater than a channel width-to-length ratio of the fifth transistor.
  • the first pull-down unit includes a sixth transistor and a third capacitor; a gate of the sixth transistor is connected to the first node, a first pole is connected to the second clock signal end, and a second pole is The first signal output terminal is connected; one end of the third capacitor is connected to the second pole of the sixth transistor, and the other end is connected to the gate of the sixth transistor.
  • the second pull-down unit includes a seventh transistor and a fourth capacitor; a gate of the seventh transistor is connected to the first node, a first pole is connected to the second clock signal end, and a second pole is connected to the second pole The second signal output terminal is connected; one end of the fourth capacitor is connected to the second pole of the seventh transistor, and the other end is connected to the gate of the seventh transistor.
  • the first pull-down unit includes a sixth transistor and the second pull-down unit includes a seventh transistor; a channel width-to-length ratio of the sixth transistor is greater than a channel width-to-length ratio of the seventh transistor.
  • a gate driving circuit comprising any one of the above-described shift register units cascaded in at least two stages; the signal input terminal of the first stage shift register unit is used The start signal is received; except for the first stage shift register unit, the signal input ends of the other first stage shift register units are connected to the second signal output end of the previous stage shift register unit.
  • a display device comprising any of the gate drive circuits as described above.
  • a driving method of a shift register unit comprising: a first stage, wherein a first control unit controls a voltage at a signal input end under control of a first clock signal end Outputting to the first node, and storing the voltage outputted by the signal input end to the first pull-down control unit and the second pull-down control unit respectively; under the control of the first node and the first clock signal end, the second control The unit outputs the voltage of the first voltage terminal to the second node; under the control of the second node, the first pull-up control unit and the second pull-up control unit respectively output the voltage of the second voltage terminal to the second a signal output end and a second signal output end; the first pull-down control unit and the second pull-down control unit respectively output voltages of the second clock signal end to the first signal under control of the first node An output terminal and the second signal output terminal; a second phase, wherein the first pull-down control unit and the second pull-down control unit store voltage in
  • the first control unit is capable of controlling the potential of the first node, and at the first node Under control, the first pull-down unit and the second pull-down unit can output the voltages of the second clock signal end to the first signal output end and the second signal output end, respectively.
  • the first node, the first clock signal end and the second voltage end can control the potential of the second node by the second control unit, and under the control of the second node, the first pull-up unit and the second pull-up unit can The voltages at the second voltage terminals are output to the first signal output terminal and the second signal output terminal, respectively.
  • the voltage of the second voltage terminal is output to the first signal output terminal through the first pull-up unit, and is also output to the second signal output terminal through the second pull-up unit.
  • the voltage of the second clock signal terminal is output to the second signal output terminal through the first pull-down unit, and is also output to the second signal output terminal through the second pull-down unit. Therefore, the output signals of the first signal output and the second signal output can be individually controlled by different units.
  • the first signal output terminal when the first signal output terminal is connected to the gate line and the second signal output terminal is connected to the signal input terminal of the next stage shift register unit, even if a certain stage shift register unit is damaged, The first signal output terminal cannot output normally, and the second signal output terminal can also output a normal output signal to the shift register unit in the next stage, thereby ensuring damage to the shift register unit of the first stage to the output of the shift register unit of the next stage.
  • the voltage is normal.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the specific structure of each unit in the shift register unit shown in FIG. 1;
  • FIG. 3 is a timing chart of control signals for controlling the shift register unit shown in FIG. 2;
  • FIG. 4 is a block diagram showing the structure of a gate drive circuit composed of a plurality of cascaded shift register units as shown in FIG. 2.
  • An embodiment of the present invention provides a shift register unit, as shown in FIG. 1, including a first control unit 10, a second control unit 20, a first pull-up unit 30, a second pull-up unit 40, and a first pull-down unit. 50 and a second pull down unit 60.
  • the first control unit 10 is connected to the signal input terminal IN, the first clock signal terminal CK and the first node N1 for outputting the voltage of the signal input terminal IN to the first node N1 under the control of the first clock signal terminal CK. .
  • the second control unit 20 is connected to the first clock signal terminal CK, the first voltage terminal VGL, the first node N1 and the second node N2 for outputting the voltage of the first voltage terminal VGL under the control of the first clock signal terminal CK.
  • the voltage of the first clock signal terminal CK is output to the second node N2 to the second node N2, and/or under the control of the first node N1.
  • the first pull-up unit 30 is connected to the second node N2, the second voltage terminal VGH, and the first signal output terminal OUTPUT1 for outputting the voltage of the second voltage terminal VGH to the first signal output under the control of the second node N2. End OUTPUT1.
  • the second pull-up unit 40 is connected to the second node N2, the second voltage terminal VGH, and the second signal output terminal OUTPUT1 for outputting the voltage of the second voltage terminal VGH to the second signal output under the control of the second node N2. End OUTPUT2.
  • the first pull-down unit 50 is connected to the first node N1, the second clock signal terminal CKB, and the first signal output terminal OUTPUT1 for outputting the voltage of the second clock signal terminal CKB to the first under the control of the first node N1.
  • the second pull-down unit 60 is connected to the first node N1, the second clock signal terminal CKB, and the second signal output terminal OUTPUT2 for outputting the voltage of the second clock signal terminal CKB to the second signal under the control of the first node N1.
  • the first control unit can control the potential of the first node, and under the control of the first node, the first pull-down unit and the second pull-down unit can output the voltage of the second clock signal end to the first signal output end and the first Two signal outputs.
  • the first node, the first clock signal end and the second voltage end can control the potential of the second node by the second control unit, and under the control of the second node, the first pull-up unit and the second pull-up unit can The voltages at the second voltage terminals are output to the first signal output terminal and the second signal output terminal, respectively.
  • the voltage of the second voltage terminal is output to the first signal output terminal through the first pull-up unit, and is also output to the second signal output terminal through the second pull-up unit.
  • the voltage of the second clock signal terminal is output to the first signal output terminal through the first pull-down unit, and is also output to the second signal output terminal through the second pull-down unit. Therefore, the signals can be output to the first signal output terminal and the second signal output terminal through different units. Take separate controls.
  • the first signal output terminal when the first signal output terminal is connected to the gate line and the second signal output terminal is connected to the signal input terminal of the next stage shift register unit, even if a certain stage shift register unit is damaged, The first signal output terminal cannot output normally, and the second signal output terminal can output the signal normally to the shift register unit in the next stage, thereby ensuring damage to the voltage outputted by the shift register unit of the first stage to the shift register unit of the next stage. normal.
  • the first control unit 10 includes a first transistor T1, the gate of the first transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the signal input terminal IN, and the second pole and the second A node N1 is connected.
  • the first control unit 10 may further include a plurality of transistors connected in parallel with the first transistor T1.
  • the second control unit 20 may include a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is connected to the first node N1, the first pole is connected to the first clock signal terminal CK, and the second pole is connected to the second node N2.
  • the gate of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal VGL, and the second pole is connected to the second node N2.
  • the second control unit 20 may further include a plurality of transistors connected in parallel with the second transistor T2, and a plurality of transistors connected in parallel with the third transistor T3.
  • the first pull-up unit 30 may include a fourth transistor T4 and a first capacitor C1.
  • the gate of the fourth transistor T4 is connected to the second node N2, the first pole is connected to the second voltage terminal VGH, and the second pole is connected to the first signal output terminal OUTPUT1.
  • One end of the first capacitor C1 is connected to the first pole of the fourth transistor T4, and the other end is connected to the gate of the fourth transistor T4.
  • the first pull-up unit 30 may further include a plurality of transistors connected in parallel with the fourth transistor T4.
  • the second pull-up unit 40 includes a fifth transistor T5 and a second capacitor C2.
  • the gate of the fifth transistor T5 is connected to the second node N2, the first pole is connected to the second voltage terminal VGH, and the second pole is connected to the second signal output terminal OUTPUT2.
  • One end of the second capacitor C2 is connected to the first pole of the fifth transistor T5, and the other end is connected to the gate of the fifth transistor T5.
  • the second pull-up unit 40 may further include a plurality of transistors connected in parallel with the fifth transistor T5.
  • the first pull-up is performed.
  • the signal output by the unit 30 needs to drive the gate line, so a strong driving force is required, and the signal output by the second pull-up unit 40 only needs to be transmitted to the next-stage shift register unit without driving a large load. Therefore, when the first pull-up unit 30 includes the fourth transistor T4, and the second pull-up unit 40 includes the fifth transistor T5, the channel width-to-length ratio W/L of the fourth transistor T4 is greater than the channel of the fifth transistor T5. The width to length ratio is W/L. In this way, the fifth transistor T5 can occupy a small layout space, thereby facilitating the narrow bezel design of the display panel.
  • the first pull-down unit 50 includes a sixth transistor T6 and a third capacitor C3.
  • the gate of the sixth transistor T6 is connected to the first
  • the node N1 has a first pole connected to the second clock signal terminal CKB and a second pole connected to the first signal output terminal OUTPUT1.
  • One end of the third capacitor C3 is connected to the second pole of the sixth transistor T6, and the other end is connected to the gate of the sixth transistor T6.
  • the first pull-down unit 50 may further include a plurality of transistors connected in parallel with the sixth transistor T6.
  • the second pull-down unit 60 includes a seventh transistor T7 and a fourth capacitor C4.
  • the gate of the seventh transistor T4 is connected to the first node N1, the first pole is connected to the second clock signal terminal CKB, and the second pole is connected to the second signal output terminal OUTPUT2.
  • One end of the fourth capacitor C4 is connected to the second pole of the seventh transistor T7, and the other end is connected to the gate of the seventh transistor T7.
  • the second pull-down unit may further include a plurality of transistors connected in parallel with the seventh transistor T7.
  • the first pull-down unit 50 includes the sixth transistor T6 and the second pull-down unit 60 includes the seventh transistor T7, the channel width-to-length ratio W/L of the sixth transistor T6 is greater than the channel width of the seventh transistor T7. Than W/L. In this way, the seventh transistor T7 can occupy a small layout space, thereby facilitating the narrow bezel design of the display panel.
  • each of the above-mentioned cells may be a P-type transistor or an N-type transistor, which is not limited in the present invention.
  • the first pole of the transistor may be a source
  • the second pole may be a drain
  • the first pole may be a drain
  • the second pole may be a source, which is not limited in the present invention.
  • the specific working process of the shift register unit shown in FIG. 2 in a picture frame will be described in detail below with reference to FIG.
  • the following description will be made by taking an example in which all of the transistors in the shift register unit shown in FIG. 2 are P-type transistors.
  • the first voltage terminal VGL in the embodiment of the present invention may output a low level or a ground, and the second voltage terminal VGH outputs a high level.
  • the first clock signal terminal CK is input with a low level
  • the first transistor T1 is turned on
  • the low level input by the signal input terminal IN is output to the first node N1 through the first transistor T1, and passes through the third capacitor C3.
  • the fourth capacitor C4 stores the low level of the first node N1.
  • the sixth transistor T6 and the seventh transistor T7 are turned on. At this time, the high level of the second clock signal terminal CKB is output to the first signal output terminal OUTPUT1 through the sixth transistor T6, and the high level of the second clock signal terminal CKB is output to the second signal through the seventh transistor T7. Output OUTPUT2.
  • the second transistor T2 under the control of the first node N1, the second transistor T2 is turned on, and the first clock signal terminal CK The low level output value is the second node N2, and the third transistor T3 is turned on under the control of the first clock signal terminal CK, and outputs the low level of the first voltage terminal VGL to the second node N2.
  • the fourth transistor T4 and the fifth transistor T5 are turned on under the control of the second node N2. At this time, the high level of the second voltage terminal VGH is output to the first signal output terminal OUTPUT1 through the fourth transistor T4, and the The high level of the second voltage terminal VGH is output to the second signal output terminal OUTPUT2 through the fifth transistor T5.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a high level.
  • the first clock signal terminal CK outputs a high level
  • the first transistor T1 is turned off
  • the third capacitor C3 and the fourth capacitor C4 output the low level stored in the previous stage to the first node N1, so that the first node N1 Keep it low.
  • the sixth transistor T6 and the seventh transistor T7 are turned on, and the low level of the second clock signal terminal CKB is output to the first signal output terminal OUTPUT1 through the sixth transistor T6, and the second clock signal terminal CKB is The low level is also output to the second signal output terminal OUTPUT2 through the seventh transistor.
  • the third transistor T3 is turned off under the control of the first clock signal terminal CK.
  • the second transistor T2 is turned on, and outputs the high level of the first clock signal terminal CK to the second node N2.
  • the fourth transistor T4 and the fifth transistor T5 are in an off state.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a low level.
  • the first transistor T1 Under the control of the first clock signal terminal CK, the first transistor T1 is turned on, outputs a low level of the signal input terminal IN to the first node N1, and under the control of the first node N1, the sixth transistor T6 and The seventh transistor T7 outputs an off state.
  • the second transistor T2 is turned off.
  • the low level of the first voltage terminal VGL is output to the second node N2, and under the control of the second node N2, the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the high level of the second voltage terminal VGH is output to the first signal output terminal OUTPUT1 through the fourth transistor T4, and the high level of the second voltage terminal VGH is output to the second signal output terminal through the fifth transistor T5. OUTPUT2.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a high level.
  • the control signals of the terminal IN, the first clock signal terminal CK and the second clock signal terminal CKB are such that the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 maintain the voltage of the second voltage terminal VGH.
  • the waveform of the control signal in FIG. 3 needs to be inverted, and the unit connected to the first voltage terminal VGL in FIG. 1 is connected. And the transistor connected to the first voltage terminal VGL in FIG. 2 is connected to the second voltage terminal VGH, and the transistor connected to the second voltage terminal VGH in FIG. 1 and the transistor connected to the second voltage terminal VGH in FIG. The first voltage terminal VGL is connected.
  • the working process of the shift register unit is the same as above, and details are not described herein again.
  • An embodiment of the present invention provides a gate driving circuit, as shown in FIG. 4, including any one of the above-described shift register units cascaded in at least two stages, and the first signal output terminal OUTPUT1 of each stage shift register And sequentially connecting the gate lines (G1, G2, ..., G(n-1), G(n)) for progressively scanning the gate lines.
  • the shift register unit in the gate driving circuit has the same structure and advantageous effects as the shift register unit provided in the foregoing embodiment, and the structure and advantageous effects of the shift register unit have been described in detail since the foregoing embodiments, I will not repeat them here.
  • the signal input terminal IN of the first stage shift register unit RS1 is configured to receive the start signal STV.
  • the signal input terminals IN of the first stage shift register units (RS2 ... RS(n-1), RS(n)) are connected to the first stage shift register unit.
  • the second signal output terminal OUTPUT2 of the last stage shift register unit RS can be vacant processing.
  • the first clock signal terminal CK and the second clock signal terminal CKB are alternately connected to the clock signal CK1 and the clock signal CK2 in sequence.
  • Embodiments of the present invention provide a display device including the gate driving circuit as described above, which has the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiment, since the foregoing embodiment has already been applied to the gate driving circuit.
  • the structure and beneficial effects are described in detail and will not be described here.
  • the display device in the embodiment of the present invention may be a liquid crystal display device or an organic light emitting diode display device.
  • the display device may be any display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer. Product or component.
  • Embodiments of the present invention provide a method for driving a shift register unit.
  • the method includes:
  • the first control unit 10 In the first phase P1, under the control of the first clock signal terminal CK, the first control unit 10 outputs the voltage of the signal input terminal IN to the first node N1, and saves the voltage outputted by the signal input terminal IN to the first The control unit 50 and the second pull-down control unit 60 are pulled down. Under the control of the first node N1 and the first clock signal terminal CK, the second control unit 20 outputs the voltage of the first voltage terminal CK to the second node N2.
  • the first clock signal terminal CK is input with a low level
  • the first transistor T1 is turned on
  • the low level input by the signal input terminal IN is output to the first node N1 through the first transistor T1, and passes through the third capacitor C3.
  • fourth capacitor C4 The low level of the first node N1 described above is stored.
  • the second transistor T2 is turned on, and outputs a low level of the first clock signal terminal CK to the second node N2, and is third under the control of the first clock signal terminal CK.
  • the transistor T3 is turned on, and outputs a low level of the first voltage terminal VGL to the second node N2.
  • the first pull-up control unit 30 and the second pull-up control unit 40 output the voltages of the second voltage terminal VGH to the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2, respectively.
  • the fourth transistor T4 and the fifth transistor T5 are turned on. At this time, the high level of the second voltage terminal VGH is output to the first signal output terminal OUTPUT1 through the fourth transistor T4. And the high level of the second voltage terminal VGH is output to the second signal output terminal OUTPUT2 through the fifth transistor T5.
  • the first pull-down control unit 50 and the second pull-down control unit 60 output the voltages of the second clock signal terminal CKB to the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2, respectively.
  • the sixth transistor T6 and the seventh transistor T7 are turned on. At this time, the high level of the second clock signal terminal CKB is output to the first signal output terminal OUTPUT1 through the sixth transistor T6, and the high level of the second clock signal terminal CKB is output to the second signal through the seventh transistor T7. Output OUTPUT2.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a high level.
  • the first pull-down control unit 50 and the second pull-down control unit 60 output the voltage of the second clock signal terminal CKB to the first signal output terminal OUTPUT1 and the device respectively under the action of the previous phase storage voltage.
  • the second signal output terminal OUTPUT2 is described.
  • the third capacitor C3 and the fourth capacitor C4 output the low level stored in the previous stage to the first node N1, so that the first node N1 is kept at a low level.
  • the sixth transistor T6 and the seventh transistor T7 are turned on, and the low level of the second clock signal terminal CKB is output to the first signal output terminal OUTPUT1 through the sixth transistor T6, and the second clock signal terminal CKB is The low level is also output to the second signal output terminal OUTPUT2 through the seventh transistor.
  • the first node N1 maintains the voltage of the previous stage and controls the second control unit 20 to output the voltage of the first clock signal terminal CK to the second node N2. Specifically, under the control of the first clock signal terminal CK, the third transistor T3 is turned off. Under the control of the first node N1, the second transistor T2 is turned on, and outputs the high level of the first clock signal terminal CK to the second node N2.
  • the first control unit 10, the first pull-up unit 30, and the second pull-up unit 40 have no signal output. Specifically, the first clock signal terminal CK outputs a high level, and the first transistor T1 is turned off. Under the control of the second node N2, the fourth transistor T4 and the fifth transistor T5 are in an off state.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a low level.
  • the first control unit 10 outputs the voltage of the signal input terminal IN to the first node N1.
  • the second control unit 20 outputs the voltage of the first voltage terminal VGL to the second node N2.
  • the first transistor T1 under the control of the first clock signal terminal CK, the first transistor T1 is turned on, and the low level of the signal input terminal IN is output to the first node N1. Under the control of the first node N1, the second transistor T2 is turned off. Under the control of the first clock signal terminal CK, the low level of the first voltage terminal VGL is output to the second node N2.
  • the first pull-up unit 30 and the second pull-up unit 40 output the voltages of the second voltage terminal VGH to the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2, respectively.
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the high level of the second voltage terminal VGH is output to the first signal output terminal OUTPUT1 through the fourth transistor T4
  • the high level of the second voltage terminal VGH is output to the second signal output terminal through the fifth transistor T5. OUTPUT2.
  • the first pull-down unit 50 and the second pull-down unit 60 have no signal output.
  • the sixth transistor T6 and the seventh transistor T7 output an off state.
  • the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 both output a high level.
  • control signals of the signal input terminal IN of the second phase P2 and the third phase P3, the first clock signal terminal CK and the second clock signal terminal CKB are repeated before the next image frame, so that the first signal output terminal OUTPUT1 And the second signal output terminal OUTPUT2 maintains a voltage outputting the second voltage terminal VGH.

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Abstract

一种移位寄存器单元、栅极驱动电路及其驱动方法、显示装置。移位寄存器单元包括第一控制单元(10)、第二控制单元(20)、第一上拉单元(30)、第二上拉单元(40)、第一下拉单元(50)、第二下拉单元(60)。第一控制单元(10)控制第一节点(N1)的电位，在第一节点(N1)的控制下，第一下拉单元(50)和第二下拉单元(60)将第二时钟信号端(CKB)的电压分别输出至第一信号输出端(OUTPUT1)和第二信号输出端(OUTPUT2)。此第一节点(N1)、第一时钟信号端(CK)以及第二电压端(VGH)能够通过第二控制单元(20)控制第二节点(N2)的电位，在第二节点(N2)的控制下，第一上拉单元(30)和第二上拉单元(40)将第二电压端(VGH)的电压分别输出至第一信号输出端(OUTPUT1)和第二信号输出端(OUTPUT2)。

Description

移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
本申请要求于2016年5月11日提交的、申请号为201610311714.3的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器单元、栅极驱动电路及其驱动方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)以及AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)显示装置被越来越多地被应用于高性能显示领域当中。上述显示装置通常设置有GOA(Gate Driver on Array，阵列基板行驱动)电路，该GOA电路包括多个移位寄存器单元，每一级移位寄存器单元输出端与一行栅线相连接，用于向该栅线输出栅极扫描信号，以实现对栅线的逐行扫描。此外，最后一级移位寄存器单元以外，其余移位寄存器单元的输出端需要与下一级移位寄存器单元的输入端相连接。
然而，当GOA电路中的某一级移位寄存器单元损坏时，会影响与其级联的其余移位寄存器单元的输出结果，从而使得显示面板显示异常。
发明内容
根据本发明实施例的一方面，提供了一种移位寄存器单元，包括：第一控制单元，第一控制单元连接信号输入端、第一时钟信号端以及第一节点，用于在所述第一时钟信号端的控制下将所述信号输入端的电压输出至所述第一节点；第二控制单元，所述第二控制单元连接第一时钟信号端、第一电压端、所述第一节点以及第二节点，用于在所述第一时钟信号端的控制下将所述第一电压端的电压输出至所述第二节点，和/或在所述第一节点的控制下将第一时钟信号端的电压输出至所述第二节点；第一上拉单元，所述第一上拉单元连接所述第二节点、第二电压端、第一信号输出端，用于在所述第二节点的控制下，将所述第二电压端的电压输出至所述第一信号输出端；第二上拉单元，所述第二上拉单元连接所述第二节点、第二电压端、 第二信号输出端，用于在所述第二节点的控制下，将所述第二电压端的电压输出至所述第二信号输出端；第一下拉单元连接所述第一节点、第二时钟信号端、第一信号输出端，所述第一下拉单元用于在所述第一节点的控制下，将所述第二时钟信号端的电压输出至所述第一信号输出端；以及第二下拉单元，所述第二下拉单元连接所述第一节点、第二时钟信号端、第二信号输出端，用于在所述第一节点的控制下，将所述第二时钟信号端的电压输出至所述第二信号输出端。
例如，所述第一控制单元包括第一晶体管，所述第一晶体管的栅极连接所述第一时钟信号端，第一极连接所述信号输入端，第二极与所述第一节点相连接。
例如，所述第二控制单元包括第二晶体管和第三晶体管；所述第二晶体管的栅极连接所述第一节点，第一极连接所述第一时钟信号端，第二极与所述第二节点相连接；所述第三晶体管的栅极连接所述第一时钟信号端，第一极连接第一电压端，第二极与所述第二节点相连接。
例如，所述第一上拉单元包括第四晶体管和第一电容；所述第四晶体管的栅极连接所述第二节点，第一极连接所述第二电压端，第二极与所述第一信号输出端相连接；所述第一电容的一端连接所述第四晶体管的第一极，另一端与所述第四晶体管的栅极相连接。
例如，所述第二上拉单元包括第五晶体管和第二电容；所述第五晶体管的栅极连接所述第二节点，第一极连接所述第二电压端，第二极与所述第二信号输出端相连接；所述第二电容的一端连接所述第五晶体管的第一极，另一端与所述第五晶体管的栅极相连接。
例如，当所述第一上拉单元包括第四晶体管，第二上拉单元包括第五晶体管时；所述第四晶体管的沟道宽长比大于所述第五晶体管的沟道宽长比。
例如，所述第一下拉单元包括第六晶体管和第三电容；所述第六晶体管的栅极连接所述第一节点，第一极连接所述第二时钟信号端，第二极与所述第一信号输出端相连接；所述第三电容的一端连接所述第六晶体管的第二极，另一端与所述第六晶体管的栅极相连接。
例如，所述第二下拉单元包括第七晶体管和第四电容；所述第七晶体管的栅极连接所述第一节点，第一极连接所述第二时钟信号端，第二极与所述第二信号输出端相连接；所述第四电容的一端连接所述第七晶体管的第二极，另一端与所述第七晶体管的栅极相连接。
例如，当所述第一下拉单元包括第六晶体管，第二下拉单元包括第七晶体管时；所述第六晶体管的沟道宽长比大于所述第七晶体管的沟道宽长比。
根据本发明实施例的另一方面，提供了一种栅极驱动电路，包括至少两级级联的如上所述的任意一种移位寄存器单元；第一级移位寄存器单元的信号输入端用于接收起始信号；除了第一级移位寄存器单元以外，其余第一级移位寄存器单元的信号输入端连接上一级移位寄存器单元的第二信号输出端。
根据本发明实施例的又一方面，提供了一种显示装置，包括如上所述的任意一种栅极驱动电路。
根据本发明实施例的再一方面，提供了一种移位寄存器单元的驱动方法，所述方法包括：第一阶段，其中在第一时钟信号端的控制下，第一控制单元将信号输入端的电压输出至第一节点，并将所述信号输入端输出的电压分别保存至第一下拉控制单元和第二下拉控制单元；在第一节点以及所述第一时钟信号端的控制下，第二控制单元将第一电压端的电压输出至第二节点；在所述第二节点的控制下，所述第一上拉控制单元和所述第二上拉控制单元将第二电压端的电压分别输出至第一信号输出端和第二信号输出端；在第一节点的控制下，所述第一下拉控制单元和所述第二下拉控制单元将第二时钟信号端的电压分别输出至所述第一信号输出端和所述第二信号输出端；第二阶段，其中所述第一下拉控制单元和所述第二下拉控制单元在上一阶段存储电压的作用下，将所述第二时钟信号端的电压分别输出至所述第一信号输出端和所述第二信号输出端；所述第一节点保持上一阶段的电压，并控制所述第二控制单元将所述第一时钟信号端的电压输出至第二节点；其中，所述第一控制单元、所述第一上拉单元以及所述第二上拉单元无信号输出；以及第三阶段，其中，在所述第一时钟信号端的控制下，所述第一控制单元将所述信号输入端的电压输出至所述第一节点；在所述第一节点以及所述第一时钟信号端的控制下，所述第二控制单元将所述第一电压端的电压输出至第二节点；在所述第二节点的控制下，所述第一上拉单元和所述第二上拉单元将所述第二电压端的电压分别输出至所述第一信号输出端和所述第二信号输出端；其中，所述第一下拉单元和所述第二下拉单元无信号输出；在下一图像帧之前重复第二阶段和第三阶段的所述信号输入端、所述第一时钟信号端以及所述第二时钟信号端的控制信号，使得所述第一信号输出端和所述第二信号输出端保持输出所述第二电压端的电压。
根据本发明实施例，第一控制单元能够控制第一节点的电位，且在第一节点的 控制下，第一下拉单元和第二下拉单元能够将第二时钟信号端的电压分别输出至第一信号输出端和第二信号输出端。此外，第一节点、第一时钟信号端以及第二电压端能够通过第二控制单元控制第二节点的电位，且在第二节点的控制下，第一上拉单元和第二上拉单元能够将第二电压端的电压分别输出至第一信号输出端和第二信号输出端。
综上所述，第二电压端的电压通过第一上拉单元输出至第一信号输出端的同时，还通过第二上拉单元输出至第二信号输出端。此外，第二时钟信号端的电压通过第一下拉单元输出至第二信号输出端的同时，还通过第二下拉单元输出至第二信号输出端。因此可以通过不同的单元对第一信号输出端和第二信号输出端输出信号进行单独控制。在此情况下，当将第一信号输出端与栅线相连接，第二信号输出端与下一级移位寄存器单元的信号输入端相连接时，即使某一级移位寄存器单元发生损坏导致上述第一信号输出端无法正常输出，第二信号输出端也可以向下一级移位寄存器单元正常输出信号，从而能够确保损坏一级的移位寄存器单元向下一级移位寄存器单元输出的电压正常。
附图说明
为了更清楚地说明本发明实施例或传统的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种移位寄存器单元的结构示意图；
图2为图1所述的移位寄存器单元中各个单元的具体结构示意图；
图3为用于控制图2所示的移位寄存器单元的控制信号时序图；
图4为由多个级联的如图2所示的移位寄存器单元构成的栅极驱动电路的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实 施例，都属于本发明保护的范围。
本发明实施例提供一种移位寄存器单元，如图1所示，包括第一控制单元10、第二控制单元20、第一上拉单元30、第二上拉单元40、第一下拉单元50以及第二下拉单元60。
其中，第一控制单元10连接信号输入端IN、第一时钟信号端CK以及第一节点N1，用于在第一时钟信号端CK的控制下将信号输入端IN的电压输出至第一节点N1。
第二控制单元20连接第一时钟信号端CK、第一电压端VGL、第一节点N1以及第二节点N2，用于在第一时钟信号端CK的控制下将第一电压端VGL的电压输出至第二节点N2，和/或在第一节点N1的控制下将第一时钟信号端CK的电压输出至第二节点N2。
第一上拉单元30连接第二节点N2、第二电压端VGH、第一信号输出端OUTPUT1，用于在第二节点N2的控制下，将第二电压端VGH的电压输出至第一信号输出端OUTPUT1。
第二上拉单元40连接第二节点N2、第二电压端VGH、第二信号输出端OUTPUT1，用于在第二节点N2的控制下，将第二电压端VGH的电压输出至第二信号输出端OUTPUT2。
第一下拉单元50连接第一节点N1、第二时钟信号端CKB、第一信号输出端OUTPUT1，用于在第一节点N1的控制下，将第二时钟信号端CKB的电压输出至第一信号输出端OUTPUT2。
第二下拉单元60连接第一节点N1、第二时钟信号端CKB、第二信号输出端OUTPUT2，用于在第一节点N1的控制下，将第二时钟信号端CKB的电压输出至第二信号输出端OUTPUT2。
由于第一控制单元能够控制第一节点的电位，且在第一节点的控制下，第一下拉单元和第二下拉单元能够将第二时钟信号端的电压分别输出至第一信号输出端和第二信号输出端。此外，第一节点、第一时钟信号端以及第二电压端能够通过第二控制单元控制第二节点的电位，且在第二节点的控制下，第一上拉单元和第二上拉单元能够将第二电压端的电压分别输出至第一信号输出端和第二信号输出端。
综上所述，第二电压端的电压通过第一上拉单元输出至第一信号输出端的同时，还通过第二上拉单元输出至第二信号输出端。此外，第二时钟信号端的电压通过第一下拉单元输出至第一信号输出端的同时，还通过第二下拉单元输出至第二信号输出端。因此可以通过不同的单元对第一信号输出端和第二信号输出端输出信号 进行单独控制。在此情况下，当将第一信号输出端与栅线相连接，第二信号输出端与下一级移位寄存器单元的信号输入端相连接时，即使某一级移位寄存器单元发生损坏导致上述第一信号输出端无法正常输出，第二信号输出端可以向下一级移位寄存器单元正常输出信号，从而能够确保损坏一级的移位寄存器单元向下一级移位寄存器单元输出的电压正常。
以下对上述移位寄存器单元中各个单元的具体结构进行详细的说明。
具体的，如图2所示，第一控制单元10包括第一晶体管T1，该第一晶体管T1的栅极连接第一时钟信号端CK，第一极连接信号输入端IN，第二极与第一节点N1相连接。其中，上述第一控制单元10还可以包括多个与第一晶体管T1并联的多个晶体管。
第二控制单元20可以包括第二晶体管T2和第三晶体管T3。第二晶体管T2的栅极连接第一节点N1，第一极连接第一时钟信号端CK，第二极与第二节点N2相连接。
第三晶体管T3的栅极连接第一时钟信号端CK，第一极连接第一电压端VGL，第二极与第二节点N2相连接。其中，上述第二控制单元20还可以包括多个与第二晶体管T2并联的晶体管，以及多个与第三晶体管T3并联的晶体管。
第一上拉单元30可以包括第四晶体管T4和第一电容C1。第四晶体管T4的栅极连接第二节点N2，第一极连接第二电压端VGH，第二极与第一信号输出端OUTPUT1相连接。第一电容C1的一端连接第四晶体管T4的第一极，另一端与第四晶体管T4的栅极相连接。其中，上述第一上拉单元30还可以包括多个与第四晶体管T4并联的多个晶体管。
第二上拉单元40包括第五晶体管T5和第二电容C2。第五晶体管T5的栅极连接第二节点N2，第一极连接第二电压端VGH，第二极与第二信号输出端OUTPUT2相连接。第二电容C2的一端连接第五晶体管T5的第一极，另一端与第五晶体管T5的栅极相连接。其中，上述第二上拉单元40还可以包括多个与第五晶体管T5并联的多个晶体管。
进一步的，在第一信号输出端OUTPUT1连接显示面板中的栅线，而第二信号输出端OUTPUT2用于与下一级移位寄存器单元的信号输入端IN相连接的情况下，第一上拉单元30输出的信号需要驱动栅线，因此需要较强的驱动力，而第二上拉单元40输出的信号仅仅需要传输至下一级移位寄存器单元即可，无需带动较大的负载。因此，当第一上拉单元30包括第四晶体管T4，第二上拉单元40包括第五晶体管T5时，该第四晶体管T4的沟道宽长比W/L大于第五晶体管T5的沟道宽长比W/L。这样一来，第五晶体管T5能够占据较小版图空间，从而有利于显示面板的窄边框设计。
第一下拉单元50包括第六晶体管T6和第三电容C3。第六晶体管T6的栅极连接第一 节点N1，第一极连接第二时钟信号端CKB，第二极与第一信号输出端OUTPUT1相连接。第三电容C3的一端连接第六晶体管T6的第二极，另一端与第六晶体管T6的栅极相连接。其中，上述第一下拉单元50还可以包括多个与第六晶体管T6并联的晶体管。
第二下拉单元60包括第七晶体管T7和第四电容C4。第七晶体管T4的栅极连接第一节点N1，第一极连接第二时钟信号端CKB，第二极与第二信号输出端OUTPUT2相连接。第四电容C4的一端连接第七晶体管T7的第二极，另一端与第七晶体管T7的栅极相连接。其中，上述第二下拉单元还可以包括多个与第七晶体管T7并联的晶体管。
进一步的，在第一信号输出端OUTPUT1连接显示面板中的栅线，而第二信号输出端OUTPUT2用于与下一级移位寄存器单元的信号输入端IN相连接的情况下，第一下拉单元50输出的信号需要驱动栅线，因此需要较强的驱动力，而第二下拉单元60输出的信号仅仅需要传输至下一级移位寄存器单元即可，无需带动较大的负载。因此，当第一下拉单元50包括第六晶体管T6，第二下拉单元60包括第七晶体管T7时，第六晶体管T6的沟道宽长比W/L大于第七晶体管T7的沟道宽长比W/L。这样一来，第七晶体管T7能够占据较小版图空间，从而有利于显示面板的窄边框设计。
需要说明的是，上述单元中的各个晶体管可以均为P型晶体管也可以为N型晶体管，本发明对此不作限制。此外，上述晶体管的第一极可以为源极，第二极可以为漏极，或者，第一极可以为漏极，第二极可以为源极，本发明对此不作限制。
以下结合图3对图2所示的移位寄存器单元在一画面帧中的具体工作过程进行详细的介绍。其中，以下说明是以图2所示的移位寄存器单元中的所有晶体管均为P型晶体管为例进行的说明。此外，本发明实施例中的第一电压端VGL可以输出低电平或者接地，而第二电压端VGH输出高电平。
在一画面帧的第一阶段P1，IN＝0，CK＝0，CKB＝1；其中，“0”表示低电平，“1”表示高电平。
具体的，第一时钟信号端CK输入低电平，第一晶体管T1导通，并将信号输入端IN输入的低电平通过第一晶体管T1输出至第一节点N1，并通过第三电容C3和第四电容C4将上述第一节点N1的低电平进行存储。
在该第一节点N1的控制下，第六晶体管T6和第七晶体管T7导通。此时，将第二时钟信号端CKB的高电平通过第六晶体管T6输出至第一信号输出端OUTPUT1，且该第二时钟信号端CKB的高电平通过第七晶体管T7输出至第二信号输出端OUTPUT2。
此外，在第一节点N1的控制下，第二晶体管T2导通，并将第一时钟信号端CK的 低电平输出值第二节点N2，且在第一时钟信号端CK的控制下第三晶体管T3导通，并将第一电压端VGL的低电平输出至第二节点N2。在该第二节点N2的控制下，第四晶体管T4和第五晶体管T5导通，此时，第二电压端VGH的高电平通过第四晶体管T4输出至第一信号输出端OUTPUT1，且该第二电压端VGH的高电平通过第五晶体管T5输出至第二信号输出端OUTPUT2。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出高电平。
在一画面帧的第二阶段P2，IN＝1，CK＝1，CKB＝0；
具体的，第一时钟信号端CK输出高电平，第一晶体管T1截止，第三电容C3和第四电容C4将上一阶段存储的低电平输出至第一节点N1，使得第一节点N1保持低电平。在此情况下，第六晶体管T6和第七晶体管T7导通，第二时钟信号端CKB的低电平通过第六晶体管T6输出至第一信号输出端OUTPUT1，且该第二时钟信号端CKB的低电平还通过第七晶体管输出至第二信号输出端OUTPUT2。
在第一时钟信号端CK的控制下，第三晶体管T3截止。在第一节点N1的控制下，第二晶体管T2导通，并将第一时钟信号端CK的高电平输出至第二节点N2。此时，在第二节点N2的控制下，第四晶体管T4和第五晶体管T5处于截止状态。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出低电平。
在一画面帧的第三阶段P3，IN＝1，CK＝0，CKB＝1；
在第一时钟信号端CK的控制下，第一晶体管T1导通，将信号输入端IN的低电平输出至第一节点N1，且在该第一节点N1的控制下，第六晶体管T6和第七晶体管T7输出截止状态。
此外，在第一节点N1的控制下，第二晶体管T2截止。在第一时钟信号端CK的控制下，第一电压端VGL的低电平输出至第二节点N2，并在该第二节点N2的控制下，第四晶体管T4和第五晶体管T5导通。在此情况下，第二电压端VGH的高电平通过第四晶体管T4输出至第一信号输出端OUTPUT1，且第二电压端VGH的高电平通过第五晶体管T5输出至第二信号输出端OUTPUT2。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出高电平。
需要说明的是，在下一图像帧之前重复第二阶段P2和第三阶段P3的信号输入 端IN、第一时钟信号端CK以及第二时钟信号端CKB的控制信号，使得第一信号输出端OUTPUT1和第二信号输出端OUTPUT2保持输出第二电压端VGH的电压。
此外，当图2所述的移位寄存器单元中的所有晶体管均为N型晶体管时，需要将图3中的控制信号的波形进行翻转，将图1中与第一电压端VGL相连接的单元以及图2中与第一电压端VGL相连接的晶体管连接第二电压端VGH，以及将图1中与第二电压端VGH相连接的单元以及图2中与第二电压端VGH相连接的晶体管连接第一电压端VGL，具体该移位寄存器单元的工作过程同上，此处不再赘述。
本发明实施例提供一种栅极驱动电路，如图4所示，包括至少两级级联的如上所述的任意一种移位寄存器单元，每一级移位寄存器的第一信号输出端OUTPUT1与依次连接栅线(G1、G2…G(n-1)、G(n))，用于对栅线进行逐行扫描。该栅极驱动电路中的移位寄存器单元具有与前述实施例提供的移位寄存器单元相同的结构和有益效果，由于前述实施例已经对移位寄存器单元的结构和有益效果进行了详细的描述，此处不再赘述。
具体的，第一级移位寄存器单元RS1的信号输入端IN用于接收起始信号STV。
除了第一级移位寄存器单元RS1以外，其余第一级移位寄存器单元(RS2……RS(n-1)、RS(n))的信号输入端IN连接上一级移位寄存器单元的第二信号输出端OUTPUT2。且最后一级移位寄存器单元RS的第二信号输出端OUTPUT2可以空置处理。且第一时钟信号端CK和第二时钟信号端CKB依次交替连接时钟信号CK1和时钟信号CK2。
本发明实施例提供一种显示装置，包括如上所述的栅极驱动电路，具有与前述实施例提供的栅极驱动电路相同的结构和有益效果，由于前述实施例已经对该栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，本发明实施例中的显示装置可以为液晶显示装置或有机发光二极管显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本发明实施例提供一种移位寄存器单元的驱动方法，在一图像帧内，上述方法包括：
在第一阶段P1，在第一时钟信号端CK的控制下，第一控制单元10将信号输入端IN的电压输出至第一节点N1，并将信号输入端IN输出的电压分别保存至第一下拉控制单元50和第二下拉控制单元60。在第一节点N1以及第一时钟信号端CK的控制下，第二控制单元20将第一电压端CK的电压输出至第二节点N2。
具体的，第一时钟信号端CK输入低电平，第一晶体管T1导通，并将信号输入端IN输入的低电平通过第一晶体管T1输出至第一节点N1，并通过第三电容C3和第四电容C4 将上述第一节点N1的低电平进行存储。此外，在第一节点N1的控制下，第二晶体管T2导通，并将第一时钟信号端CK的低电平输出值第二节点N2，且在第一时钟信号端CK的控制下第三晶体管T3导通，并将第一电压端VGL的低电平输出至第二节点N2。
在第二节点N2的控制下，第一上拉控制单元30和第二上拉控制单元40将第二电压端VGH的电压分别输出至第一信号输出端OUTPUT1和第二信号输出端OUTPUT2。
具体的，在该第二节点N2的控制下，第四晶体管T4和第五晶体管T5导通，此时，第二电压端VGH的高电平通过第四晶体管T4输出至第一信号输出端OUTPUT1，且该第二电压端VGH的高电平通过第五晶体管T5输出至第二信号输出端OUTPUT2。
在第一节点N1的控制下，第一下拉控制单元50和第二下拉控制单元60将第二时钟信号端CKB的电压分别输出至第一信号输出端OUTPUT1和第二信号输出端OUTPUT2。
具体的，在该第一节点N1的控制下，第六晶体管T6和第七晶体管T7导通。此时，将第二时钟信号端CKB的高电平通过第六晶体管T6输出至第一信号输出端OUTPUT1，且该第二时钟信号端CKB的高电平通过第七晶体管T7输出至第二信号输出端OUTPUT2。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出高电平。
在第二阶段P2，第一下拉控制单元50和第二下拉控制单元60在上一阶段存储电压的作用下，将第二时钟信号端CKB的电压分别输出至第一信号输出端OUTPUT1和所述第二信号输出端OUTPUT2。
具体的，第三电容C3和第四电容C4将上一阶段存储的低电平输出至第一节点N1，使得第一节点N1保持低电平。在此情况下，第六晶体管T6和第七晶体管T7导通，第二时钟信号端CKB的低电平通过第六晶体管T6输出至第一信号输出端OUTPUT1，且该第二时钟信号端CKB的低电平还通过第七晶体管输出至第二信号输出端OUTPUT2。
第一节点N1保持上一阶段的电压，并控制第二控制单元20将第一时钟信号端CK的电压输出至第二节点N2。具体的，在第一时钟信号端CK的控制下，第三晶体管T3截止。在第一节点N1的控制下，第二晶体管T2导通，并将第一时钟信号端CK的高电平输出至第二节点N2。
其中，第一控制单元10、第一上拉单元30以及第二上拉单元40无信号输出。具体的，第一时钟信号端CK输出高电平，第一晶体管T1截止。在第二节点N2的控制下，第四晶体管T4和第五晶体管T5处于截止状态。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出低电平。
在第三阶段P3，在第一时钟信号端CK的控制下，第一控制单元10将信号输入端IN的电压输出至第一节点N1。在第一节点N1以及第一时钟信号端CK的控制下，第二控制单元20将第一电压端VGL的电压输出至第二节点N2。
具体的，在第一时钟信号端CK的控制下，第一晶体管T1导通，将信号输入端IN的低电平输出至第一节点N1。在第一节点N1的控制下，第二晶体管T2截止。在第一时钟信号端CK的控制下，第一电压端VGL的低电平输出至第二节点N2。
在第二节点N2的控制下，第一上拉单元30和第二上拉单元40将第二电压端VGH的电压分别输出至第一信号输出端OUTPUT1和第二信号输出端OUTPUT2。
具体的，在第二节点N2的控制下，第四晶体管T4和第五晶体管T5导通。在此情况下，第二电压端VGH的高电平通过第四晶体管T4输出至第一信号输出端OUTPUT1，且第二电压端VGH的高电平通过第五晶体管T5输出至第二信号输出端OUTPUT2。
其中，第一下拉单元50和第二下拉单元60无信号输出。
具体的，在第一节点N1的控制下，第六晶体管T6和第七晶体管T7输出截止状态。
综上所述，在该阶段，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2均输出高电平。
需要说明的是，在下一图像帧之前重复第二阶段P2和第三阶段P3的信号输入端IN、第一时钟信号端CK以及第二时钟信号端CKB的控制信号，使得第一信号输出端OUTPUT1和第二信号输出端OUTPUT2保持输出第二电压端VGH的电压。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种移位寄存器单元，包括：
    第一控制单元，所述第一控制单元连接信号输入端、第一时钟信号端以及第一节点，用于在所述第一时钟信号端的控制下将所述信号输入端的电压输出至所述第一节点；
    第二控制单元，所述第二控制单元连接第一时钟信号端、第一电压端、所述第一节点以及第二节点，用于在所述第一时钟信号端的控制下将所述第一电压端的电压输出至所述第二节点，和/或在所述第一节点的控制下将第一时钟信号端的电压输出至所述第二节点；
    第一上拉单元，所述第一上拉单元连接所述第二节点、第二电压端、第一信号输出端，用于在所述第二节点的控制下，将所述第二电压端的电压输出至所述第一信号输出端；
    第二上拉单元，所述第二上拉单元连接所述第二节点、第二电压端、第二信号输出端，用于在所述第二节点的控制下，将所述第二电压端的电压输出至所述第二信号输出端；
    第一下拉单元，所述第一下拉单元连接所述第一节点、第二时钟信号端、第一信号输出端，用于在所述第一节点的控制下，将所述第二时钟信号端的电压输出至所述第一信号输出端；以及
    第二下拉单元，所述第二下拉单元连接所述第一节点、第二时钟信号端、第二信号输出端，用于在所述第一节点的控制下，将所述第二时钟信号端的电压输出至所述第二信号输出端。
  2. 根据权利要求1所述的移位寄存器单元，其特征在于，所述第一控制单元包括第一晶体管，所述第一晶体管的栅极连接所述第一时钟信号端，第一极连接所述信号输入端，第二极与所述第一节点相连接。
  3. 根据权利要求1或2所述的移位寄存器单元，其特征在于，所述第二控制单元包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极连接所述第一节点，第一极连接所述第一时钟信号端，第二极与所述第二节点相连接；
    所述第三晶体管的栅极连接所述第一时钟信号端，第一极连接第一电压端，第 二极与所述第二节点相连接。
  4. 根据权利要求1-3之一所述的移位寄存器单元，其特征在于，所述第一上拉单元包括第四晶体管和第一电容；
    所述第四晶体管的栅极连接所述第二节点，第一极连接所述第二电压端，第二极与所述第一信号输出端相连接；
    所述第一电容的一端连接所述第四晶体管的第一极，另一端与所述第四晶体管的栅极相连接。
  5. 根据权利要求1或4所述的移位寄存器单元，其特征在于，所述第二上拉单元包括第五晶体管和第二电容；
    所述第五晶体管的栅极连接所述第二节点，第一极连接所述第二电压端，第二极与所述第二信号输出端相连接；
    所述第二电容的一端连接所述第五晶体管的第一极，另一端与所述第五晶体管的栅极相连接。
  6. 根据权利要求5所述的移位寄存器单元，其特征在于，当所述第一上拉单元包括第四晶体管，第二上拉单元包括第五晶体管时；
    所述第四晶体管的沟道宽长比大于所述第五晶体管的沟道宽长比。
  7. 根据权利要求1所述的移位寄存器单元，其特征在于，所述第一下拉单元包括第六晶体管和第三电容；
    所述第六晶体管的栅极连接所述第一节点，第一极连接所述第二时钟信号端，第二极与所述第一信号输出端相连接；
    所述第三电容的一端连接所述第六晶体管的第二极，另一端与所述第六晶体管的栅极相连接。
  8. 根据权利要求1或7所述的移位寄存器单元，其特征在于，所述第二下拉单元包括第七晶体管和第四电容；
    所述第七晶体管的栅极连接所述第一节点，第一极连接所述第二时钟信号端，第二极与所述第二信号输出端相连接；
    所述第四电容的一端连接所述第七晶体管的第二极，另一端与所述第七晶体管的栅极相连接。
  9. 根据权利要求8所述的移位寄存器单元，其特征在于，当所述第一下拉单元包括第六晶体管，第二下拉单元包括第七晶体管时；
    所述第六晶体管的沟道宽长比大于所述第七晶体管的沟道宽长比。
  10. 一种栅极驱动电路，包括至少两级级联的如权利要求1-9任一项所述的移位寄存器单元；
    其中，第一级移位寄存器单元的信号输入端用于接收起始信号；以及
    除了第一级移位寄存器单元以外的移位寄存器单元的信号输入端连接上一级移位寄存器单元的第二信号输出端。
  11. 一种显示装置，包括如权利要求10所述的栅极驱动电路。
  12. 一种如权利要求1所述的移位寄存器单元的驱动方法，包括：
    在第一时段，第一控制单元将信号输入端的电压输出至第一节点，并将所述信号输入端输出的电压分别保存至第一下拉控制单元和第二下拉控制单元；第二控制单元将第一电压端的电压输出至第二节点；所述第一上拉控制单元和所述第二上拉控制单元将第二电压端的电压分别输出至第一信号输出端和第二信号输出端；以及所述第一下拉控制单元和所述第二下拉控制单元将第二时钟信号端的电压分别输出至所述第一信号输出端和所述第二信号输出端；
    在第二时段，所述第一下拉控制单元和所述第二下拉控制单元将所述第二时钟信号端的电压分别输出至所述第一信号输出端和所述第二信号输出端；所述第二控制单元将所述第一时钟信号端的电压输出至第二节点；以及
    在第三时段，所述第一控制单元将所述信号输入端的电压输出至所述第一节点，所述第二控制单元将所述第一电压端的电压输出至第二节点；所述第一上拉单元和所述第二上拉单元将所述第二电压端的电压分别输出至所述第一信号输出端和所述第二信号输出端；
    其中，在下一图像帧之前重复第二阶段和第三阶段的所述信号输入端、所述第一时钟信号端以及所述第二时钟信号端的控制信号，使得所述第一信号输出端和所述第二信号输出端保持输出所述第二电压端的电压。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105957556A (zh) * 2016-05-11 2016-09-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
KR102578837B1 (ko) * 2016-09-30 2023-09-15 엘지디스플레이 주식회사 게이트 구동 회로와 이를 이용한 표시장치
CN108428425B (zh) * 2017-02-15 2022-03-08 上海和辉光电股份有限公司 一种扫描驱动电路、移位寄存器及其驱动方法
CN106601208A (zh) * 2017-03-01 2017-04-26 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN109243351B (zh) 2017-07-10 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107316603B (zh) * 2017-08-31 2021-01-29 京东方科技集团股份有限公司 移位寄存单元和显示装置
CN107633799A (zh) * 2017-10-13 2018-01-26 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN107799070A (zh) * 2017-12-08 2018-03-13 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
CN108665865B (zh) * 2018-05-14 2020-12-01 昆山龙腾光电股份有限公司 栅极驱动单元以及显示装置
CN209265989U (zh) 2018-12-06 2019-08-16 北京京东方技术开发有限公司 移位寄存器、发光控制电路、显示面板
CN109584799A (zh) * 2019-02-02 2019-04-05 京东方科技集团股份有限公司 一种像素驱动电路、像素电路、显示面板和显示装置
WO2021053707A1 (ja) * 2019-09-17 2021-03-25 シャープ株式会社 表示装置およびその駆動方法
CN111445833B (zh) * 2020-05-09 2022-09-13 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路
CN112419960B (zh) * 2020-12-15 2022-09-23 云谷（固安）科技有限公司 移位寄存器、显示面板及显示装置
CN112599067B (zh) * 2020-12-15 2022-11-15 上海中航光电子有限公司 一种移位寄存电路及显示装置
US20240071312A1 (en) * 2021-03-23 2024-02-29 Boe Technology Group Co., Ltd. Shift register circuit and driving method thereof, gate driving circuit, and display device
CN113299334B (zh) * 2021-06-29 2023-10-20 上海中航光电子有限公司 一种移位寄存电路及显示装置
CN114038386B (zh) * 2021-11-30 2023-08-11 长沙惠科光电有限公司 栅极驱动器及显示装置
CN114333705A (zh) * 2021-12-30 2022-04-12 厦门天马显示科技有限公司 驱动电路、显示面板、显示装置和稳压控制方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104282285A (zh) * 2014-10-29 2015-01-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN104732946A (zh) * 2015-04-10 2015-06-24 京东方科技集团股份有限公司 一种移位寄存器和显示装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN105529009A (zh) * 2016-02-04 2016-04-27 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105957556A (zh) * 2016-05-11 2016-09-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729099B1 (ko) * 2005-09-20 2007-06-14 삼성에스디아이 주식회사 주사 구동회로와 이를 이용한 유기 전계발광 장치
KR100658284B1 (ko) * 2005-09-30 2006-12-14 삼성에스디아이 주식회사 주사 구동회로와 이를 이용한 유기 전계발광 장치
KR100762690B1 (ko) * 2005-11-07 2007-10-01 삼성에스디아이 주식회사 데이터구동회로와 이를 이용한 유기발광표시장치
KR100719670B1 (ko) * 2006-04-06 2007-05-18 삼성에스디아이 주식회사 데이터 구동부 및 이를 이용한 유기 전계발광 표시장치
KR100748321B1 (ko) * 2006-04-06 2007-08-09 삼성에스디아이 주식회사 주사 구동회로와 이를 이용한 유기 전계발광 표시장치
KR101272337B1 (ko) * 2006-09-01 2013-06-07 삼성디스플레이 주식회사 부분 화면 표시가 가능한 표시장치 및 그 구동방법
JP4912186B2 (ja) * 2007-03-05 2012-04-11 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
KR101678214B1 (ko) * 2010-03-11 2016-11-29 엘지디스플레이 주식회사 쉬프트 레지스터와 이를 이용한 표시장치
CN102479477B (zh) * 2010-11-26 2015-03-04 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
TWI493557B (zh) * 2011-04-28 2015-07-21 Au Optronics Corp 移位暫存器電路
CN102646387B (zh) * 2011-05-19 2014-09-17 京东方科技集团股份有限公司 移位寄存器及行扫描驱动电路
US9443608B2 (en) * 2012-04-25 2016-09-13 Joled Inc. Shift register having multiple output units connected in cascade as display device scan line driving circuit
CN104299583B (zh) * 2014-09-26 2016-08-17 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
US10019923B2 (en) * 2015-02-03 2018-07-10 Boe Technology Group Co., Ltd. Shift register and driving method thereof, gate driving circuit, display apparatus
CN104821148B (zh) * 2015-05-28 2016-11-09 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN104900189B (zh) * 2015-06-19 2017-08-01 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN104900192B (zh) * 2015-07-01 2017-10-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN104966506B (zh) * 2015-08-06 2017-06-06 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN105096865B (zh) * 2015-08-06 2018-09-07 京东方科技集团股份有限公司 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104282285A (zh) * 2014-10-29 2015-01-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104732946A (zh) * 2015-04-10 2015-06-24 京东方科技集团股份有限公司 一种移位寄存器和显示装置
CN105529009A (zh) * 2016-02-04 2016-04-27 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105957556A (zh) * 2016-05-11 2016-09-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置

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