WO2017177493A1 - 薄膜晶体管阵列面板及其制作方法 - Google Patents

薄膜晶体管阵列面板及其制作方法 Download PDF

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Publication number
WO2017177493A1
WO2017177493A1 PCT/CN2016/081564 CN2016081564W WO2017177493A1 WO 2017177493 A1 WO2017177493 A1 WO 2017177493A1 CN 2016081564 W CN2016081564 W CN 2016081564W WO 2017177493 A1 WO2017177493 A1 WO 2017177493A1
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Prior art keywords
layer
metal layer
thin film
film transistor
transistor array
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PCT/CN2016/081564
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English (en)
French (fr)
Inventor
周志超
夏慧
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/123,147 priority Critical patent/US10074817B2/en
Publication of WO2017177493A1 publication Critical patent/WO2017177493A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array panel and a method of fabricating the same.
  • the above conventional thin film transistor array panel is generally provided with a protective layer/passivation layer (Passivation) Layer).
  • Passivation protective layer/passivation layer
  • the fabrication of the protective/passivation layer requires a reticle process.
  • An object of the present invention is to provide a thin film transistor array panel and a manufacturing method thereof, which can simplify the fabrication process of the thin film transistor array panel and save manufacturing costs.
  • a thin film transistor array panel wherein the thin film transistor array panel comprises: a substrate; a thin film transistor comprising: a gate; a semiconductor layer; a source; and a drain; an insulating layer, the insulating layer is disposed on On the gate and the substrate; an etch barrier layer, the etch barrier layer is disposed on the semiconductor layer and the insulating layer; and an electrode layer, the electrode layer includes a first electrode portion and a second electrode portion The first electrode portion is disposed on the source, the first electrode portion is configured to cover and protect the source, the second electrode portion is disposed on the drain, and the second The electrode portion is configured to cover and protect the drain; wherein the semiconductor layer is disposed on the insulating layer, the etch barrier layer is provided with a first through hole and a second through hole, the source and The drain is connected to the semiconductor layer through the first via hole and the second via hole respectively; the gate is formed by disposing a first metal layer on the substrate and implementing the metal layer The first mask process is formed; The semiconductor layer is formed
  • the etch stop layer is further provided with a accommodating pit for accommodating at least a portion of the source, at least a portion of the drain, and the At least a portion of the electrode layer.
  • the accommodating pit is formed by performing the third mask process on the etch barrier material.
  • the semiconductor layer includes indium gallium zinc oxide.
  • the etch barrier layer serves to protect the semiconductor layer to prevent water vapor or oxygen from affecting the electrical stability of the indium gallium zinc oxide.
  • the channel is configured to perform the fourth mask process on the second metal layer and the third metal layer, and to the second metal layer and the third metal
  • the layer is formed by etching.
  • a thin film transistor array panel comprising: a substrate; a thin film transistor comprising: a gate; a semiconductor layer; a source; and a drain; an insulating layer, the insulating layer being disposed on the On the gate and the substrate; an etch barrier layer, the etch barrier layer is disposed on the semiconductor layer and the insulating layer; and an electrode layer, the electrode layer includes a first electrode portion and a second electrode portion, The first electrode portion is disposed on the source, the first electrode portion is configured to cover and protect the source, the second electrode portion is disposed on the drain, and the second electrode portion is For covering and protecting the drain; wherein the semiconductor layer is disposed on the insulating layer, the etch barrier layer is provided with a first via and a second via, the source and the A drain is connected to the semiconductor layer through the first via and the second via, respectively.
  • the gate electrode is formed by disposing a first metal layer on the substrate and performing a first mask process on the metal layer; a semiconductor material is disposed on the insulating layer, and the semiconductor material is formed by performing a second mask process; the first via hole and the second via hole are disposed on the insulating layer and the semiconductor layer Etching the barrier material and performing a third mask process on the etch barrier material; the source, the drain and the electrode layer are on the etch stop layer, the first pass Providing a second metal layer in the second through hole, then providing a third metal layer on the second metal layer, and performing a fourth light on the second metal layer and the third metal layer Formed by a mask process, wherein the source and the drain correspond to the second metal layer, and the first electrode portion and the second electrode portion of the electrode layer are both The three metal layers correspond.
  • the etch stop layer is further provided with a accommodating pit for accommodating at least a portion of the source, at least a portion of the drain, and the At least a portion of the electrode layer.
  • the accommodating pit is formed by performing the third mask process on the etch barrier material.
  • the semiconductor layer includes indium gallium zinc oxide.
  • the etch barrier layer serves to protect the semiconductor layer to prevent water vapor or oxygen from affecting the electrical stability of the indium gallium zinc oxide.
  • a channel between the source and the drain is used for a first integral composed of the source and the first electrode portion and by the drain and The second integral portion of the second electrode portion is formed.
  • the channel is configured to perform the fourth mask process on the second metal layer and the third metal layer, and to the second metal layer and the third metal
  • the layer is formed by etching.
  • a method of fabricating a thin film transistor array panel comprising the steps of: providing a first metal layer on the substrate, and performing a first mask process on the first metal layer to form the a gate electrode; B, the insulating layer is disposed on the substrate and the gate; C, a semiconductor material is disposed on the insulating layer, and a second mask process is performed on the semiconductor material to form the a semiconductor layer; D, an etch stop material is disposed on the insulating layer and the semiconductor layer, and a third mask process is performed on the etch barrier material to form the first via hole and the second via hole And forming a second metal layer on the etching barrier layer, in the first via hole, in the second via hole, and then providing a third metal layer on the second metal layer, and Performing a fourth mask process on the second metal layer and the third metal layer to form the source, the drain, and the electrode layer, wherein the source and the drain are both Corresponding to the second metal layer, the first electrode portion of the electrode layer and Each said second electrode portion
  • the etch stop layer is further provided with a accommodating trench for accommodating at least a portion of the source and at least a portion of the drain And at least a portion of the electrode layer.
  • the step D is: providing an etching stopper material on the insulating layer and the semiconductor layer, and performing a third mask process on the etching stopper material to form a The first through hole, the second through hole, and the receiving pit.
  • the semiconductor layer comprises indium gallium zinc oxide; the etch stop layer is for protecting the semiconductor layer to prevent water vapor or oxygen from affecting the indium gallium zinc oxide Electrical stability.
  • the method further includes the step of: simultaneously applying the hydrogen peroxide-based copper acid to the second metal layer and the third metal after the fourth mask process The layer is etched.
  • the invention can simplify the manufacturing process of the thin film transistor array panel and save the manufacturing cost.
  • FIG. 5 are schematic diagrams showing a method of fabricating a thin film transistor array panel of the present invention.
  • FIG. 6 is a flow chart of a method of fabricating a thin film transistor array panel of the present invention.
  • the thin film transistor array panel of the present invention can be applied to a display panel, which can be a TFT-LCD (Thin Film) Transistor Liquid Crystal Display, OLED (Organic Light Emitting) Diode, organic light emitting diode display panel) and so on.
  • a display panel which can be a TFT-LCD (Thin Film) Transistor Liquid Crystal Display, OLED (Organic Light Emitting) Diode, organic light emitting diode display panel) and so on.
  • the thin film transistor array panel of the present invention may be an array panel used in the thin film transistor liquid crystal display panel, in which case the second electrode portion 504 in the electrode layer in the thin film transistor array panel may be strip-shaped An electrode, the thin film transistor array panel is configured to form the thin film transistor liquid crystal display panel with a liquid crystal layer and a color filter array panel.
  • the thin film transistor array panel of the present invention may also be an array panel used in the organic light emitting diode display panel, in which case the second electrode portion 504 of the electrode layer in the thin film transistor array panel may be a cathode layer
  • the thin film transistor array panel is configured to form the organic light emitting diode display panel with an organic light emitting material layer and an anode layer.
  • the thin film transistor array panel of the present invention includes a substrate 101, a scan line, a thin film transistor, an insulating layer 201, an etch barrier layer 401, a data line, and an electrode layer.
  • the scan line and the data line are all connected to the thin film transistor, and the thin film transistor is connected to the electrode layer.
  • the thin film transistor includes a gate electrode 102, a semiconductor layer 301, a source electrode 501, and a drain electrode 502.
  • the insulating layer 201 is disposed on the gate electrode 102 and the substrate 101.
  • the etch stop layer 401 is disposed on the semiconductor layer 301 and the insulating layer 201.
  • the electrode layer includes a first electrode portion 503 and a second electrode portion 504.
  • the first electrode portion 503 is disposed on the source electrode 501, and the first electrode portion 503 is configured to cover the source electrode 501. And protecting, the first electrode portion 503 is in contact with the source 501, the second electrode portion 504 is disposed on the drain 502, and the second electrode portion 504 is configured to perform the drain 502 Covering and protecting, the second electrode portion 504 is in contact with the drain 502.
  • the semiconductor layer 301 is disposed on the insulating layer 201.
  • the etch stop layer 401 is provided with a first via 404 and a second via 405, and the source 501 and the drain 502 respectively pass through the A via hole 404 and the second via hole 405 are connected to the semiconductor layer 301.
  • the gate electrode 102 and the scan line are formed by providing a first metal layer on the substrate 101 and performing a first mask process on the metal layer. Specifically, the gate electrode 102 and the scan line are formed by performing the first mask process on the first metal layer and etching the first metal layer.
  • the semiconductor layer 301 is formed by disposing a semiconductor material on the insulating layer 201 and performing a second mask process on the semiconductor material. Specifically, the semiconductor layer 301 is formed by performing the second mask process on the semiconductor material and etching the semiconductor material.
  • the first via hole 404 and the second via hole 405 are formed by providing an etching stopper material on the insulating layer 201 and the semiconductor layer 301, and performing a third mask process on the etching stopper material. of.
  • the etch barrier layer 401 is further provided with a accommodating trench (402, 403) for accommodating at least a portion of the source 501 and the drain 502. At least a portion and at least a portion of the electrode layer.
  • the accommodating pits (402, 403) are formed by performing the third mask process on the etch barrier material. That is, the first through hole 404, the second through hole 405, and the receiving pit (402, 403) are all formed by the same mask process (the third mask process). Specifically, the first through hole 404, the second through hole 405, and the receiving pit (402, 403) are all performed by performing the third mask process on the etching stopper material, and The etch stop material is formed by etching.
  • the source 501, the drain 502, the data line, and the electrode layer are disposed on the etch stop layer 401, in the first via 404, and in the second via 405.
  • the second metal layer and the third metal layer may be simultaneously etched using a hydrogen peroxide-based copper acid.
  • a channel between the source 501 and the drain 502 is used to separate the source 501 and the drain 502, and is used to separate the first electrode portion 503 and the second electrode portion 504 That is, the channel is for a first body composed of the source electrode 501 and the first electrode portion 503 and a second body composed of the drain electrode 502 and the second electrode portion 504 Separate.
  • the channel is formed by performing the fourth mask process on the second metal layer and the third metal layer, and etching the second metal layer and the third metal layer.
  • a protective layer/passivation layer can be saved in the thin film transistor array panel while saving a mask process required for fabricating the protective layer/the passivation layer, and further, due to the electrode
  • the layers and the source and the drain are formed in the same mask process, so that the two mask processes can be combined into a mask process, that is, a mask process is saved. That is, the above technical solution is advantageous in saving (reducing) the six mask processes required for fabricating the thin film transistor array panel into four mask processes.
  • the semiconductor layer 301 includes indium gallium zinc oxide. That is, the semiconductor material is composed of the indium gallium zinc oxide.
  • the semiconductor layer 301 may also include amorphous silicon, low temperature polysilicon, or the like.
  • the etch stop layer 401 is used to protect the semiconductor layer 301 to prevent water vapor or oxygen from affecting the electrical stability of the semiconductor layer 301 (the indium gallium zinc oxide). Sex.
  • FIG. 1 to FIG. 5 are schematic diagrams showing a method of fabricating a thin film transistor array panel of the present invention.
  • 6 is a flow chart of a method of fabricating a thin film transistor array panel of the present invention.
  • the manufacturing method of the thin film transistor array panel of the present invention comprises the following steps:
  • a first metal layer is disposed on the substrate 101, and a first mask process is performed on the first metal layer to form the gate electrode 102 and the scan line.
  • the first metal layer is disposed on the substrate 101, the first mask process is performed on the first metal layer, and the first metal layer is etched to form the gate 102 and the scan line.
  • the insulating layer 201 is disposed on the substrate 101, the gate 102, and the scan line.
  • a semiconductor material is disposed on the insulating layer 201, and a second mask process is performed on the semiconductor material to form the semiconductor layer 301.
  • the semiconductor material is disposed on the insulating layer 201, a second mask process is performed on the semiconductor material, and the semiconductor material is etched to form the semiconductor layer 301.
  • step 604 providing an etch barrier material on the insulating layer 201 and the semiconductor layer 301, and performing a third mask process on the etch barrier material to form the first via hole 404 and the The second through hole 405.
  • an etch stop material is disposed on the insulating layer 201 and the semiconductor layer 301, a third mask process is performed on the etch barrier material, and the etch barrier material is etched to form the first a through hole 404 and the second through hole 405.
  • step 605 providing a second metal layer on the etching stopper layer 401, the first via hole 404, the second via hole 405, and then placing a third layer on the second metal layer a metal layer, and performing a fourth mask process on the second metal layer and the third metal layer to form the source 501, the drain 502, the data line, and the electrode layer, wherein
  • the source 501, the drain 502, and the data line each correspond to the second metal layer, and the first electrode portion 503 and the second electrode portion 504 of the electrode layer are both
  • the third metal layer corresponds to the above.
  • the first electrode portion 503 is disposed on the source electrode 501, the first electrode portion 503 is used for covering and protecting the source electrode 501, and the first electrode portion 503 is in contact with the source electrode 501.
  • the second electrode portion 504 is disposed on the drain 502, and the second electrode portion 504 is configured to cover and protect the drain 502, the second electrode portion 504 and the drain 502 contact.
  • the second metal layer is disposed on the etch stop layer 401, the first via 404, and the second via 405, and then a third metal is disposed on the second metal layer.
  • a fourth mask process is performed on the second metal layer and the third metal layer, and the second metal layer and the third metal layer are etched to form the source 501 and the The drain 502, the data line, and the electrode layer.
  • the hydrogen peroxide-based copper acid is used to simultaneously etch the second metal layer and the third metal layer.
  • the etch stop layer 401 is further provided with a accommodating pit (402, 403) for accommodating at least a part of the source 501. At least a portion of the drain 502 and at least a portion of the electrode layer.
  • the step D is:
  • An etching stopper material is disposed on the insulating layer 201 and the semiconductor layer 301, and a third mask process is performed on the etching stopper material to form the first via hole 404, the second via hole 405, and The receiving pits (402, 403).
  • a protective layer/passivation layer can be saved in the thin film transistor array panel while saving a mask process required for fabricating the protective layer/the passivation layer, and further, due to the electrode
  • the layers and the source and the drain are formed in the same mask process, so that the two mask processes can be combined into a mask process, that is, a mask process is saved. That is, the above technical solution is advantageous in saving (reducing) the six mask processes required for fabricating the thin film transistor array panel into four mask processes.
  • the semiconductor layer 301 includes indium gallium zinc oxide. That is, the semiconductor material is composed of the indium gallium zinc oxide.
  • the semiconductor layer 301 may also include amorphous silicon, low temperature polysilicon, or the like.
  • the etch stop layer 401 is used to protect the semiconductor layer 301 to prevent water vapor or oxygen from affecting the electrical stability of the semiconductor layer 301 (the indium gallium zinc oxide).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管阵列面板及其制作方法，薄膜晶体管阵列面板包括：基板（101）；栅极（102）；半导体层（301）；源极（501）；漏极（502）；绝缘层（201）；蚀刻阻挡层（401），设置于半导体层（301）及绝缘层（201）上；第一电极部（503），设置于源极（501）上，用于对源极（501）进行覆盖和保护；第二电极部（504），设置于漏极（502）上，用于对漏极（502）进行覆盖和保护。该制作方法能简化制作工艺，节省制作成本。

Description

薄膜晶体管阵列面板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列面板及其制作方法。
 背景技术
传统的薄膜晶体管阵列面板中一般需要六道光罩制程。
上述传统的薄膜晶体管阵列面板一般设置有保护层/钝化层（Passivation Layer）。该保护层/钝化层的制作需要耗费其中的一道光罩制程。
由于需要六道光罩制程，因此上述传统的薄膜晶体管阵列面板的制作工艺较复杂，成本较高。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列面板及其制作方法，其能简化薄膜晶体管阵列面板的制作工艺，节省制作成本。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：基板；薄膜晶体管，所述薄膜晶体管包括：栅极；半导体层；源极；以及漏极；绝缘层，所述绝缘层设置在所述栅极和所述基板上；蚀刻阻挡层，所述蚀刻阻挡层设置于所述半导体层及所述绝缘层上；电极层，所述电极层包括第一电极部和第二电极部，所述第一电极部设置于所述源极上，所述第一电极部用于对所述源极进行覆盖和保护，所述第二电极部设置于所述漏极上，所述第二电极部用于对所述漏极进行覆盖和保护；其中，所述半导体层设置于所述绝缘层上，所述蚀刻阻挡层设置有第一通孔和第二通孔，所述源极和所述漏极分别通过所述第一通孔和所述第二通孔与所述半导体层连接；所述栅极是通过在所述基板上设置第一金属层，并对所述金属层实施第一光罩制程来形成的；所述半导体层是通过在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程来形成的；所述第一通孔和所述第二通孔是通过在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程来形成的；所述源极、所述漏极和所述电极层是通过在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程来形成的，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应；所述源极与所述漏极之间的沟道用于将由所述源极和所述第一电极部所组成的第一整体和由所述漏极和所述第二电极部所组成的第二整体分隔。
在上述薄膜晶体管阵列面板中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
在上述薄膜晶体管阵列面板中，所述容置坑槽是通过对所述蚀刻阻挡材料实施所述第三光罩制程来形成的。
在上述薄膜晶体管阵列面板中，所述半导体层包括铟镓锌氧化物。
在上述薄膜晶体管阵列面板中，所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
在上述薄膜晶体管阵列面板中，所述沟道是对所述第二金属层和所述第三金属层实施所述第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻来形成的。
一种薄膜晶体管阵列面板，所述薄膜晶体管阵列面板包括：基板；薄膜晶体管，所述薄膜晶体管包括：栅极；半导体层；源极；以及漏极；绝缘层，所述绝缘层设置在所述栅极和所述基板上；蚀刻阻挡层，所述蚀刻阻挡层设置于所述半导体层及所述绝缘层上；电极层，所述电极层包括第一电极部和第二电极部，所述第一电极部设置于所述源极上，所述第一电极部用于对所述源极进行覆盖和保护，所述第二电极部设置于所述漏极上，所述第二电极部用于对所述漏极进行覆盖和保护；其中，所述半导体层设置于所述绝缘层上，所述蚀刻阻挡层设置有第一通孔和第二通孔，所述源极和所述漏极分别通过所述第一通孔和所述第二通孔与所述半导体层连接。
在上述薄膜晶体管阵列面板中，所述栅极是通过在所述基板上设置第一金属层，并对所述金属层实施第一光罩制程来形成的；所述半导体层是通过在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程来形成的；所述第一通孔和所述第二通孔是通过在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程来形成的；所述源极、所述漏极和所述电极层是通过在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程来形成的，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应。
在上述薄膜晶体管阵列面板中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
在上述薄膜晶体管阵列面板中，所述容置坑槽是通过对所述蚀刻阻挡材料实施所述第三光罩制程来形成的。
在上述薄膜晶体管阵列面板中，所述半导体层包括铟镓锌氧化物。
在上述薄膜晶体管阵列面板中，所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
在上述薄膜晶体管阵列面板中，所述源极与所述漏极之间的沟道用于将由所述源极和所述第一电极部所组成的第一整体和由所述漏极和所述第二电极部所组成的第二整体分隔。
在上述薄膜晶体管阵列面板中，所述沟道是对所述第二金属层和所述第三金属层实施所述第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻来形成的。
一种上述薄膜晶体管阵列面板的制作方法，所述方法包括以下步骤：A、在所述基板上设置第一金属层，并对所述第一金属层实施第一光罩制程，以形成所述栅极；B、在所述基板和所述栅极上设置所述绝缘层；C、在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程，以形成所述半导体层；D、在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔和所述第二通孔；E、在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程，以形成所述源极、所述漏极和所述电极层，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应。
在上述薄膜晶体管阵列面板的制作方法中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
在上述薄膜晶体管阵列面板的制作方法中，所述步骤D为：在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔、所述第二通孔和所述容置坑槽。
在上述薄膜晶体管阵列面板的制作方法中，所述半导体层包括铟镓锌氧化物；所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
在上述薄膜晶体管阵列面板的制作方法中，所述方法还包括以下步骤：在所述第四光罩制程之后，采用双氧水系的铜酸来同时对所述第二金属层和所述第三金属层进行蚀刻。
 有益效果
相对现有技术，本发明能简化薄膜晶体管阵列面板的制作工艺，节省制作成本。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
图1至图5为本发明的薄膜晶体管阵列面板的制作方法的示意图；
图6为本发明的薄膜晶体管阵列面板的制作方法的流程图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的薄膜晶体管阵列面板可以应用于显示面板中，所述显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
本发明的薄膜晶体管阵列面板可以是用于所述薄膜晶体管液晶显示面板中的阵列面板，在这种情况下，所述薄膜晶体管阵列面板中的电极层中的第二电极部504可以是条状电极，所述薄膜晶体管阵列面板用于与液晶层、彩色滤光片阵列面板组成所述薄膜晶体管液晶显示面板。
本发明的薄膜晶体管阵列面板也可以是用于所述有机发光二极管显示面板中的阵列面板，在这种情况下，所述薄膜晶体管阵列面板中的电极层的第二电极部504可以是阴极层，所述薄膜晶体管阵列面板用于与有机发光材料层、阳极层组成所述有机发光二极管显示面板。
参考图5，本发明的薄膜晶体管阵列面板包括基板101、扫描线、薄膜晶体管、绝缘层201、蚀刻阻挡层401、数据线、电极层。
其中，所述扫描线、所述数据线均与所述薄膜晶体管连接，所述薄膜晶体管与所述电极层连接。
所述薄膜晶体管包括栅极102、半导体层301、源极501、漏极502。
所述绝缘层201设置在所述栅极102和所述基板101上。所述蚀刻阻挡层401设置于所述半导体层301及所述绝缘层201上。所述电极层包括第一电极部503和第二电极部504，所述第一电极部503设置于所述源极501上，所述第一电极部503用于对所述源极501进行覆盖和保护，所述第一电极部503与所述源极501接触，所述第二电极部504设置于所述漏极502上，所述第二电极部504用于对所述漏极502进行覆盖和保护，所述第二电极部504与所述漏极502接触。
所述半导体层301设置于所述绝缘层201上，所述蚀刻阻挡层401设置有第一通孔404和第二通孔405，所述源极501和所述漏极502分别通过所述第一通孔404和所述第二通孔405与所述半导体层301连接。
在本发明的薄膜晶体管阵列面板中，所述栅极102和所述扫描线是通过在所述基板101上设置第一金属层，并对所述金属层实施第一光罩制程来形成的。具体地，所述栅极102和所述扫描线均是通过对所述第一金属层实施所述第一光罩制程，并对所述第一金属层进行蚀刻来形成的。
所述半导体层301是通过在所述绝缘层201上设置半导体材料，并对所述半导体材料实施第二光罩制程来形成的。具体地，所述半导体层301是通过在所述半导体材料实施所述第二光罩制程，并对所述半导体材料进行蚀刻来形成的。
所述第一通孔404和所述第二通孔405是通过在所述绝缘层201和所述半导体层301上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程来形成的。所述蚀刻阻挡层401上还设置有容置坑槽（402、403），所述容置坑槽（402、403）用于容置所述源极501的至少一部分、所述漏极502的至少一部分和所述电极层的至少一部分。所述容置坑槽（402、403）是通过对所述蚀刻阻挡材料实施所述第三光罩制程来形成的。即，所述第一通孔404、所述第二通孔405和所述容置坑槽（402、403）均是通过同一道光罩制程（所述第三光罩制程）来形成的。具体地，所述第一通孔404、所述第二通孔405和所述容置坑槽（402、403）均是通过对所述蚀刻阻挡材料实施所述第三光罩制程，并对所述蚀刻阻挡材料进行蚀刻来形成的。
所述源极501、所述漏极502、所述数据线和所述电极层是通过在所述蚀刻阻挡层401上、所述第一通孔404内、所述第二通孔405内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程来形成的，其中，所述源极501、所述漏极502和所述数据线均与所述第二金属层对应，所述电极层的所述第一电极部503和所述第二电极部504均与所述第三金属层对应。在所述第四光罩制程之后，所述第二金属层和所述第三金属层均可同时采用双氧水系的铜酸来进行蚀刻。所述源极501与所述漏极502之间的沟道用于将所述源极501和所述漏极502分隔，以及用于将第一电极部503和所述第二电极部504分隔，即，所述沟道用于将由所述源极501和所述第一电极部503所组成的第一整体和由所述漏极502和所述第二电极部504所组成的第二整体分隔。所述沟道是对所述第二金属层和所述第三金属层实施所述第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻来形成的。
通过上述技术方案，可以在所述薄膜晶体管阵列面板中节省保护层/钝化层，同时节省为制作所述保护层/所述钝化层所需要的一道光罩制程，此外，由于所述电极层和源极、所述漏极均在同一道光罩制程中形成，因此可以将两道光罩制程合成一道光罩制程，即，节约了一道光罩制程。即，上述技术方案有利于将为制作所述薄膜晶体管阵列面板所需的六道光罩制程节省（缩减）为四道光罩制程。
在本发明的薄膜晶体管阵列面板中，所述半导体层301包括铟镓锌氧化物。即，所述半导体材料是由所述铟镓锌氧化物组成的。所述半导体层301还可以包括非晶硅、低温多晶硅等。
在本发明的薄膜晶体管阵列面板中，所述蚀刻阻挡层401用于保护所述半导体层301，以防止水蒸气或氧气影响所述半导体层301（所述铟镓锌氧化物）的电性稳定性。
参考图1至图6，图1至图5为本发明的薄膜晶体管阵列面板的制作方法的示意图。图6为本发明的薄膜晶体管阵列面板的制作方法的流程图。
本发明的薄膜晶体管阵列面板的制作方法包括以下步骤：
A（步骤601）、在所述基板101上设置第一金属层，并对所述第一金属层实施第一光罩制程，以形成所述栅极102和所述扫描线。具体地，在所述基板101上设置所述第一金属层，对所述第一金属层实施所述第一光罩制程，并对所述第一金属层进行蚀刻，以形成所述栅极102和所述扫描线。
B（步骤602）、在所述基板101、所述栅极102和所述扫描线上设置所述绝缘层201。
C（步骤603）、在所述绝缘层201上设置半导体材料，并对所述半导体材料实施第二光罩制程，以形成所述半导体层301。具体地，在所述绝缘层201上设置所述半导体材料，对所述半导体材料实施第二光罩制程，并对所述半导体材料进行蚀刻，以形成所述半导体层301。
D（步骤604）、在所述绝缘层201和所述半导体层301上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔404和所述第二通孔405。具体地，在所述绝缘层201和所述半导体层301上设置蚀刻阻挡材料，对所述蚀刻阻挡材料实施第三光罩制程，并对所述蚀刻阻挡材料进行蚀刻，以形成所述第一通孔404和所述第二通孔405。
E（步骤605）、在所述蚀刻阻挡层401上、所述第一通孔404内、所述第二通孔405内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程，以形成所述源极501、所述漏极502、所述数据线和所述电极层，其中，所述源极501、所述漏极502和所述数据线均与所述第二金属层对应，所述电极层的所述第一电极部503和所述第二电极部504均与所述第三金属层对应。所述第一电极部503设置于所述源极501上，所述第一电极部503用于对所述源极501进行覆盖和保护，所述第一电极部503与所述源极501接触，所述第二电极部504设置于所述漏极502上，所述第二电极部504用于对所述漏极502进行覆盖和保护，所述第二电极部504与所述漏极502接触。
具体地，在所述蚀刻阻挡层401上、所述第一通孔404内、所述第二通孔405内设置所述第二金属层，然后在所述第二金属层上设置第三金属层，对所述第二金属层和所述第三金属层实施第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻，以形成所述源极501、所述漏极502、所述数据线和所述电极层。其中，在所述第四光罩制程之后，采用双氧水系的铜酸来同时对所述第二金属层和所述第三金属层进行蚀刻。
作为一种改进，所述蚀刻阻挡层401上还设置有容置坑槽（402、403），所述容置坑槽（402、403）用于容置所述源极501的至少一部分、所述漏极502的至少一部分和所述电极层的至少一部分。
在本发明的薄膜晶体管阵列面板的制作方法中，所述步骤D为：
在所述绝缘层201和所述半导体层301上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔404、所述第二通孔405和所述容置坑槽（402、403）。
通过上述技术方案，可以在所述薄膜晶体管阵列面板中节省保护层/钝化层，同时节省为制作所述保护层/所述钝化层所需要的一道光罩制程，此外，由于所述电极层和源极、所述漏极均在同一道光罩制程中形成，因此可以将两道光罩制程合成一道光罩制程，即，节约了一道光罩制程。即，上述技术方案有利于将为制作所述薄膜晶体管阵列面板所需的六道光罩制程节省（缩减）为四道光罩制程。
在本发明的薄膜晶体管阵列面板的制作方法中，所述半导体层301包括铟镓锌氧化物。即，所述半导体材料是由所述铟镓锌氧化物组成的。所述半导体层301还可以包括非晶硅、低温多晶硅等。
所述蚀刻阻挡层401用于保护所述半导体层301，以防止水蒸气或氧气影响所述半导体层301（所述铟镓锌氧化物）的电性稳定性。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    基板；
    薄膜晶体管，所述薄膜晶体管包括：
    栅极；
    半导体层；
    源极；以及
    漏极；
    绝缘层，所述绝缘层设置在所述栅极和所述基板上；
    蚀刻阻挡层，所述蚀刻阻挡层设置于所述半导体层及所述绝缘层上；
    电极层，所述电极层包括第一电极部和第二电极部，所述第一电极部设置于所述源极上，所述第一电极部用于对所述源极进行覆盖和保护，所述第二电极部设置于所述漏极上，所述第二电极部用于对所述漏极进行覆盖和保护；
    其中，所述半导体层设置于所述绝缘层上，所述蚀刻阻挡层设置有第一通孔和第二通孔，所述源极和所述漏极分别通过所述第一通孔和所述第二通孔与所述半导体层连接；
    所述栅极是通过在所述基板上设置第一金属层，并对所述金属层实施第一光罩制程来形成的；
    所述半导体层是通过在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程来形成的；
    所述第一通孔和所述第二通孔是通过在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程来形成的；
    所述源极、所述漏极和所述电极层是通过在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程来形成的，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应；
    所述源极与所述漏极之间的沟道用于将由所述源极和所述第一电极部所组成的第一整体和由所述漏极和所述第二电极部所组成的第二整体分隔。
  2. 根据权利要求1所述的薄膜晶体管阵列面板，其中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
  3. 根据权利要求2所述的薄膜晶体管阵列面板，其中，所述容置坑槽是通过对所述蚀刻阻挡材料实施所述第三光罩制程来形成的。
  4. 根据权利要求1所述的薄膜晶体管阵列面板，其中，所述半导体层包括铟镓锌氧化物。
  5. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
  6. 根据权利要求1所述的薄膜晶体管阵列面板，其中，所述沟道是对所述第二金属层和所述第三金属层实施所述第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻来形成的。
  7. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    基板；
    薄膜晶体管，所述薄膜晶体管包括：
    栅极；
    半导体层；
    源极；以及
    漏极；
    绝缘层，所述绝缘层设置在所述栅极和所述基板上；
    蚀刻阻挡层，所述蚀刻阻挡层设置于所述半导体层及所述绝缘层上；
    电极层，所述电极层包括第一电极部和第二电极部，所述第一电极部设置于所述源极上，所述第一电极部用于对所述源极进行覆盖和保护，所述第二电极部设置于所述漏极上，所述第二电极部用于对所述漏极进行覆盖和保护；
    其中，所述半导体层设置于所述绝缘层上，所述蚀刻阻挡层设置有第一通孔和第二通孔，所述源极和所述漏极分别通过所述第一通孔和所述第二通孔与所述半导体层连接。
  8. 根据权利要求7所述的薄膜晶体管阵列面板，其中，所述栅极是通过在所述基板上设置第一金属层，并对所述金属层实施第一光罩制程来形成的；
    所述半导体层是通过在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程来形成的；
    所述第一通孔和所述第二通孔是通过在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程来形成的；
    所述源极、所述漏极和所述电极层是通过在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程来形成的，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应。
  9. 根据权利要求8所述的薄膜晶体管阵列面板，其中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
  10. 根据权利要求9所述的薄膜晶体管阵列面板，其中，所述容置坑槽是通过对所述蚀刻阻挡材料实施所述第三光罩制程来形成的。
  11. 根据权利要求7所述的薄膜晶体管阵列面板，其中，所述半导体层包括铟镓锌氧化物。
  12. 根据权利要求11所述的薄膜晶体管阵列面板，其中，所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
  13. 根据权利要求7所述的薄膜晶体管阵列面板，其中，所述源极与所述漏极之间的沟道用于将由所述源极和所述第一电极部所组成的第一整体和由所述漏极和所述第二电极部所组成的第二整体分隔。
  14. 根据权利要求13所述的薄膜晶体管阵列面板，其中，所述沟道是对所述第二金属层和所述第三金属层实施所述第四光罩制程，并对所述第二金属层和所述第三金属层进行蚀刻来形成的。
  15. 一种如权利要求7所述的薄膜晶体管阵列面板的制作方法，其中，所述方法包括以下步骤：
    A、在所述基板上设置第一金属层，并对所述第一金属层实施第一光罩制程，以形成所述栅极；
    B、在所述基板和所述栅极上设置所述绝缘层；
    C、在所述绝缘层上设置半导体材料，并对所述半导体材料实施第二光罩制程，以形成所述半导体层；
    D、在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔和所述第二通孔；
    E、在所述蚀刻阻挡层上、所述第一通孔内、所述第二通孔内设置第二金属层，然后在所述第二金属层上设置第三金属层，并对所述第二金属层和所述第三金属层实施第四光罩制程，以形成所述源极、所述漏极和所述电极层，其中，所述源极和所述漏极均与所述第二金属层对应，所述电极层的所述第一电极部和所述第二电极部均与所述第三金属层对应。
  16. 根据权利要求15所述的薄膜晶体管阵列面板的制作方法，其中，所述蚀刻阻挡层上还设置有容置坑槽，所述容置坑槽用于容置所述源极的至少一部分、所述漏极的至少一部分和所述电极层的至少一部分。
  17. 根据权利要求16所述的薄膜晶体管阵列面板的制作方法，其中，所述步骤D为：
    在所述绝缘层和所述半导体层上设置蚀刻阻挡材料，并对所述蚀刻阻挡材料实施第三光罩制程，以形成所述第一通孔、所述第二通孔和所述容置坑槽。
  18. 根据权利要求15所述的薄膜晶体管阵列面板的制作方法，其中，所述半导体层包括铟镓锌氧化物；
    所述蚀刻阻挡层用于保护所述半导体层，以防止水蒸气或氧气影响所述铟镓锌氧化物的电性稳定性。
  19. 根据权利要求15所述的薄膜晶体管阵列面板的制作方法，其中，所述方法还包括以下步骤：
    在所述第四光罩制程之后，采用双氧水系的铜酸来同时对所述第二金属层和所述第三金属层进行蚀刻。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108010917A (zh) * 2017-11-02 2018-05-08 中华映管股份有限公司 有源器件阵列基板及其制作方法
CN112331679B (zh) * 2020-11-05 2022-08-19 湖北长江新型显示产业创新中心有限公司 显示装置
US20250015091A1 (en) * 2022-06-30 2025-01-09 Fuzhou Boe Optoelectronics Technology Co., Ltd. Array substrate, method for manufacturing same, and display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1462901A (zh) * 2002-05-28 2003-12-24 友达光电股份有限公司 液晶显示装置的有源阵列基板及其制造方法
US20040124417A1 (en) * 2001-03-02 2004-07-01 Woo Young So Active matrix display device and manufacturing method thereof
CN104037129A (zh) * 2014-06-20 2014-09-10 深圳市华星光电技术有限公司 Tft背板的制造方法及tft背板结构
CN104362127A (zh) * 2014-11-21 2015-02-18 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制造设备
CN105390507A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 Tft阵列基板的制备方法、阵列基板及显示装置
CN105529336A (zh) * 2016-01-28 2016-04-27 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法和液晶面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100963104B1 (ko) * 2008-07-08 2010-06-14 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
TWI491032B (zh) * 2013-02-05 2015-07-01 Innolux Corp 主動矩陣式影像感測面板及裝置
TW201523738A (zh) * 2013-12-06 2015-06-16 中華映管股份有限公司 薄膜電晶體基板及其製造方法
TWI565082B (zh) * 2015-04-14 2017-01-01 鴻海精密工業股份有限公司 薄膜電晶體及其製造方法
CN104867942B (zh) * 2015-04-29 2018-03-06 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
TWI578546B (zh) * 2015-05-28 2017-04-11 鴻海精密工業股份有限公司 薄膜電晶體的製造方法
JP6668160B2 (ja) * 2016-05-06 2020-03-18 株式会社ジャパンディスプレイ 表示装置の製造方法
KR102519678B1 (ko) * 2016-08-01 2023-04-07 삼성디스플레이 주식회사 유기 발광 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040124417A1 (en) * 2001-03-02 2004-07-01 Woo Young So Active matrix display device and manufacturing method thereof
CN1462901A (zh) * 2002-05-28 2003-12-24 友达光电股份有限公司 液晶显示装置的有源阵列基板及其制造方法
CN104037129A (zh) * 2014-06-20 2014-09-10 深圳市华星光电技术有限公司 Tft背板的制造方法及tft背板结构
CN104362127A (zh) * 2014-11-21 2015-02-18 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制造设备
CN105390507A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 Tft阵列基板的制备方法、阵列基板及显示装置
CN105529336A (zh) * 2016-01-28 2016-04-27 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法和液晶面板

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