US10074817B2 - Thin film transistor array panel and method of fabricating the same - Google Patents

Thin film transistor array panel and method of fabricating the same Download PDF

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US10074817B2
US10074817B2 US15/123,147 US201615123147A US10074817B2 US 10074817 B2 US10074817 B2 US 10074817B2 US 201615123147 A US201615123147 A US 201615123147A US 10074817 B2 US10074817 B2 US 10074817B2
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layer
electrode
metal layer
thin film
film transistor
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US20180097190A1 (en
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Zhichao ZHOU
Hui Xia
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H01L51/0508—
    • H01L27/1225—
    • H01L27/1259—
    • H01L27/3262—
    • H01L29/66765—
    • H01L29/768—
    • H01L29/78618—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to a display technique field, and more particularly to a thin film transistor array panel and a method of fabricating the same.
  • the above conventional thin film transistor array panel generally has a protective layer/a passivation layer.
  • a production of the protective layer/the passivation layer needs to consume one of the mask processes.
  • the above conventional thin film transistor array panel has a relatively complex fabricating process and a relatively high cost.
  • An object of the present invention is to provide a thin film transistor array panel and a method of fabricating the same, which can simplify the fabricating process of the thin film transistor array panel and reduce the fabricating cost.
  • the present invention provides a technical solution as follows.
  • a thin film transistor array panel comprising: a substrate; a thin film transistor, comprising: a gate electrode; a semiconductor layer; a source electrode; and a drain electrode; an insulating layer disposed on the gate electrode and the substrate; an etch stop layer disposed on the semiconductor layer and the insulating layer; an electrode layer, comprising a first electrode portion and a second electrode portion, wherein the first electrode portion is disposed on the source electrode and configured to cover and protect the source electrode, and the second electrode portion is disposed on the drain electrode and configured to cover and protect the drain electrode; wherein the semiconductor layer is disposed on the insulating layer, the etch stop layer has a first through hole and a second through hole, and the source electrode and the drain electrode are connected with the semiconductor layer through the first through hole and the second through hole respectively; wherein the gate electrode is formed by disposing a first metal layer on the substrate and performing a first mask process on the first metal layer; wherein the semiconductor layer is formed by disposing a semiconductor material on the insulating layer and performing a second
  • the thin film transistor array panel further comprises receiving cavities formed in the etch stop layer, wherein the receiving cavities are configured to receive at least one part of the source electrode, at least one part of the drain electrode and at least one part of the electrode layer.
  • the receiving cavities are formed by performing the third mask process on the etch stop material.
  • the semiconductor layer comprises indium gallium zinc oxide.
  • the etch stop layer is configured to protect the semiconductor layer from water vapor or oxygen gas affecting an electrical stability of the indium gallium zinc oxide.
  • the channel is formed by performing the fourth mask process to the second metal layer and the third metal layer, and etching the second metal layer and the third metal layer.
  • a thin film transistor array panel comprising: a substrate; a thin film transistor, comprising: a gate electrode; a semiconductor layer; a source electrode; and a drain electrode; an insulating layer disposed on the gate electrode and the substrate; an etch stop layer disposed on the semiconductor layer and the insulating layer; an electrode layer, comprising a first electrode portion and a second electrode portion, wherein the first electrode portion is disposed on the source electrode and configured to cover and protect the source electrode, and the second electrode portion is disposed on the drain electrode and configured to cover and protect the drain electrode; and wherein the semiconductor layer is disposed on the insulating layer, the etch stop layer has a first through hole and a second through hole, and the source electrode and the drain electrode are connected with the semiconductor layer through the first through hole and the second through hole respectively.
  • the gate electrode is formed by disposing a first metal layer on the substrate and performing a first mask process on the first metal layer; wherein the semiconductor layer is formed by disposing a semiconductor material on the insulating layer and performing a second mask process on the semiconductor material; wherein the first through hole and the second through hole are formed by disposing an etch stop material on the insulating layer and the semiconductor layer and performing a third mask process on the etch stop material; and wherein the source electrode, the drain electrode and the electrode layer are formed by disposing a second metal layer on the etch stop layer, in the first through hole and in the second through hole, respectively, then disposing a third metal layer on the second metal layer and performing a fourth mask process to the second metal layer and the third metal layer, wherein the source electrode and the drain electrode are both corresponding to the second metal layer, and the first electrode portion and the second electrode portion of the electrode layer are both corresponding to the third metal layer.
  • the thin film transistor array panel further comprises receiving cavities formed in the etch stop layer, wherein the receiving cavities are configured to receive at least one part of the source electrode, at least one part of the drain electrode, and at least one part of the electrode layer.
  • the receiving cavities are formed by performing the third mask process on the etch stop material.
  • the semiconductor layer comprises indium gallium zinc oxide.
  • the etch stop layer is configured to protect the semiconductor layer from water vapor or oxygen gas affecting an electrical stability of the indium gallium zinc oxide.
  • a channel between the source electrode and the drain electrode is configured to isolate a first entirety constructed by the source electrode and the first electrode portion from a second entirety constructed by the drain electrode and the second electrode portion.
  • the channel is formed by performing the fourth mask process to the second metal layer and the third metal layer, and etching the second metal layer and the third metal layer.
  • a method of fabricating a thin film transistor array panel described above comprising the following steps of: (A) disposing a first metal layer on the substrate, and performing a first mask process to the first metal layer for forming the gate electrode; (B) disposing the insulating layer on the substrate and the gate electrode; (C) disposing a semiconductor material on the insulating layer, and performing a second mask process on the semiconductor material for forming the semiconductor layer; (D) disposing an etch stop material on the insulating layer and the semiconductor layer, and performing a third mask process to the etch stop material for forming the first through hole and the second through hole; and (E) disposing a second metal layer on the etch stop layer, in the first through hole and in the second through hole, then disposing a third metal layer on the second metal layer, and performing a fourth mask process on the second metal layer and the third metal layer for forming the source electrode, the drain electrode and the electrode layer, wherein the source electrode and the drain electrode are both corresponding to the second metal layer, and the first
  • the method further comprising receiving cavities formed in the etch stop layer, wherein the receiving cavities are configured to receive at least one part of the source electrode, at least one part of the drain electrode and at least one part of the electrode layer.
  • the step (D) comprises: disposing the etch stop material on the insulating layer and the semiconductor layer, and performing the third mask process on the etch stop material for forming the first through hole, the second through hole and the receiving cavities.
  • the semiconductor layer comprises indium gallium zinc oxide; and the etch stop layer is configured to protect the semiconductor layer from water vapor or oxygen gas affecting an electrical stability of the indium gallium zinc oxide.
  • the method further comprises the following step of: etching the second metal layer and the third metal layer at the same time by a copper etching solution of a hydrogen peroxide system after the fourth mask process is performed.
  • the present invention can simplify the fabricating process of the thin film transistor array panel and reduce the fabricating cost.
  • FIGS. 1-5 are schematic diagrams of a method of fabricating a thin film transistor array panel of the present invention.
  • FIG. 6 is a flow chart of a method of fabricating a thin film transistor array panel of the present invention.
  • an embodiment means an instance, an example, or an illustration.
  • the article “a”, as used in this specification and the appended claims, can be interpreted generally as “one or more than one” unless specified otherwise or a singular form can be clearly determined from a context.
  • a thin film transistor array panel of the present invention can be applied in a display panel, wherein the display panel can be a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode (OLED), and so on.
  • TFT-LCD thin film transistor liquid crystal display
  • OLED organic light emitting diode
  • a thin film transistor array panel of the present invention can be applied in an array panel of the thin film transistor liquid crystal display.
  • a second electrode portion 504 of an electrode layer of the thin film transistor array panel can be a strip-shape electrode, and the thin film transistor array panel is used in the thin film transistor liquid crystal display panel which is constructed by a liquid crystal layer and a color filter array panel.
  • a thin film transistor array panel of the present invention can be also used in an array panel of the organic light emitting diode.
  • a second electrode portion 504 of an electrode layer of the thin film transistor array panel can be a cathode layer, and the thin film transistor array panel is used in the organic light emitting diode which is constructed by an organic emitting material layer and a cathode layer.
  • a thin film transistor array panel of the present invention includes a substrate 101 , a scanning line, a thin film transistor, an insulating layer 201 , an etch stop layer 401 , a data line, and an electrode layer.
  • the scan line and the data line are both connected with the thin film transistor, and the thin film transistor is connected with the electrode layer.
  • the thin film transistor includes a gate electrode 102 , a semiconductor layer 301 , a source electrode 501 , and a drain electrode 502 .
  • the insulating layer 201 is disposed on the gate electrode 102 and the substrate 101 .
  • the etch stop layer 401 is disposed on the semiconductor layer 301 and the insulating layer 201 .
  • the electrode layer comprises a first electrode portion 503 and a second electrode portion 504 .
  • the first electrode portion 503 is disposed on the source electrode 501 and configured to cover and protect the source electrode 501 , wherein the first electrode portion 503 contacts with the source electrode 501 .
  • the second electrode portion 504 is disposed on the drain electrode 502 and configured to cover and protect the drain electrode 502 , wherein the second electrode portion 504 contacts with the drain electrode 502 .
  • the semiconductor layer 301 is disposed on the insulating layer 201 .
  • the etch stop layer 401 has a first through hole 401 and a second through hole 405 , and the source electrode 501 and the drain electrode 502 are connected with the semiconductor layer 301 through the first through hole 404 and the second through hole 405 respectively.
  • the gate electrode 102 and the scan line are formed by disposing a first metal layer on the substrate 101 and performing a first mask process on the first metal layer. Specifically, the gate electrode 102 and the scan line are both formed by performing a first mask process on the first metal layer and etching the first metal layer.
  • the semiconductor layer 301 is formed by disposing a semiconductor material on the insulating layer 201 and performing a second mask process on the semiconductor material. Specifically, the semiconductor layer 301 is formed by performing a second mask process to the semiconductor material and etching the semiconductor material.
  • the first through hole 404 and the second through hole 405 are formed by disposing an etch stop material on the insulating layer 201 and the semiconductor layer 301 and performing a third mask process on the etch stop material.
  • Receiving cavities ( 402 , 403 ) are formed in the etch stop layer 401 , wherein the receiving cavities ( 402 , 403 ) are configured to receive at least one part of the source electrode 501 , at least one part of the drain electrode 502 and at least one part of the electrode layer.
  • the receiving cavities ( 402 , 403 ) are formed by performing the third mask process on the etch stop material.
  • the first through hole 404 , the second through hole 405 , and the receiving cavities ( 402 , 403 ) are all formed by the same mask process (the third mask process). Specifically, the first through hole 404 , the second through hole 405 , and the receiving cavities ( 402 , 403 ) are formed by performing the third mask process to the etch stop material and etching the etch stop material.
  • the source electrode 501 , the drain electrode 502 , the data line, and the electrode layer are formed by disposing a second metal layer on the etch stop layer 401 , in the first through hole 404 and in the second through hole 405 , respectively, then disposing a third metal layer on the second metal layer and performing a fourth mask process on the second metal layer and the third metal layer, wherein the source electrode 501 , the drain electrode 502 , and the data line are all corresponding to the second metal layer, and the first electrode portion 503 and the second electrode portion 504 of the electrode layer are both corresponding to the third metal layer.
  • the second metal layer and the third metal layer can be etched at the same time by a copper etching solution of a hydrogen peroxide system.
  • a channel between the source electrode 501 and the drain electrode 502 is configured to isolate the source electrode 501 from the drain electrode 502 and isolate the first electrode portion 503 from the second electrode portion 504 .
  • the channel is configured to isolate a first entirety constructed by the source electrode 501 and the first electrode portion 503 from a second entirety constructed by the drain electrode 502 and the second electrode portion 504 .
  • the channel is formed by performing the fourth mask process on the second metal layer and the third metal layer, and etching the second metal layer and the third metal layer.
  • a protective layer/a passivation layer can be saved in the thin film transistor array panel, and a mask process required for fabricating the protective layer/the passivation layer is simultaneously saved. Furthermore, since the electrode layer, the source electrode, and the drain electrode are all formed in the same mask process, two mask processes can be combined into a single mask process. Namely, a mask process is saved. Namely, the above technique solution is beneficial to save (reduce) the mask processes required for fabricating the thin film transistor array panel from six to four.
  • the semiconductor layer 301 comprises indium gallium zinc oxide.
  • the semiconductor material consists of the indium gallium zinc oxide.
  • the semiconductor layer 301 can further comprise amorphous silicon, low-temperature polysilicon, and so on.
  • the etch stop layer 401 is configured to protect the semiconductor layer 301 from water vapor or oxygen gas affecting an electrical stability of the semiconductor layer 301 (the indium gallium zinc oxide).
  • FIGS. 1-5 are schematic diagrams of a method of fabricating a thin film transistor array panel of the present invention.
  • FIG. 6 is a flow chart of a method of fabricating a thin film transistor array panel of the present invention.
  • a method of fabricating a thin film transistor array panel comprises the following steps of:
  • the second metal layer is disposed on the etch stop layer, in the first through hole 404 and in the second through hole 405 , then a third metal layer is disposed on the second metal layer, a fourth mask process is performed to the second metal layer and the third metal layer, so as to form the source electrode 501 , the drain electrode 502 , the data line, and the electrode layer, wherein the second metal layer and the third metal layer are etched at the same time by a copper etching solution of a hydrogen peroxide system after the fourth mask process is performed.
  • receiving cavities ( 402 , 403 ) are formed in the etch stop layer 401 , wherein the receiving cavities ( 402 , 403 ) are configured to receive at least one part of the source electrode 501 , at least one part of the drain electrode 502 and at least one part of the electrode layer.
  • the step (D) comprises:
  • the etch stop material on the insulating layer 201 and the semiconductor layer 301 , and performing the third mask process to the etch stop material for forming the first through hole 404 , the second through hole 405 , and the receiving cavities ( 402 , 403 ).
  • a protective layer/a passivation layer can be saved in the thin film transistor array panel, and a mask process required for fabricating the protective layer/the passivation layer is simultaneously saved. Furthermore, since the electrode layer, the source electrode, and the drain electrode are all formed in the same mask process, two mask processes can be combined into a single mask process. Namely, a mask process is saved. Namely, the above technique solution is beneficial to save (reduce) the mask processes required for fabricating the thin film transistor array panel from six to four.
  • the semiconductor layer 301 comprises indium gallium zinc oxide.
  • the semiconductor material consists of the indium gallium zinc oxide.
  • the semiconductor layer 301 can further comprise amorphous silicon, low-temperature polysilicon, and so on.
  • the etch stop layer 401 is configured to protect the semiconductor layer 301 from water vapor or oxygen gas affecting an electrical stability of the semiconductor layer 301 (the indium gallium zinc oxide).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
US15/123,147 2016-04-13 2016-05-10 Thin film transistor array panel and method of fabricating the same Active 2036-09-01 US10074817B2 (en)

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CN201610226945.4 2016-04-13
CN201610226945 2016-04-13
CN201610226945.4A CN105742297B (zh) 2016-04-13 2016-04-13 薄膜晶体管阵列面板及其制作方法
PCT/CN2016/081564 WO2017177493A1 (zh) 2016-04-13 2016-05-10 薄膜晶体管阵列面板及其制作方法

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CN108010917A (zh) * 2017-11-02 2018-05-08 中华映管股份有限公司 有源器件阵列基板及其制作方法
CN112331679B (zh) * 2020-11-05 2022-08-19 湖北长江新型显示产业创新中心有限公司 显示装置
US20250015091A1 (en) * 2022-06-30 2025-01-09 Fuzhou Boe Optoelectronics Technology Co., Ltd. Array substrate, method for manufacturing same, and display panel

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