WO2017161645A1 - 薄膜晶体管及其制作方法、以及显示装置 - Google Patents

薄膜晶体管及其制作方法、以及显示装置 Download PDF

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WO2017161645A1
WO2017161645A1 PCT/CN2016/081415 CN2016081415W WO2017161645A1 WO 2017161645 A1 WO2017161645 A1 WO 2017161645A1 CN 2016081415 W CN2016081415 W CN 2016081415W WO 2017161645 A1 WO2017161645 A1 WO 2017161645A1
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layer
gate
gate insulating
insulating layer
metal layer
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PCT/CN2016/081415
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English (en)
French (fr)
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田慧
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京东方科技集团股份有限公司
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Priority to US15/533,336 priority Critical patent/US10205026B2/en
Publication of WO2017161645A1 publication Critical patent/WO2017161645A1/zh

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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Definitions

  • the present disclosure relates to the field of display and semiconductor device technologies, and in particular, to a thin film transistor, a method of fabricating the same, and a display device.
  • the mobility of carriers in the channel region of the active layer affects the electrical conductivity and operating frequency of the device, so the increase in carrier mobility is beneficial to the improvement of device performance.
  • the methods for utilizing stress-increasing carriers in the prior art mainly include two types.
  • the carrier heterojunction structure is disposed under the active layer or a heterojunction source/drain structure is disposed on both sides of the channel region in the active layer to introduce stress to improve carrier mobility.
  • the substrate heterojunction structure or the heterojunction source/drain structure is a semiconductor structure, which causes introduction of impurity defects and lattice defects into the channel region.
  • the manufacturing process of this method is complicated and limits the size reduction.
  • a high-stress film is overlaid on the device, and the underlying device is deformed by the deformation of the film itself, thereby generating stress in the active layer to change the carrier mobility characteristics of the device.
  • the manufacturing process in this manner is also complicated and limits the size reduction.
  • An object of the present disclosure is to provide a thin film transistor and a method of fabricating the same, and a display device for improving carrier mobility of a channel region in a thin film transistor and simplifying a fabrication process.
  • the present disclosure provides a thin film transistor including: a substrate substrate, and a source, a drain, a gate, a gate insulating layer, and an active layer on the substrate; wherein the gate An insulating layer is disposed between the gate and the active layer; the source and the drain are respectively connected to the active layer; and the gate is a composite metal layer; the composite metal layer includes At least one first metal layer having dopant ions adjacent to the gate insulating layer, and at least one second metal layer remote from the gate insulating layer.
  • the first metal layer having dopant ions is configured to introduce stress to the active layer.
  • the doping ions in the first metal layer having dopant ions are nitrogen ions.
  • the dose of nitrogen ions ranges from 1.0 e 12 to 1.0 e 13 /cm 2 .
  • the material of the gate insulating layer comprises at least silicon oxide and silicon nitride.
  • the materials of the first metal layer and the second metal layer include at least one of molybdenum, titanium, and aluminum.
  • the composite metal layer comprises a layer of the first metal layer having doping ions and two second metal layers; the material of the first metal layer is molybdenum or titanium, adjacent to the first metal The material of the second metal layer of the layer is aluminum, and the material of the second metal layer remote from the first metal layer is molybdenum or titanium.
  • a stacking order of the gate, the active layer, and the gate insulating layer on the substrate is sequentially the active layer, the gate insulating layer, and the gate.
  • the thin film transistor further includes an interlayer dielectric layer; wherein the interlayer dielectric layer covers the gate electrode and the gate insulating layer; the source penetrates the interlayer dielectric layer and the gate insulating layer a layer is connected to the active layer; and the drain is connected to the active layer through the interlayer dielectric layer and the gate insulating layer.
  • a stacking order of the gate, the active layer, and the gate insulating layer on the substrate is sequentially the gate and the gate insulating layer.
  • the present disclosure provides a display device including the thin film transistor described above.
  • the present disclosure provides a method of fabricating a thin film transistor, including: forming a gate, a gate insulating layer, an active layer, a source and a drain on a base substrate; wherein the gate insulating a layer is formed between the gate and the active layer; the source and the drain are formed to be respectively connected to the active layer; wherein the step of forming a gate comprises: forming a composite metal layer Forming a gate electrode; the composite metal layer comprising at least one first metal layer having dopant ions adjacent to the gate insulating layer, and at least one second metal layer remote from the gate insulating layer.
  • the first metal layer having dopant ions is configured to introduce stress to the active layer through the gate insulating layer.
  • the composite metal layer is formed by an ion implantation process and a patterning process to form a gate electrode.
  • the step of forming a gate, a gate insulating layer, an active layer, a source and a drain on the base substrate comprising: forming an active layer on the base substrate; forming the active layer and a gate insulating layer on the base substrate; using an ion implantation process and a patterning process, Forming a composite metal layer on the gate insulating layer and above the active layer to form a gate; using the composite metal layer as a mask, using the gate insulating layer to penetrate the gate insulating layer Ion implantation is performed in the active layer; and a source and a drain connected to the active layer are respectively formed.
  • the step of forming a gate electrode on the gate insulating layer and over the active layer to form a gate electrode by using an ion implantation process and a patterning process includes: insulating the gate Forming at least one first metal film on the layer and above the active layer; performing nitrogen ion implantation on the first metal film; forming at least one layer on the first metal film into which nitrogen ions have been implanted a metal thin film; and etching the first metal thin film and the second metal thin film by a patterning process to form a gate electrode.
  • the energy value of the nitrogen ions ranges from 20 to 40 keV.
  • the manufacturing method further includes: forming an interlayer dielectric layer covering the gate and the gate insulating layer; and the steps of respectively forming a source and a drain connected to the active layer, including Forming a first contact hole and a second contact hole penetrating the interlayer dielectric layer and the gate insulating layer by a patterning process to expose the active layer; and respectively toward the first contact hole and the second contact hole A source metal layer and a drain metal layer are deposited to form a source and a drain.
  • the present disclosure provides a thin film transistor and a method of fabricating the same, and a display device including the above thin film transistor.
  • the gate is a structure of a composite metal layer.
  • the first metal layer in the composite metal layer adjacent to the gate insulating layer has dopant ions. This makes it possible to introduce stress into the active layer, change the energy band structure of the channel region in the active layer, and change the effective mass of the carriers and the anisotropic scattering, etc., thereby improving the mobility of the carriers.
  • the second metal layer in the composite metal layer remote from the gate insulating layer is not doped with ions, so that the effective resistance of the entire gate can be ensured.
  • the improvement of the gate electrode in the thin film transistor achieves the purpose of enhancing the carrier mobility without adding an additional structure, which makes the process in the production process simpler.
  • FIG. 1 is a schematic structural view of a thin film transistor provided by the present disclosure
  • FIG. 2 is a schematic structural view of another thin film transistor provided by the present disclosure.
  • FIG. 3 is a schematic structural diagram of another thin film transistor provided by the present disclosure.
  • FIG. 4 is a schematic structural diagram of another thin film transistor provided by the present disclosure.
  • FIG. 5 is a schematic structural diagram of another thin film transistor according to the present disclosure.
  • FIG. 6 is a schematic structural diagram of another thin film transistor according to the present disclosure.
  • FIG. 7 is a flow chart of a method of fabricating a thin film transistor provided by the present disclosure.
  • FIGS. 8a-8c are schematic structural diagrams of a thin film transistor provided in the manufacturing process of the present disclosure.
  • 9a-9d are schematic structural views of a gate of a thin film transistor provided in the manufacturing process of the present disclosure.
  • FIG. 10 is a schematic structural view of a source and a drain of a thin film transistor provided in the present disclosure during fabrication;
  • FIG. 11 is a schematic structural view of a source and a drain of another thin film transistor according to the present disclosure during fabrication.
  • the structure of the active layer in the thin film transistor will be briefly described.
  • the semiconductor structure When the carriers are electrons, the semiconductor structure is referred to as N-type doping.
  • the semiconductor structure When the carriers are holes, the semiconductor structure is referred to as P-type doping.
  • the two electrodes that form an ohmic contact with the two semiconductor structures in the active layer are the source and drain. Accordingly, the two semiconductor structures are referred to as source and drain regions.
  • the source region and the drain region are referred to as a channel region.
  • a carrier current flows in the channel region by applying an appropriate bias voltage between the source and the drain, and applying a gate voltage to the gate, thereby forming a channel current.
  • the thin film transistor includes: a substrate substrate, and a source, a drain, a gate, a gate insulating layer, and an active layer on the substrate; wherein the gate insulating layer is disposed between the gate and the active layer; The pole and the drain are respectively connected to the active layer; and the gate is a composite metal layer; the composite metal layer includes at least one first metal layer having doping ions close to the gate insulating layer, and at least one layer away from the gate insulating layer Two metal layers. Specifically, the first metal layer having dopant ions is configured to introduce stress to the active layer.
  • ions doped in the first metal layer can change their atomic arrangement such that the stress of the first metal layer changes.
  • the first metal layer will be in contact with the underside
  • the gate insulating layer and the active layer generate contact or diffusion compressive stress or tensile stress.
  • the result will be that the energy band of the active layer is bent and its band structure is changed, including the band structure change of the channel region in the active layer.
  • the gate is a structure of a composite metal layer.
  • the first metal layer in the composite metal layer adjacent to the gate insulating layer has dopant ions. This makes it possible to introduce stress into the active layer, change the energy band structure of the channel region in the active layer, and change the effective mass of the carriers and the anisotropic scattering, etc., thereby improving the mobility of the carriers.
  • the second metal layer in the composite metal layer remote from the gate insulating layer is not doped with ions, so that the effective resistance of the entire gate can be ensured.
  • the improvement of the gate electrode in the thin film transistor achieves the purpose of enhancing the carrier mobility without adding an additional structure, which makes the process in the production process simpler.
  • the stacking order of the gate electrode, the active layer, and the gate insulating layer on the substrate substrate has the following two cases: First, the stacking order of the gate electrode, the active layer, and the gate insulating layer on the substrate substrate may be The order of the gate layer, the active layer and the gate insulating layer on the substrate substrate may be a gate, a gate insulating layer and an active layer in this order.
  • the thin film transistor provided by the present disclosure will be described in more detail below by taking the first lamination sequence as an example.
  • the present disclosure provides a thin film transistor including: a substrate 1 , and a source 2 , a drain 3 , a gate 4 , a gate insulating layer 5 , and an active layer 6 on the substrate 1 .
  • the gate insulating layer 5 is disposed between the gate electrode 4 and the active layer 6 (shown by the dashed box); the source 2 and the drain 3 are respectively connected to the active layer 6; and the gate 4 is a composite metal layer;
  • the composite metal layer includes at least one first metal layer 41 having dopant ions adjacent to the gate insulating layer, and at least one second metal layer 42 remote from the gate insulating layer 5.
  • the first metal layer 41 having dopant ions is configured to introduce stress to the active layer 6.
  • the source and drain regions are embodied in different filling manners, and a channel region is formed between the source and drain regions of the active layer 6.
  • the active layer 6 is on the base substrate 1, the gate insulating layer 5 covers the active layer 6 and the base substrate 1, and the gate 4 is located on the active layer 6.
  • the first metal layer 41 having dopant ions can be used to inject stress into the active layer to enhance carrier mobility, and can effectively block other impurity ions from being insulated from the gate through the gate 4.
  • Layer 5 diffuses. In this way, the leakage current of the device can be reduced and the drift of the threshold voltage can be improved. Thereby the electrical characteristics of the device are improved overall.
  • the first metal layer there may be various types of dopant ions in the first metal layer.
  • the conditions to be satisfied include that the bond energy of the doping ions is stable and does not affect the insulating properties of the gate insulating layer.
  • the doping ions in the first metal layer having doping ions are nitrogen ions.
  • the magnitude of the stress introduced into the active layer by the first metal layer having dopant ions can be controlled by controlling the doping dose.
  • the more doping the dose the greater the stress introduced.
  • the effect on the effective resistance of the gate should also be considered. Therefore, the dose of the doping ions in the first metal layer should be set according to actual needs to ensure that the effective resistance of the gate is not affected, and the purpose of stress introduction can be achieved.
  • the dose of nitrogen ions ranges from 1.0e 12 to 1.0e 13 /cm 2 .
  • the above dose range of nitrogen ions means that 1.0e 12 - 1.0e 13 nitrogen ions are doped per square centimeter in the first metal layer.
  • the overall thickness of the at least one first metal layer having dopant ions does not exceed 40% of the total thickness of the gate.
  • the material of the gate insulating layer comprises at least silicon oxide and silicon nitride.
  • the nitrogen ions will not affect the performance of the gate insulating layer made of silicon oxide and/or silicon nitride.
  • the materials of the first metal layer and the second metal layer include at least one of molybdenum, titanium, and aluminum.
  • the composite metal layer includes a first metal layer 41 having doping ions and two second metal layers 42 (different filling pairs in the figure) The second metal layer of the layer is distinguished); wherein the material of the first metal layer 41 is molybdenum or titanium, the material of the second metal layer 42 adjacent to the first metal layer 41 is aluminum, and the first layer away from the first metal layer 41 The material of the second metal layer 42 is molybdenum or titanium.
  • the ratio of the thickness of the first metal layer 41 to the two second metal layers 42 may be, but not limited to, 2:1:2.
  • the thin film transistor further includes an interlayer dielectric layer 7; wherein the interlayer dielectric layer 7 covers the gate electrode 4 and the gate insulating layer 5; the source electrode 2 penetrates the interlayer dielectric layer 7 and The gate insulating layer 5 is connected to the active layer 6; and the drain 3 penetrates the interlayer dielectric layer 7 The gate insulating layer 5 is connected to the active layer 6.
  • the interlayer dielectric layer 7 in this embodiment can insulate the gate 4 from the source 2 and the drain 3.
  • the material of the interlayer dielectric layer may be, but not limited to, silicon oxide and silicon nitride.
  • the thin film transistor further includes a buffer layer 8 between the active layer 6 and the base substrate 1.
  • the gate insulating layer 5 covers the active layer 6 and the buffer layer 8.
  • the buffer layer 8 in the present embodiment can block diffusion of impurity ions in the substrate to the active layer 6.
  • the interface characteristics of the buffer layer 8 and the active layer 6 are good, defects in the active layer 6 are further reduced, so that carrier mobility can be improved.
  • the material of the buffer layer 8 may be, but not limited to, silicon oxide and silicon nitride.
  • the composite metal layer includes a first metal layer 41 having doped ions and two second metal layers 42.
  • the gate 4 is on the base substrate 1
  • the gate insulating layer 5 covers the gate.
  • the base substrate 1, and the active layer 6 is on the gate insulating layer 5.
  • the thin film transistor as shown in FIG. 6 further includes a buffer layer between the gate and the substrate.
  • the thin film transistor as shown in FIG. 6 further includes an interlayer dielectric layer, the interlayer dielectric layer being located at the uppermost layer, exposing the source and the drain.
  • the specific structure of the gate may refer to the related embodiments of the present disclosure, and details are not described herein again.
  • the present disclosure also provides a display device including the thin film transistor described in any of the above embodiments.
  • the present disclosure further provides a method of fabricating a thin film transistor, including: forming a gate, a gate insulating layer, an active layer, a source and a drain on a base substrate; wherein the gate insulating layer is formed Between the gate and the active layer; the source and the drain are formed to be respectively connected to the active layer; wherein the step of forming the gate comprises: forming a composite metal layer to form a gate; wherein the composite metal layer comprises at least a first metal layer having dopant ions adjacent to the gate insulating layer, and at least one second metal layer away from the gate insulating layer. Specifically, the first metal layer having dopant ions is configured to introduce stress to the active layer.
  • a composite metal layer is formed using an ion implantation process and a patterning process to form a gate electrode.
  • the gate is a structure of a composite metal layer.
  • the first metal layer in the composite metal layer adjacent to the gate insulating layer has dopant ions. This makes it possible to introduce stress into the active layer, change the energy band structure of the channel region in the active layer, and change the effective mass of the carriers and the anisotropic scattering, etc., thereby improving the mobility of the carriers.
  • the second metal layer in the composite metal layer remote from the gate insulating layer is not doped with ions, so that the effective resistance of the entire gate can be ensured.
  • the improvement of the gate electrode in the thin film transistor achieves the purpose of enhancing the carrier mobility without adding an additional structure, which makes the process in the production process simpler.
  • a composite metal layer is formed using an ion implantation process and a patterning process to form a gate electrode. Further specifically, a first metal thin film is formed; ion implantation is performed on the first metal thin film; at least one second metal thin film is formed on the first metal thin film on which the ions have been implanted; and the first metal thin film and the first through the patterning process The two metal films are etched to form a gate.
  • the active layer, the gate insulating layer and the gate are sequentially arranged on the substrate, and the thin film transistor shown in FIG. 1 is taken as an example below to explain the film in detail.
  • the method of making transistors is taken as an example below to explain the film in detail.
  • the steps of forming a gate, a gate insulating layer, an active layer, a source and a drain on the base substrate include at least the following steps.
  • Step 710 forms an active layer 6 on a substrate.
  • amorphous silicon is deposited on the base substrate, crystallized and patterned to form an active layer.
  • the crystallization method of polycrystalline silicon includes a method such as excimer laser annealing.
  • Step 720 as shown in FIG. 8a, a gate insulating layer 5 on the active layer 6 and the substrate 1 is formed.
  • the gate insulating layer is a silicon oxide and silicon nitride composite film.
  • Step 730 as shown in FIG. 8b, a composite metal layer on the gate insulating layer 5 and over the active layer 6 is formed by an ion implantation process and a patterning process to form the gate electrode 4.
  • Step 740 using the composite metal layer as a mask, ion implantation into the active layer 6 through the gate insulating layer 5 by an ion implantation process.
  • This step is mainly used to form source and drain regions in the active layer.
  • the implanted ions may be boron ions or phosphorus ions.
  • Step 750 forming a source and a drain connected to the active layer, respectively.
  • an ion implantation process and a patterning process are used to form a step of forming a gate electrode 4 on the gate insulating layer and over the active layer 6 to form the gate electrode 4, comprising at least the following sub-steps: a first sub-step, as shown in FIG. 9a, on the gate insulating layer 5 Forming at least one first metal film 41' over the active layer 6; a second sub-step, as shown in FIG. 9b, ion implantation of the first metal film 41'; exemplarily, the implant may be nitrogen ions . a third sub-step, as shown in FIG.
  • the energy value of the nitrogen ions ranges from 20 to 40 keV.
  • the steps of respectively forming the source 2 and the drain 3 connected to the active layer 6 include the following sub-steps: a first sub-step, as shown in FIG. 10, forming a through layer by a patterning process a first contact hole 9 and a second contact hole 10 of the gate insulating layer to expose the active layer 6; and a second sub-step of depositing a source metal layer into the first contact hole 9 and the second contact hole 10, respectively A drain metal layer is formed to form source 2 and drain 3.
  • the manufacturing method further includes forming an interlayer dielectric layer 7 covering the gate electrode 4 and the gate insulating layer 5; and forming source 2 and drain 3 connected to the active layer 6, respectively.
  • the step includes the following sub-steps: a first sub-step 1, as shown in FIG. 11, forming a first contact hole 9 and a second contact hole 10 penetrating the interlayer dielectric layer 7 and the gate insulating layer 5 by a patterning process to expose The active layer 6; and a second sub-step, respectively depositing a source metal layer and a drain metal layer into the first contact hole 9 and the second contact hole 10 to form the source 2 and the drain 3.
  • the interlayer dielectric layer 7 is a composite film of silicon oxide and silicon nitride.
  • the above manufacturing method further comprises: forming a buffer layer 8 on the substrate 1 .
  • the buffer layer 8 is a composite film of silicon oxide and silicon nitride.
  • the buffer layer, the amorphous silicon layer and the gate insulating layer may be formed by deposition by a Plasma Enhanced Chemical Vapor Deposit (PECVD) method.
  • PECVD Plasma Enhanced Chemical Vapor Deposit
  • the gate electrode, the gate insulating layer and the active layer are sequentially arranged on the base substrate, and the specific fabrication steps of the gate electrode in the manufacturing method of the thin film transistor may be Referring to the related embodiments of the present disclosure above, there is no longer a A narrative. Further, specific fabrication steps of the active layer, the gate insulating layer, the source, the drain, the buffer layer, and the like can be referred to the related art. Moreover, the specific fabrication sequence of the structure of the gate, the active layer, the gate insulating layer, the source, the drain, the buffer layer, and the like can also refer to the prior art, and details are not described herein again.
  • Embodiments of the present disclosure provide a thin film transistor and a method of fabricating the same, and a display device including the above thin film transistor.
  • the gate is a structure of a composite metal layer.
  • the first metal layer in the composite metal layer adjacent to the gate insulating layer has dopant ions. This makes it possible to introduce stress into the active layer, change the energy band structure of the channel region in the active layer, and change the effective mass of the carriers and the anisotropic scattering, etc., thereby improving the mobility of the carriers.
  • the second metal layer in the composite metal layer remote from the gate insulating layer is not doped with ions, so that the effective resistance of the entire gate can be ensured.
  • the improvement of the gate electrode in the thin film transistor achieves the purpose of enhancing the carrier mobility without adding an additional structure, which makes the process in the production process simpler.

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Abstract

提供一种薄膜晶体管及其制作方法、以及一种显示装置。在该薄膜晶体管中，栅极（4）为复合金属层的结构。具体地，该复合金属层中靠近栅绝缘层（5）的第一金属层（41）具有掺杂离子。这使得能够对有源层引入应力，改变有源层中沟道区的能带结构，并且改变载流子的有效质量和各向异性散射等，从而提高载流子的迁移率。此外，该复合金属层中远离栅绝缘层（5）的第二金属层（42）未掺杂有离子，从而可以保证整个栅极的有效电阻。通过对薄膜晶体管中的栅极（4）的改进达到了提升载流子迁移率的目的，而同时无需增加额外的结构，这使得生产过程中的工艺更为简单。

Description

薄膜晶体管及其制作方法、以及显示装置 技术领域
本公开涉及显示及半导体器件技术领域，尤其涉及一种薄膜晶体管及其制作方法、以及显示装置。
背景技术
对于薄膜晶体管来说，有源层中沟道区的载流子的迁移率影响了器件的电导率和工作频率，所以载流子的迁移率的提升有利于器件性能的提升。现有技术中利用应力提高载流子的方法主要包括两种。第一种，通过在有源层下方设置衬底异质结结构或在有源层中沟道区的两侧设置异质结源漏结构，以引入应力来提高载流子的迁移率。但是，衬底异质结结构或异质结源漏结构均为半导体结构，这会导致向沟道区引入杂质缺陷和晶格缺陷。而且，这种方式的制作工艺复杂，并且限制了尺寸的缩小。第二种，在器件上方覆盖高应力薄膜，通过薄膜自身的形变带动下方的器件发生形变，从而在有源层中产生应力，以改变器件的载流子迁移特征。同样地，这种方式的制作工艺也较复杂，并且限制了尺寸的缩小。
发明内容
本公开的目的是提供一种薄膜晶体管及其制作方法、以及一种显示装置，用于提升薄膜晶体管中沟道区的载流子的迁移率，并且简化制作工艺。
在一方面中，本公开提供一种薄膜晶体管，包括：衬底基板，和位于所述衬底基板上的源极、漏极、栅极、栅绝缘层和有源层；其中，所述栅绝缘层设置在所述栅极与所述有源层之间；所述源极和所述漏极分别与所述有源层连接；并且所述栅极为复合金属层；所述复合金属层包括至少一层靠近所述栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离所述栅绝缘层的第二金属层。
可选地，所述具有掺杂离子的第一金属层配置成对所述有源层引入应力。
可选地，所述具有掺杂离子的第一金属层中的掺杂离子为氮离子。
可选地，所述氮离子的剂量范围为1.0e12～1.0e13/cm2。
可选地，所述栅绝缘层的材料至少包括氧化硅和氮化硅。
可选地，所述第一金属层和第二金属层的材料至少包括钼、钛和铝中的一种。
可选地，所述复合金属层包括一层所述具有掺杂离子的第一金属层和两层第二金属层；所述第一金属层的材料为钼或钛，靠近所述第一金属层的第二金属层的材料为铝，并且远离所述第一金属层的第二金属层的材料为钼或钛。
可选地，所述栅极、所述有源层和所述栅绝缘层在所述衬底基板上的层叠顺序依次为所述有源层、所述栅绝缘层和所述栅极。
可选地，上述薄膜晶体管还包括层间介质层；其中，所述层间介质层覆盖所述栅极和所述栅绝缘层；所述源极贯穿所述层间介质层和所述栅绝缘层与所述有源层连接；并且所述漏极贯穿所述层间介质层和所述栅绝缘层与所述有源层连接。
可选地，所述栅极、所述有源层和所述栅绝缘层在所述衬底基板上的层叠顺序依次为所述栅极、所述栅绝缘层。
在另一方面中，本公开提供一种显示装置，包括以上所述薄膜晶体管。
在又一方面中，本公开提供一种薄膜晶体管的制作方法，包括：在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤；其中，所述栅绝缘层形成在所述栅极与所述有源层之间；所述源极和所述漏极形成为分别与所述有源层连接；其中，形成栅极的步骤，包括：形成复合金属层，以形成栅极；所述复合金属层包括至少一层靠近所述栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离所述栅绝缘层的第二金属层。
可选地，所述具有掺杂离子的第一金属层配置成通过所述栅绝缘层对所述有源层引入应力。
可选地，在上述制作方法中，利用离子注入工艺和构图工艺形成复合金属层，以形成栅极。
可选地，在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤，包括：形成位于衬底基板上的有源层；形成位于所述有源层和所述衬底基板上的栅绝缘层；利用离子注入工艺和构图工艺，形 成位于所述栅绝缘层上且在所述有源层上方的复合金属层，以形成栅极；以所述复合金属层为掩膜，利用离子注入工艺透过所述栅绝缘层向所述有源层中进行离子注入；以及分别形成与所述有源层连接的源极和漏极。
可选地，所述利用离子注入工艺和构图工艺，形成位于所述栅绝缘层上且在所述有源层上方的复合金属层，以形成栅极这一步骤，包括：在所述栅绝缘层上且在所述有源层上方形成至少一层第一金属薄膜；对所述第一金属薄膜进行氮离子注入；在已注入氮离子的所述第一金属薄膜上形成至少一层第二金属薄膜；以及通过构图工艺对所述第一金属薄膜和第二金属薄膜进行刻蚀，以形成栅极。
可选地，对所述第一金属薄膜进行氮离子注入时，所述氮离子的能量值的范围为20～40kev。
可选地，上述制作方法还包括：形成覆盖所述栅极和所述栅绝缘层的层间介质层；并且所述分别形成与所述有源层连接的源极和漏极的步骤，包括：通过构图工艺形成贯穿所述层间介质层和栅绝缘层的第一接触孔和第二接触孔，以暴露出所述有源层；以及分别向所述第一接触孔和第二接触孔中沉积源极金属层和漏极金属层，以形成源极和漏极。
本公开提供了一种薄膜晶体管及其制作方法、以及一种包括上述薄膜晶体管的显示装置。在上述薄膜晶体管中，栅极为复合金属层的结构。具体地，该复合金属层中靠近栅绝缘层的第一金属层具有掺杂离子。这使得能够对有源层引入应力，改变有源层中沟道区的能带结构，并且改变载流子的有效质量和各向异性散射等，从而提高载流子的迁移率。此外，该复合金属层中远离栅绝缘层的第二金属层未掺杂有离子，从而可以保证整个栅极的有效电阻。在本公开的实施例中，通过对薄膜晶体管中的栅极的改进达到了提升载流子迁移率的目的，而同时无需增加额外的结构，这使得生产过程中的工艺更为简单。
附图说明
图1为本公开提供的薄膜晶体管的结构示意图；
图2为本公开提供的另一薄膜晶体管的结构示意图；
图3为本公开提供的另一薄膜晶体管的结构示意图；
图4为本公开提供的另一薄膜晶体管的结构示意图；
图5为本公开提供的另一薄膜晶体管的结构示意图；
图6为本公开提供的另一薄膜晶体管的结构示意图；
图7为本公开提供的薄膜晶体管的制作方法的流程图；
图8a～图8c为本公开提供的薄膜晶体管在制作过程中的结构示意图；
图9a～图9d为本公开提供的薄膜晶体管的栅极在制作过程中的结构示意图；
图10为本公开提供的薄膜晶体管的源极和漏极在制作过程中的结构示意图；以及
图11为本公开提供的另一薄膜晶体管的源极和漏极在制作过程中的结构示意图。
具体实施方式
为了能够更加清楚的介绍本公开的技术方案，首先对薄膜晶体管中有源层的结构进行简单说明。有源层中有两个通过注入离子而形成的半导体结构，其中注入离子不同，产生的载流子就不同。当载流子为电子时，该半导体结构称为N型掺杂。当载流子为空穴时，该半导体结构称为P型掺杂。与有源层中两个半导体结构形成欧姆接触的两个电极即为源极和漏极。相应地，这两个半导体结构就称为源区和漏区。源区和漏区之间称为沟道区。当薄膜晶体管正常工作时，通过在源极和漏极之间施加适当的偏压，并且向栅极施加栅压，在沟道区内将出现载流子流动，从而形成沟道电流。
在不提高工艺复杂度的前提下，为了提升薄膜晶体管中载流子的迁移率，本公开提供一种薄膜晶体管。该薄膜晶体管包括：衬底基板，和位于衬底基板上的源极、漏极、栅极、栅绝缘层和有源层；其中，栅绝缘层设置在栅极与有源层之间；源极和漏极分别与有源层连接；并且栅极为复合金属层；复合金属层包括至少一层靠近栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离栅绝缘层的第二金属层。具体地，具有掺杂离子的第一金属层配置成对有源层引入应力。
具体地，掺杂在第一金属层中的离子能够改变其原子排布，从而使得第一金属层的应力发生变化。这样，第一金属层将会对下面接触 的栅绝缘层和有源层产生接触式或扩散式压应力或张应力。在这样的情况下，结果将是有源层的能带弯曲，并且其能带结构改变，包括有源层中沟道区的能带结构改变。
在本公开提供的薄膜晶体管中，栅极为复合金属层的结构。具体地，该复合金属层中靠近栅绝缘层的第一金属层具有掺杂离子。这使得能够对有源层引入应力，改变有源层中沟道区的能带结构，并且改变载流子的有效质量和各向异性散射等，从而提高载流子的迁移率。此外，该复合金属层中远离栅绝缘层的第二金属层未掺杂有离子，从而可以保证整个栅极的有效电阻。在本公开的实施例中，通过对薄膜晶体管中的栅极的改进达到了提升载流子迁移率的目的，而同时无需增加额外的结构，这使得生产过程中的工艺更为简单。
具体地，栅极、有源层和栅绝缘层在衬底基板上的层叠顺序有以下两种情况：第一种，栅极、有源层和栅绝缘层在衬底基板上的层叠顺序可以依次为有源层、栅绝缘层和栅极；第二种，栅极、有源层和栅绝缘层在衬底基板上的层叠顺序可以依次为栅极、栅绝缘层和有源层。
下面以第一种层叠顺序为例，对本公开提供的薄膜晶体管进行更加详细的说明。
如图1所示，本公开提供一种薄膜晶体管，包括：衬底基板1，和位于衬底基板1上的源极2，漏极3，栅极4，栅绝缘层5和有源层6；其中，栅绝缘层5设置在栅极4与有源层6(虚线框所示)之间；源极2和漏极3分别与有源层6连接；并且栅极4为复合金属层；复合金属层包括至少一层靠近栅绝缘层的具有掺杂离子的第一金属层41，和至少一层远离栅绝缘层5的第二金属层42。具体地，具有掺杂离子的第一金属层41配置成对有源层6引入应力。
在图4中，以不同的填充方式体现了源区和漏区，并且在有源层6的源区和漏区之间形成沟道区。
具体地，有源层6位于衬底基板1上，栅绝缘层5覆盖有源层6和衬底基板1，并且栅极4位于有源层6上。在该薄膜晶体管中，具有掺杂离子的第一金属层41除了可以用于对有源层引入应力以提升载流子迁移率之外，还能有效阻挡其它杂质离子通过栅极4向栅绝缘层5扩散。这样，能够减小器件的漏电流并且改善阈值电压的漂移问题， 从而使得器件的电学特性得到整体提升。
具体地，第一金属层中的掺杂离子的种类可以有多种。而需要满足的条件包括该掺杂离子的键能稳定，并且不会影响栅绝缘层的绝缘性能。
具体实施时，可选地，具有掺杂离子的第一金属层中的掺杂离子为氮离子。
具体实施时，具有掺杂离子的第一金属层对有源层引入的应力的大小可以通过控制掺杂的剂量进行控制。掺杂的剂量越多，引入的应力就越大。当然，也要考虑对栅极的有效电阻的影响。因此，第一金属层中的掺杂离子的剂量要根据实际需要进行设置，以保证既不影响栅极的有效电阻，又能达到应力引入的目的。
以第一金属层中掺杂氮离子为例，在具体实施例时，可选地，氮离子的剂量范围为1.0e12～1.0e13/cm2。
上述氮离子的剂量范围表示在第一金属层中每平方厘米掺杂1.0e12～1.0e13个氮离子。
为了进一步保证栅极的有效电阻不会受到影响，在具体实施时，上述至少一层具有掺杂离子的第一金属层的整体厚度不超过栅极总厚度的40％。
可选地，栅绝缘层的材料至少包括氧化硅和氮化硅。这样，氮离子将不会影响以氧化硅和/或氮化硅为材料的栅绝缘层的性能。
具体实施时，可选地，第一金属层和第二金属层的材料至少包括钼、钛和铝中的一种。
参照图2，在本公开提供的一种可能的薄膜晶体管中，复合金属层包括一层具有掺杂离子的第一金属层41和两层第二金属层42(图中以不同的填充对两层第二金属层进行区分)；其中第一金属层41的材料为钼或钛，靠近该第一金属层41的第二金属层42的材料为铝，并且远离该第一金属层41的第二金属层42的材料为钼或钛。
具体地，第一金属层41与两层第二金属层42的厚度之比可以但不限于2∶1∶2。
参照图3，在具体实施例时，可选地，薄膜晶体管还包括层间介质层7；其中层间介质层7覆盖栅极4和栅绝缘层5；源极2贯穿层间介质层7和栅绝缘层5与有源层6连接；并且漏极3贯穿层间介质层7 和栅绝缘层5与有源层6连接。
本实施例中的层间介质层7可以对栅极4，与源极2、漏极3起到绝缘作用。
具体地，层间介质层的材料可以但不限于氧化硅和氮化硅。
参照图4，在具体实施时，可选地，薄膜晶体管还包括位于有源层6和衬底基板1之间的缓冲层8。栅绝缘层5覆盖有源层6和缓冲层8。
一方面，本实施例中的缓冲层8可以阻挡衬底基板中的杂质离子向有源层6扩散。另一方面，由于缓冲层8与有源层6的界面特性较好，所以进一步减少了有源层6中的缺陷，从而可以提升载流子迁移率。
具体地，缓冲层8的材料可以但不限于氧化硅和氮化硅。
可选地，如图5所示，复合金属层包括一层具有掺杂离子的第一金属层41和两层第二金属层42。
参照图6，对于第二种层叠顺序，即栅极、栅绝缘层和有源层依次排布在衬底基板上的情况，栅极4位于衬底基板1上，栅绝缘层5覆盖栅极和衬底基板1，并且有源层6位于栅绝缘层5上。
可选地，如图6中所示的薄膜晶体管还包括缓冲层，该缓冲层位于栅极与衬底基板之间。
可选地，如图6中所示的薄膜晶体管还包括层间介质层，该层间介质层位于最上层，露出源极和漏极。
在具体实施时，栅极的具体结构可以参照以上本公开的相关实施例，此处不再一一赘述。
基于同样的构思，本公开还提供一种显示装置，包括以上任意实施例所述的薄膜晶体管。
基于同样的构思，本公开还提供一种薄膜晶体管的制作方法，包括：在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤；其中，栅绝缘层形成在栅极与有源层之间；源极和漏极形成为分别与有源层连接；其中，形成栅极的步骤，包括：形成复合金属层，以形成栅极；其中复合金属层包括至少一层靠近栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离栅绝缘层的第二金属层。具体地，具有掺杂离子的第一金属层配置成对有源层引入应力。另外具体地，利用离子注入工艺和构图工艺形成复合金属层，以形成栅极。
本公开实施例提供的薄膜晶体管中，栅极为复合金属层的结构。具体地，该复合金属层中靠近栅绝缘层的第一金属层具有掺杂离子。这使得能够对有源层引入应力，改变有源层中沟道区的能带结构，并且改变载流子的有效质量和各向异性散射等，从而提高载流子的迁移率。此外，该复合金属层中远离栅绝缘层的第二金属层未掺杂有离子，从而可以保证整个栅极的有效电阻。在本公开的实施例中，通过对薄膜晶体管中的栅极的改进达到了提升载流子迁移率的目的，而同时无需增加额外的结构，这使得生产过程中的工艺更为简单。
具体地，利用离子注入工艺和构图工艺形成复合金属层，以形成栅极。进一步具体地，形成一层第一金属薄膜；对第一金属薄膜进行离子注入；在已注入离子的第一金属薄膜上形成至少一层第二金属薄膜；通过构图工艺对第一金属薄膜和第二金属薄膜进行刻蚀，以形成栅极。
针对上述相关实施例中所描述的第一种层叠顺序，即有源层、栅绝缘层和栅极依次排布衬底基板上，下面以图1所示的薄膜晶体管为例，详细地说明薄膜晶体管的制作方法。
可选地，如图7所示，在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤，至少包括以下步骤。
步骤710，如图8a所示，形成位于衬底基板上的有源层6。
具体地，在衬底基板上沉积非晶硅，晶化并图案化形成有源层。示例性地，多晶硅的结晶方法包括准分子激光退火等方法。
步骤720，如图8a所示，形成位于有源层6和衬底基板1上的栅绝缘层5。
具体地，栅绝缘层为氧化硅和氮化硅复合薄膜。
步骤730，如图8b所示，利用离子注入工艺和构图工艺，形成位于栅绝缘层5上且在有源层6上方的复合金属层，以形成栅极4。
步骤740，如图8c所示，以复合金属层为掩膜，利用离子注入工艺透过栅绝缘层5向有源层6中进行离子注入。
该步骤主要用于形成有源层中的源区和漏区。另外，在该步骤中，所注入的离子可以是硼离子或者磷离子。
步骤750、分别形成与有源层连接的源极和漏极。
在具体实施例时，可选地，利用离子注入工艺和构图工艺，形成 位于栅绝缘层上且在有源层6上方的复合金属层，以形成栅极4这一步骤，至少包括以下子步骤：第一子步骤、如图9a所示，在栅绝缘层5上且在有源层6上方形成至少一层第一金属薄膜41’；第二子步骤、如图9b所示，对第一金属薄膜41’进行离子注入；示例性地，所注入的可以是氮离子。第三子步骤、如图9c所示，在已注入离子的第一金属薄膜41’上形成至少一层第二金属薄膜42’；在该步骤中，可以形成两层第二金属薄膜(如图9d所示)；第四子步骤、通过构图工艺对第一金属薄膜41’和第二金属薄膜42’进行刻蚀，以形成栅极4。
可选地，根据具体实施例，对第一金属薄膜41’进行氮离子注入时，氮离子的能量值的范围为20～40kev。
在具体实施时，可选地，分别形成与有源层6连接的源极2和漏极3的步骤，包括以下子步骤：第一子步骤，如图10所示，通过构图工艺形成贯穿层栅绝缘层的第一接触孔9和第二接触孔10，以暴露出有源层6；以及第二子步骤，分别向第一接触孔9和第二接触孔10中沉积源极金属层和漏极金属层，以形成源极2和漏极3。
在具体实施例时，可选地，上述制作方法还包括形成覆盖栅极4和栅绝缘层5的层间介质层7；并且分别形成与有源层6连接的源极2和漏极3的步骤，包括以下子步骤：第一子步骤一，如图11所示，通过构图工艺形成贯穿层间介质层7和栅绝缘层5的第一接触孔9和第二接触孔10，以暴露出有源层6；以及第二子步骤，分别向第一接触孔9和第二接触孔10中沉积源极金属层和漏极金属层，以形成源极2和漏极3。
具体地，层间介质层7为氧化硅和氮化硅的复合薄膜。
在具体实施例时，可选地，在形成位于衬底基板1上的有源层6之前，上述制作方法还包括：形成位于衬底基板1上的缓冲层8。具体地，缓冲层8为氧化硅和氮化硅的复合薄膜。
在具体实施时，缓冲层、非晶硅层和栅绝缘层均可以采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Depositon，PECVD)方式沉积形成。
针对上述相关实施例中所描述的第二种层叠顺序，即栅极、栅绝缘层和有源层依次排布在衬底基板上，薄膜晶体管的制作方法中关于栅极的具体制作步骤，可以参照以上本公开相关实施例，此处不再一 一赘述。另外，关于有源层、栅绝缘层、源极、漏极、缓冲层等的具体制作步骤可以参照现有技术。而且，关于栅极、有源层、栅绝缘层、源极、漏极、缓冲层等结构的具体制作顺序也可以参照现有技术，此处不再赘述。
本公开实施例提供了一种薄膜晶体管及其制作方法、以及一种包括上述薄膜晶体管的显示装置。在上述薄膜晶体管中，栅极为复合金属层的结构。具体地，该复合金属层中靠近栅绝缘层的第一金属层具有掺杂离子。这使得能够对有源层引入应力，改变有源层中沟道区的能带结构，并且改变载流子的有效质量和各向异性散射等，从而提高载流子的迁移率。此外，该复合金属层中远离栅绝缘层的第二金属层未掺杂有离子，从而可以保证整个栅极的有效电阻。在本公开的实施例中，通过对薄膜晶体管中的栅极的改进达到了提升载流子迁移率的目的，而同时无需增加额外的结构，这使得生产过程中的工艺更为简单。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。因此，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种薄膜晶体管，包括：衬底基板，以及位于所述衬底基板上的源极、漏极、栅极、栅绝缘层和有源层；其中，所述栅绝缘层设置在所述栅极与所述有源层之间；所述源极和所述漏极分别与所述有源层连接；并且
    所述栅极为复合金属层；所述复合金属层包括至少一层靠近所述栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离所述栅绝缘层的第二金属层。
  2. 根据权利要求1所述的薄膜晶体管，其中所述具有掺杂离子的第一金属层配置成对所述有源层引入应力。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述具有掺杂离子的第一金属层中的掺杂离子为氮离子。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述氮离子的剂量范围为1.0e12～1.0e13/cm2。
  5. 根据权利要求3所述的薄膜晶体管，其中，所述栅绝缘层的材料至少包括氧化硅和氮化硅。
  6. 根据权利要求2所述的薄膜晶体管，其中，所述第一金属层和第二金属层的材料至少包括钼、钛和铝中的一种。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述复合金属层包括一层所述具有掺杂离子的第一金属层和两层第二金属层；所述第一金属层的材料为钼或钛，靠近所述第一金属层的第二金属层的材料为铝，并且远离所述第一金属层的第二金属层的材料为钼或钛。
  8. 根据权利要求1～6任一项所述的薄膜晶体管，其中，所述栅极、所述有源层和所述栅绝缘层在所述衬底基板上的层叠顺序依次为所述有源层、所述栅绝缘层和所述栅极。
  9. 根据权利要求8所述的薄膜晶体管，还包括层间介质层；其中，
    所述层间介质层覆盖所述栅极和所述栅绝缘层；所述源极贯穿所述层间介质层和所述栅绝缘层与所述有源层连接；并且所述漏极贯穿所述层间介质层和所述栅绝缘层与所述有源层连接。
  10. 根据权利要求1～6任一项所述的薄膜晶体管，其中，所述栅极、所述有源层和所述栅绝缘层在所述衬底基板上的层叠顺序依次为 所述栅极、所述栅绝缘层。
  11. 一种显示装置，包括如权利要求1～10任一项所述的薄膜晶体管。
  12. 一种薄膜晶体管的制作方法，包括：在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤；其中，所述栅绝缘层形成在所述栅极与所述有源层之间；所述源极和所述漏极形成为分别与所述有源层连接；其中，
    形成栅极的步骤，包括：
    形成复合金属层，以形成栅极；所述复合金属层包括至少一层靠近所述栅绝缘层的具有掺杂离子的第一金属层，和至少一层远离所述栅绝缘层的第二金属层。
  13. 根据权利要求12所述的制作方法，其中所述具有掺杂离子的第一金属层配置成对所述有源层引入应力。
  14. 根据权利要求13所述的制作方法，其中，利用离子注入工艺和构图工艺形成复合金属层，以形成栅极。
  15. 根据权利要求14所述的制作方法，其中，在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤，包括：
    形成位于衬底基板上的有源层；
    形成位于所述有源层和所述衬底基板上的栅绝缘层；
    利用离子注入工艺和构图工艺，形成位于所述栅绝缘层上且在所述有源层上方的复合金属层，以形成栅极；
    以所述复合金属层为掩膜，利用离子注入工艺透过所述栅绝缘层向所述有源层中进行离子注入；以及
    分别形成与所述有源层连接的源极和漏极。
  16. 根据权利要求15所述的制作方法，其中，所述利用离子注入工艺和构图工艺，形成位于所述栅绝缘层上且在所述有源层上方的复合金属层，以形成栅极这一步骤，包括：
    在所述栅绝缘层上且在所述有源层上方形成至少一层第一金属薄膜；
    对所述第一金属薄膜进行氮离子注入；
    在已注入氮离子的所述第一金属薄膜上形成至少一层第二金属薄膜；以及
    通过构图工艺对所述第一金属薄膜和第二金属薄膜进行刻蚀，以形成栅极。
  17. 根据权利要求16所述的制作方法，其中，对所述第一金属薄膜进行氮离子注入时，所述氮离子的能量值的范围为20～40kev。
  18. 根据权利要求16所述的制作方法，还包括：形成覆盖所述栅极和所述栅绝缘层的层间介质层；并且
    所述分别形成与所述有源层连接的源极和漏极的步骤，包括：
    通过构图工艺形成贯穿所述层间介质层和栅绝缘层的第一接触孔和第二接触孔，以暴露出所述有源层；以及
    分别向所述第一接触孔和第二接触孔中沉积源极金属层和漏极金属层，以形成源极和漏极。
PCT/CN2016/081415 2016-03-22 2016-05-09 薄膜晶体管及其制作方法、以及显示装置 WO2017161645A1 (zh)

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