WO2017157117A1 - 一种应用于集成电路的静电放电esd保护电路 - Google Patents

一种应用于集成电路的静电放电esd保护电路 Download PDF

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WO2017157117A1
WO2017157117A1 PCT/CN2017/073392 CN2017073392W WO2017157117A1 WO 2017157117 A1 WO2017157117 A1 WO 2017157117A1 CN 2017073392 W CN2017073392 W CN 2017073392W WO 2017157117 A1 WO2017157117 A1 WO 2017157117A1
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mos transistor
esd protection
protection circuit
voltage
channel mos
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安建宏
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China Academy of Telecommunications Technology CATT
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

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  • the present application relates to the field of electronic circuits, and more particularly to an electrostatic discharge ESD protection circuit applied to an integrated circuit.
  • ESD Electrostatic Discharge
  • the ESD phenomenon can mainly cause the following damage to the electronic device: the oxide film is broken due to dielectric breakdown in the semiconductor device; the metal wire is melted due to overheating caused by EOS (Electrical Overstress); due to the parasitic PNPN structure Leading to the occlusion of CMOS (Complementary Metal-Oxide-Semiconductor) devices; causing hidden defects in the structure of the components, they do not immediately fail, but cause intermittent failure and long-term reliability problems.
  • the damage is very weak and difficult to find, that is, potential damage.
  • the loss caused by ESD in the integrated circuit industry is a very serious problem.
  • the failure mechanism caused by ESD is mainly thermal breakdown and electrical breakdown.
  • the role of the ESD protection circuit is to provide a low impedance discharge path when the ESD pulse is present and to clamp the voltage to a certain level. This path opens the ESD pulse faster than the internal circuit and has less impact on normal operation, including smaller leakage current, parasitic, latching and so on.
  • the ESD protection circuit is generally designed in the integrated circuit design next to the chip pin pad PAD to protect the internal circuit of the chip.
  • One or more devices are usually used to form an ESD protection circuit. There are many devices for forming an ESD protection circuit, and a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) is one of them.
  • Figure 1 (a) and Figure 1 (b) show the structure and current-voltage characteristics of the NMOS transistor, respectively, mainly using the Snapback effect of the NMOS transistor to clamp the instantaneous high voltage and shunt, as shown in Figure 1 (a As shown in the figure, there is a lateral parasitic npn transistor inside the NMOS transistor, which is formed by the source source, the p-substrate p-substrate and the drain Drain.
  • 1(b) is For the voltage and current when the parasitic transistor is turned on, when the ESD occurs, the parasitic npn transistor triggers the conduction, and the electrostatic charge discharged by the ESD can be discharged to the ground through the device, and the voltage across the device falls back to the Vhold, so that The voltage across the protected device is limited to Vhold, ie the clamp voltage is Vhold.
  • a good ESD protection circuit should be able to withstand multiple ESD events; it should also be fast enough to turn it on. Speed and low turn-on resistance to ensure that the voltage is clamped quickly when an ESD event occurs, so that the corresponding protected circuit is not damaged.
  • the protection circuit should also be independent. When the circuit is protected, the protection circuit should be in a high-impedance state and will not affect the normal operation of the protected internal circuit, especially in low-power system applications, such as low-power crystal solutions.
  • the leakage requirement of the ESD protection circuit is relatively high, and the leakage is required to be small.
  • the embodiment of the present application provides an ESD protection circuit applied to an integrated circuit for implementing an ESD protection circuit with a small leakage current to reduce system power consumption.
  • One embodiment of the present application provides an electrostatic discharge ESD protection circuit for an integrated circuit, including: a main ESD protection circuit, a resistor, and a slave ESD protection circuit.
  • the main ESD protection circuit includes at least a high voltage N-channel metal oxide semiconductor field effect MOS transistor, and a gate, a source and a body terminal of the high voltage N-channel MOS transistor are connected to ground, and the high voltage N-channel MOS The drain of the transistor is connected to the pin pad PAD of the integrated circuit.
  • the slave ESD protection circuit includes at least a low voltage N-channel MOS transistor, a gate, a source and a body terminal of the low voltage N-channel MOS transistor are connected to ground, and a drain of the low voltage N-channel MOS transistor is passed through The resistor is coupled to the drain of the high voltage N-channel MOS transistor and to the circuit protected within the integrated circuit.
  • the high voltage N-channel MOS transistor has an operating voltage greater than or equal to 5V.
  • the operating voltage of the low voltage N-channel MOS transistor is less than or equal to 1.8V.
  • the high voltage N-channel MOS transistor is a high voltage N-channel enhancement type MOS transistor; and the low voltage N-channel MOS transistor is a low voltage N-channel enhancement type MOS transistor.
  • the main ESD protection circuit further includes a high voltage P-channel MOS transistor, the gate, the source and the body end of the high voltage P-channel MOS transistor are connected to the positive pole of the power source, and the high voltage P-channel A drain of the MOS transistor is connected to a drain of the high voltage N-channel MOS transistor.
  • a low-voltage P-channel MOS transistor is further included in the ESD protection circuit, and a gate, a source, and a body terminal of the low-voltage P-channel MOS transistor are connected to a positive electrode of the power source, and the low-voltage P-channel A drain of the MOS transistor is connected to a drain of the low voltage N-channel MOS transistor.
  • the resistor is a current limiting resistor having a resistance level in the range of one hundred K ohms.
  • the current limiting resistor is a polysilicon resistor or a diffusion resistor.
  • a resistor is also connected in series between the gate of the high voltage N-channel MOS transistor and ground.
  • the ESD protection circuit applied to the integrated circuit provided by the embodiment of the present application includes a two-stage ESD protection circuit, and a high-voltage NMOS tube is used in the main ESD protection circuit, so that the high-voltage NMOS tube can be utilized.
  • the electrical characteristics enable a small leakage current to reduce the power consumption of the system, so as to better meet the application requirements of low-power systems.
  • Figure 1 (a) is a schematic structural view of an NMOS transistor
  • Figure 1 (b) is a schematic diagram of current and voltage characteristics of an NMOS transistor
  • FIG. 2 is a schematic structural diagram of an ESD protection circuit in the background art
  • FIG. 3 is a schematic structural diagram of another ESD protection circuit in the background art
  • FIG. 4 is a schematic structural diagram of an ESD protection circuit applied to an integrated circuit according to some embodiments of the present application.
  • FIG. 5 is a schematic structural diagram of an ESD protection circuit applied to an integrated circuit according to still another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an ESD protection circuit applied to an integrated circuit according to still another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an ESD protection circuit applied to an integrated circuit according to still another embodiment of the present application.
  • ESD protection devices include resistors, diodes, bipolar transistors, MOS transistors, SCR (Silicon Controlled Rectifier), and the like. Since MOS tubes are compatible with CMOS processes, they are usually used. MOS tube construction protection circuit.
  • FIG. 2 shows an ESD protection circuit commonly used in the prior art, which includes a two-stage ESD protection circuit (main ESD 201 and slave ESD 203) and a current limiting resistor R. 0 202.
  • the main ESD 201 is used to amplify a portion of the electrostatic current when an ESD event occurs, from the ESD 203 for the clamping voltage and further to discharge the electrostatic current, and the resistor R 0 202 is used for current limiting.
  • the internal MOS transistor of the protected internal circuit 204 connected to the ESD protection circuit is a low voltage (LV) MOS.
  • the ESD protection circuit used in the low-voltage or low-power system is also composed of electronic components with low operating voltage.
  • the main ESD 201 and the slave ESD 203 are each composed of a low voltage (LV) gg-NMOS transistor (grounded-gate NMOS), such as a low voltage MOS transistor operating at 1.2 V or 1.8 V.
  • LV low voltage
  • gg-NMOS Grounded-gate NMOS
  • the drain terminal (Drain) of the low voltage gg-NMOS transistor of the main ESD 201 is connected to the PAD, that is, the pin pad of the integrated circuit, the gate terminal (Gate), and the source and source (p-substrate) ground;
  • the drain terminal of the low voltage gg-NMOS transistor of the ESD 203 is connected to the PAD through the resistor R 0 202, the gate terminal and the source terminal and the body terminal are grounded;
  • the drain terminal of the low voltage gg-NMOS transistor of the ESD 203 is connected to the internal circuit 204, as shown in FIG.
  • the gate of the low voltage MOS transistor connected to internal circuit 204 is shown.
  • the resistance of R 0 202 is generally a few K ohms.
  • FIG. 3 shows another common ESD protection circuit in the prior art. Similar to the ESD protection circuit shown in FIG. 2, the ESD protection circuit shown in FIG. 3 also includes a two-stage ESD protection circuit (main ESD301). And from the ESD 303) and the current limiting resistor R 1 302, the difference between the main ESD 301 and the slave ESD 303 in the ESD protection circuit shown in FIG. 3 includes a low voltage (LV) gg-NMOS transistor and a low voltage (LV) gc-PMOS, respectively. The grounded-coupled PMOS (gate-connected PMOS) can be seen. The ESD protection circuit shown in Figure 3 is based on the ESD protection circuit shown in Figure 2. The main ESD301 further includes a low-voltage gc-PMOS.
  • main ESD301 further includes a low-voltage gc-PMOS.
  • the drain terminal of the transistor is connected to the PAD, the gate terminal and the source terminal and the body terminal (n-substrate) are connected to the positive pole of the power source, and the ESD 303 further comprises a low voltage gc-PMOS transistor whose drain terminal is connected to the PAD through the resistor R 1 302.
  • the gate terminal and the source terminal and the body terminal are connected to the positive pole of the power supply.
  • the principle is also to use a MOS transistor, including an NMOS transistor and a PMOS transistor. When the voltage at the drain terminal reaches a certain value, the parasitic npn transistor inside the NMOS transistor and the parasitic pnp inside the PMOS transistor The transistor is turned on and the ESD current is applied. Road, protects internal circuitry.
  • the ESD protection circuit commonly used in the background art as shown in FIG. 2 or FIG. 3 has a low clamp voltage and a low turn-on voltage
  • the advantages of resistance, but its application in low-voltage and low-power systems still has a large disadvantage, that is, the leakage current of the low-voltage MOS tube of the ESD protection circuit will be relatively large, which has a great influence on the internal circuit, and often cannot be very good.
  • the ESD protection circuit has high leakage requirements and requires little leakage.
  • an ESD protection technical solution that can better meet the application requirements of the low-power system.
  • the embodiment of the present application provides an ESD protection circuit, which is applied to an integrated circuit. It can achieve a small leakage current, which can reduce the power consumption of the system.
  • FIG. 4 is a schematic diagram of an ESD protection circuit for an integrated circuit provided by an embodiment of the present application.
  • the ESD protection circuit includes a main ESD protection circuit 401, a resistor 402, and a slave ESD protection circuit 403. Also shown in FIG. 4 is the portion of the ESD protection circuit for protecting the internal circuitry from the ESD protection circuit, which may be part of an integrated circuit in a low voltage or low power system, and thus the electronics employed
  • the component is a low voltage electronic component, that is, the internal circuit 404 shown in FIG. 4 is connected to the resistor 402 through the gate of a low voltage NMOS transistor, and the source of the low voltage NMOS transistor is grounded. It should be understood that the internal portion shown in FIG.
  • the circuit portion and its structure connected to the ESD protection circuit are only a schematic diagram of a common connection.
  • the ESD protection circuit provided by the embodiment of the present application is not limited to the internal circuit shown in FIG. 4 and FIG. 4 in the application.
  • the connection, the protected circuit, and the connection to the ESD protection circuit provided by the embodiment of the present application may be various, and the present application does not specifically limit this.
  • the main ESD protection circuit 401 includes at least a high voltage N-channel MOS transistor, that is, a high voltage (HV) NMOS transistor T1 shown in FIG.
  • the gate, source and body terminals of the high voltage N-channel MOS transistor T1 are connected to ground, and the drain of the high voltage N-channel MOS transistor T1 is connected to the pin pad PAD of the integrated circuit.
  • the pad pad PAD is a pad in a PCB (Printed Circuit Board), which can generally be used to set IC chip pins, wires, connection points, etc.
  • PCB Print Circuit Board
  • the PAD in the PCB is based on The different conditions of the connected working circuit are used to input or output control signals, power supplies, pulses, etc., or also to connect to ground, to resistors, to float, and the like.
  • ESD protection circuitry is typically designed next to the PAD.
  • the ESD is generally introduced into the chip through the pin pad PAD of the chip.
  • the ESD protection circuit To provide a low-resistance bypass of the ESD current, such as a PAD-to-ground low-resistance discharge path, PAD to the power supply.
  • the low-resistance discharge path, the low-resistance discharge path from PAD to PAD, etc., for the entire chip, the ESD protection circuit should be able to be referenced multiple times in the chip.
  • the low-voltage N-channel MOS transistor that is, the low-voltage (LV) NMOS transistor T2 shown in FIG. 4, is included in the ESD protection circuit 403.
  • the gate, the source and the body of the low-voltage N-channel MOS transistor T2 are connected to the ground, and the drain of the low-voltage N-channel MOS transistor T2 is connected to the drain of the high-voltage N-channel MOS transistor T1 via a resistor R402.
  • the drain of the N-channel MOS transistor T2 is also connected to a circuit protected inside the integrated circuit, that is, the internal circuit 404 shown in FIG.
  • the operating voltage of the high voltage N-channel MOS transistor T1 employed by the main ESD protection circuit 401 is higher than or equal to 5V.
  • the operating voltage of the electronic component in the internal circuit protected by the ESD protection circuit can be selected. For example, if the working voltage of the MOS transistor connected to the ESD protection circuit in the internal circuit is 1.2 or 1.8V, the operating voltage can be selected. It is a 5V NMOS transistor to form a main ESD protection circuit.
  • the operating voltage of the low voltage N-channel MOS transistor T2 employed from the ESD protection circuit 403 is less than or equal to 1.8V.
  • the operating voltage of the electronic component in the internal circuit protected by the ESD protection circuit can be selected. For example, if the working voltage of the MOS transistor connected to the ESD protection circuit in the internal circuit is 1.2 or 1.8V, the operating voltage can be selected. It is a 1.2V or 1.8V NMOS transistor to form a slave ESD protection circuit.
  • the high voltage NMOS transistor T1 used by the main ESD protection circuit 401 is a high voltage N-channel enhancement type MOS transistor; the low voltage NMOS transistor T2 used from the ESD protection circuit 403 is a low voltage N-channel enhancement type. MOS tube.
  • the ESD protection circuit provided by the embodiment of the present application shown in FIG. 4 uses a high voltage NMOS in the main ESD protection circuit 401 as compared with an ESD protection circuit in the prior art as shown in FIG. 2 .
  • the tube can thereby utilize the electrical characteristics of the high-voltage NMOS transistor to achieve a small leakage current, thereby achieving the effect of reducing system power consumption.
  • a high-voltage NMOS transistor can be used for the ESD protection circuit 403, since the area of the MOS transistor having a higher operating voltage is larger in the fabrication process, if the main ESD protection circuit 401 and the slave ESD are protected, The circuit 403 adopts a high-voltage MOS scheme, which is contrary to the current trend of miniaturization of integrated circuits, and is not conducive to manufacturing.
  • the resistor R402 used in the ESD protection circuit is a current limiting resistor having a resistance level in the range of 100 K ohms, such as a resistance ranging from 400 K ohms to 600 K ohms.
  • the resistor R402 may be a polysilicon (poly) resistor or a diffusion resistor or the like.
  • the basic concept can also be adaptively applied to another common ESD protection in the prior art as shown in FIG.
  • the circuit that is, the ESD protection circuit applied to the integrated circuit provided by still other embodiments of the present application may be as shown in FIG. 5.
  • the main ESD protection circuit 401 further includes a high voltage P-channel MOS transistor, that is, a high voltage (HV) PMOS transistor T3 as shown in FIG.
  • the gate, the source and the body of the high-voltage P-channel MOS transistor T3 are connected to the positive pole of the power supply, and the drain of the high-voltage P-channel MOS transistor T3 is connected to the drain of the high-voltage N-channel MOS transistor T1 of the main ESD protection circuit 401. pole.
  • the ESD protection circuit applied to the integrated circuit provided by still other embodiments of the present application may also be as shown in FIG. 6.
  • the low-voltage P-channel MOS transistor that is, the low-voltage (LV) PMOS transistor T4 shown in FIG. 6, is further included in the ESD protection circuit 403.
  • the gate, source and body terminals of the low-voltage P-channel MOS transistor T4 are connected to the positive electrode of the power supply, and the drain of the low-voltage P-channel MOS transistor T4 is connected to the drain of the low-voltage N-channel MOS transistor T2 from the ESD protection circuit 403. pole.
  • the ESD protection circuit applied to the integrated circuit provided by still other embodiments of the present application may also be as shown in FIG. 7.
  • the circuit shown in FIG. 7 combines the high voltage P-channel MOS transistor further included in the main ESD protection circuit 401 shown in FIG. 5, that is, the high voltage (HV) PMOS transistor T3 shown in FIG. 5, and as shown in FIG.
  • the determination of the operating voltage of the NMOS transistor used in the ESD protection circuit provided in the embodiment of the present application as shown in FIG. 4 and the concept of using the enhanced MOS transistor are also applicable to FIG. 5, FIG. 6, and FIG. The choice of NMOS and PMOS transistors in the ESD protection circuit shown.
  • a resistor Rgate may be connected in series between the gate of the high voltage NMOS transistor T1 and the ground shown in FIG.
  • the purpose of the ESD protection circuit is to prevent the working circuit (protected circuit) from being damaged by the ESD discharge path.
  • the chip design should ensure that an ESD event occurs between any two chip pins.
  • a suitable low-impedance bypass (ESD protection circuit) is available to bleed the ESD current. Therefore, similar to the existing ESD protection circuit in practical applications, the ESD protection circuit provided by the embodiment of the present application is generally designed in the layout of the PAD in the actual circuit design, thereby ensuring that when ESD occurs, The ESD current is applied and the circuit voltage is clamped effectively immediately, where the ESD protection circuit should be placed as close as possible to the protected internal circuit in order to reduce the resistance of the wiring.
  • the ESD protection circuit provided by the embodiments of the present application can be fabricated in the same process as the devices in the protected internal circuit, such as BCD (Bipolar CMOS DMOS) integration process technology.
  • the ESD protection circuit applied to the integrated circuit provided by the embodiment of the present application can inherit not only the advantages of the ESD protection circuit in the prior art, but also the ESD current of the amplified portion through the main ESD protection circuit and By protecting the circuit clamp voltage from the ESD, the working circuit is prevented from being damaged due to ESD, and can be quickly responded when ESD occurs, and the ESD protection circuit provided by the embodiment of the present application uses a high voltage MOS tube in the main ESD protection circuit.
  • the ESD protection circuit in the technology has a large leakage defect, which can reduce the power consumption of the system, and thus can better meet the application requirements of the low-voltage or low-power system.
  • ESD protection circuit for an integrated circuit provided by the present application. It should be understood that the ESD protection circuit provided by the present application is not limited to the above preferred embodiment. In the design of the integrated circuit, the ESD protection circuit provided by the present application can generate various electronic components in combination with actual application requirements. Select the situation and the implementation of the circuit.

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Abstract

一种应用于集成电路的静电放电ESD保护电路，包括：主ESD保护电路(401)、电阻(402)和从ESD保护电路(403)；主ESD保护电路(401)中至少包括一个高压N沟道MOS管(T1)，该高压N沟道MOS管(T1)的栅极、源极和体端连接到地，该高压N沟道MOS管(T1)的漏极连接集成电路芯片的引脚焊盘PAD；从ESD保护电路(403)中至少包括一个低压N沟道MOS晶体管(T2)，该低压N沟道MOS管(T2)的栅极、源极和体端连接到地，该低压N沟道MOS管(T2)的漏极通过所述电阻(402)连接到高压N沟道MOS管(T1)的漏极，并连接到集成电路芯片内部被保护的电路(404)。该静电放电ESD保护电路能够实现一种漏电电流较小的ESD保护电路，降低系统功耗。

Description

一种应用于集成电路的静电放电ESD保护电路
本申请要求在2016年3月17日提交中国专利局、申请号为201610154495.2、申请名称为“一种应用于集成电路的静电放电ESD保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路领域，尤其涉及一种应用于集成电路的静电放电ESD保护电路。
背景技术
ESD(Electrostatic Discharge，静电放电)是当今集成电路中最重要的可靠性问题之一。ESD现象主要能对电子器件造成以下的损坏：在半导体器件中由于介质击穿而导致氧化物薄膜破裂；由于EOS(Electrical Overstress，电气过应力)引起过热导致金属导线熔化；由于寄生的PNPN结构而导致CMOS(Complementary Metal-Oxide-Semiconductor，互补金属氧化物半导体)器件闭锁；使元器件结构中产生潜藏的缺陷，它们并不立即失效，但会引起断续的故障以及长期可靠性问题，这种损伤非常微弱，不易发现，即潜在损伤.集成电路工业由ESD导致的损失是一个非常严重的问题。ESD造成的失效机理主要热击穿和电击穿。
ESD保护电路的作用是：当ESD脉冲出现后，能提供一条低阻抗的放电通路，并能够将电压钳位在一定水平。该通路对ESD脉冲的开启速度快于内部电路，对正常工作影响较小，包括较小漏电流、寄生、栓锁等。ESD保护电路在集成电路设计中一般设计在芯片引脚焊盘PAD旁，用以保护芯片的内部电路。通常用一个或多个器件构成ESD保护电路，用来构成ESD保护电路的器件有很多种，MOS管(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应管)就是其中一种，包括NMOS管(N-Channel MOS，N沟道MOS管)和PMOS管(P-Channel MOS，P沟道MOS管)。图1(a)和图1(b)分别示出了NMOS管的结构和电流电压特性，主要利用NMOS管的瞬间崩溃(Snapback)效应来钳位瞬间高压和进行分流的，如图1(a)所示，NMOS管内部有一个横向寄生n-p-n晶体管，即由源极Source、P型衬底p-substrate和漏极Drain形成的，图1(b)中的E(V1，I1)坐标点即为该寄生晶体管开启时的电压电流，在ESD发生时，该寄生n-p-n晶体管触发导通，ESD放出的静电电荷则能够通过该器件泄放到地，此时该器件两端的电压回落至Vhold，使得被保护器件两端电压被限制在Vhold，即钳位电压为Vhold。
一个好的ESD保护电路应该能够可以抵抗多次ESD事件；还应该具有足够快的开启 速度以及低的开启电阻，以保证在ESD事件发生时，能够快速将电压钳位，使得相应的被保护电路不受损伤。保护电路还应该具有独立性，在被保护电路工作时，保护电路应该是高阻状态，不影响被保护内部电路的正常工作，尤其在低功耗系统应用中，如低功耗晶振解决方案，对ESD保护电路漏电要求比较高，要求漏电很小。
因此，如何实现一种漏电电流较小的ESD保护电路，从而降低系统功耗，满足低功耗系统的要求，是业界所亟待研究和解决的问题。
发明内容
本申请实施例提供一种应用于集成电路的静电放电ESD保护电路，用以实现一种漏电电流较小的ESD保护电路，降低系统功耗。
本申请的一个实施例提供的一种应用于集成电路的静电放电ESD保护电路，包括：主ESD保护电路、电阻和从ESD保护电路。
所述主ESD保护电路中至少包括高压N沟道金属氧化物半导体场效应MOS管，所述高压N沟道MOS管的栅极、源极和体端连接到地，所述高压N沟道MOS管的漏极连接集成电路的引脚焊盘PAD。
所述从ESD保护电路中至少包括低压N沟道MOS晶体管，所述低压N沟道MOS管的栅极、源极和体端连接到地，所述低压N沟道MOS管的漏极通过所述电阻连接到所述高压N沟道MOS管的漏极，并连接到所述集成电路内部被保护的电路。
本申请的一些实施例中，高压N沟道MOS管的工作电压高于或等于5V。
本申请的一些实施例中，低压N沟道MOS管的工作电压低于或等于1.8V。
本申请的一些实施例中，高压N沟道MOS管为高压N沟道增强型MOS管；低压N沟道MOS管为低压N沟道增强型MOS管。
本申请的一些实施例中，主ESD保护电路中还包括高压P沟道MOS管，所述高压P沟道MOS管的栅极、源极和体端连接到电源正极，所述高压P沟道MOS管的漏极连接到所述高压N沟道MOS管的漏极。
本申请的一些实施例中，从ESD保护电路中还包括低压P沟道MOS管，所述低压P沟道MOS管的栅极、源极和体端连接到电源正极，所述低压P沟道MOS管的漏极连接到所述低压N沟道MOS管的漏极。
本申请的一些实施例中，电阻为阻值量级在百K欧姆范围内的限流电阻。
本申请的一些实施例中，限流电阻为多晶硅电阻或扩散电阻。
本申请的一些实施例中，高压N沟道MOS管的栅极与地之间还串联有电阻。
可以看到，本申请实施例所提供的一种应用于集成电路的ESD保护电路，包括有两级ESD保护电路，并在主ESD保护电路中采用的是高压NMOS管，从而能够利用高压NMOS管的电气特性，实现较小的漏电电流，达到降低系统功耗的效果，从而能够更好地满足低功耗系统的应用要求。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1(a)为NMOS管的结构示意图；
图1(b)为NMOS管的电流电压特性示意图；
图2为背景技术中一种ESD保护电路的结构示意图；
图3为背景技术中又一种ESD保护电路的结构示意图；
图4为本申请的一些实施例提供的一种应用于集成电路的ESD保护电路的结构示意图；
图5为本申请的又一些实施例提供的一种应用于集成电路的ESD保护电路的结构示意图；
图6为本申请的又一些实施例提供的一种应用于集成电路的ESD保护电路的结构示意图；
图7为本申请的又一些实施例提供的一种应用于集成电路的ESD保护电路的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，显然，所描述的实施例仅仅是本申请一部份实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
随着IC(Integrated Circuit，集成电路)设计和制造技术的发展，ESD对集成电路的影响也越来越大。常用的ESD保护器件有电阻、二极管、双极性晶体管、MOS管、SCR(Silicon Controlled Rectifier，可控硅晶闸管)等。由于MOS管与CMOS工艺兼容性好，通常采用 MOS管构造保护电路。
对于低压或低功耗系统的集成电路设计，图2示出了现有技术中常用的一种ESD保护电路，该保护电路包括两级ESD保护电路(主ESD201和从ESD203)以及限流电阻R0202。其中，主ESD201用于在发生ESD事件时泄放大部分静电电流，从ESD203用于钳位电压以及进一步泄放静电电流，电阻R0202用于限流。由于低压或低功耗系统往往采用低压电子元器件来构造集成电路，即如图2所示的，受保护的内部电路204中与该ESD保护电路相连接的内部MOS管为低压(LV)MOS管，比如工作电压为1.2V或1.8V的低压MOS管，因此为了配合内部电路的工作电压，应用在低压或低功耗系统中的ESD保护电路也采用工作电压低的电子元器件构成。
具体如图2所示，主ESD201和从ESD203均由低压(LV)gg-NMOS管(grounded-gate NMOS，栅极接地NMOS管)构成，比如工作电压为1.2V或1.8V的低压MOS管。其中，主ESD201的低压gg-NMOS管的漏极端(Drain)连接至PAD，即集成电路的引脚焊盘，栅极端(Gate)以及源极端(Source)和体端(p-substrate)接地；从ESD203的低压gg-NMOS管的漏极端通过电阻R0202连接至PAD，栅极端以及源极端和体端接地；从ESD203的低压gg-NMOS管的漏极端连接至内部电路204，如图2所示的连接到内部电路204的低压MOS管的栅极。在如图2所示的ESD电路结构中，R0202的阻值一般取几K欧姆。通过利用gg-NMOS管内寄生的n-p-p三极管，形成一个低阻抗的放电通路，当在PAD上施加ESD脉冲时，低压gg-NMOS管被触发，内部的寄生n-p-n晶体管开启，对ESD电流进行旁路，从而实现对内部电路204的保护。
图3示出了现有技术中的又一种较为常见的ESD保护电路，与图2所示的ESD保护电路类似的，图3所示的ESD保护电路也包括两级ESD保护电路(主ESD301和从ESD303)以及限流电阻R1302，区别在于图3所示的ESD保护电路中的主ESD301和从ESD303均分别包括一个低压(LV)gg-NMOS管和一个低压(LV)gc-PMOS管(grounded-coupled PMOS，栅接电源PMOS管)，可以看到，如图3所示的ESD保护电路为在图2所示的ESD保护电路的基础上，主ESD301进一步包括一个低压gc-PMOS管，其漏极端连接至PAD，栅极端以及源极端和体端(n-substrate)连接到电源正极，从ESD303进一步包括一个低压gc-PMOS管，其漏极端通过电阻R1302连接至PAD，栅极端以及源极端和体端连接到电源正极，其原理也是利用MOS管，包括NMOS管和PMOS管，在漏极端电压达到一定值时，NMOS管内部的寄生n-p-n晶体管以及PMOS管内部的寄生p-n-p晶体管开启，对ESD电流进行旁路，实现对内部电路的保护。
尽管如图2或图3所示的背景技术中常用的ESD保护电路具有钳位电压低和低开启电 阻的优点，但其在低压低功耗系统中的应用仍然存在有较大的缺点，即ESD保护电路的低压MOS管的漏电电流会比较大，对内部电路影响很大，往往不能够很好的满足低压或低功耗系统的应用要求，比如低功耗晶振解决方案对ESD保护电路漏电要求就很高，要求漏电很小。
为了克服现有ESD保护电路的上述缺陷，提供一种能够更好满足低功耗系统应用要求的ESD保护技术方案，本申请实施例提出一种ESD保护电路，该ESD保护电路应用于集成电路中，能够实现较小的漏电电流，从而达到降低系统功耗的效果。
下面结合附图对本申请实施例进行详细描述。
图4示出了本申请实施例提供的一种应用于集成电路的静电放电ESD保护电路的示意图，该ESD保护电路包括：主ESD保护电路401、电阻402和从ESD保护电路403。图4中还示出了该ESD保护电路用以保护的内部电路与该ESD保护电路连接的部分，该内部电路404可以是低压或低功耗系统中的集成电路的部分，因此所采用的电子元器件为低压电子元器件，即图4所示的内部电路404通过一个低压NMOS管的栅极连接到电阻402，该低压NMOS管的源极接地，应当理解的是，图4所示的内部电路部分以及其与ESD保护电路连接的结构仅是一种常用的连接情况的示意，本申请实施例所提供的ESD保护电路在应用中并不限于如图4所示的内部电路以及如图4所示的连接情况，被保护的电路以及其与本申请实施例所提供的ESD保护电路的连接可以有多种情况，本申请对此不作具体限定。
如图4所示，主ESD保护电路401中至少包括高压N沟道MOS管，即图4所示的高压(HV)NMOS管T1。该高压N沟道MOS管T1的栅极、源极和体端连接到地，该高压N沟道MOS管T1的漏极连接集成电路的引脚焊盘PAD。
其中，引脚焊盘PAD是PCB(Printed Circuit Board，印刷电路板)中的焊盘，一般可以用于设置IC芯片引脚、导线、连通点等，在PCB实际应用中，PCB中的PAD根据所连接的工作电路的不同情况用于输入或输出控制信号、电源、脉冲等，或者还用于连接到地，连接到电阻，悬空等。为了保护内部电路，ESD保护电路一般设计在PAD旁。
比如以芯片为例，ESD一般通过芯片的引脚焊盘PAD导入芯片内部，为了防止芯片受ESD损伤，应当能够保证芯片引脚焊盘PAD处可能发生的ESD都可以由低阻旁路释放，即芯片的I/O(Input/Output，输入输出)电路中与PAD直接相连的器件需要建立ESD保护电路以提供ESD电流的低阻旁路，如PAD到地的低阻放电通路，PAD到电源的低阻放电通路，PAD到PAD的低阻放电通路等，就整个芯片来说，ESD保护电路在芯片中应能够多次引用。
从ESD保护电路403中至少包括低压N沟道MOS晶体管，即图4所示的低压(LV)NMOS管T2。该低压N沟道MOS管T2的栅极、源极和体端连接到地，该低压N沟道MOS管T2的漏极通过电阻R402连接到高压N沟道MOS管T1的漏极，该低压N沟道MOS管T2的漏极还连接到集成电路内部被保护的电路，即图4所示的内部电路404。
在本申请的一些实施例中，主ESD保护电路401所采用的高压N沟道MOS管T1的工作电压高于或等于5V。具体可以根据该ESD保护电路用于保护的内部电路中电子元器件的工作电压来选择，比如对于内部电路中与该ESD保护电路连接的MOS管工作电压为1.2或1.8V，则可以选择工作电压为5V的NMOS管来构成主ESD保护电路。
在本申请的一些实施例中，从ESD保护电路403所采用的低压N沟道MOS管T2的工作电压低于或等于1.8V。具体可以根据该ESD保护电路用于保护的内部电路中电子元器件的工作电压来选择，比如对于内部电路中与该ESD保护电路连接的MOS管工作电压为1.2或1.8V，则可以选择工作电压为1.2V或者1.8V的NMOS管来构成从ESD保护电路。
本申请的一些优选实施例中，主ESD保护电路401所采用的高压NMOS管T1为高压N沟道增强型MOS管；从ESD保护电路403所采用的低压NMOS管T2为低压N沟道增强型MOS管。
可以看到，图4所示的本申请实施例所提供的ESD保护电路与如图2所示的现有技术中的一种ESD保护电路相比，在主ESD保护电路401中采用了高压NMOS管，从而能够利用高压NMOS管的电气特性，实现较小的漏电电流，从而达到降低系统功耗的效果。尽管理论上对从ESD保护电路403也可以采用高压NMOS管来构成，但是由于在制作工艺上，工作电压越高的MOS管的面积也越大，因此如果对主ESD保护电路401和从ESD保护电路403均采用高压MOS的方案，有悖于目前集成电路小型化的趋势，不利于生产制造。
由于主ESD保护电路401采用的是高压NMOS管，为了保护从ESD保护电路403所采用的低压NMOS以及内部电路404的低压NMOS管的栅氧层不被击穿，在本申请实施例所提供的ESD保护电路中所采用的电阻R402为阻值量级在百K欧姆范围内的限流电阻，比如阻值为400K欧姆至600K欧姆范围的电阻。在本申请的一些优选实施例中，电阻R402可以采用多晶硅(poly)电阻或扩散电阻等。
对于如图4所示的本申请实施例所提供的应用于集成电路的ESD保护电路，其基本构思还可以适应性应用到如图3所示的现有技术中的又一种常见的ESD保护电路，即本申请的又一些实施例所提供的应用于集成电路的ESD保护电路可以如图5所示。
如图5所示的，主ESD保护电路401中还进一步地包括有高压P沟道MOS管，即图5所示的高压(HV)PMOS管T3。该高压P沟道MOS管T3的栅极、源极和体端连接到电源正极，该高压P沟道MOS管T3的漏极连接到主ESD保护电路401中高压N沟道MOS管T1的漏极。
本申请的又一些实施例所提供的应用于集成电路的ESD保护电路也可以如图6所示。如图6所示的，从ESD保护电路403中还进一步地包括有低压P沟道MOS管，即图6所示的低压(LV)PMOS管T4。该低压P沟道MOS管T4的栅极、源极和体端连接到电源正极，该低压P沟道MOS管T4的漏极连接到从ESD保护电路403中低压N沟道MOS管T2的漏极。
本申请的又一些实施例所提供的应用于集成电路的ESD保护电路还可以如图7所示。如图7所示的电路综合了图5所示的主ESD保护电路401中进一步包括的高压P沟道MOS管，即图5所示的高压(HV)PMOS管T3，以及如图6所示的从ESD保护电路403中进一步包括的低压P沟道MOS管，即图6所示的低压(LV)PMOS管T4。
具体地，如图4所示的本申请实施例所提供的ESD保护电路中对所采用NMOS管工作电压的确定以及采用增强型MOS管的构思也同样适应于如图5、图6以及图7所示的ESD保护电路中对NMOS管与PMOS管的选择。
此外，为了使ESD发生时，ESD电流分布更均匀，提高NMOS管的防护能力，在图4所示的高压NMOS管T1的栅极与地之间可以串联一个电阻Rgate。
对于集成电路设计，ESD保护电路的目的就是要避免工作电路(被保护的电路)成为ESD的放电通路而遭到损害，比如芯片设计，应当保证在任意两芯片引脚之间在发生ESD事件时都有适合的低阻旁路(ESD保护电路)将ESD电流泄放。因此，与现有的ESD保护电路在实际应用中类似的，本申请实施例所提供的ESD保护电路在实际的电路设计中，在版图中一般设计在PAD旁，从而保证在ESD发生时，旁路ESD电流，并立即有效地钳位电路电压，其中从ESD保护电路在版图中应当尽量靠近被保护的内部电路，以减小连线的电阻。在工艺制作上，本申请实施例所提供的ESD保护电路可以与被保护的内部电路中能够的器件采用相同的工艺制作，比如采用BCD(Bipolar CMOS DMOS)集成工艺技术。
综上所述，本申请实施例所提供的应用于集成电路的ESD保护电路不仅能够继承现有技术中的ESD保护电路所具备的优点，即可以通过主ESD保护电路泄放大部分的ESD电流以及通过从ESD保护电路钳位电压，防止工作电路由于ESD而受损，并能够在ESD发生时快速响应，同时本申请实施例所提供的ESD保护电路由于在主ESD保护电路中采用了高压MOS管，从而能够利用高压MOS管的电气特性，实现较小的漏电电流，克服现有 技术中的ESD保护电路漏电较大的缺陷，达到降低系统功耗的效果，进而能够更好地满足低压或低功耗系统的应用要求。
以上所描述的仅是本申请所提供的一种应用于集成电路的ESD保护电路的部分优选实施例。应当理解的是，本申请所提供的ESD保护电路并不局限于上述优选实施例，在集成电路设计中，本申请所提供的ESD保护电路能够结合实际的应用需求，产生多种电子元器件的选择情况和电路的实现情况。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (9)

  1. 一种应用于集成电路的静电放电ESD保护电路，其特征在于，包括：主ESD保护电路、电阻和从ESD保护电路；
    所述主ESD保护电路中至少包括高压N沟道金属氧化物半导体场效应MOS管，所述高压N沟道MOS管的栅极、源极和体端连接到地，所述高压N沟道MOS管的漏极连接集成电路的引脚焊盘PAD；
    所述从ESD保护电路中至少包括低压N沟道MOS晶体管，所述低压N沟道MOS管的栅极、源极和体端连接到地，所述低压N沟道MOS管的漏极通过所述电阻连接到所述高压N沟道MOS管的漏极，并连接到所述集成电路内部被保护的电路。
  2. 如权利要求1所述的ESD保护电路，其特征在于，所述高压N沟道MOS管的工作电压高于或等于5V。
  3. 如权利要求1所述的ESD保护电路，其特征在于，所述低压N沟道MOS管的工作电压低于或等于1.8V。
  4. 如权利要求1所述的ESD保护电路，其特征在于，所述高压N沟道MOS管为高压N沟道增强型MOS管；所述低压N沟道MOS管为低压N沟道增强型MOS管。
  5. 如权利要求1所述的ESD保护电路，其特征在于，所述主ESD保护电路中还包括高压P沟道MOS管，所述高压P沟道MOS管的栅极、源极和体端连接到电源正极，所述高压P沟道MOS管的漏极连接到所述高压N沟道MOS管的漏极。
  6. 如权利要求1所述的ESD保护电路，其特征在于，所述从ESD保护电路中还包括低压P沟道MOS管，所述低压P沟道MOS管的栅极、源极和体端连接到电源正极，所述低压P沟道MOS管的漏极连接到所述低压N沟道MOS管的漏极。
  7. 如权利要求1所述的ESD保护电路，其特征在于，所述电阻为阻值量级在百K欧姆范围内的限流电阻。
  8. 如权利要求7所述的ESD保护电路，其特征在于，所述限流电阻为多晶硅电阻或扩散电阻。
  9. 如权利要求1所述的ESD保护电路，其特征在于，所述高压N沟道MOS管的栅极与地之间还串联有电阻。
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