WO2022217560A1 - 集成电路、电子设备及通信装置 - Google Patents

集成电路、电子设备及通信装置 Download PDF

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Publication number
WO2022217560A1
WO2022217560A1 PCT/CN2021/087609 CN2021087609W WO2022217560A1 WO 2022217560 A1 WO2022217560 A1 WO 2022217560A1 CN 2021087609 W CN2021087609 W CN 2021087609W WO 2022217560 A1 WO2022217560 A1 WO 2022217560A1
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Prior art keywords
integrated circuit
unit
coupled
terminal
power supply
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PCT/CN2021/087609
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English (en)
French (fr)
Inventor
于宝亮
莫秉轩
王邦麟
Original Assignee
华为技术有限公司
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Priority to CN202180090402.3A priority Critical patent/CN116783708A/zh
Priority to PCT/CN2021/087609 priority patent/WO2022217560A1/zh
Publication of WO2022217560A1 publication Critical patent/WO2022217560A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present application relates to the technical field of chip electrostatic protection, and in particular, to an integrated circuit, an electronic device and a communication device.
  • Electrostatic discharge is one of the important factors affecting the reliability of integrated circuits.
  • an electrostatic discharge (ESD) circuit is set in the integrated circuit.
  • the ESD circuit is frequently triggered when the partial load circuit unit of the integrated circuit, such as the low noise amplifier (LNA) of the bluetooth (BT) system, switches between the two states of off or on. A larger current is generated, which can reach several hundred milliamps to several amperes. The long-term high current causes the electromigration (EM) effect of the integrated circuit, which seriously affects the reliability of the integrated circuit.
  • LNA low noise amplifier
  • BT bluetooth
  • Embodiments of the present application provide an integrated circuit, an electronic device, and a communication device, which are used to improve the reliability of the integrated circuit.
  • an integrated circuit including an electrostatic protection circuit, a clamping unit and a current limiting unit.
  • the first end of the electrostatic protection circuit and the first end of the clamping unit are coupled to the first node.
  • the second terminal of the electrostatic protection circuit is coupled to the I/O terminal of the integrated circuit.
  • the third terminal of the electrostatic protection circuit and the second terminal of the clamping unit are respectively coupled to the ground terminal of the integrated circuit.
  • the first node is coupled to the power supply terminal of the integrated circuit through the current limiting unit.
  • the integrated circuit supplies power to the load circuit of the integrated circuit through the power supply terminal of the integrated circuit.
  • the current limiting unit is not in the discharge path from the I/O terminal to the ground through the clamping unit. Therefore, the setting of the current limiting unit does not affect the discharge of ESD energy at the I/O terminal.
  • the current limiting unit can divide the voltage with the clamping unit to reduce the clamping force.
  • the voltage at both ends of the bit cell reduces the discharge current when the clamp cell is accidentally triggered, thereby reducing the EM effect and improving the reliability of the integrated circuit.
  • the impedance from the power supply terminal to the I/O terminal can be increased, so that the isolation degree from the power supply terminal to the I/O terminal can be significantly improved, thereby reducing the off-chip power supply to the I/O terminal. Coupling noise at the /O terminal.
  • the electrostatic protection circuit may include a first diode unit and a second diode unit.
  • the anode of the first diode unit is coupled to the I/O terminal, and the cathode of the first diode unit is coupled to the first node.
  • the cathode of the second diode unit is coupled to the I/O terminal.
  • the anode of the second diode unit is coupled to the ground of the integrated circuit.
  • the first diode unit is used to conduct positive ESD energy to the clamping unit for discharging
  • the second diode unit is used to conduct negative ESD energy to the ground, so that the I/O terminal can be electrostatically charged protection.
  • first diode unit and the second diode unit may comprise one or more diodes connected in series.
  • the clamping unit may include a first resistance unit, a capacitance unit, an inverter unit, and a first transistor.
  • the first end of the first resistance unit and the first end of the capacitance unit are both coupled to the input end of the inverter unit.
  • the output of the inverter unit is coupled to the gate of the first transistor.
  • the second terminal of the first resistance unit, the power terminal of the inverter unit, and the drain of the first transistor are all coupled to the first node.
  • the second terminal of the capacitor unit, the ground terminal of the inverter unit, and the source of the first transistor are all coupled to the ground terminal of the integrated circuit.
  • the input terminal of the inverter unit has no time to charge, and will maintain a lower voltage.
  • a high voltage is output at the output end of the inverter, and the first transistor will be turned on, thereby discharging the high voltage energy of the first node to protect the integrated circuit.
  • the first resistance unit may include one or more resistors connected in series
  • the capacitor unit may include one or more capacitors connected in series
  • the inverter unit may include one or more inverters connected in series.
  • the integrated circuit may also include a power supply module, such as an LDO.
  • the power supply module is coupled between the power supply terminal of the integrated circuit and the current limiting unit, and is used for supplying power to the load circuit.
  • the LDO has a certain ability to suppress the noise of the off-chip power supply, which can reduce the noise coupled from the off-chip power supply to the I/O terminal.
  • the current limiting unit may include a second resistance unit coupled between the power supply module and the first node.
  • the equivalent capacitance of the second resistance unit and the clamping unit forms a low-pass filter, so that the rising edge speed of the voltage transmitted from the power supply terminal to the first node can be reduced, thereby reducing the possibility of the clamping unit being triggered by mistake.
  • the setting of the second resistance unit can also increase the impedance of the bleeder path from the power supply terminal to the ground through the clamping unit, so as to reduce the bleeder current when the clamping unit is triggered by mistake, and further Improve the reliability of integrated circuits.
  • the impedance between the power supply terminal and the I/O terminal increases from the equivalent impedance of the first diode unit to the sum of the impedances of the first diode unit and the second resistance unit , thereby reducing the noise voltage component coupled to the I/O terminal by the off-chip power supply and reducing the noise at the I/O terminal.
  • the second resistance unit may comprise one or more resistors connected in series.
  • the current limiting unit may include a third diode unit.
  • the cathode of the third diode unit is coupled to the first node.
  • the anode of the third diode unit is coupled to the power supply module.
  • the third diode unit clamps the voltage of the first node at the difference between the power supply voltage of the power supply terminal and the turn-on voltage drop of the third diode unit, so as to reduce the voltage across the clamping unit, thereby reducing the voltage across the clamping unit.
  • the discharge current is reduced, thereby reducing the EM effect and ensuring the reliability of the integrated circuit.
  • the impedance between the power supply terminal and the I/O terminal increases from the equivalent impedance of the first diode unit to the first diode unit and the third diode unit The sum of the equivalent impedance of , thereby reducing the noise voltage component coupled to the I/O terminal from the off-chip power supply, and reducing the noise at the I/O terminal.
  • the integrated circuit may further include a fourth diode unit.
  • the cathode of the fourth diode unit is coupled with the power supply terminal of the integrated circuit.
  • the anode of the fourth diode unit is coupled to the ground of the integrated circuit.
  • the third diode unit is multiplexed, so that the third diode unit is used to conduct positive ESD energy to the clamping unit for discharging, and the fourth diode unit is set to conduct negative ESD energy to ground, thereby forming electrostatic protection for the power supply terminal or the output terminal of the power supply module.
  • the current limiting unit may further include a third resistance unit.
  • the third resistance unit is connected in parallel with the third diode unit.
  • the third resistance unit is provided, which can boost the cathode bias voltage of the first diode unit to the power supply voltage of the power supply terminal or the output voltage of the power supply module.
  • the increase of the cathode bias voltage of the first diode unit reduces the junction capacitance of the first diode unit, that is, the capacitive load is reduced, so that the integrated circuit can be suitable for high frequency scenarios.
  • the power supply module has a power-on state and a power-off state.
  • the switching time of the power supply module between the power-off state and the power-on state is less than 25 microseconds. That is to say, this solution can improve the reliability of integrated circuits that require power-on time within 25 microseconds.
  • an integrated circuit in a second aspect, includes: an electrostatic protection circuit, a clamping unit and a current limiting unit.
  • the first end of the electrostatic protection circuit and the first end of the clamping unit are coupled to the first node.
  • the second end of the electrostatic protection circuit is coupled with the power supply end of the integrated circuit.
  • the third terminal of the electrostatic protection circuit and the second terminal of the clamping unit are respectively coupled to the ground terminal of the integrated circuit.
  • the first node is coupled to the power supply terminal of the integrated circuit through the current limiting unit.
  • the integrated circuit supplies power to the load circuit of the integrated circuit through the power supply terminal of the integrated circuit.
  • the integrated circuit is coupled with the power supply terminal outside the integrated circuit through the power supply terminal of the integrated circuit.
  • the integrated circuit is used for ESD protection of the power supply terminal.
  • the first node also has the problem of rapid power-on, which causes the false triggering of the clamping unit.
  • the integrated circuit also sets a current limiting unit between the first node and the power supply terminal, and divides the voltage through the current limiting unit and the clamping unit to reduce the voltage across the clamping unit, thereby reducing the error of the clamping unit. The discharge current during triggering reduces the EM effect and ensures the reliability of the integrated circuit.
  • the electrostatic protection circuit may include a fifth diode unit and a sixth diode unit.
  • the anode of the fifth diode unit is coupled to the power supply terminal of the integrated circuit, and the cathode of the fifth diode unit is coupled to the first node.
  • the cathode of the sixth diode unit is coupled to the power supply terminal of the integrated circuit, and the anode of the sixth diode unit is coupled to the ground terminal of the integrated circuit.
  • the fifth diode unit is used to conduct positive ESD energy to the clamping unit for discharging
  • the sixth diode unit is used to conduct negative ESD energy to the ground, so that the power supply terminal can be protected from static electricity.
  • the clamping unit may include a first resistance unit, a capacitance unit, an inverter unit, and a first transistor.
  • the first end of the first resistance unit and the first end of the capacitance unit are both coupled to the input end of the inverter unit.
  • the output of the inverter unit is coupled to the gate of the first transistor.
  • the second terminal of the first resistance unit, the power terminal of the inverter unit, and the drain of the first transistor are all coupled to the first node.
  • the second terminal of the capacitor unit, the ground terminal of the inverter unit, and the source of the first transistor are all coupled to the ground terminal of the integrated circuit.
  • the integrated circuit may also include a power supply module, such as an LDO.
  • the power supply module is coupled between the power supply terminal of the integrated circuit and the current limiting unit.
  • the LDO has a certain ability to suppress the noise of the off-chip power supply, which can reduce the noise coupled from the off-chip power supply to the I/O terminal.
  • the power supply module has a power-on state and a power-off state.
  • the switching time of the power supply module between the power-off state and the power-on state is less than 25 microseconds. That is to say, this solution can improve the reliability of integrated circuits that require power-on time within 25 microseconds.
  • the current limiting unit may include a fourth resistance unit coupled between the power supply module and the first node. And the fourth resistance unit is connected in parallel with the fifth diode unit.
  • the fifth diode unit is multiplexed as the electrostatic protection circuit and the current limiting unit of the power supply end or the output end of the power supply module, that is, the current limiting unit includes the fifth diode unit and the fourth resistance unit connected in parallel. Therefore, for the technical effect of this solution, reference may be made to the technical effect of the relevant part of the integrated circuit described in the first aspect, and details are not repeated here.
  • an integrated circuit in a third aspect, includes the integrated circuit described in any one of the first aspect or the second aspect.
  • the integrated circuit also includes a radio frequency receive channel.
  • the RF receive channel includes a low noise amplifier, a first mixer, a first filter and an analog-to-digital converter coupled in sequence.
  • the load circuit described in the first aspect or the second aspect includes one or more of a low noise amplifier, a first mixer, a first filter and an analog-to-digital converter.
  • the integrated circuit further includes a radio frequency transmission channel.
  • the radio frequency transmission channel includes a digital-to-analog converter, a second filter, a second mixer and a power amplifier coupled in sequence.
  • the load circuit of the first aspect or the second aspect further includes one or more of a digital-to-analog converter, a second filter, a second mixer, and a power amplifier.
  • an electronic device in a fourth aspect, includes a circuit board, and further includes the integrated circuit described in any one of the first aspect, or the integrated circuit described in any one of the second aspect.
  • a communication device in a fifth aspect, includes a first system and a second system. Wherein, both the first system and the second system include the integrated circuit according to any one of the first aspect, or the integrated circuit according to any one of the second aspect.
  • the integrated circuit supplies power to the load circuit of the first system and the load circuit of the second system respectively through the power supply terminal of the integrated circuit.
  • the first system is a WiFi system
  • the second system is a Bluetooth system
  • FIG. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram 1 of the architecture of a chip provided by an embodiment of the present application.
  • FIG. 3 is a second schematic diagram of the architecture of a chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a functional circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an electrostatic integrated circuit in a possible implementation manner provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram 1 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a clamping unit according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another clamping unit provided by an embodiment of the present application.
  • FIG. 9 is a second schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 10 is a comparison diagram of a transfer function curve provided by an embodiment of the present application.
  • FIG. 11 is a comparison diagram 1 of a discharge current curve provided by an embodiment of the application.
  • FIG. 12 is a schematic diagram 3 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 13 is a comparison diagram of a transfer function curve provided by an embodiment of the present application.
  • FIG. 2 is a comparison diagram of a transfer function curve provided by an embodiment of the present application.
  • FIG. 14 is a comparison diagram of a discharge current curve provided by an embodiment of the present application.
  • FIG. 2 is a comparison diagram of a discharge current curve provided by an embodiment of the present application.
  • FIG. 15 is a fourth schematic diagram of an electrostatic integrated circuit provided by an embodiment of the application.
  • FIG. 16 is a schematic diagram 5 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 17 is a sixth schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 18 is a seventh schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • the communication device may be a device with fast power-on requirements and/or low noise requirements, for example, a communication device with a bluetooth (BT) system.
  • BT bluetooth
  • the internal part of the The module will switch quickly between the two states of off and on, which requires that the power supply of this module also needs to follow the switch.
  • the power supply of the BT system is required to switch quickly, that is, to have a fast power-on requirement.
  • a communication device with a WiFi system which has low noise requirements.
  • a communication device that integrates a first system (eg, a WiFi system) with a low noise requirement and a second system (eg, a BT system) with a fast power-on requirement.
  • a first system eg, a WiFi system
  • a second system eg, a BT system
  • the first system and the second system share a power management unit, which needs to meet the requirements of low noise and fast power-on at the same time.
  • the communication device may include an application subsystem, a memory, a massive storage, a digital signal processing subsystem, a radio frequency integrated circuit (RFIC), a radio frequency front-end (radio frequency integrated circuit), and a radio frequency integrated circuit (RFIC).
  • RFIC radio frequency integrated circuit
  • RFFE radio frequency front end
  • ANT antennas
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the transmit path
  • Rx represents the receive path
  • different numbers represent different paths.
  • FBRx represents the feedback receiving path
  • PRx represents the primary receiving path
  • DRx represents the diversity receiving path.
  • HB means high frequency
  • LB means low frequency, both refer to the relative high and low frequency.
  • BB stands for baseband.
  • the radio frequency integrated circuit can be further divided into the radio frequency receive channel (RF receive path) and the radio frequency transmit channel (RF transmit path).
  • the RF receive channel can receive the RF signal through the antenna, process the RF signal (eg, amplify, filter and down-convert) to obtain the baseband signal, and transmit it to the digital signal processing subsystem.
  • the RF transmit channel can receive the baseband signal from the digital signal processing subsystem, perform RF processing (such as up-conversion, amplification and filtering) on the baseband signal to obtain the RF signal, and finally radiate the RF signal into space through the antenna.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer (mixer), a local oscillator (LOO) ), filters and other electronic devices, which can be integrated into one or more chips as required. Antennas can also sometimes be considered part of the RF subsystem.
  • LNA low noise amplifier
  • PA power amplifier
  • mixer mixer
  • LEO local oscillator
  • the digital signal processing subsystem can extract useful information or data bits from the baseband signal, or convert the information or data bits into the baseband signal to be transmitted. These information or data bits may be data representing user data or control information such as voice, text, video, etc.
  • a digital signal processing subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding.
  • the digital signal processing subsystem is generally integrated into one or more chips, and the chip integrating the digital signal processing subsystem is generally called a baseband intergreted circuit (BBIC).
  • BBIC baseband intergreted circuit
  • the radio frequency signal is an analog signal
  • the signal processed by the digital signal processing subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the communication device.
  • the analog-to-digital conversion device includes an analog-to-digital converter (ADC) that converts an analog signal to a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal to an analog signal.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the analog-to-digital conversion device may be arranged in the digital signal processing subsystem, or may be arranged in the radio frequency subsystem.
  • the application subsystem can be used as the main control system or main computing system of the communication device to run the main operating system and application programs, manage the hardware and software resources of the entire communication device, and provide users with a user interface.
  • the application subsystem may include one or more processing cores.
  • the application subsystem may also include driver software related to other subsystems (eg, digital signal processing subsystem).
  • the digital signal processing subsystem may also include one or more processing cores, as well as hardware accelerators (HACs) and caches.
  • HACs hardware accelerators
  • the radio frequency subsystem may include an independent antenna, an independent radio frequency front end (RF front end, RFFE) device, and an independent radio frequency chip.
  • a radio frequency chip is also sometimes referred to as a receiver, transmitter, or transceiver.
  • Antennas, RF front-end devices, and RF chips can all be manufactured and sold separately.
  • the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, some devices belonging to the radio frequency front-end are integrated into the radio frequency chip, and even the antenna and the radio frequency front-end device are integrated into the radio frequency chip, and the radio frequency chip can also be called a radio frequency antenna module or an antenna module.
  • the digital signal processing subsystem may be used as an independent chip, and the chip may be called a modem chip.
  • the hardware components of the digital signal processing subsystem can be manufactured and sold in units of modem chips. Modem chips are also sometimes called baseband chips or baseband processors.
  • the digital signal processing subsystem can also be further integrated in the SoC chip, and the SoC chip is manufactured and sold as a unit.
  • the components and subsystems in the communication device shown in FIG. 1 may be integrated into one SoC chip, and manufactured and sold in units of SoC chips.
  • the digital signal processing subsystem and the radio frequency subsystem can be integrated into a SoC chip, and the software components of the digital signal processing subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be obtained from other non-easy-to-use components after the chip leaves the factory.
  • the SoC chip can be called a transceiver chip.
  • FIG. 2 is a schematic structural diagram 1 of a chip provided by an embodiment of the present application. It should be understood that the chips shown in FIG. 2 may be the chips involved in the communication device shown in FIG. 1 . For example, radio frequency chips, transceiver chips, baseband processor chips, etc. For another example, the chip in FIG. 2 may be one of one or more chips integrated with each electronic device in the radio frequency subsystem.
  • the chip includes an integrated circuit 01, and may also include a package substrate (not shown in the figure).
  • the integrated circuit 01 includes an input/output terminal (I/O) (hereinafter referred to as I/O terminal), a power terminal VCC, a ground terminal GND, and a power terminal VCC coupled to the ground terminal GND. between the electrostatic integrated circuit 10 and the functional circuit 20 . It should be understood that although FIG. 2 shows only one I/O terminal, the integrated circuit 01 may include two or more I/O terminals.
  • the functional circuit 20 is composed of one or more load circuits coupled to realize the basic functions of the integrated circuit 01 .
  • the functional circuit 20 is coupled with the external device through the I/O terminal, receives and processes the signal transmitted by the external device, and/or processes and transmits the signal to the external device.
  • the integrated circuit 01 is coupled with a power supply terminal outside the integrated circuit (eg, an output terminal of an off-chip power supply) through the power supply terminal VCC to obtain a power supply voltage and supply power to the functional circuit 20 . Since both the I/O terminal and the power terminal VCC need to be led off-chip, the I/O terminal and the power terminal VCC usually require electrostatic protection.
  • the electrostatic integrated circuit 10 is used for electrostatic protection for the I/O terminal and/or the power terminal VCC, so as to prevent the static electricity entering the I/O terminal and/or the power terminal VCC from damaging the functional circuit 20 .
  • the electrostatic integrated circuit 10 when the integrated circuit 01 works normally, the electrostatic integrated circuit 10 is not triggered to be turned on, and the functional circuit 20 can work normally under the power supply voltage of the power supply terminal VCC.
  • the electrostatic integrated circuit 10 is triggered and turned on, and the ESD energy is released to the ground, so as to prevent the functional circuit 20 from being damaged by excessive voltage and ensure the normal operation of the functional circuit 20 .
  • FIG. 3 is a second schematic structural diagram of a chip provided by an embodiment of the present application.
  • the integrated circuit 01 of the chip may further include a power supply module for converting the power supply of the power supply terminal VCC into the power supply voltage or current required by the load circuit .
  • the power supply module may be a low dropout regulator (low dropout regulator, LDO).
  • LDO low dropout regulator
  • the power supply module is described as an LDO.
  • the electrostatic integrated circuit 10 and the functional circuit 20 are coupled to the power supply terminal VCC through the LDO.
  • the LDO has a certain ability to suppress the noise of the off-chip power supply, which can reduce the noise coupled to the I/O terminal.
  • the off-chip power supply can provide the power supply terminal VCC with a power supply voltage with a normal power-on speed. . After the power supply voltage is processed by the LDO, the output voltage Vout that meets the fast power-on requirement can be provided.
  • the power supply module may also be a direct current to direct current converter (DCDC).
  • DCDC direct current to direct current converter
  • FIG. 4 is a schematic diagram of a functional circuit provided by an embodiment of the present application.
  • the functional circuit 20 includes a radio frequency transmitting channel, a radio frequency receiving channel, and a digital signal processing unit. It should be understood that although FIG. 4 has only one radio frequency receiving channel and one radio frequency transmitting channel, the functional circuit 20 may include two or more radio frequency transmitting channels and radio frequency receiving channels.
  • the RF receive channel is generally used to process the received RF signal into an intermediate frequency signal.
  • the RF transmission channel is generally used to process the intermediate frequency signal into the transmitted RF signal.
  • the RF receive channel may include LNA, mixer, local oscillator, filter and ADC.
  • the LNA is used to send the amplified radio frequency signal to the mixer, and the mixer mixes the amplified radio frequency signal with the local oscillator signal LO_Rx provided by the local oscillator, and obtains an intermediate frequency signal after mixing.
  • the IF signal is filtered and supplied to the ADC.
  • the ADC converts the analog signal into a digital signal and sends it to the digital signal processing unit.
  • the RF transmit channel may include DACs, filters, mixers, local oscillators (not shown) and PAs.
  • the DAC converts the digital signal output by the digital signal processing unit into an analog signal and sends it to the filter, and the filter sends the filtered signal to the mixer.
  • the mixer mixes the filtered analog signal and the local oscillator signal LO_Tx provided by the local oscillator into a radio frequency signal, and the PA then amplifies the power of the radio frequency signal.
  • the input end of the LNA is coupled to one I/O end of the integrated circuit 01, and the radio frequency signal is received from the antenna through the I/O end; the output end of the PA is coupled to the other end of the integrated circuit 01.
  • the load circuit of the functional circuit 20 may include some or all of the components in the radio frequency receiving channel, and may also include some or all of the components in the radio frequency transmitting channel, and may also be a combination of the two.
  • the load circuit of the functional circuit 20 is coupled to the power supply terminal VCC shown in FIG. 2 , or the LDO shown in FIG. 3 .
  • FIG. 5 is a schematic diagram of an electrostatic integrated circuit in a possible implementation manner.
  • ESD electrostatic discharge
  • the positive ESD energy entering the I/O terminal passes through the diode D1, and will quickly pull up the first
  • the voltage of a node X1 triggers the clamping unit 11 to discharge the positive ESD energy to the ground; the negative ESD energy entering the I/O terminal is directly conducted to the ground through the diode D2.
  • the discharge process is similar when an ESD event occurs at the power supply terminal VCC, which will not be repeated here.
  • the noise of the off-chip power supply will enter the electrostatic integrated circuit 10 through the power supply terminal VCC, and pass through the diode D1 and the diode D1. After D2 is divided, it is coupled to the I/O terminal, thereby affecting the signal-to-noise ratio of the I/O signal at the I/O terminal. If the electrostatic integrated circuit 10 shown in FIG. 5 is applied to a communication device with a low noise requirement, it obviously cannot meet the low noise requirement.
  • the electrostatic integrated circuit 10 shown in FIG. 5 is applied to a communication device with fast power-on requirements, for example, the power terminal VCC in FIG. 2 or the output terminal of the LDO in FIG. 3 is in a power-off state (ie, not powered on).
  • the switching time between the power-on state) and the power-on state is less than 25 microseconds, such as 15 microseconds, 10 microseconds, and the rapid power-on of the power supply terminal VCC or the output terminal of the LDO will also quickly pull The voltage of the first node X1 is raised, thereby triggering the clamping unit 11 by mistake to discharge the current.
  • the clamping unit 11 Since the power terminal VCC or the output terminal of the LDO will frequently switch between the power-on state and the power-off state, the clamping unit 11 will be frequently triggered to generate a large current.
  • the long-term frequent high current causes the electrostatic integrated circuit 10 to generate EM effects, which seriously affects the reliability of the electrostatic integrated circuit 10 .
  • the present application provides an electrostatic integrated circuit, which is applied to the chip shown in FIG. 2 or FIG. 3 to replace the electrostatic integrated circuit 10 shown in FIG. 5 .
  • the chip shown in FIG. 3 is taken as an example below, and the electrostatic integrated circuit provided by the embodiments of the present application is described in detail with reference to FIGS. 6 to 18 .
  • FIG. 6 is a schematic diagram 1 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the electrostatic integrated circuit 10 includes a clamping unit 11 , an electrostatic protection circuit 12 , and a current limiting unit 13 .
  • the first end of the electrostatic protection circuit 12 and the first end of the clamping unit 11 are coupled to the first node X1.
  • the second terminal of the electrostatic protection circuit 12 is coupled to the I/O terminal.
  • the voltage of the first node X1 is quickly pulled up to couple the positive ESD energy to the first node X1.
  • the third terminal of the electrostatic protection circuit 12 is coupled to the ground terminal GND for discharging negative ESD energy to the ground when a negative ESD event occurs at the I/O terminal.
  • the second terminal of the clamping unit 11 is coupled to the ground terminal GND, and is used for coupling the positive ESD energy of the electrostatic protection circuit 12 to the first node X1, and the positive ESD energy is discharged to the ground through the ground terminal GND.
  • the first node X1 is coupled with the output terminal of the LDO through the current limiting unit 11, and further realizes coupling with the power terminal VCC.
  • the current limiting unit 13 is provided between the first node X1 and the output end of the LDO.
  • the impedance from the output end of the LDO to the I/O end is the sum of the impedance of the current limiting unit 13 and the equivalent impedance of the first diode unit 121.
  • the I/O terminal maintains the equivalent impedance of the first diode unit 121 to the ground terminal GND.
  • the noise voltage component coupled to the I/O terminal is reduced, where Z1 is the impedance from the output terminal of the LDO to the I/O terminal, and Z2 is the The impedance from the I/O terminal to the ground terminal GND, Vout is the output voltage of the LDO, and Vi/o is the noise voltage component coupled to the I/O terminal.
  • the setting of the current limiting unit 13 can significantly improve the isolation between the power supply terminal VCC and the I/O terminal, thereby reducing the coupling noise from the off-chip power supply and the LDO to the I/O terminal.
  • the current limiting unit 13 can divide the voltage with the clamping unit 11 to reduce the clamping
  • the voltage at both ends of the unit 11 reduces the discharge current Iout when the clamping unit 11 is triggered by mistake, thereby reducing the EM effect and ensuring the reliability of the electrostatic integrated circuit 10 .
  • the setting position of the current limiting unit 13 does not affect the output of the LDO output terminal to the functional circuit 20 shown in FIG. 3 to output a voltage that meets its fast power-on requirements, that is, the electrostatic integrated circuit 10 shown in FIG. 6 does not affect the functional circuit. 20 was quickly powered up.
  • the current limiting unit 13 is not in the discharge path from the I/O terminal to the ground through the clamping unit 11, therefore, it does not affect the discharge of the ESD energy of the I/O terminal.
  • the electrostatic protection circuit 12 includes a first diode unit 121 and a second diode unit 122 .
  • the anode of the first diode unit 121 is coupled to the I/O terminal, and the cathode of the first diode unit 121 is coupled to the first node X1.
  • the cathode of the second diode unit 122 is coupled to the I/O terminal, and the anode of the second diode unit 122 is coupled to the ground terminal GND.
  • the positive ESD energy entering the I/O terminal will be coupled to the first node X1 through the first diode unit 121, thereby rapidly increasing the voltage of the first node X1.
  • the negative ESD energy entering the I/O terminal will be coupled to the ground terminal GND through the second diode unit 122, and then be conducted to the ground to achieve discharge.
  • the first diode unit 121 and the second diode unit 122 may include one or more diodes connected in series in sequence, which is not limited in this embodiment of the present application. It is assumed that the number of diodes connected in series in the forward direction is N. Diodes connected in series in forward direction means that the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, and so on, the cathode of the N-1th diode is connected to the Nth diode
  • N is a positive integer greater than 2.
  • the anode of the first diode unit 121 and the anode of the second diode unit 122 refer to the anode of the first diode
  • the cathode of the first diode unit 121 and the cathode of the second diode unit 122 are Refers to the cathode of the Nth diode.
  • the clamping unit 11 includes a first resistor unit 111 , a capacitor unit 112 , an inverter unit 113 , and a first transistor 114 .
  • the first end of the first resistance unit 111 and the first end of the capacitance unit 112 are both coupled to the input end of the inverter unit 113 .
  • the output of the inverter unit 113 is coupled to the gate of the first transistor 114 .
  • the second terminal of the first resistance unit 111, the power terminal of the inverter unit 113, and the drain of the first transistor 114 are all coupled to the first node X1.
  • the second terminal of the capacitor unit 112, the ground terminal of the inverter unit 113, and the source of the first transistor 114 are all coupled to the ground terminal GND of the integrated circuit.
  • the first resistance unit 111 may include one or more resistors connected in series in sequence
  • the capacitor unit 112 may include one or more capacitors connected in series in sequence
  • the inverter unit 113 may include one or more than one, and the number is an odd number inverters in series.
  • each unit shown in FIG. 6 constitutes the minimum component unit of the clamping unit 11
  • the clamping unit 11 may further include other components, such as latches, which are not limited in this embodiment of the present application.
  • FIG. 7 is a schematic diagram of a clamping unit provided by an embodiment of the present application.
  • the clamping unit 11 includes a resistor R1 , a capacitor C1 , an inverter composed of a transistor PM1 and a transistor NM1 , and a transistor NM2 .
  • the gate of the transistor PM1 and the gate of the transistor NM1 are coupled to form the input terminal of the inverter
  • the drain of the transistor PM1 and the drain of the transistor NM1 are coupled to form the input terminal of the inverter
  • the source of the transistor PM1 forms an inverted phase
  • the power supply terminal of the inverter, the source of the transistor NM1 forms the ground terminal of the inverter.
  • the first end of the resistor R1, the first end of the capacitor C1, and the input end of the inverter are coupled to the second node X2.
  • the second terminal of the resistor R1, the power terminal of the inverter, and the drain of the transistor NM2 are all coupled to the first node X1.
  • the second terminal of the capacitor C1, the ground terminal of the inverter, and the source of the transistor NM2 are all coupled to the ground terminal GND.
  • the working principle of the clamping unit 11 shown in FIG. 7 is as follows: the resistor R1 and the capacitor C1 form a low-pass filter.
  • the second node X2 can follow the charging, and the second node X2 will maintain a relatively high voltage. high voltage.
  • a low voltage is output at the third node X3 (ie, the output terminal of the inverter). At this time, the transistor NM2 is not turned on.
  • the second node X2 When the voltage of the first node X1 rises rapidly and the second node X2 has no time to charge, the second node X2 will maintain a lower voltage. After inversion by the inverter, a high voltage is output at the third node X3 (ie, the output terminal of the inverter). At this time, the transistor NM2 will be turned on, thereby discharging the ESD energy of the first node X1.
  • Another possible implementation solution is to exchange the positions of the first resistance unit 111 and the capacitance unit 112 , and the number of inverters in the inverter unit 113 is an even number, thereby obtaining the clamping unit.
  • FIG. 8 is a schematic structural diagram of another clamping unit provided by an embodiment of the present application.
  • the difference between the clamping unit 11 and the clamping unit 11 shown in FIG. 7 is:
  • the clamping unit 11 includes two inverters, which are the first inverter composed of the transistor PM1 and the transistor NM1, and the first inverter composed of the transistor PM2 and the transistor NM3. the second inverter.
  • the working principle of the clamping unit 11 shown in FIG. 8 is as follows: the resistor R1 and the capacitor C1 form a high-pass filter. When the voltage of the first node X1 rises normally, the voltage of the second node X2 is discharged through the resistor R1, thereby maintaining a low voltage voltage. After passing through the two-stage inverter, a low voltage is output at the third node X3. At this time, the transistor NM2 is not turned on.
  • the second node X2 When the voltage of the first node X1 rises rapidly, the second node X2 can follow the charging, and the second node X2 is pulled to a high voltage. After passing through the two-stage inverter, a high voltage is output at the third node X3. At this time, the transistor NM2 will be turned on, thereby discharging the ESD energy of the first node X1.
  • FIG. 9 is a second schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the current limiting unit 13 includes a second resistance unit 131 .
  • the first end of the second resistance unit 131 is coupled to the first node X1, and the second end of the second resistance unit 131 is coupled to the output end of the LDO.
  • the second resistance unit 131 may include one or more resistors connected in series in sequence, which is not limited in this embodiment of the present application.
  • the noise voltage component coupled to the I/O terminal Vi/o Z2/(Z1+Z2)*Vout, in the electrostatic integrated circuit 10 shown in FIG. 9, Z2 is determined by the second diode unit 122, and Z1 is determined by the first two The electrode tube unit 121 and the second resistance unit 131 are determined. It can be seen that the setting of the second resistance unit 131 increases Z1, thereby reducing the noise voltage component coupled to the I/O terminal and reducing the noise at the I/O terminal.
  • Fig. 10 shows a comparison diagram of the transfer function curve from the output end of the LDO to the I/O end in the electrostatic integrated circuit 10 shown in Fig. 5 and Fig. 9 .
  • Arch1 is the transfer function curve of the electrostatic integrated circuit 10 shown in FIG. 5
  • Arch2 is the transfer function curve of the electrostatic integrated circuit 10 shown in FIG. 9 .
  • the ordinate is the transfer function
  • the abscissa is the frequency.
  • the transfer function is the ratio of the Laplace transform of the interference signal received at the I/O end to the Laplace transform of the interference signal at the output end of the LDO. The higher the amplitude of the transfer function, the noise coupled to the I/O end. bigger.
  • the magnitude of the transfer function of the electrostatic integrated circuit 10 shown in FIG. 9 is higher than that of the electrostatic integrated circuit 10 shown in FIG. noise to the I/O terminals.
  • the equivalent capacitance of the second resistance unit 131 and the clamping unit 11 forms a low-pass filter, so that the transmission of the output end of the LDO to the first node X1 can be reduced.
  • the rising edge speed of the voltage reduces the possibility of the clamping unit 11 being triggered by mistake.
  • the setting of the second resistance unit 131 can increase the impedance of the bleeder path from the output end of the LDO to the ground through the clamping unit 11, thereby reducing the false triggering of the clamping unit 11.
  • the discharge current Iout is increased, thereby improving the reliability of the electrostatic integrated circuit 10 .
  • FIG. 11 shows a comparison diagram of the discharge current curves of the electrostatic integrated circuit 10 shown in FIGS. 5 and 9 .
  • Vout is the output voltage of the LDO
  • Iout_Arch1 is the discharge current curve of the electrostatic integrated circuit 10 shown in FIG. 5
  • Iout_Arch2 is the discharge current curve of the electrostatic integrated circuit 10 shown in FIG. 9 .
  • Iout_Arch1 has a peak current (outlined by a dashed circle)
  • Iout_Arch2 is relatively gentle, that is, the second resistance unit 131 is used as the current limiting unit 13, which can reduce the error of the clamping unit 11.
  • the bleeder current Iout when triggered.
  • the discharge current Iout can be reduced by increasing the impedance of the second resistance unit 131 .
  • the impedance of the second resistance unit 131 should not be too large, because when the impedance of the second resistance unit 131 is too large, a small current fluctuation will lead to a large voltage fluctuation, so that the clamping unit 11 cannot be reliably provided. of DC bias.
  • the discharge current Iout cannot be reduced by continuously increasing the impedance of the second resistance unit 131, that is, the electrostatic integrated circuit 10 shown in FIG. 9 is suitable for the electrostatic integrated circuit 10 The required supply voltage is lower.
  • FIG. 12 is a schematic diagram 3 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the difference between the electrostatic integrated circuit 10 and the electrostatic integrated circuit 10 shown in FIG. 9 is that the electrostatic integrated circuit 10 shown in FIG.
  • the second resistor unit 131 is replaced with the third diode unit 132 .
  • the cathode of the third diode unit 132 is coupled to the first node X1; the anode of the third diode unit 132 is coupled to the output end of the LDO. It should be understood that the third diode unit 132 may include one or more diodes connected in series in sequence, which is not limited in this embodiment of the present application.
  • the noise voltage component coupled to the I/O terminal Vi/o Z2/(Z1+Z2)*Vout, in the electrostatic integrated circuit 10 shown in FIG. 12, Z2 is determined by the second diode unit 122, and Z1 is determined by the first two The electrode tube unit 121 and the third diode unit 132 are determined. It can be seen that the arrangement of the third diode unit 132 increases Z1, thereby reducing the noise voltage component coupled to the I/O terminal.
  • Fig. 13 shows a comparison diagram of the transfer function curves between the output end of the LDO and the I/O end in the electrostatic integrated circuit 10 shown in Figs. 5 and 12 .
  • Arch3 is the transfer function curve of the electrostatic integrated circuit 10 shown in FIG. 5
  • Arch4 is the transfer function curve of the electrostatic integrated circuit 10 shown in FIG. 13 . It can be seen from the figure that the magnitude of the transfer function of the electrostatic integrated circuit 10 shown in FIG. 13 is higher than that of the electrostatic integrated circuit 10 shown in FIG. Noise coupled from the power supply to the I/O terminals.
  • the third diode unit 132 clamps the voltage of the first node X1 to the difference between the output voltage Vout of the LDO and the on-voltage drop of the third diode unit 132 , compared with the electrostatic integrated circuit 10 shown in FIG. 5 , the voltage of the first node X1 is reduced, thereby reducing the discharge current Iout when the clamping unit 11 is triggered by mistake, thereby reducing the EM effect and improving the electrostatic integrated circuit. 10 reliability.
  • FIG. 14 shows a comparison diagram of the discharge current curve of the electrostatic integrated circuit 10 shown in FIG. 5 and FIG. 12 .
  • Vout is the output voltage of the LDO
  • Iout_Arch3 is the discharge current curve of the electrostatic integrated circuit 10 shown in FIG. 5
  • Iout_Arch4 is the discharge current curve of the electrostatic integrated circuit 10 shown in FIG. 14 .
  • the on-voltage drop across the third diode unit 132 is stable and constant. Therefore, compared with the second resistance unit 131 shown in FIG. That is, the third diode unit 132 can provide a reliable DC bias for the clamping unit 11 .
  • the turn-on voltage drop can be increased by increasing the number of diodes in the third diode unit 132, so as to clamp the voltage of the first node X1 to a smaller voltage, So as to achieve the purpose of reducing the discharge current Iout.
  • the electrostatic integrated circuit 10 shown in FIG. 12 is also applicable to the scenario where the output voltage Vout of the LDO is low. It should be noted that, in order to prevent the anode of the third diode unit 132 from being in a high resistance state, no matter whether the output voltage Vout of the LDO is high or low, it may be less than the on-voltage drop of the third diode unit 132 .
  • the output end of the LDO when the output end of the LDO needs to be led out of the chip, the output end of the LDO also needs to be ESD protected.
  • the output end of the LDO also needs charged device model (CDM) protection.
  • CDM charged device model
  • the positive ESD energy entering the output end of the LDO of the electrostatic integrated circuit 10 can be discharged to the ground through the third diode unit 132 through the clamping unit 11 . But when negative ESD energy enters, there is no venting path.
  • FIG. 15 is a fourth schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the difference between the electrostatic integrated circuit 10 and the electrostatic integrated circuit 10 shown in FIG. 12 is that a fourth diode unit 141 is added to the electrostatic integrated circuit 10 shown in FIG. 15 .
  • the cathode of the fourth diode unit 141 is coupled to the power supply terminal VCC of the electrostatic integrated circuit 10 ; the anode of the fourth diode unit 141 is coupled to the ground terminal GND of the electrostatic integrated circuit 10 .
  • the cathode of the fourth diode unit 141 is coupled to the output terminal of the LDO.
  • the fourth diode unit 141 may include one or more diodes connected in series in a forward sequence, which is not limited in this embodiment of the present application.
  • the output end of the LDO is protected from static electricity.
  • the positive ESD energy enters the output end of the LDO of the electrostatic integrated circuit 10
  • it will be coupled to the first node X1 through the third diode unit 132, thereby rapidly pulling up the voltage of the first node X1, and passing through the clamping unit 11 vented to the ground.
  • negative ESD energy enters the output end of the LDO of the electrostatic integrated circuit 10
  • it will be directly discharged to the ground through the fourth diode unit 141 to protect the output end of the LDO and avoid damage to the internal functional circuit.
  • the clamping unit 11 may also be separated set up.
  • the capacitive load on the I/O side affects its operating frequency. In high frequency scenarios, it is hoped that the capacitive load on the I/O side should be as small as possible.
  • the addition of the third diode unit 132 will cause the cathode bias voltage of the first diode unit 121 to drop, thereby causing the first diode unit 121 junction capacitance increases. It can be seen that the electrostatic integrated circuit 10 shown in FIG. 12 and FIG. 15 is not suitable for high frequency scenarios.
  • FIG. 16 is a schematic diagram 5 of an electrostatic integrated circuit provided by an embodiment of the present application. As shown in FIG. 16 , the difference between the electrostatic integrated circuit 10 and the electrostatic integrated circuit 10 shown in FIG. 12 is that a third resistance unit 133 is added to the electrostatic integrated circuit 10 shown in FIG. 16 .
  • the third resistor unit 133 is connected in parallel with the third diode unit 132 . It should be understood that the third resistor unit 133 may include one or more resistors connected in series in sequence, which is not limited in this embodiment of the present application.
  • the electrostatic integrated circuit 10 further includes a fourth diode unit 141 .
  • the clamping unit 11 in the normal working state, the clamping unit 11 is not turned on, and the discharge current Iout is zero. Therefore, by setting the third resistance unit 133 , the voltage of the first diode unit 121 can be reduced. Cathode bias voltage, boosted to LDO output voltage Vout.
  • the cathode bias voltage of the first diode unit 121 is the difference between the output voltage Vout of the LDO and the on-voltage drop of the third diode unit 132 .
  • the provision of the third resistance unit 133 increases the cathode bias voltage of the first diode unit 121 , thereby reducing the first diode unit 121 junction capacitance. It can be seen that the electrostatic integrated circuit 10 shown in FIG. 16 may be suitable for high frequency scenarios.
  • electrostatic integrated circuit 10 shown in FIG. 16 can also be applied to low frequency scenarios.
  • the noise isolation effects of the electrostatic integrated circuit 10 shown in FIG. 16 at low frequencies and high frequencies will be described below.
  • the equivalent capacitance of the diode increases and the equivalent impedance decreases, but the resistance does not change with the frequency. Therefore, at low frequencies, the equivalent impedance of the diode is much larger than that of the resistor unit, and at high frequencies, the equivalent impedance of the diode is much smaller than the resistance.
  • the equivalent impedance of the first diode unit 121 is much larger than that of the second resistance unit 131, and the second resistance unit 131 is negligible. Therefore, the output terminal of the LDO reaches I
  • the impedance of the /O terminal is basically determined by the first diode unit 121 . That is, at low frequencies, the noise isolation of the electrostatic integrated circuit 10 shown in FIG. 9 is similar to that of FIG. 5, but slightly improved. At high frequencies, the equivalent impedance of the first diode unit 121 is much smaller than that of the second resistance unit 131, and the first diode unit 121 can be ignored.
  • the impedance from the output end of the LDO to the I/O end is basically given by The second resistance unit 131 is determined. That is, at high frequencies, the electrostatic integrated circuit 10 shown in FIG. 9 has a better effect on noise isolation than that shown in FIG. 5 .
  • the equivalent impedances of the first diode unit 121 , the second diode unit 122 , and the third diode unit 132 change in equal proportions as the frequency changes. , therefore, the noise voltage component coupled to the I/O terminals is fixed regardless of whether it is high frequency or low frequency. That is, the electrostatic integrated circuit 10 shown in FIG. 12 or FIG. 15 has the same effect of suppressing noise at low frequency and high frequency.
  • the electrostatic integrated circuit 10 shown in FIG. 12 or FIG. 15 has better noise isolation at low frequencies, and the electrostatic integrated circuit 10 shown in FIG. 9 has better noise isolation at high frequencies.
  • a diode unit 121 , a third diode unit 132 , and a third resistance unit 133 are determined.
  • the equivalent impedance of the third diode unit 132 is much larger than that of the third resistance unit 133. Therefore, the total impedance of the third diode unit 132 and the third resistance unit 133 in parallel is substantially determined by the third resistance unit. 133 decision. That is, at low frequencies, the electrostatic integrated circuit 10 shown in FIG. 16 and the electrostatic integrated circuit 10 shown in FIG. 9 have similar isolation degrees to noise.
  • the equivalent impedance of the third diode unit 132 is much smaller than that of the third resistance unit 133. Therefore, the total impedance of the third diode unit 132 and the third resistance unit 133 in parallel is substantially equal to that of the third diode unit 132 and the third resistance unit 133.
  • the electrode tube unit 132 is determined, and the impedance is similar to that of FIG. 12 and FIG. 15 .
  • the addition of the third resistance unit 133 reduces the junction capacitance of the first diode unit 121 , thereby increasing the equivalent impedance of the first diode unit 121 .
  • the addition of the second resistance unit 131 increases the impedance from the output terminal of the LDO to the I/O terminal as a whole, which further increases the noise resistance compared with the electrostatic integrated circuit 10 shown in FIG. 12 and FIG. 15 . of isolation.
  • the voltage of the first node X1 is also clamped at the difference between the output voltage Vout of the LDO and the on-voltage drop of the third diode unit 132 , that is, the voltage of the first node X1 decreases.
  • the discharge current Iout is basically determined by the quotient of the voltage of the first node X1 and the on-resistance of the first transistor 114 in FIG. 6 . Since the voltage of the first node X1 is reduced, the discharge current Iout is reduced, and the limiting effect on the discharge current Iout is similar to the electrostatic integrated circuit 10 shown in FIG. 12 and the electrostatic integrated circuit 10 shown in FIG. 15 .
  • the discharge current Iout basically flows into the clamping unit 11 only through the third resistance unit 133, that is, the discharge current Iout is basically determined by the output voltage Vout of the LDO, and the third resistance unit 133 and the third resistance unit 133.
  • the quotient of the total impedance of the on-resistance of the first transistor 114 in FIG. 6 is jointly determined.
  • the discharge current Iout is reduced, and the limiting effect on the discharge current Iout is similar to that of the electrostatic integrated circuit 10 shown in FIG. 9 .
  • the electrostatic integrated circuit provided by the embodiment of the present application has been described in detail above with reference to FIGS. 6 to 16 , and the I/O terminal is taken as an example.
  • the electrostatic integrated circuit is described in detail.
  • FIG. 17 is a schematic diagram 6 of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the electrostatic integrated circuit 10 includes an electrostatic protection circuit 15 , a clamping unit 11 and a current limiting unit 13 .
  • the first end of the electrostatic protection circuit 15 and the first end of the clamping unit 11 are coupled to the first node X1.
  • the second terminal of the electrostatic protection circuit 15 is coupled to the output terminal of the LDO.
  • the voltage of the first node X1 is quickly pulled up to couple the positive ESD energy to the first node X1.
  • the third terminal of the electrostatic protection circuit 15 is coupled to the ground terminal GND, and is used for discharging the negative ESD energy to the ground when a negative ESD event occurs at the output terminal of the LDO.
  • the second terminal of the clamping unit 11 is coupled to the ground terminal GND, and is used for coupling the positive ESD energy of the electrostatic protection circuit 15 to the first node X1, and the positive ESD energy is discharged to the ground through the ground terminal GND.
  • the specific implementation of the clamping unit 11 may refer to the electrostatic integrated circuit 10 shown in FIG. 6 , which will not be repeated here.
  • the first node X1 is coupled with the output terminal of the LDO through the current limiting unit 11, and further realizes coupling with the power terminal VCC.
  • the power supply voltage provided by the off-chip power supply to the electrostatic integrated circuit 10 through the power supply terminal VCC is regulated by the LDO and then output to the current limiting unit 13 .
  • the current limiting unit 13 can divide the voltage with the clamping unit 11 to reduce the clamping unit. 11, thereby reducing the discharge current Iout when the clamping unit 11 is triggered by mistake, thereby reducing the EM effect and ensuring the reliability of the electrostatic integrated circuit 10.
  • the setting position of the current limiting unit 13 does not affect the output of the LDO output terminal to the functional circuit 20 shown in FIG. 3 to output a voltage that meets its fast power-on requirements, that is, the electrostatic integrated circuit 10 shown in FIG. 17 does not affect the functional circuit. 20 was quickly powered up.
  • the electrostatic protection circuit 15 includes a fifth diode unit 151 and a sixth diode unit 152 .
  • the anode of the fifth diode unit 151 is coupled to the output end of the LDO, and the cathode of the fifth diode unit 151 is coupled to the first node X1.
  • the cathode of the sixth diode unit 152 is coupled to the output terminal of the LDO, and the anode of the sixth diode unit 152 is coupled to the ground terminal GND.
  • the positive ESD energy entering the output end of the LDO will be coupled to the first node X1 through the fifth diode unit 151 , thereby rapidly increasing the voltage of the first node X1 .
  • the negative ESD energy entering the output terminal of the LDO will be coupled to the ground terminal GND through the sixth diode unit 152, and then be conducted to the ground to realize discharge.
  • the fifth diode unit 151 and the sixth diode unit 152 may include one or more diodes connected in series in a forward sequence, which is not limited in this embodiment of the present application.
  • FIG. 18 is a seventh schematic diagram of an electrostatic integrated circuit provided by an embodiment of the present application.
  • the current limiting unit 13 includes a fourth resistance unit 134 .
  • the fifth diode unit 151 is multiplexed into the electrostatic protection circuit and the current limiting unit 13 . Therefore, the electrostatic integrated circuit 10 shown in FIG. 18 is similar to the electrostatic integrated circuit 10 shown in FIG. 16 , and the working process thereof can be referred to, and will not be repeated here.
  • the electrostatic integrated circuit 10 described in any one of FIGS. 6 to 18 is applied to the chip shown in FIG. 2 .
  • the first node X1 of the electrostatic integrated circuit 10 is coupled to the power terminal VCC through the current limiting unit 13 .
  • the off-chip power supply is the power supply voltage output to the current limiting unit 13 of the electrostatic integrated circuit 10 through the power supply terminal VCC.
  • the ESD protection of the power terminal VCC passes through the electrostatic integrated circuit 10 shown in FIGS. 15 to 18 .
  • the electrostatic integrated circuit 10 described in any one of FIG. 6 to FIG. 18 is applied to the chip shown in FIG. 3 , the output end and the power supply end of the LDO are two different terminals, as described in any one of FIGS. 6 to 18 .
  • the power supply terminal VCC can also be used for ESD protection.
  • the present application also provides an electronic device, including a circuit board, and the integrated circuit 01 shown in FIG. 2 or FIG. 3 , wherein, in the integrated circuit 01 shown in FIG. 2 or FIG. 3 , the electrostatic integrated circuit 10 is shown in FIGS. 6 to 3 .
  • the electrostatic integrated circuit 10 of any one of 18.
  • At least one means one or more, and “plurality” means two or more.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • at least one item (a) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple .
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, removable hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请提供一种集成电路、电子设备及通信装置，能够解决集成电路中的ESD电路被频繁触发产生大电流的问题，避免影响集成电路的可靠性。该集成电路中静电防护电路的第一端与钳位单元的第一端耦合于第一节点；静电防护电路的第二端与集成电路的I/O端耦合；静电防护电路的第三端以及钳位单元的第二端分别与集成电路的接地端耦合；第一节点通过限流单元与集成电路的电源端耦合；集成电路通过集成电路的电源端为集成电路的负载电路供电。限流单元可以和钳位单元进行分压，减小钳位单元两端的电压，从而减小钳位单元误触发时的泄放电流，进而降低EM效应，保证集成电路的可靠性。

Description

集成电路、电子设备及通信装置 技术领域
本申请涉及芯片静电防护的技术领域，尤其涉及一种集成电路、电子设备及通信装置。
背景技术
静电放电是影响集成电路可靠性的重要因素之一。为防止静电释放造成集成电路失效，会在集成电路中设置静电防护(electro static discharge，ESD)电路。
但申请人发现，集成电路的部分负载电路单元，如蓝牙(bluetooth，BT)系统的低噪声放大器(low noise amplifier，LNA)，在关闭或打开两个状态之间切换时，ESD电路被频繁触发而产生较大的电流，该电流能够达到几百毫安到几安培。长期的大电流使得集成电路的电迁移(electromigration，EM)效应，严重影响集成电路的可靠性。
发明内容
本申请实施例提供一种集成电路、电子设备及通信装置，用于提高集成电路的可靠性。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种集成电路，包括：静电防护电路、钳位单元和限流单元。静电防护电路的第一端与钳位单元的第一端耦合于第一节点。静电防护电路的第二端与集成电路的I/O端耦合。静电防护电路的第三端以及钳位单元的第二端，分别与集成电路的接地端耦合。第一节点通过限流单元与集成电路的电源端耦合。集成电路通过集成电路的电源端为集成电路的负载电路供电。
应理解，限流单元不在I/O端经钳位单元到地的泄放通路中，因此，限流单元的设置并不影响I/O端的ESD能量的泄放。
该集成电路中，通过在第一节点和电源端之间设置限流单元，当集成电路由于快速上电而误触发钳位单元时，限流单元可以和钳位单元进行分压，减小钳位单元两端的电压，从而减小钳位单元误触发时的泄放电流，进而降低EM效应，提升集成电路的可靠性。此外，通过在第一节点和电源端之间设置限流单元，可以增加电源端到I/O端的阻抗，如此，可以显著提高电源端到I/O端的隔离度，从而减少片外电源到I/O端的耦合噪声。
一种可能的实现方案，静电防护电路可以包括第一二极管单元和第二二极管单元。第一二极管单元的阳极与I/O端耦合，第一二极管单元的阴极与第一节点耦合。第二二极管单元的阴极与I/O端耦合。第二二极管单元的阳极与集成电路的接地端耦合。本方案中，第一二极管单元用于将正ESD能量传导至钳位单元进行泄放，第二二极管单元用于将负ESD能量传导至地，从而能够对I/O端进行静电防护。
可选地，第一二极管单元和第二二极管单元可以包括一个或多个串联的二极管。
一种可能的实现方案，钳位单元可以包括第一电阻单元、电容单元、反相器单元、 以及第一晶体管。第一电阻单元的第一端和电容单元的第一端均耦合至反相器单元的输入端。反相器单元的输出端耦合至第一晶体管的栅极。第一电阻单元的第二端、反相器单元的电源端、第一晶体管的漏极均耦合至第一节点。电容单元的第二端、反相器单元的接地端、第一晶体管的源极均耦合至集成电路的接地端。该钳位单元中，当第一节点的电压迅速上升，反相器单元的输入端来不及充电，将维持较低的电压。经过反相器单元反相后，在反相器的输出端输出高电压，第一晶体管将被导通，从而泄放第一节点的高压能量，以保护集成电路。
可选地，第一电阻单元可以包括一个或多个串联的电阻，电容单元可以包括一个或多个串联的电容，反相器单元可以包括一个或多个串联的反相器。
一种可能的实现方案，集成电路还可以包括供电模块，如LDO。供电模块耦合于集成电路的电源端和限流单元之间，用于为负载电路供电。本方案中，LDO对片外电源的噪声有一定的抑制能力，可以降低片外电源耦合到I/O端的噪声。
可选地，限流单元可以包括第二电阻单元，第二电阻单元耦合于供电模块和第一节点之间。一方面，第二电阻单元和钳位单元的等效电容形成低通滤波器，从而可以降低电源端传输到第一节点的电压的上升沿速度，进而降低钳位单元被误触发的可能性。此外，即使钳位单元被误触发，第二电阻单元的设置，也可以增加电源端经钳位单元到地的泄放通路的阻抗，从而可以降低钳位单元误触发时的泄放电流，进而提高集成电路的可靠性。另一方面，设置第二电阻单元后，电源端到I/O端之间的阻抗由第一二极管单元的等效阻抗增至第一二极管单元和第二电阻单元的阻抗之和，从而降低了片外电源耦合至I/O端的噪声电压分量，减小了I/O端的噪声。
应理解，第二电阻单元可以包括一个或多个串联的电阻。
可选地，限流单元可以包括第三二极管单元。其中，第三二极管单元的阴极与第一节点耦合。第三二极管单元的阳极与供电模块耦合。一方面，第三二极管单元将第一节点的电压钳制在，电源端的电源电压与第三二极管单元的导通压降之差，以降低钳位单元两端的电压，从而在钳位单元被误触发时，减小泄放电流，进而可以降低EM效应，保证集成电路的可靠性。另一方面，设置第三二极管单元后，电源端到I/O端之间的阻抗由第一二极管单元的等效阻抗增至第一二极管单元和第三二极管单元的等效阻抗之和，从而降低了片外电源耦合至I/O端的噪声电压分量，减小了I/O端的噪声。
进一步地，集成电路还可以包括第四二极管单元。其中，第四二极管单元的阴极与集成电路的电源端耦合。第四二极管单元的阳极与集成电路的接地端耦合。本方案中，复用第三二极管单元，使第三二极管单元用于将正ESD能量传导至钳位单元进行泄放，并设置第四二极管单元用于将负ESD能量传导至地，从而形成对电源端或供电模块的输出端的静电防护。
更进一步地，限流单元还可以包括第三电阻单元。第三电阻单元与第三二极管单元并联。本方案中，设置第三电阻单元，可以将第一二极管单元的阴极偏置电压，提升至电源端的电源电压或供电模块的输出电压。第一二极管单元的阴极偏置电压的提升，使得第一二极管单元的结电容降低，即容性负载降低，从而使得该集成电路可适用于高频场景。
一种可能的实现方案中，供电模块具有上电状态和下电状态。供电模块在下电状态和上电状态之间的切换时间小于25微秒。也就是说，本方案可以针对要求上电时间在25微秒内的集成电路，提高其可靠性。
第二方面，提供一种集成电路。该集成电路包括：静电防护电路、钳位单元和限流单元。静电防护电路的第一端与钳位单元的第一端耦合于第一节点。静电防护电路的第二端与集成电路电源端耦合。静电防护电路的第三端以及钳位单元的第二端，分别与集成电路的接地端耦合。第一节点通过限流单元与集成电路的电源端耦合。集成电路通过集成电路的电源端为集成电路的负载电路供电。集成电路通过集成电路的电源端与集成电路外部的供电端耦合。
区别于第一方面的集成电路对I/O端的ESD防护，该集成电路用于对电源端进行ESD防护。应理解，该集成电路中，第一节点同样存在快速上电而引发钳位单元误触发的问题。基于此，该集成电路同样在第一节点和电源端之间设置限流单元，并通过限流单元和钳位单元进行分压，减小钳位单元两端的电压，从而减小钳位单元误触发时的泄放电流，进而降低EM效应，保证集成电路的可靠性。
一种可能的实现方案，静电防护电路可以包括第五二极管单元和第六二极管单元。第五二极管单元的阳极与集成电路的电源端耦合，第五二极管单元的阴极与第一节点耦合。第六二极管单元的阴极与集成电路的电源端耦合，第六二极管单元的阳极与集成电路的接地端耦合。本方案中，第五二极管单元用于将正ESD能量传导至钳位单元进行泄放，第六二极管单元用于将负ESD能量传导至地，从而能够对电源端进行静电防护。
一种可能的实现方案，钳位单元可以包括第一电阻单元、电容单元、反相器单元、以及第一晶体管。第一电阻单元的第一端和电容单元的第一端均耦合至反相器单元的输入端。反相器单元的输出端耦合至第一晶体管的栅极。第一电阻单元的第二端、反相器单元的电源端、第一晶体管的漏极均耦合至第一节点。电容单元的第二端、反相器单元的接地端、第一晶体管的源极均耦合至集成电路的接地端。本方案的技术效果可以参考第一方面所述的集成电路中相关部分的技术效果，此处不再赘述。
一种可能的实现方案，集成电路还可以包括供电模块，如LDO。供电模块耦合于集成电路的电源端和限流单元之间。本方案中，LDO对片外电源的噪声有一定的抑制能力，可以降低片外电源耦合到I/O端的噪声。
一种可能的实现方案中，供电模块具有上电状态和下电状态。供电模块在下电状态和上电状态之间的切换时间小于25微秒。也就是说，本方案可以针对要求上电时间在25微秒内的集成电路，提高其可靠性。
可选地，限流单元可以包括第四电阻单元，第四电阻单元耦合在供电模块和第一节点之间。且第四电阻单元与第五二极管单元并联。本方案中，第五二极管单元复用为电源端或供电模块的输出端的静电防护电路和限流单元，即限流单元包括并联的第五二极管单元和第四电阻单元。因此，该方案的技术效果可以参考第一方面所述的集成电路中相关部分的技术效果，此处不再赘述。
第三方面，提供一种集成电路。该集成电路包括第一方面或第二方面任一项所述的集成电路。该集成电路还包括射频接收通道。该射频接收通道包括依次耦合的低噪 声放大器，第一混频器，第一滤波器和模数转换器。其中，第一方面或第二方面所述的负载电路包括低噪声放大器，第一混频器，第一滤波器和模数转换器中的一个或者多个。
可选地，该集成电路还包括射频发送通道。该射频发送通道包括依次耦合的数模转换器、第二滤波器、第二混频器和功率放大器。第一方面或第二方面所述的负载电路还包括数模转换器、第二滤波器、第二混频器和功率放大器中的一个或多个。
第四方面，提供一种电子设备。该电子设备包括电路板，还包括第一方面任一项所述的集成电路，或第二方面任一项所述的集成电路。
此外，第四方面所述的电子设备的技术效果可以参考第一方面和第二方面所述的集成电路的技术效果，此处不再赘述。
第五方面，提供一种通信装置。该通信装置包括第一系统和第二系统。其中，第一系统及第二系统均包括如第一方面任一项所述的集成电路，或第二方面任一项所述的集成电路。集成电路通过集成电路的电源端，分别为第一系统的负载电路和第二系统的负载电路供电。
可选地，第一系统为WiFi系统，第二系统为蓝牙系统。
此外，第五方面所述的通信装置的技术效果可以参考第一方面和第二方面所述的集成电路的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种通信装置的架构示意图；
图2为本申请实施例提供的芯片的架构示意图一；
图3为本申请实施例提供的芯片的架构示意图二；
图4为本申请实施例提供的一种功能电路示意图；
图5为本申请实施例提供的一种可能的实现方式中的静电集成电路示意图；
图6为本申请实施例提供的静电集成电路示意图一；
图7为本申请实施例提供的一种钳位单元示意图；
图8为本申请实施例提供的另一种钳位单元示意图；
图9为本申请实施例提供的静电集成电路示意图二；
图10为本申请实施例提供的传递函数曲线对照图一；
图11为本申请实施例提供的泄放电流曲线对照图一；
图12为本申请实施例提供的静电集成电路示意图三；
图13为本申请实施例提供的传递函数曲线对照图二；
图14为本申请实施例提供的泄放电流曲线对照图二；
图15为本申请实施例提供的静电集成电路示意图四；
图16为本申请实施例提供的静电集成电路示意图五；
图17为本申请实施例提供的静电集成电路示意图六；
图18为本申请实施例提供的静电集成电路示意图七。
具体实施方式
下面结合附图并举实施例，对本申请提供的技术方案作进一步说明。应理解，本申请实施例中提供的系统结构和业务场景主要是为了解释本申请的技术方案的一些可 能的实施方式，不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓，随着系统的演进，以及更新的业务场景的出现，本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
图1为本申请实施例提供的一种通信装置的结构示意图。该通信装置可以为具有快速上电需求和/或低噪声需求的装置，例如，具有蓝牙(bluetooth，BT)系统的通信装置，基于降低功耗考虑，BT系统在正常工作时，其内部的部分模块会在关闭和打开两个状态中快速切换，这就要求这个模块的电源也需要跟随切换。为了满足BT系统对切换时间的要求，要求BT系统的电源快速切换，即具有快速上电需求。再例如：具有WiFi系统的通信装置，其具备低噪声要求。又例如，集成了具有低噪声需求的第一系统(如WiFi系统)和具有快速上电需求的第二系统(如BT系统)的通信装置。其中，第一系统和第二系统共用一个电源管理单元，需要同时满足低噪声需求和快速上电需求。
如图1所示，该通信装置可包括应用子系统，内存(memory)，大容量存储器(massive storge)，数字信号处理子系统，射频集成电路(radio frequency intergreted circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)，这些器件可以通过各种互联总线或其他电连接方式耦合。
图1中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发送路径，Rx表示接收路径，不同的数字表示不同的路径。FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图1中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。
射频集成电路可以进一步分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给数字信号处理子系统。射频发送通道可接收来自数字信号处理子系统的基带信号，对基带信号进行射频处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。具体地，射频子系统可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。天线有时也可以认为是射频子系统的一部分。
数字信号处理子系统可以从基带信号中提取有用的信息或数据比特，或者将信息或数据比特转换为待发送的基带信号。这些信息或数据比特可以是表示语音、文本、视频等用户数据或控制信息的数据。例如，数字信号处理子系统可以实现诸如调制和解调，编码和解码等信号处理操作。数字信号处理子系统一般集成到一个或者多个芯片中，集成数字信号处理子系统的芯片一般称为基带处理器芯片(baseband intergreted circuit，BBIC)。
此外，由于射频信号是模拟信号，数字信号处理子系统处理的信号主要是数字信 号，通信装置中还需要有模数转换器件。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模转换器(digital to analog converter，DAC)。本申请实施例中，模数转换器件可以设置在数字信号处理子系统中，也可以设置在射频子系统中。
其中，应用子系统可作为通信装置的主控制系统或主计算系统，用于运行主操作系统和应用程序，管理整个通信装置的软硬件资源，并可为用户提供用户操作界面。应用子系统可包括一个或多个处理核心。此外，应用子系统中也可包括与其他子系统(例如数字信号处理子系统)相关的驱动软件。数字信号处理子系统也可包括以及一个或多个处理核心，以及硬件加速器(hardware accelerator，HAC)和缓存等。
本申请实施例中，射频子系统可包括独立的天线，独立的射频前端(RF front end，RFFE)器件，以及独立的射频芯片。射频芯片有时也被称为接收机(receiver)、发射机(transmitter)或收发机(transceiver)。天线、射频前端器件和射频芯片都可以单独制造和销售。当然，射频子系统也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射频芯片中，该射频芯片也可以称为射频天线模组或天线模组。
本申请实施例中，数字信号处理子系统可以作为独立的芯片，该芯片可被称调制解调器(modem)芯片。数字信号处理子系统的硬件组件可以按照modem芯片为单位来制造和销售。modem芯片有时也被称为基带芯片或基带处理器。此外，数字信号处理子系统也可以进一步集成在SoC芯片中，以SoC芯片为单位来制造和销售。
应理解，图1所示的通信装置中的各部件和子系统中的部分或全部，可以集成在一块SoC芯片，以SoC芯片为单位来制造和销售。例如，数字信号处理子系统、射频子系统可以集成在一个SoC芯片中，数字信号处理子系统的软件组件可以在芯片出厂前内置在芯片的硬件组件中，也可以在芯片出厂后从其他非易失性存储器中导入到芯片的硬件组件中，或者还可以通过网络以在线方式下载和更新这些软件组件，此时，该SoC芯片可以称为收发芯片。
图2为本申请实施例提供的芯片的架构示意图一。应理解，图2所示的芯片可以为图1所示的通信装置中涉及到的各芯片。例如，射频芯片、收发芯片、基带处理器芯片等。又例如，图2中的芯片可以是射频子系统中的各电子器件集成的一个或多个芯片中的一个。
如图2所示，该芯片包括集成电路01，还可以包括封装基板(图中未示出)。其中，集成电路01包括输入输出端(input/output，I/O)(以下简称I/O端)、电源端VCC、接地端GND、以及耦合于I/O端、电源端VCC和接地端GND之间的静电集成电路10和功能电路20。应理解，虽然图2仅示出了一个I/O端，集成电路01可以包括两个或者两个以上的I/O端。
功能电路20由一个或多个负载电路耦合构成，用于实现集成电路01的基础功能。当集成电路01工作时，功能电路20通过I/O端与外部器件耦合，接收外部器件传输信号并进行处理，和/或对信号进行处理传输给外部器件。集成电路01通过电源端VCC与集成电路外部的供电端(如片外电源的输出端)耦合，以获得电源电压，向功能电路20供电。由于I/O端和电源端VCC均需要引至片外，因此，I/O端以及电源端VCC 通常需要静电防护。
静电集成电路10，用于对I/O端和/或电源端VCC进行静电防护，以避免进入I/O端和/或电源端VCC的静电损坏功能电路20。其中，当集成电路01正常工作时，静电集成电路10未被触发导通，功能电路20在电源端VCC的电源电压下能够正常工作。当集成电路01发生ESD事件，静电集成电路10被触发导通，将ESD能量泄放到地，避免过大的电压损坏功能电路20，保证功能电路20正常工作。
图3为本申请实施例提供的芯片的架构示意图二。如图3所示，该芯片与图2所示的芯片的区别在于，该芯片的集成电路01还可以包括供电模块，用于为将电源端VCC的电源转换为负载电路需要的电源电压或者电流。示例性的，供电模块可以为低压差稳压器(low dropout regulator，LDO)，下面各实施例中，均以供电模块为LDO进行说明。此时，静电集成电路10以及功能电路20通过LDO耦合至电源端VCC。LDO对片外电源的噪声有一定的抑制能力，可以降低耦合到I/O端的噪声。需要说明的是，当图3所示的芯片具有快速上电需求，例如应用于图1中具有快速上电需求的通信装置中，片外电源可以向电源端VCC提供正常上电速度的电源电压。电源电压经LDO处理后，可以提供满足快速上电需求的输出电压Vout。
可选的，供电模块也可以为直流直流转换器(direct current to direct current converter,DCDC)。
下面以收发芯片为例，说明上述图2或图3所示的功能电路20的具体实施。
示例性地，图4为本申请实施例提供的一种功能电路示意图。如图4所示，该功能电路20包括射频发射通道、射频接收通道、以及数字信号处理单元。应当理解，虽然图4仅有一条射频接收通道和一条射频发射通道，功能电路20可以包括两条或者两条以上的射频发射通道和射频接收通道。射频接收通道一般用于将接收RF的信号处理为中频信号。射频发送通道一般用于将中频信号处理为发送的射频信号。
如图4所示，射频接收通道可以包括LNA、混频器、本地振荡器、滤波器和ADC。LNA用于将放大后的射频信号发送给混频器，混频器将放大后的射频信号与本地振荡器提供的本振信号LO_Rx进行混频，混频后得到中频信号。中频信号经过滤波器后提供给ADC。ADC将模拟信号转换为数字信号后发送给数字信号处理单元。射频发送通道可以包括DAC、滤波器、混频器、本地振荡器(图中未示出)和PA。DAC将数字信号处理单元输出的数字信号转换为模拟信号后发送给滤波器，滤波器再将滤波后的信号发送给混频器。混频器将滤波器后的模拟信号和本地振荡器提供的本振信号LO_Tx进行混频搬移为射频信号，PA再对射频信号进行功率放大。
结合图2或图3，如图4所示，LNA的输入端耦合集成电路01的一个I/O端，通过I/O端从天线处接收射频信号；PA的输出端耦合集成电路01的另一个I/O端，通过I/O端将射频信号经天线发射。应理解，LNA的输入端、PA的输出端也可以耦合至集成电路01的同一I/O端。功能电路20的负载电路可以包括射频接收通道中的部分器件或全部器件，也可以包括射频发送通道中的部分器件或全部器件，还可以为两者的组合。功能电路20的负载电路耦合至图2所示的电源端VCC，或图3所示的LDO。
示例性地，图5为一种可能的实施方式中的静电集成电路示意图。如图5所示，以I/O端为例，当I/O端发生静电放电(electro static discharge，ESD)事件时，进入 I/O端的正ESD能量通过二极管D1后，会迅速拉升第一节点X1的电压，进而触发钳位单元11，将正ESD能量泄放到地；进入I/O端的负ESD能量通过二极管D2直接被传导到地。电源端VCC发生ESD事件时泄放过程类似，此处不再赘述。
可见，图5所示的静电集成电路10中，当集成电路01的电源端VCC与片外电源耦合时，片外电源的噪声会经过电源端VCC进入静电集成电路10，并通过二极管D1和二极管D2分压后耦合到I/O端，进而影响I/O端的I/O信号的信噪比。若图5所示的静电集成电路10应用于具有低噪声需求的通信装置中，这显然不能够满足其低噪声需求。
此外，若图5所示的静电集成电路10应用于具有快速上电需求的通信装置中，例如，图2中的电源端VCC或图3中的LDO的输出端在下电状态(即未上电的状态)和上电状态(即供电电压稳定的状态)之间的切换时间小于25微秒，如15微秒、10微秒，电源端VCC或LDO的输出端的快速上电，同样会迅速拉升第一节点X1的电压，进而误触发钳位单元11进行电流泄放。由于电源端VCC或LDO的输出端会在上电状态和下电状态之间频繁切换，因此，钳位单元11将会被频繁触发产生大电流。长期频繁的大电流使得静电集成电路10产生EM效应，严重影响静电集成电路10的可靠性。
为了解决上述噪声耦合问题，以及快速上电引发的可靠性问题，本申请提供一种静电集成电路，应用于图2或图3所示的芯片中，以替换图5所示的静电集成电路10。下面以图3所示的芯片为例，并结合图6至图18对本申请实施例提供的静电集成电路进行了详细说明。
示例性地，图6为本申请实施例提供的静电集成电路示意图一。
如图6所示，该静电集成电路10包括钳位单元11、静电防护电路12、限流单元13。
静电防护电路12的第一端与钳位单元11的第一端耦合于第一节点X1。
静电防护电路12的第二端与I/O端耦合。用于当I/O端发生正ESD事件时，迅速拉升第一节点X1的电压，以将正ESD能量耦合到第一节点X1。静电防护电路12的第三端与接地端GND耦合，用于当I/O端发生负ESD事件时，将负ESD能量泄放到地。
钳位单元11的第二端与接地端GND耦合，用于将静电防护电路12耦合至第一节点X1的正ESD能量，通过接地端GND泄放到地。
第一节点X1通过限流单元11与LDO的输出端耦合，进而实现与电源端VCC耦合。
可见，图6所示的静电集成电路10中，一方面，当图6所示的静电集成电路10具有低噪声需求时，通过在第一节点X1和LDO的输出端之间设置限流单元13，LDO的输出端到I/O端的阻抗为限流单元13的阻抗和第一二极管单元121的等效阻抗之和，相比于图5中的二极管D1的等效阻抗来说，增加了阻抗。而I/O端对接地端GND维持第一二极管单元121的等效阻抗。根据阻抗分压原理Vi/o＝Z2/(Z1+Z2)*Vout可知，耦合至I/O端的噪声电压分量得以减小，其中，Z1为LDO的输出端到I/O端的阻抗，Z2为I/O端到接地端GND的阻抗，Vout为LDO的输出电压，Vi/o为耦合至I/O 端的噪声电压分量。换而言之，限流单元13的设置能够显著提高电源端VCC到I/O端的隔离度，从而减少片外电源以及LDO到I/O端的耦合噪声。
另一方面，当图6所示的静电集成电路10具有快速上电需求，而导致钳位单元11被触发导通时，限流单元13可以和钳位单元11进行分压，减小钳位单元11两端的电压，从而减小钳位单元11误触发时的泄放电流Iout，进而降低EM效应，保证静电集成电路10的可靠性。
应理解，限流单元13的设置位置未影响LDO的输出端向图3所示的功能电路20输出满足其快速上电需求的电压，即图6所示的静电集成电路10并未影响功能电路20被快速上电。并且，限流单元13不在I/O端经钳位单元11到地的泄放通路中，因此，并不影响I/O端的ESD能量的泄放。
一种可能的实现方案，如图6所示，静电防护电路12包括第一二极管单元121和第二二极管单元122。其中，第一二极管单元121的阳极与I/O端耦合，第一二极管单元121的阴极与第一节点X1耦合。第二二极管单元122的阴极与I/O端耦合，第二二极管单元122的阳极与接地端GND耦合。
当I/O端发生正ESD事件时，进入I/O端的正ESD能量将通过第一二极管单元121耦合到第一节点X1，从而迅速拉升第一节点X1的电压。当I/O端发生负ESD事件时，进入I/O端的负ESD能量将通过第二二极管单元122耦合到接地端GND，进而被传导到地实现泄放。
应理解，第一二极管单元121和第二二极管单元122可以包括一个或一个以上依次顺向串联的二极管，本申请实施例对此不进行限定。假设顺向串联的二极管的数量为N个。顺向串联的二极管是指，第一个二极管的阴极连接第二个二极管的阳极，第二个二极管的阴极连接第三个二极管的阳极，依次类推，第N-1个二极管的阴极连接第N个二极管的阳极，N为大于2的正整数。其中，第一二极管单元121的阳极和第二二极管单元122的阳极是指第一个二极管的阳极，第一二极管单元121的阴极和第二二极管单元122的阴极是指第N个二极管的阴极。
一种可能的实现方案，如图6所示，钳位单元11包括第一电阻单元111、电容单元112、反相器单元113、以及第一晶体管114。第一电阻单元111的第一端和电容单元112的第一端均耦合至反相器单元113的输入端。反相器单元113的输出端耦合至第一晶体管114的栅极。第一电阻单元111的第二端、反相器单元113的电源端、第一晶体管114的漏极均耦合至第一节点X1。电容单元112的第二端、反相器单元113的接地端、第一晶体管114的源极均耦合至集成电路的接地端GND。
应理解，第一电阻单元111可以包括一个或一个以上依次串联的电阻，电容单元112可以包括一个或一个以上依次串联的电容，反相器单元113可以包括一个或一个以上，且数量为奇数的依次串联的反相器。此外，图6所示的各单元构成钳位单元11的最小组成单元，钳位单元11还可以包括其他元器件，例如锁存器，本申请实施例对此不进行限定。
示例性地，图7为本申请实施例提供的一种钳位单元示意图。如图7所示，该钳位单元11包括电阻R1、电容C1、由晶体管PM1和晶体管NM1构成的反相器、以及晶体管NM2。
其中，晶体管PM1的栅极和晶体管NM1的栅极耦合形成反相器的输入端，晶体管PM1的漏极和晶体管NM1的漏极耦合形成反相器的输入端，晶体管PM1的源级形成反相器的电源端，晶体管NM1的源极形成反相器的接地端。
电阻R1的第一端、电容C1的第一端、反相器的输入端耦合于第二节点X2。电阻R1的第二端、反相器的电源端、晶体管NM2的漏极均耦合至第一节点X1。电容C1的第二端、反相器的接地端、晶体管NM2的源极均耦合至接地端GND。
图7所示的钳位单元11的工作原理如下：电阻R1和电容C1构成低通滤波器，当第一节点X1的电压正常上升，第二节点X2可以跟随充电，第二节点X2将维持较高的电压。经过反相器反相后，在第三节点X3(即反相器的输出端)输出低电压。此时，晶体管NM2不导通。
当第一节点X1的电压迅速上升，第二节点X2来不及充电，第二节点X2将维持较低的电压。经过反相器反相后，在第三节点X3(即反相器的输出端)输出高电压。此时，晶体管NM2将被导通，从而泄放第一节点X1的ESD能量。
另一种可能的实现方案，结合图6，调换第一电阻单元111和电容单元112的位置，且反相器单元113中反相器的数量为偶数，进而获得该钳位单元。
示例性地，图8为本申请实施例提供的另一种钳位单元的结构示意图。该钳位单元11与图7所示的钳位单元11的区别在于：
电阻R1和电容C1的位置进行了调换，并且该钳位单元11包含两个反相器，分别为由晶体管PM1和晶体管NM1构成的第一个反相器、以及由晶体管PM2和晶体管NM3构成的第二个反相器。
图8所示的钳位单元11的工作原理如下：电阻R1和电容C1构成高通滤波器，当第一节点X1的电压正常上升，第二节点X2的电压通过电阻R1放电，从而维持在较低的电压。经过两级反相器后，在第三节点X3输出低电压。此时，晶体管NM2不导通。
当第一节点X1的电压迅速上升，第二节点X2可以跟随充电，第二节点X2被拉至高电压。经过两级反相器后，在第三节点X3输出高电压。此时，晶体管NM2将被导通，从而泄放第一节点X1的ESD能量。
下面结合图9-图15，对图6中的限流单元13的具体实施进行详细说明。
示例性地，图9为本申请实施例提供的静电集成电路示意图二。如图9所示，限流单元13包括第二电阻单元131。其中，第二电阻单元131的第一端与第一节点X1耦合，第二电阻单元131的第二端与LDO的输出端耦合。应理解，第二电阻单元131可以包括一个或一个以上依次串联的电阻，本申请实施例对此不进行限定。
需要说明的是，图9所示的静电集成电路10中，各组成部分的具体实施以及相互之间的连接关系可以参照图6实施，此处不再赘述。
耦合至I/O端的噪声电压分量Vi/o＝Z2/(Z1+Z2)*Vout，图9所示的静电集成电路10中，Z2由第二二极管单元122决定，Z1由第一二极管单元121和第二电阻单元131决定。可见，设置第二电阻单元131，增加了Z1，从而降低了耦合至I/O端的噪声电压分量，减小了I/O端的噪声。
图10示出了图5、图9所示的静电集成电路10中，LDO的输出端至I/O端的传 递函数曲线对照图。如图10可知，Arch1为图5所示的静电集成电路10的传递函数曲线；Arch2为图9所示的静电集成电路10的传递函数曲线。纵坐标为传递函数，横坐标为频率。传递函数为I/O端接收到的干扰信号的拉普拉斯变换与LDO的输出端的干扰信号的拉普拉斯变换之比，传递函数的幅值越高，代表耦合到I/O端的噪声越大。由图可见，图9所示的静电集成电路10的传递函数的幅值高于图5所示的静电集成电路10，即第二电阻单元131作为限流单元13，可以减小片外电源耦合到I/O端的噪声。
此外，图9所示的静电集成电路10中，一方面，第二电阻单元131和钳位单元11的等效电容形成低通滤波器，从而可以降低LDO的输出端传输到第一节点X1的电压的上升沿速度，进而降低钳位单元11被误触发的可能性。此外，即使钳位单元11被误触发，第二电阻单元131的设置，也可以增加LDO的输出端经钳位单元11到地的泄放通路的阻抗，从而可以降低钳位单元11误触发时的泄放电流Iout，进而提高静电集成电路10的可靠性。
图11示出了图5、图9所示的静电集成电路10的泄放电流曲线对照图。如图11所示，Vout为LDO的输出电压，Iout_Arch1为图5所示的静电集成电路10的泄放电流曲线图；Iout_Arch2为图9所示的静电集成电路10的泄放电流曲线图。由图可见，当LDO的输出电压Vout快速上升时，Iout_Arch1出现了峰值电流(虚线圈出)，而Iout_Arch2较为平缓，即第二电阻单元131作为限流单元13，能够减小钳位单元11误触发时的泄放电流Iout。
图9所示的静电集成电路10中，可以通过增加第二电阻单元131的阻抗，减小泄放电流Iout。然而，第二电阻单元131的阻抗不能过大，原因在于：当第二电阻单元131的阻抗过大时，较小的电流波动将导致较大的电压波动，从而无法为钳位单元11提供可靠的直流偏置。基于此，当LDO的输出电压Vout较高时，不能够通过持续增加第二电阻单元131的阻抗的方式，来降低泄放电流Iout，即图9所示的静电集成电路10适用于静电集成电路10所需的供电电压较低的情况。
基于此，示例性地，图12为本申请实施例提供的静电集成电路示意图三。如图12所示，该静电集成电路10与图9所示的静电集成电路10的区别在于：图12所示的静电集成电路10将图6中的限流单元13由图9所示的第二电阻单元131替换成了第三二极管单元132。
其中，第三二极管单元132的阴极与第一节点X1耦合；第三二极管单元132的阳极与LDO的输出端耦合。应理解，第三二极管单元132可以包括一个或一个以上依次串联的二极管，本申请实施例对此不进行限定。
需要说明的是，图12所示的静电集成电路10中，各组成部分的具体实施以及相互之间的连接关系可以参照图9实施，此处不再赘述。
耦合至I/O端的噪声电压分量Vi/o＝Z2/(Z1+Z2)*Vout，图12所示的静电集成电路10中，Z2由第二二极管单元122决定，Z1由第一二极管单元121和第三二极管单元132决定。可见，设置第三二极管单元132，增加了Z1，从而降低了耦合至I/O端的噪声电压分量。
图13示出了图5、图12所示的静电集成电路10中，LDO的输出端与I/O端的传 递函数曲线对照图。如图13可知，Arch3为图5所示的静电集成电路10的传递函数曲线；Arch4为图13所示的静电集成电路10的传递函数曲线。由图可见，图13所示的静电集成电路10的传递函数的幅值高于图5所示的静电集成电路10，即第三二极管单元132作为限流单元13，可以减小片外电源耦合到I/O端的噪声。
此外，图12所示的静电集成电路10中，第三二极管单元132将第一节点X1的电压钳制在，LDO的输出电压Vout与第三二极管单元132的导通压降之差，相比于图5所示的静电集成电路10，降低了第一节点X1的电压，从而可以降低钳位单元11被误触发时的泄放电流Iout，进而可以降低EM效应，提高静电集成电路10的可靠性。
图14示出了图5、图12所示的静电集成电路10的泄放电流曲线对照图。如图14所示，Vout为LDO的输出电压，Iout_Arch3为图5所示的静电集成电路10的泄放电流曲线图；Iout_Arch4为图14所示的静电集成电路10的泄放电流曲线图。由图可见，当LDO的输出电压Vout快速上升时，Iout_Arch3出现了峰值电流(虚线圈出)，而Iout_Arch4较为平缓，即第三二极管单元132作为限流单元13，能够减小钳位单元11被误触发时的泄放电流Iout。
值得注意的是，图12所示的静电集成电路10中，第三二极管单元132两端的导通压降是稳定不变的，因此，相对于图9所示的第二电阻单元131来说，第三二极管单元132可以为钳位单元11提供可靠的直流偏置。当LDO的输出电压Vout较高时，可以通过增加第三二极管单元132中二极管的个数，来增加其导通压降，以将第一节点X1的电压钳制在一个较小的电压，从而达到减小泄放电流Iout的目的。
应理解，图12所示的静电集成电路10同样适用于LDO的输出电压Vout较低的场景。需要说明的是，为避免第三二极管单元132的阳极处于高阻态，无论LDO的输出电压Vout高或低，可以小于第三二极管单元132的导通压降。
需要说明的是，当LDO的输出端需要引出到片外时，LDO的输出端也需要进行ESD保护，或者，当LDO的走线尺寸较大，例如，走线长度大于1.5mm，此时，LDO的输出端也需要荷电器件型(charged device model，CDM)保护。而图9所示的静电集成电路10的LDO的输出端经钳位单元11到地的泄放通路中存在第二电阻单元131，致使泄放通路阻抗较大，无法泄放ESD能量。图12所示的静电集成电路10中，进入静电集成电路10的LDO的输出端的正ESD能量，可以通过第三二极管单元132经钳位单元11泄放到地。但当负ESD能量进入时，却不存在泄放通路。
基于此，示例性地，图15为本申请实施例提供的静电集成电路示意图四。如图15所示，该静电集成电路10与图12所示的静电集成电路10的区别在于：图15所示的静电集成电路10增加了第四二极管单元141。
其中，第四二极管单元141的阴极与静电集成电路10的电源端VCC耦合；第四二极管单元141的阳极与静电集成电路10的接地端GND耦合。可选地，当静电集成电路10包括LDO时，第四二极管单元141的阴极与LDO的输出端耦合。应理解，第四二极管单元141可以包括一个或一个以上依次顺向串联的二极管，本申请实施例对此不进行限定。
需要说明的是，图15所示的静电集成电路10中，各组成部分的具体实施以及相 互之间的连接关系可以参照图12实施，此处不再赘述。基于此，图15所示的静电集成电路10的实施效果可以参照图12所示的静电集成电路10。
图15所示的静电集成电路10中，通过增加第四二极管单元141，并复用图12所示的第三二极管单元132和钳位单元11，对LDO的输出端静电防护。如此，当正ESD能量进入静电集成电路10的LDO的输出端时，将通过第三二极管单元132耦合到第一节点X1，从而迅速拉升第一节点X1的电压，并通过钳位单元11泄放到地。当负ESD能量进入静电集成电路10的LDO的输出端时，将通过第四二极管单元141直接泄放到地，以对LDO的输出端进行保护，避免损坏内部的功能电路。
应理解，虽然图15所示的静电集成电路10中，虽然LDO的输出端在进行ESD防护时和I/O端共用一个钳位单元11，在其他实施例中，钳位单元11也可以分开设置。
I/O端的容性负载影响其工作频率，在高频场景下，希望I/O端的容性负载尽可能小。而图12、图15所示的静电集成电路10中，第三二极管单元132的加入，将使得第一二极管单元121的阴极偏置电压下降，从而导致第一二极管单元121的结电容变大。可见，图12、图15所示的静电集成电路10不适用于高频场景。
基于此，示例性地，图16为本申请实施例提供的静电集成电路示意图五。如图16所示，该静电集成电路10与图12所示的静电集成电路10的区别在于：图16所示的静电集成电路10增加了第三电阻单元133。
其中，第三电阻单元133与第三二极管单元132并联。应理解，第三电阻单元133可以包括一个或一个以上依次串联的电阻，本申请实施例对此不进行限定。
可选地，该静电集成电路10还包括第四二极管单元141。
需要说明的是，图16所示的静电集成电路10中，各组成部分的具体实施以及相互之间的连接关系可以参照图15实施，此处不再赘述。基于此，图16所示的静电集成电路10的实施效果可以参照图15所示的静电集成电路10。
图16所示的静电集成电路10中，正常工作状态下，钳位单元11未导通，泄放电流Iout为零，因此，设置第三电阻单元133，可以将第一二极管单元121的阴极偏置电压，提升至LDO的输出电压Vout。而图12、图15所示的静电集成电路10中，第一二极管单元121的阴极偏置电压为，LDO的输出电压Vout与第三二极管单元132的导通压降之差。显然，相比于图12、图15所示的静电集成电路10，设置第三电阻单元133，提高了第一二极管单元121的阴极偏置电压，从而降低了第一二极管单元121的结电容。可见，图16所示的静电集成电路10可以适用于高频场景。
应理解，图16所示的静电集成电路10同样可以适用于低频场景。下面对图16所示的静电集成电路10在低频和高频下的噪声隔离效果分别说明。
首先说明，随着频率的增加，二极管的等效电容增大，等效阻抗变小，但电阻不会随着频率改变。因此，在低频时，二极管的等效阻抗远大于电阻单元，在高频时，二极管的等效阻抗远小于电阻。
图9所示的静电集成电路10，在低频时，第一二极管单元121的等效阻抗远大于第二电阻单元131，第二电阻单元131可忽略不计，因此，LDO的输出端到I/O端的阻抗基本上由第一二极管单元121决定。即低频时，图9所示的静电集成电路10对噪 声的隔离度和图5类似，但有略微提升。在高频时，第一二极管单元121的等效阻抗远小于第二电阻单元131，第一二极管单元121可忽略不计，因此，LDO的输出端到I/O端的阻抗基本上由第二电阻单元131决定。即高频时，图9所示的静电集成电路10对噪声的隔离度相比于图5来说，效果较好。
图12或图15所示的静电集成电路10，随着频率的变化，第一二极管单元121、第二二极管单元122、第三二极管单元132的等效阻抗是等比例变化的，因此，无论是高频还是低频，耦合至I/O端的噪声电压分量是固定的。即图12或图15所示的静电集成电路10在低频和高频对噪声的抑制效果是不变的。
基于此，图12或图15所示的静电集成电路10对噪声的隔离度在低频时效果较好，图9所示的静电集成电路10对噪声的隔离度在高频时效果较好。
图16所示的静电集成电路10中，耦合至I/O端的噪声电压分量Vi/o＝Z2/(Z1+Z2)*Vout，其中，Z2由第二二极管单元122决定，Z1由第一二极管单元121、第三二极管单元132、第三电阻单元133决定。
在低频时，第三二极管单元132的等效阻抗远大于第三电阻单元133，因此，第三二极管单元132和第三电阻单元133并联后的总阻抗基本上由第三电阻单元133决定。即低频时，图16所示的静电集成电路10和图9所示的静电集成电路10对噪声的隔离度类似。
在高频时，第三二极管单元132的等效阻抗远小于第三电阻单元133，因此，第三二极管单元132和第三电阻单元133并联后的总阻抗基本上由第三二极管单元132决定，阻抗和图12、图15类似。与此同时，第三电阻单元133的加入，降低了第一二极管单元121的结电容，进而增加第一二极管单元121的等效阻抗。也就是说，第二电阻单元131的加入，整体上提升了LDO的输出端到I/O端的阻抗，相比于图12、图15所示的静电集成电路10来说，进一步增加了对噪声的隔离度。
下面对图16所示的静电集成电路10的泄放电流Iout的限制过程进行说明。
同图12和图15类似，图16所示的静电集成电路10中，第一节点X1的电压同样被钳制在，LDO的输出电压Vout与第三二极管单元132的导通压降之差，即第一节点X1的电压降低了。
若LDO的输出电压Vout大于第三二极管单元132的导通压降，此时，第三二极管单元132将导通，导通内阻几乎为零，第三电阻单元133几乎被短路。因此，钳位单元11导通泄放时，泄放电流Iout基本由第一节点X1的电压和图6中的第一晶体管114的导通内阻之商决定。由于第一节点X1的电压降低了，因此，泄放电流Iout得以降低，对泄放电流Iout的限制效果与图12所示的静电集成电路10，以及图15所示的静电集成电路10类似。
若LDO的输出电压Vout小于第三二极管单元132的导通压降，此时，第三二极管单元132不导通，导通内阻无穷大。因此，钳位单元11导通泄放时，泄放电流Iout基本仅经第三电阻单元133流入钳位单元11，即泄放电流Iout基本由LDO的输出电压Vout，与第三电阻单元133及图6中的第一晶体管114的导通内阻的总阻抗之商共同决定。由于LDO的输出端到接地端GND之间的阻抗增加了第三电阻单元133的阻抗，泄放电流Iout得以降低，对泄放电流Iout的限制效果与图9所示的静电集成电路 10类似。
以上结合图6至图16，并以I/O端为例对本申请实施例提供的静电集成电路进行了详细说明，以下结合图17至图18，以LDO的输出端为例对本申请实施例提供的静电集成电路进行具体阐述。
示例性地，图17为本申请实施例提供的静电集成电路示意图六。如图17所示，该静电集成电路10包括静电防护电路15、钳位单元11、限流单元13。
静电防护电路15的第一端与钳位单元11的第一端耦合于第一节点X1。
静电防护电路15的第二端与LDO的输出端耦合。用于当LDO的输出端发生正ESD事件时，迅速拉升第一节点X1的电压，以将正ESD能量耦合到第一节点X1。静电防护电路15的第三端与接地端GND耦合，用于当LDO的输出端发生负ESD事件时，将负ESD能量泄放到地。
钳位单元11的第二端与接地端GND耦合，用于将静电防护电路15耦合至第一节点X1的正ESD能量，通过接地端GND泄放到地。钳位单元11的具体实施可以参考图6所示的静电集成电路10，此处不再赘述。
第一节点X1通过限流单元11与LDO的输出端耦合，进而实现与电源端VCC耦合。此时，片外电源经电源端VCC向静电集成电路10提供的电源电压，经过LDO稳压后向限流单元13输出。
可见，当图17所示的静电集成电路10具有快速上电需求时，而导致钳位单元11被触发导通时，限流单元13可以和钳位单元11进行分压，减小钳位单元11两端的电压，从而减小钳位单元11误触发时的泄放电流Iout，进而可以降低EM效应，保证静电集成电路10的可靠性。
应理解，限流单元13的设置位置未影响LDO的输出端向图3所示的功能电路20输出满足其快速上电需求的电压，即图17所示的静电集成电路10并未影响功能电路20被快速上电。
一种可能的实现方案，如图17所示，静电防护电路15包括第五二极管单元151和第六二极管单元152。
其中，第五二极管单元151的阳极与LDO的输出端耦合，第五二极管单元151的阴极与第一节点X1耦合。
第六二极管单元152的阴极与LDO的输出端耦合，第六二极管单元152的阳极与接地端GND耦合。
当LDO的输出端发生正ESD事件时，进入LDO的输出端的正ESD能量将通过第五二极管单元151耦合到第一节点X1，从而迅速拉升第一节点X1的电压。当LDO的输出端发生负ESD事件时，进入LDO的输出端的负ESD能量将通过第六二极管单元152耦合到接地端GND，进而被传导到地实现泄放。
应理解，第五二极管单元151和第六二极管单元152可以包括一个或一个以上依次顺向串联的二极管，本申请实施例对此不进行限定。
图18为本申请实施例提供的静电集成电路示意图七。如图18所示，限流单元13包括第四电阻单元134。应理解，该静电集成电路10中，第五二极管单元151复用为静电防护电路和限流单元13。因此，图18所示的静电集成电路10和图16所示的静 电集成电路10类似，其工作过程可以参考，此处不再赘述。
应理解，若图6至图18任一项所述的静电集成电路10应用于图2所示的芯片。静电集成电路10的第一节点X1通过限流单元13和电源端VCC耦合。片外电源经电源端VCC向静电集成电路10的限流单元13输出的电源电压。
需要说明的是，当图6至图18任一项所述的静电集成电路10应用于图2所示的芯片时，电源端VCC的ESD防护通过图15至图18所示的静电集成电路10实现。当图6至图18任一项所述的静电集成电路10应用于图3所示的芯片时，LDO的输出端和电源端为两个不同的端子，图6至图18任一项所述的静电集成电路10中，电源端VCC也可以进行ESD防护，具体实施可以参考I/O端的ESD防护，例如，可以设置单独的静电防护电路，并和I/O端共用一个钳位单元，以进行ESD防护，此处不再赘述。
本申请还提供一种电子设备，包括电路板、以及图2或图3所示的集成电路01，其中，图2或图3所示的集成电路01中，静电集成电路10为图6至图18任一项所述的静电集成电路10。
本申请实施例中，有时候下标如W1可能会笔误为非下标的形式如W1，在不强调其区别时，其所要表达的含义是一致的。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系，但也可能表示的是一种“和/或”的关系，具体可参考前后文进行理解。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执 行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种集成电路，其特征在于，包括：静电防护电路、钳位单元和限流单元；
    所述静电防护电路的第一端与所述钳位单元的第一端耦合于第一节点；
    所述静电防护电路的第二端与所述集成电路的I/O端耦合；
    所述静电防护电路的第三端以及所述钳位单元的第二端分别与所述集成电路的接地端耦合；
    所述第一节点通过所述限流单元与所述集成电路的电源端耦合；
    所述集成电路通过所述集成电路的电源端为所述集成电路的负载电路供电。
  2. 如权利要求1所述的集成电路，其特征在于，所述静电防护电路包括第一二极管单元和第二二极管单元；
    所述第一二极管单元的阳极与所述I/O端耦合，所述第一二极管单元的阴极与所述第一节点耦合；
    所述第二二极管单元的阴极与所述I/O端耦合，所述第二二极管单元的阳极与所述集成电路的接地端耦合。
  3. 如权利要求1或2所述的集成电路，其特征在于，所述钳位单元包括第一电阻单元、电容单元、反相器单元、以及第一晶体管；
    所述第一电阻单元的第一端和所述电容单元的第一端均耦合至所述反相器单元的输入端；
    所述反相器单元的输出端耦合至所述第一晶体管的栅极；
    所述第一电阻单元的第二端、所述反相器单元的电源端、所述第一晶体管的漏极均耦合至所述第一节点；
    所述电容单元的第二端、所述反相器单元的接地端、所述第一晶体管的源极均耦合至所述集成电路的接地端。
  4. 如权利要求1-3任一项所述的集成电路，其特征在于，还包括供电模块；
    所述供电模块耦合于所述集成电路的电源端和所述限流单元之间，用于为所述负载电路供电。
  5. 如权利要求4所述的集成电路，其特征在于，所述限流单元包括第二电阻单元，所述第二电阻单元耦合于所述供电模块和所述第一节点之间。
  6. 如权利要求4所述的集成电路，其特征在于，所述限流单元包括第三二极管单元；
    其中，所述第三二极管单元的阴极与所述第一节点耦合；所述第三二极管单元的阳极与所述供电模块耦合。
  7. 如权利要求6所述的集成电路，其特征在于，还包括第四二极管单元；
    其中，所述第四二极管单元的阴极与所述集成电路的电源端耦合；所述第四二极管单元的阳极与所述集成电路的接地端耦合。
  8. 如权利要求6或7所述的集成电路，其特征在于，所述限流单元还包括第三电阻单元；
    所述第三电阻单元与所述第三二极管单元并联。
  9. 如权利要求4-8任一项所述的集成电路，其特征在于，所述供电模块具有上电状 态和下电状态；
    所述供电模块在所述下电状态和所述上电状态之间的切换时间小于25微秒。
  10. 一种如权利要求1-9任一项所述的集成电路，所述集成电路还包括射频接收通道，所述射频接收通道包括依次耦合的低噪声放大器，第一混频器，第一滤波器和模数转换器；
    所述负载电路包括所述低噪声放大器，第一混频器，第一滤波器和模数转换器中的一个或者多个。
  11. 如权利要求10所述的集成电路，其特征在于，还包括射频发送通道，所述射频发送通道包括依次耦合的数模转换器、第二滤波器、第二混频器和功率放大器；
    所述负载电路还包括所述数模转换器、第二滤波器、第二混频器和功率放大器中的一个或多个。
  12. 一种电子设备，其特征在于，包括电路板，还包括如权利要求1至9任一项所述的集成电路，或权利要求10至11任一项所述的集成电路，所述集成电路设置于所述电路板上。
  13. 一种通信装置，其特征在于，包括第一系统和第二系统；
    其中，所述第一系统及所述第二系统均包括如权利要求1-9任一项所述的集成电路，或权利要求10至11任一项所述的集成电路；
    所述集成电路通过所述集成电路的电源端，分别为所述第一系统的负载电路和所述第二系统的负载电路供电。
  14. 如权利要求13所述的通信装置，其特征在于，所述第一系统为WiFi系统，所述第二系统为蓝牙系统。
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