WO2017156671A1 - 芯片封装设备及其方法 - Google Patents

芯片封装设备及其方法 Download PDF

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Publication number
WO2017156671A1
WO2017156671A1 PCT/CN2016/076233 CN2016076233W WO2017156671A1 WO 2017156671 A1 WO2017156671 A1 WO 2017156671A1 CN 2016076233 W CN2016076233 W CN 2016076233W WO 2017156671 A1 WO2017156671 A1 WO 2017156671A1
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WO
WIPO (PCT)
Prior art keywords
chip
platform
picking
chips
bonding
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Application number
PCT/CN2016/076233
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English (en)
French (fr)
Inventor
俞峰
王宏刚
李洋
王永新
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华封科技有限公司
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Publication date
Application filed by 华封科技有限公司 filed Critical 华封科技有限公司
Priority to SG11201807973RA priority Critical patent/SG11201807973RA/en
Priority to KR1020187029567A priority patent/KR102281279B1/ko
Priority to US16/084,611 priority patent/US11189507B2/en
Priority to PCT/CN2016/076233 priority patent/WO2017156671A1/zh
Priority to MYPI2018001570A priority patent/MY198186A/en
Priority to CN201680083539.5A priority patent/CN108886002B/zh
Publication of WO2017156671A1 publication Critical patent/WO2017156671A1/zh
Priority to PH12018501980A priority patent/PH12018501980A1/en

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Definitions

  • the present invention relates to the field of advanced packaging in the semiconductor industry, and more particularly to an apparatus and method for chip packaging.
  • microelectronic circuits includes the packaging of the chip, that is, mounting the chip on a substrate or wafer.
  • the substrate plays the role of placing, fixing, protecting the chip and enhancing the electrothermal performance, and is also a bridge between the internal world and the external circuit of the chip.
  • the contacts on the chip are electrically connected to the substrate, and then established through the substrate and other devices. Electrical connection. Therefore, packaging plays an important role in integrated circuits. There are many ways to package, including wire bonding, automatic tape bonding, flip bonding, and positive bonding.
  • the chip In the flip-chip bonding process, the chip is placed on the substrate and the bumps of the chip for making electrical connections with the external components face down, ie toward the substrate, the basic workflow of which involves picking up the chip from the wafer, flipping the chip so that The up and down direction is reversed, flux is applied to the chip, the position is aligned at the inspection camera, and the chip is bonded to the substrate.
  • the chip In the dressing bonding process, the chip is placed on the substrate and the bumps of the chip are upward, that is, the bumps of the chip face away from the substrate. Therefore, the formal bonding process does not require the step of flipping the chip compared to the flip-chip bonding process.
  • microelectronics product wants to win in this brutal competition, and time to market is a key.
  • the process from design to launch must be as short as possible to deliver the most innovative and technologically advanced products.
  • manufacturers of microelectronic products have been eager to have more innovative technologies to improve product production efficiency, reduce unit product costs, and provide products that are as technically as possible as possible and cost-effective as possible to improve their products.
  • Market competitive advantage to meet the huge consumer demand of the market.
  • I hope that the product has more powerful features.
  • One way to achieve this is to bond different types of chips to the same substrate to obtain circuits that can perform more complex tasks.
  • chip package devices typically include a single bond head that repeatedly moves between the wafer and the substrate, and the bond head can bond one chip to the substrate in each cycle.
  • the bond head can bond one chip to the substrate in each cycle.
  • the conventional bonding device if it is desired to increase the production efficiency, only the running speed of the device is accelerated.
  • the effect of obtaining higher productivity by increasing the speed of the machine is very limited, because the chips are picked up and bonded one by one, and the work cycle for the latter chip must work for the previous chip. It can't be started until the loop is complete.
  • the present invention provides a chip package apparatus comprising: at least one chip supply device; at least one chip processing device configured to process a chip provided by a corresponding chip supply device; at least one chip transfer device, each Each of the chip transfer devices has a plurality of bond heads, each bond head for transferring one of the chips processed by the corresponding chip processing device; wherein each of the chip processing devices includes at least two pick-up platforms, Each pick-up platform is configured to simultaneously arrange a plurality of said chips, and a plurality of bond heads on respective chip transfer devices are configured to pick up a plurality of said chips simultaneously from each pick-up platform at a time.
  • a plurality of pick-up platforms can be set to take turns to perform chip loading, thereby achieving uninterrupted operation of the chip processing device, effectively improving the overall chip packaging device. Processing efficiency.
  • the pickup platform in the chip processing apparatus of the chip package device can simultaneously arrange a plurality of chips
  • a plurality of bonding heads of the chip transfer device in the device are disposed to have positions with a plurality of chips on the pickup platform Corresponding to each other, so that the plurality of bonding heads can simultaneously pick up a plurality of said ones from the picking platform at the same time chip.
  • the bonding head directly detects, selects, aligns, and picks up the chip one by one from the wafer, which can greatly improve the production efficiency of the device.
  • each of the chip processing devices includes a first picking platform and a second picking platform, and the corresponding chip transferring device sequentially picks up a plurality of chips from the first picking platform and the second picking platform. Since two picking platforms are provided, and the two picking platforms are arranged to be alternately in the loading position and the picking position, the chip processing apparatus can continue to work while the picking step completes the loading step while one picking platform completes the picking step The picking platform implements a chip loading step, thereby realizing the uninterrupted operation of the chip processing device, and effectively providing the overall processing efficiency of the chip packaging device.
  • each of the picking platforms is moveable between a loading position and a picking position, the picking platform being adapted to be arranged with a plurality of said chips when in said loading position, said picking platform being in said picking The position is adapted to allow the plurality of bond heads to simultaneously pick up a plurality of the chips at a time.
  • each of said chip processing devices is arranged such that said first picking platform and said second picking platform are alternately in a loading position and a picking position.
  • the chip package device has a first chip supply device and a second chip supply device that operate independently.
  • the first chip supply device and the second chip supply device respectively provide different chips.
  • the chip package device has a first chip processing device and a second chip processing device that operate independently, which respectively process the chips provided by the corresponding first chip supply device and the second chip supply device.
  • the chip package device has a first chip transfer device and a second chip transfer device that operate independently, and respectively transfer the chips processed by the corresponding first chip processing device and the second chip processing device.
  • the chip package apparatus further includes a bonding platform on which the substrate is disposed, and the chip is bonded to the substrate by the bonding head.
  • the bonding platform is provided with a heating device adapted to heat the substrate disposed on the bonding platform to bond it to the chip.
  • the present invention provides a method for packaging a chip, comprising: providing a first chip processing device, the first chip processing device including a first picking platform and a second picking platform; causing the first picking platform And the second picking platform alternately in a loading position and a picking position, wherein the picking platform is at The loading position is adapted to be arranged with a plurality of said chips, said picking platform being adapted to allow a plurality of bonding heads of the chip transfer device to simultaneously pick up a plurality of said chips at a time when in said picking position.
  • a second chip processing device is also provided, the second chip processing device processing the different chips independently of the first chip processing device.
  • the method further includes providing a bonding platform for arranging the wafer, the chip being bonded to the wafer by the bonding head.
  • the method further includes activating a heating device on the bonding platform to heat the wafer disposed on the bonding platform to bond the chip to the wafer.
  • the chip transfer device is further provided with an image pickup device for detecting one by one of the plurality of chips on the pick-up platform to determine whether the positions of the respective chips meet the requirements.
  • the chip transfer device places the chip one by one onto the substrate to perform bonding.
  • Figure 1 shows a perspective view of a chip package device in accordance with one embodiment of the present invention
  • FIG. 2 is a partial perspective view of the chip packaging apparatus of FIG. 1 with portions of the housing and components removed to better illustrate the internal configuration thereof;
  • FIG. 3 is a top plan view of the chip package device of FIG. 1 with portions of the housing and components removed to better illustrate its internal configuration;
  • FIG. 4 is a perspective view of a portion of a chip supply device and a chip processing device of the chip package device of FIG. 1;
  • Figure 5 is a perspective view of a portion of the chip processing apparatus of the chip package apparatus of Figure 1;
  • Figure 6 is a partially enlarged perspective view of the chip package device of Figure 1, mainly showing the chip transfer device;
  • Figure 7 is a partially enlarged perspective view of the bonding head portion of the chip transfer device of Figure 6;
  • FIG. 8 is a schematic view of a plurality of bonding heads of the chip packaging device of FIG. 1 when picking up a chip;
  • FIG. 9 is a schematic view of a bonding platform portion of the chip package device of FIG. 1;
  • FIG. 11 is a block flow diagram of one embodiment of a method for packaging a chip in accordance with the present invention.
  • the term "chip” may also be referred to as a "die” as the case may be, but those skilled in the art will appreciate that components or products suitable for use in the apparatus and methods of the present invention include a die or chip, such as This includes, but is not limited to, integrated circuits (ICs), discrete devices, modules, modules, etc. These components or products should be considered equivalent to "chip” or “die” in this context.
  • ICs integrated circuits
  • the chip package apparatus and method according to the present invention can be used to process a variety of suitable chips.
  • suitable chips for example, specific embodiments thereof are specifically described below only with the processing of integrated chips.
  • the chips in these embodiments can be replaced with other suitable chips, and such embodiments are also within the scope of the present invention.
  • Figure 1 shows a specific chip package device in accordance with the present invention.
  • the chip package device is mainly composed of a chip supply portion A, a chip processing portion C, and a substrate supply portion B, wherein the substrate supply portion B includes a substrate holder 11 and a robot 12.
  • the wafer cassette is supplied into the chip supply portion A, and the robot 12 takes the substrate from the substrate holder 11 and places it in the processing portion C.
  • the specified position is then processed, that is, the chip on the wafer is bonded to the substrate until the desired package is completed.
  • the device shown in the figures has a housing mounted on the frame and a plurality of doors that can be opened and closed, such as wafer cassette loading doors, beam doors, etc., which are used to load objects such as chips or substrates, or for mounting Observe, or inspect, the various modules or components of the equipment. Therefore, the settings of these doors can be set according to specific needs, and can be set to start the device and perform the machining operation only when all the doors are safely closed.
  • the substrate described herein generally refers to any carrier that can be used to carry a chip or other microelectronic component, such as a substrate, a substrate, a wafer, or the like.
  • the chip supply portion A includes the independently operated first chip supply device 20 and the second chip supply device 20' which are symmetrically arranged in the longitudinal direction
  • the processing portion C includes the first arrangement which is symmetrically arranged and operates independently.
  • First chip supply device 20 and second chip supply device 20', first chip processing device 30 and second chip processing device 30', first chip transfer device 40 and second chip transfer device of chip package device according to the present invention 40' can be basically the same or different.
  • the devices are the same, so in the following description, only the first chip supply device 20, the first chip processing device 30, and the first chip transfer supply device 40 will be described.
  • the various devices in the device according to the invention operate independently of each other under a unified control system.
  • Chip processing device 30 includes a gripper 31 that grabs a wafer from a wafer cassette. As shown in FIG. 4, the grip 31 is supported on a slide rail 32 and movable along the slide rail 32.
  • the gripper 31 moves along the slide rail 32 to the wafer cassette, and after grabbing a wafer from the wafer cassette, the wafer is moved to the wafer table and placed on the wafer table 33, and then Continue moving away from wafer table 33 to safety Full position.
  • Wafer table 33 can be moved vertically and rotated to align the position of the wafer.
  • the camera on wafer table 33 will then detect the wafer to find a chip in good condition. Once the chip in good condition is found, the ejector 34 on the wafer table 33 separates the chip from the wafer.
  • the chip processing apparatus 30 further includes a gripper 36, a first picking platform 37, and a second picking platform 37'.
  • the gripper 36 is used to grasp the chips that have been separated on the wafer table 33 and placed on the stations on the picking platforms 37 and 37'.
  • the first picking platform 37 and the second picking platform 37' shown in the figures have the same structure and function, both for receiving the chip transferred by the gripper 36.
  • the picking platform 37 is provided with a plurality of stations 39
  • the picking platform 37' is also provided with a plurality of stations 39', each station for placing one chip. The number of stations on each picking platform is fixed.
  • a variety of platens can be provided, each with a different number of stations, so that the platen with the corresponding number of stations can be selected as needed before operation.
  • a vacuum device may be disposed on the pickup platform for fixing the chip placed on the platen.
  • Each of the picking platforms of the chip package apparatus according to the present invention is movable between a loading position and a picking position, the picking platform being adapted to be loaded with a plurality of the chips when in the loading position, the picking platform When in the picking position, it is suitable for the plurality of bonding heads to simultaneously pick up a plurality of the chips at a time.
  • each picking platform can be adjusted in its vertical direction. When it is lowered to a height close to the gripper 36, that is, to reach the loading position, the hand 36 can place the chips one by one on the picking platform. On the bit.
  • the plurality of bonding heads can simultaneously pick up and transfer the chips on the picking platform to the substrate at one time.
  • the first picking platform 37 and the second picking platform 37' are disposed to be alternately in the loading position and the picking position. That is, when the first picking platform 37 is in the lower loading position, the second picking platform 37' is in the upper picking position, and when the first picking platform 37 is filled with the chip and raised to the picking position for the picking head to pick up At this time, the chip on the second pick-up platform 37' has been removed by the bonding head and lowered to the lower loading position for the gripper to load the chip.
  • Such an arrangement can effectively provide processing efficiency of the device.
  • the pick-up head needs to check a plurality of chips on the pick-up platform one by one to determine whether the position and the like meet the requirements and make corresponding adjustments when picking up the chip, which makes the grabbing step very time consuming. It is conceivable that in a chip package device in which only one pick-up platform is provided, the chip separation step of the chip processing device must be stopped to wait for the completion of the chip capture step.
  • the platform is arranged to be alternately in the loading position and the picking position such that when one picking platform completes the loading step and continues the picking step, the chip processing device can continue to operate, performing a chip loading step on the other picking platform, thereby implementing the chip processing device
  • the uninterrupted work effectively provides the overall processing efficiency of the chip packaging equipment.
  • the chip transfer device 40 mainly includes a plurality of bonding heads 41 (six in the drawing) and a driving mechanism (not shown) and a camera 47 mounted together.
  • the camera 47 is used to check whether the position of the chip on the pickup platform meets the requirements or the like.
  • the bonding head 41 is mounted on a beam 42 while the two ends of the beam 42 are mounted on the two longitudinal rails 43, respectively.
  • the plurality of bond heads 41 can be moved together along the beam 42 in the length direction of the beam 42, and the beam 42 can be moved along the longitudinal rails 43, thereby enabling the plurality of bond heads 41 to be horizontal together. Move horizontally and vertically.
  • the plurality of bonding heads 41 are disposed to be independently movable in the vertical direction with respect to the beam 42, and the plurality of bonding heads 41 are disposed to be independently rotatable about respective axes . Accordingly, the bonding head 41 has sufficient freedom of movement to perform any fine movement to complete a precise operation process. Further, the bonding heads 41 can also be arranged such that the horizontal distance between each other can be adjusted such that the position of each of the bonding heads 41 is aligned with the position of the corresponding station 39 of the platen 38 on the picking platform 37.
  • a plurality of bond heads on a chip transfer device on a device in accordance with the present invention are configured to pick up a plurality of said chips simultaneously from each picking platform at a time.
  • the position of each of the bond heads 41 on the chip transfer device is aligned with the position of the chip 70 on the platen of the pick-up platform 37 so that the plurality of bond heads can be disposable from the pick-up platform
  • a plurality of the chips 70 are picked up at the same time.
  • the bonding head directly detects, selects, aligns, and picks up the chip one by one from the wafer, which can greatly improve the production efficiency of the device.
  • FIG. 9 shows a schematic diagram of a bonding platform 50 in the chip package apparatus shown in FIG. 1.
  • the bonding platform 50 is disposed at a substantially intermediate position of the chip package device, as shown in FIG.
  • the bonding platform 50 includes a support plate 51 for supporting the substrate.
  • the support plate 51 is provided with a plurality of vacuum holes 53 for providing a negative pressure to provide a negative pressure to adsorb and fix the substrate on the support plate 51.
  • a plurality of struts 54 that can be controlled to move up and down are also provided on the support plate 51.
  • Below the support plate is provided a heating plate 52 which can be activated to heat the support plate 51.
  • the robot 12 grabs the substrate from the substrate holder 11 and places it above the support plate 51, at which time the post 54 is raised above the surface of the support plate, so the substrate is actually supported by the support With. After the machine The robot 12 is removed and the post 54 is retracted below the support plate so that the wafer is supported by the support plate. Thereafter, the heating means, i.e., the heating plate 52, is activated, and the heat of the heating plate 52 is transferred to the support plate 51 and further transferred to the substrate. When the substrate is heated to a suitable temperature, the chip attached to the substrate is firmly bonded to the substrate because the adhesive at the bottom is melted.
  • the heating means i.e., the heating plate 52
  • FIGS 10A-10C illustrate several specific scenarios that can be implemented using the chip package device of the present invention.
  • the apparatus of the present invention can be used to bond the same chip 70 to the substrate 80, in this case, as long as the first chip supply device and the second chip supply device respectively provide the same during processing.
  • the wafer is ready, and the same chip is processed by two independently operating chip processing devices and chip transfer devices and transferred to the single substrate for bonding.
  • 10B and 10C by providing different wafers in the first chip supply device and the second chip supply device, the different chips D1 and D2 are processed by two independently working chip processing devices and chip transfer devices.
  • FIG. 10B realizes that different chips are respectively bonded to the substrate
  • FIG. 10C realizes that one chip D1 is superposed and bonded to the other chip D2.
  • a method for packaging a chip according to the present invention will be described in detail below.
  • the method is specifically implemented in accordance with the flow shown in FIG. 11, and the method is accomplished by the apparatus shown in FIG.
  • the chip packaging method of the present invention can also be used to package suitable components other than the chip, and can also be implemented using other devices than the device shown in FIG.
  • the main steps of the exemplary method are listed in detail.
  • the chip package device is activated, the first pick-up platform in the chip processing device is lowered to the loading position, and the second pick-up platform is raised to the pick-up position.
  • the gripper in the chip processing device of the device will grab the wafer from the wafer cassette under the control of the control system of the device, and place the wafer on the wafer table, and the wafer table will open the wafer. Let the camera detect the wafer, find the chip in good condition, and separate the chip from the wafer through the ejector.
  • the gripper then grabs the separated chip and places it on the designated station of the first picking platform.
  • the first picking platform rises to the picking position, and the bonding head moves over the first picking platform, and the cameras therein detect one by one whether the positions of the respective chips are aligned one by one. .
  • the plurality of bonding heads simultaneously pick up the plurality of chips on the first picking platform, and then continue to move over the bonding platform, and place the plurality of chips one by one on the base. The predetermined location on the film.
  • the second picking platform 37' When the first picking platform is filled with chips and raised to the picking position for picking up by the bonding head, the second picking platform 37' is lowered to the loading position, and the gripper then grabs and places the separated chips into the second picking At the designated station of the platform until the second picking platform is filled with chips.
  • the system of the device can be set such that when one of the pick-up platforms is full of chips, the chip on the other pick-up platform is just detected and removed by the chip transfer device.
  • the chip on the first pick-up platform is just removed by the bond head and lowered to the loading position.
  • the chip processing device since two pickup platforms are provided, and the two pickup platforms are disposed alternately in the loading position and the pickup position, when the pickup step is completed by one pickup platform and the pickup step is continued, the chip processing device The operation can be continued, and the chip loading step is implemented on another picking platform, thereby realizing the uninterrupted work of the chip processing device, and effectively providing the overall processing efficiency of the chip packaging device.

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Abstract

一种芯片封装设备,包括:至少一个芯片供给装置;至少一个芯片处理装置,其被构造成处理对应的芯片供给装置所提供的芯片;至少一个芯片移送装置,每个芯片移送装置分别具有多个键合头,每个键合头用于移送经相应的芯片处理装置处理后的一个芯片;其中,每个芯片处理装置包括至少两个拾取平台,每个拾取平台被构造成可同时布置多个芯片,并且相应的芯片移送装置上的多个键合头被构造成可从每个拾取平台一次性同时拾取多个芯片。以及一种用于封装芯片的方法。

Description

芯片封装设备及其方法 技术领域
本发明涉及半导体工业先进封装领域,尤其涉及一种用于芯片封装的设备以及方法。
背景技术
微电子电路的生产包括芯片的封装,即将芯片安装至基片或晶圆上。其中,基片起着安放、固定、保护芯片和增强电热性能等的作用,同时还是沟通芯片内部世界与外部电路的桥梁,芯片上的接点电连接到基片,再通过基片与其他器件建立电连接。因此,封装对集成电路起着重要的作用。封装的方式有很多,包括引线键合、脚带自动键合、倒装键合、正装键合等。在倒装键合工艺中,芯片被布置在基片上并且芯片的用于与外部部件形成电连接的凸点朝下,即朝向基片,其基本工作流程包括从晶圆拾取芯片、翻转芯片使其上下方向颠倒过来、施加助焊剂至芯片、在检测摄像头处对准位置、将芯片键合至基片上。而在正装键合工艺中,芯片被布置在基片上并且芯片的凸点是朝上的,也即芯片的凸点背离基片。所以,与倒装键合工艺相比,正装键合工艺不需要翻转芯片的步骤。
当前,使用微电子芯片的电子产品的消费需求不断增加,而产品之间的竞争也越来越激烈。一种微电子产品想要在这残酷的竞争中获胜,产品的上市时间是一个关键。也就是说,产品从设计到上市的这一过程必须尽可能短,以能推出在设计上最为新颖并且在技术上最为领先的产品。为此,微电子产品的生产厂家一直渴望能够有更为创新的技术来提高产品的生产效率,降低单位产品成本,以提供技术上尽可能领先、性价比尽可能高的产品,来提高其产品的市场竞争优势,满足市场的巨大消费需求。此外,还希望产品具有更为强大的功能。为实现此目的,其中的一个手段是将不同类型的芯片键合至同一个基片上,以获得能够完成更为复杂的任务的电路。
在现有技术中,芯片封装设备通常包括单个键合头,该单个键合头重复地在晶圆与基片之间运动,键合头在每一个循环中可以键合一个芯片至基片上。对于所述传统的键合设备而言,如果想要提高生产效率,只有加快设备的运行速度。但是在生产实践中已经发现,通过提高机器速度来获得更高的生产效率的效果十分有限,因为芯片是逐个地被拾取和键合,针对在后芯片的工作循环必须在针对在先芯片的工作循环完成之后才能开始。
此外,传统的芯片封装设备在一个工作流程中只能处理一种晶圆,从而只能将一种芯片键合至一个基片上。如果想要将多种芯片同时键合至同一个基片上,需要将多台设备连线组装在一起。这种通过将多台设备连线组合的方式使得生产线变得十分庞大复杂,而且可靠性难以得到保证。
为此,现有技术中仍然存在着进一步提高芯片封装生产效率的技术需求,同时也还希望能够以单个设备来处理更为复杂的封装生产任务。
发明内容
在一个方面,本发明提供了一种芯片封装设备,包括:至少一个芯片供给装置;至少一个芯片处理装置,其被构造成处理对应的芯片供给装置所提供的芯片;至少一个芯片移送装置,每个芯片移送装置分别具有多个键合头,每个键合头用于移送经相应的芯片处理装置处理后的一个所述芯片;其中,每个所述芯片处理装置包括至少两个拾取平台,每个拾取平台被构造成可同时布置多个所述芯片,并且相应的芯片移送装置上的多个键合头被构造成可从每个拾取平台一次性同时拾取多个所述芯片。
在依据本发明的芯片封装设备中,由于设置有至少两个拾取平台,可将多个拾取平台设置为轮流进行芯片装载,从而实现芯片处理装置的不间断工作,有效地提高芯片封装设备的整体加工效率。
同时,由于在该芯片封装设备的芯片处理装置中的拾取平台可同时布置多个芯片,设备中的芯片移送装置的多个键合头被设置成具有与拾取平台上的多个芯片在位置上相互对应,从而所述多个键合头可从所述拾取平台一次性同时拾取多个所述 芯片。这样的构造相比现有技术中键合头直接从比如晶圆中逐个地检测、选择、对准和拾取芯片的技术方案,可以极大地提高设备的生产效率。
优选地,每个所述芯片处理装置包括第一拾取平台和第二拾取平台,相应的芯片移送装置依次从所述第一拾取平台和第二拾取平台拾取多个芯片。由于设置有两个拾取平台,并且两个拾取平台被设置成交替地处于装载位置和拾取位置,使得在一个拾取平台完成装载步骤而继续进行拾取步骤时,芯片处理装置可以继续工作,对另一个拾取平台实施芯片装载步骤,从而实现芯片处理装置的不间断工作,有效地提供芯片封装设备的整体加工效率。
优选地,每个所述拾取平台可在装载位置和拾取位置之间运动,所述拾取平台在处于所述装载位置时适于被布置多个所述芯片,所述拾取平台在处于所述拾取位置时适于让所述多个键合头一次性地同时拾取多个所述芯片。
优选地,每个所述芯片处理装置被设置成所述第一拾取平台和第二拾取平台交替地处于装载位置和拾取位置。
优选地,所述芯片封装设备具有独立工作的第一芯片供给装置和第二芯片供给装置。
优选地,所述第一芯片供给装置和第二芯片供给装置分别提供不同的芯片。
优选地,所述芯片封装设备具有独立工作的第一芯片处理装置和第二芯片处理装置,其分别处理相应的第一芯片供给装置和第二芯片供给装置所提供的芯片。
优选地,所述芯片封装设备具有独立工作的第一芯片移送装置和第二芯片移送装置,其分别移送经相应的第一芯片处理装置和第二芯片处理装置处理后的芯片。
优选地,所述芯片封装设备还包括键合平台,基片被布置在所述键合平台上,并且所述芯片被所述键合头键合至所述基片上。
优选地,所述键合平台上设置有加热装置,该加热装置适于加热布置于键合平台上的基片以使其与芯片粘合。
在另一个方面,本发明提供一种用于封装芯片的方法,包括:提供第一芯片处理装置,该第一芯片处理装置包括第一拾取平台和第二拾取平台;使所述第一拾取平台和第二拾取平台交替地处于装载位置和拾取位置,其中,所述拾取平台在处于 所述装载位置时适于被布置多个所述芯片,所述拾取平台在处于所述拾取位置时适于让芯片移送装置的多个键合头一次性地同时拾取多个所述芯片。
优选地,还提供第二芯片处理装置,该第二芯片处理装置与所述第一芯片处理装置独立地处理不同的芯片。
优选地,还包括提供键合平台,该键合平台用于布置晶圆,所述芯片被所述键合头键合至所述晶圆上。
优选地,还包括启动键合平台上的加热装置,以加热布置于键合平台上的晶圆从而使芯片粘结至晶圆上。
优选地,所述芯片移送装置上还设置有摄像装置,该摄像装置用于对所述拾取平台上的多个芯片逐一地进行检测以确定各个芯片的位置是否符合要求。
优选地,所述芯片移送装置逐一地将芯片放置到基片上以实施键合。
本发明的其他方面以及进一步的优点将在下文中参考具体实施例以及附图进行说明。
附图说明
图1示出了根据本发明的一个实施例的芯片封装设备的透视图;
图2为图1所示芯片封装设备的局部透视图,其中的部分壳体和组件已被去除,以能更好地示出其内部构造;
图3为图1所示芯片封装设备的俯视图,其中的部分壳体和组件已被去除,以能更好地示出其内部构造;
图4为图1中的芯片封装设备的芯片供给装置和芯片处理装置的一部分的透视图;
图5为图1中的芯片封装设备的芯片处理装置的一部分的透视图;
图6为图1所示芯片封装设备的局部放大透视图,其中主要示出了芯片移送装置;
图7为图6中的芯片移送装置的键合头部分的局部放大透视图;
图8为图1中的芯片封装设备的多个键合头在拾取芯片时的示意图;
图9为图1中的芯片封装设备的键合平台部分的示意图;
图10A-10C例示了可使用本发明的设备实施的几种键合情形;
图11为根据本发明的用于封装芯片的方法的一个实施例的流程框图。
具体实施方式
在详细解释本发明的任何实施例之前,应当明白,本发明的应用不限于在以下描述中所讨论的以及在附图中所示出的有关产品构造和方法流程的细节。本发明能够具有其它的实施例,并能够以各种不同的方式来实践或实施。
在本文中,术语“芯片”也可根据具体情况被称为“管芯”,但是,本领域技术人员可以明白,适用于本发明的设备和方法的元器件或产品包括管芯或芯片,例如包括但不限于:集成电路(IC)、分立器件、模组、模块等,这些元器件或产品均应当视为“芯片”或“管芯”在此语境下的等同方式。
在本文中,除非另有特别说明,术语“上”、“下”、“左”、“右”、“前”、“后”、“里”、“外”、“横向”、“纵向”、“中间”、“侧向”等均是相对附图的页面所显示的方位所做的描述。
在本文中,术语“第一”、“第二”等的使用仅仅是为了区分不同的部件或步骤,以表示这些部件或步骤相互独立,但不能用于解释这些部件或步骤之间存在有关重要性、次序、位置等方面的限定。
根据本发明的芯片封装设备以及方法可用于加工多种合适的芯片。然而,作为举例,下文仅以集成芯片的加工来具体描述其具体实施例。本领域技术人员根据本发明的精神和原理将明白,这些实施例中的芯片也可替换为其他合适的芯片,而这样的实施方式也是落入本发明的范围内的。
图1示出了根据本发明的一种具体的芯片封装设备。整体而言,在横向上,该芯片封装设备主要由芯片供给部分A、芯片加工部分C和基片供给部分B组成,其中基片供给部分B包括基片支架11和机械手12。在加工过程时,晶圆盒被提供至芯片供给部分A内,而机械手12从基片支架11处取得基片并放置于加工部分C内 的规定位置,之后完成加工处理,也即晶圆上的芯片被键合至基片上,直至完成所需的封装。图中示出的设备具有安装在框架上的外壳和众多可以打开并关闭的门,比如晶圆盒装载门、横梁门等,这些门或者用来装载物件比如芯片或基片,或者用于安装、观察或检修设备的各个模块或部件。所以,这些门的设置可以根据具体需要进行设置,并且可以设置成仅仅在所有的门均被安全关闭时才能启动设备并进行加工操作。
需要说明的是,本领域技术人员可以明白,本文所述的基片泛指一切可用于承载芯片或其他微电子元件的载体,比如其可以是基底、基板、晶圆等。
参照图2,其为图1中所示芯片封装设备在部分罩壳已被去除后的示意图,并且还去除了基片供给部分B中的基片支架11和机械手12,以能更好地示出其内部构造。继续参见图3,其为图1中所示芯片封装设备在部分罩壳已被去除后的俯视图。结合图2和图3可以看出,芯片供给部分A包括沿纵向对称布置的独立工作的第一芯片供给装置20和第二芯片供给装置20’,加工部分C包括对称布置并且独立工作的第一芯片处理装置30和第二芯片处理装置30’、第一芯片移送装置40和第二芯片移送装置40’。本领域技术人员根据本发明的精神和原理将明白,根据本发明的芯片封装设备也可以仅仅具有一个或者多于两个芯片供给装置、芯片处理装置、芯片移送装置,这样的实施方式也均落入本发明的范围内。根据本发明的芯片封装设备的第一芯片供给装置20和第二芯片供给装置20’、第一芯片处理装置30和第二芯片处理装置30’、第一芯片移送装置40和第二芯片移送装置40’可以分别基本相同,也可以不相同。在本实施例中,所述装置为相同,所以在以下的描述中将仅仅以第一芯片供给装置20、第一芯片处理装置30、第一芯片移送供给装置40来进行介绍。另外,根据本发明的设备中的各个装置是在统一的控制系统下相互独立工作的。
参见图4,其为图1中的芯片封装设备的芯片供给装置20和芯片处理装置30的一部分的透视图。如图所示,芯片供给装置20中的装载台21用于装载晶圆盒,并且装载台21可竖向移动以调节至合适高度。芯片处理装置30包括从晶圆盒抓取晶圆的抓手31。如图4所示,抓手31支撑在一个滑轨32上并可沿滑轨32移动。在需要抓取晶圆时,抓手31沿滑轨32向晶圆盒移动,在从晶圆盒抓取到一片晶圆后再向晶圆台移动并将晶圆放置在晶圆台33上,然后继续移动远离晶圆台33至安 全位置。晶圆台33可以竖向移动并且转动,以对准晶圆的位置。然后,晶圆台33上的摄像头将检测晶圆以寻找状态良好的芯片。一旦找到状态良好的芯片,晶圆台33上的推出器34将该芯片与晶圆分离。
参见图5,其为图1中的芯片封装设备的芯片处理装置30的另外一部分的透视图。如图5所示,芯片处理装置30进一步包括抓手36、第一拾取平台37和第二拾取平台37’。所述抓手36用于抓取晶圆台33上已被分离的芯片并放置在拾取平台37和37’上的工位上。而图中示出的第一拾取平台37和第二拾取平台37’具有相同的结构和功能,均用于接纳抓手36所移送的芯片。如图所示,拾取平台37上设置有多个工位39,而拾取平台37’上也设置有多个工位39’,每个工位用于放置一个芯片。每个拾取平台上的工位数量是固定的。为此,可以提供多种台板,每种台板上设置有不同数量的工位,从而可以在操作前按照需要选择具有相应工位数量的台板。此外,所述拾取平台上可以设置真空装置,以用于固定被放置在台板上的芯片。
依据本发明的芯片封装设备的每个所述拾取平台可在装载位置和拾取位置之间运动,所述拾取平台在处于所述装载位置时适于被加载多个所述芯片,所述拾取平台在处于所述拾取位置时适于让所述多个键合头一次性地同时拾取多个所述芯片。继续参见图5,每个拾取平台是可以沿竖向调节其高度的,当其降低至接近抓手36的高度时,即为达到装载位置,转手36可以将芯片逐个放置在拾取平台的各个工位上。相反地,当拾取平台升起至接近键合头的位置时,即为达到拾取位置,所述多个键合头可以一次性地同时将拾取平台上的芯片拾起并移送至基片。另外,所述第一拾取平台37和第二拾取平台37’被设置成交替地处于装载位置和拾取位置。也就是说,当第一拾取平台37处于下方的装载位置时,第二拾取平台37’处于上方的拾取位置,而当第一拾取平台37装满芯片并上升至拾取位置以供键合头拾取时,第二拾取平台37’上的芯片已被键合头取走而下降至下方的装载位置以供抓手加载芯片。这样的设置可以有效地提供设备的加工效率。键合头在拾取芯片时需要对拾取平台上的多个芯片逐个进行检查以确定其位置等各个方面是否符合要求并做出相应的调整,这使得抓取步骤十分花费时间。可以想象,在仅仅设置一个拾取平台的芯片封装设备中,芯片处理装置的芯片分离步骤必须停止,以等待芯片抓取步骤的完成。相反地,在本发明中,由于设置有两个拾取平台,并且两个拾取 平台被设置成交替地处于装载位置和拾取位置,使得在一个拾取平台完成装载步骤而继续进行拾取步骤时,芯片处理装置可以继续工作,对另一个拾取平台实施芯片装载步骤,从而实现芯片处理装置的不间断工作,有效地提供芯片封装设备的整体加工效率。
现参见图6和图7,详细介绍芯片封装设备中的芯片移送装置40。如图所示,芯片移送装置40主要包括安装在一起的多个键合头41(在图中为6个)和驱动机构(未示出)以及摄像头47。该摄像头47用于检查拾取平台上的芯片的位置是否符合要求等。键合头41安装在一根横梁42上,同时该横梁42的两端分别安装在两根纵向导轨43上。所述多个键合头41可一起在横梁42的长度方向上沿横梁42移动,而该横梁42可沿所述纵向导轨43移动,从而实现所述多个键合头41可一起在水平的横向和纵向上移动。另外,所述多个键合头41被设置成可分别独立地在竖直方向上相对所述横梁42移动,并且所述多个键合头41被设置成可分别独立地绕各自的轴线旋转。据此,所述键合头41具有充分的移动自由度来完成任何细微的运动,以完成精密的操作过程。此外,键合头41还可被设置成相互之间的水平距离可被调节,使得每个键合头41的位置对准拾取平台37上的台板38的相应工位39的位置。
根据本发明的设备上的芯片移送装置上的多个键合头被构造成可从每个拾取平台一次性同时拾取多个所述芯片。参照图8,所述芯片移送装置上的各个键合头41的位置与拾取平台37的台板上的芯片70的位置对准,从而所述多个键合头可从所述拾取平台一次性同时拾取多个所述芯片70。这样的构造相比现有技术中键合头直接从比如晶圆中逐个地检测、选择、对准和拾取芯片的技术方案,可以极大地提高设备的生产效率。
图9示出了图1所示芯片封装设备中的键合平台50的示意图。该键合平台50布置于芯片封装设备的大致中间位置,如图1所示。参见图9,键合平台50包括用于支撑基片的支撑板51。支撑板51上设置有可提供负压的多个真空孔53,以提供负压而将基片吸附固定在支撑板51上。支撑板51上还设置有可被控制上下移动的多个支柱54。支撑板下方设置有加热板52,其可被启动以对支撑板51加热。在操作的过程中,机械手12从基片支架11处抓取基片并放置在支撑板51上方,此时支柱54是升起至支撑板的表面之上的,所以基片实际上被支柱支撑着。之后,机 械手12离开,支柱54缩回至支撑板之下,使得晶片被支撑板支撑。之后,启动加热装置即加热板52,加热板52的热量传递至支撑板51,并进一步传递至基片。当基片被加热到合适温度时,附接至基片上的芯片因为底部的粘结剂被熔化而被牢固地粘结至基片上。
图10A-10C示出了可使用本发明的芯片封装设备进行实施的几种具体情形。如图10A所示,本发明的设备可用于将相同的芯片70键合至基片80上,此时,只要在加工的过程中使第一芯片供给装置和第二芯片供给装置分别提供相同的晶圆即可,相同的芯片被两个独立工作的芯片处理装置和芯片移送装置处理并移送至所述单个基片上进行键合。再如图10B和10C所示,通过在第一芯片供给装置和第二芯片供给装置分别提供不同的晶圆,不同的芯片D1和D2被两个独立工作的芯片处理装置和芯片移送装置处理并移送至所述单个基片上进行键合,也就是说,该实施例实现了单机同时处理两种不同的芯片,并且实现了在同一个基片上同时键合两种不同的芯片。其中,图10B实现的是不同的芯片分别均键合至基片上,而图10C实现的是一个芯片D1被叠加键合至另一个芯片D2上。本领域技术人员基于本发明的精神和原理可以想到,还可以在芯片封装设备上加入更多的装置,从而可以在同一基片上键合更多不同类别的芯片,以实现更为复杂的加工。
以下将详细描述根据本发明的用于封装芯片的方法。作为举例,该方法是具体按照如图11所示的流程来完成的,并且该方法是通过如图1所示的设备来完成的。但是,需要指出的是,本发明的芯片封装方法也可以用于封装芯片之外的合适元器件,并且也可以使用不同于如图1所示的设备的其他装置来实现。
参照图11,其中详细列出了所述例示性方法的主要步骤。为进行加工操作,首先需要在芯片供给部分加入晶圆盒,并且通过机械手将基片装载至键合平台。之后,启动芯片封装设备,芯片处理装置中的第一拾取平台下降至装载位置,而第二拾取平台上升至拾取位置。与此同时,设备的芯片处理装置中的抓手将在设备的控制系统的控制下从晶圆盒中抓取晶圆,并将该晶圆放置在晶圆台上,晶圆台将晶圆张开以让摄像头检测晶圆,找出状态良好的芯片,并通过推出器将芯片从晶圆分离。之后,抓手将分离出的芯片抓取并放置到第一拾取平台的指定工位上。当有足够的芯片被装载至第一拾取平台上时,第一拾取平台上升至拾取位置,而键合头移动至第一拾取平台上方,通过其中的摄像头逐个地检测各个芯片的位置是否对准。在各个 芯片的位置符合要求后,所述多个键合头同时将第一拾取平台上的多个芯片同时抓起,之后继续移动至键合平台上方,并将所述多个芯片逐个地放置在基片上的预定位置。在所述第一拾取平台装满芯片并上升至拾取位置以供键合头拾取时,第二拾取平台37’下降至装载位置,抓手进而将分离出的芯片抓取并放置到第二拾取平台的指定工位上,直至第二拾取平台被装满芯片。作为举例,可对设备的系统进行如下设定,即,在其中一个拾取平台装满芯片时,另一个拾取平台上的芯片正好被芯片移送装置检测完毕并取走。从而,当第二拾取平台被装满芯片而上升至拾取位置时,第一拾取平台上的芯片正好被键合头取走而下降至装载位置。这样,在本发明中,由于设置有两个拾取平台,并且两个拾取平台被设置成交替地处于装载位置和拾取位置,使得在一个拾取平台完成装载步骤而继续进行拾取步骤时,芯片处理装置可以继续工作,对另一个拾取平台实施芯片装载步骤,从而实现芯片处理装置的不间断工作,有效地提供芯片封装设备的整体加工效率。
以上已经通过一个或多个优选实施例和一个或多个替代性的实施例描述了本发明。此外,还描述了本发明的多个方面。本领域技术人员在任何情况下均不应当将所述多个方面或实施例解释为是限制性的,而应当解释为是示例性的。很清楚的是,本发明的范围将根据权利要求来确定。

Claims (16)

  1. 一种芯片封装设备,包括:
    至少一个芯片供给装置(20);
    至少一个芯片处理装置(30),其被构造成处理对应的芯片供给装置(20)所提供的芯片(70,D1,D2);
    至少一个芯片移送装置(40),每个芯片移送装置(40)分别具有多个键合头(41),每个键合头(41)用于移送经相应的芯片处理装置(30)处理后的一个所述芯片(70,D1,D2);
    其中,每个所述芯片处理装置(30)包括至少两个拾取平台(37,37’),每个拾取平台(37,37’)被构造成可同时布置多个所述芯片(70,D1,D2),并且相应的芯片移送装置(40)上的多个键合头(41)被构造成可从每个拾取平台(37,37’)一次性同时拾取多个所述芯片(70,D1,D2)。
  2. 根据权利要求1所述的芯片封装设备,其特征在于,每个所述芯片处理装置(30)包括第一拾取平台(37)和第二拾取平台(37’),相应的芯片移送装置(40)依次从所述第一拾取平台(37)和第二拾取平台(37’)拾取多个所述芯片(70,D1,D2)。
  3. 根据权利要求2所述的芯片封装设备,其特征在于,每个所述拾取平台(37,37’)可在装载位置和拾取位置之间运动,所述拾取平台(37,37’)在处于所述装载位置时适于被加载多个所述芯片(70,D1,D2),所述拾取平台(37,37’)在处于所述拾取位置时适于让所述多个键合头一次性地同时拾取多个所述芯片(70,D1,D2)。
  4. 根据权利要求3所述的芯片封装设备,其特征在于,每个所述芯片处理装置(30)被设置成所述第一拾取平台(37)和第二拾取平台(37’)交替地处于装载位置和拾取位置。
  5. 根据权利要求1所述的芯片封装设备,其特征在于,所述芯片封装设备具有独立工作的第一芯片供给装置(20)和第二芯片供给装置(20’)。
  6. 根据权利要求5所述的芯片封装设备,其特征在于,所述第一芯片供给装置(20)和第二芯片供给装置(20’)分别提供不同的芯片(70,D1,D2)。
  7. 根据权利要求5所述的芯片封装设备,其特征在于,所述芯片封装设备具有独立工作的第一芯片处理装置(30)和第二芯片处理装置(30’),其分别处理相应的第一芯片供给装置(20)和第二芯片供给装置(20’)所提供的芯片(70,D1,D2)。
  8. 根据权利要求7所述的芯片封装设备,其特征在于,所述芯片封装设备具有独立工作的第一芯片移送装置(40)和第二芯片移送装置(40’),其分别移送经相应的第一芯片处理装置(30)和第二芯片处理装置(30’)处理后的芯片。
  9. 根据权利要求1所述的芯片封装设备,其特征在于,所述芯片封装设备还包括键合平台(50),基片(80)被布置在所述键合平台(50)上,所述芯片被所述键合头(41)键合至所述基片(80)上。
  10. 根据权利要求9所述的芯片封装设备,其特征在于,所述键合平台(50)上设置有加热装置(52),该加热装置(50)适于加热布置于键合平台(50)上的基片(80)以使其与芯片(70,D1,D2)粘合。
  11. 一种用于封装芯片的方法,包括:
    提供第一芯片处理装置,该第一芯片处理装置包括第一拾取平台和第二拾取平台;
    使所述第一拾取平台和第二拾取平台交替地处于装载位置和拾取位置,其中,所述拾取平台在处于所述装载位置时适于被加载多个所述芯片,所述拾取平台在处于所述拾取位置时适于让芯片移送装置的多个键合头一次性地同时拾取多个所述芯片。
  12. 根据权利要求11所述的方法,其特征在于,还提供第二芯片处理装置,该第二芯片处理装置与所述第一芯片处理装置独立地处理不同的芯片。
  13. 根据权利要求11所述的方法,其特征在于,还包括提供键合平台,该键合平台用于布置晶圆,所述芯片被所述键合头键合至所述晶圆上。
  14. 根据权利要求13所述的方法,其特征在于,还包括启动键合平台上的加热装置,以加热布置于键合平台上的晶圆从而使芯片粘结至晶圆上。
  15. 根据权利要求11所述的方法,其特征在于,所述芯片移送装置上还设置有摄像装置,该摄像装置用于对所述拾取平台上的多个芯片逐一地进行检测以确定各个芯片的位置是否符合要求。
  16. 根据权利要求11所述的方法,其特征在于,所述芯片移送装置逐一地将芯片放置到基片上以实施键合。
PCT/CN2016/076233 2016-03-14 2016-03-14 芯片封装设备及其方法 WO2017156671A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466801A (zh) * 2021-01-29 2021-03-09 四川晶辉半导体有限公司 一种贴片二极管引线框架输送装置
US11774935B2 (en) 2016-10-08 2023-10-03 Capcon Limited Apparatus, control method and control device of semiconductor packaging

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11201807973RA (en) * 2016-03-14 2018-10-30 Capcon Ltd Chip packaging apparatus and method thereof
CN109461667A (zh) * 2018-12-06 2019-03-12 深圳市佳思特光电设备有限公司 半导体芯片封装键合设备及实现方法
CN111261558B (zh) * 2020-01-21 2022-11-15 深圳中科系统集成技术有限公司 一种微电子器件一体化辅助封装装置
CN113314441B (zh) * 2021-05-28 2024-03-08 安徽光智科技有限公司 元器件封装设备及其使用方法
KR102631885B1 (ko) 2023-06-13 2024-02-01 주식회사 모든다해 분광화상을 이용한 전지셀 이물 검출 방법 및 장치
CN117059519B (zh) * 2023-08-09 2024-04-26 广东省航瑞智能科技有限公司 一种多功能芯片组装一体机
CN117497434B (zh) * 2023-12-29 2024-04-09 砺铸智能设备(天津)有限公司 一种芯片倒装设备及其方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339771A (zh) * 2011-09-30 2012-02-01 中南大学 一种双焊线头引线键合装置
CN104183527A (zh) * 2013-05-28 2014-12-03 北京中电科电子装备有限公司 工件键合系统
CN104701199A (zh) * 2015-03-20 2015-06-10 北京中电科电子装备有限公司 一种倒装芯片键合设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3271461B2 (ja) 1995-02-07 2002-04-02 松下電器産業株式会社 半田ボールの搭載装置および搭載方法
KR0175267B1 (ko) * 1995-09-30 1999-04-01 김광호 회전운동을 하는 픽업 툴을 구비하는 다이 본딩 장치
US5671530A (en) * 1995-10-30 1997-09-30 Delco Electronics Corporation Flip-chip mounting assembly and method with vertical wafer feeder
JPH1065392A (ja) * 1996-08-19 1998-03-06 Matsushita Electric Ind Co Ltd 電子部品供給装置及び電子部品実装方法
US20050045914A1 (en) * 2003-07-09 2005-03-03 Newport Corporation Flip chip device assembly machine
AT512859B1 (de) * 2012-05-11 2018-06-15 Hanmi Semiconductor Co Ltd Halbleiterchip Wende- und Befestigungseinrichtung
US20140341691A1 (en) * 2013-05-14 2014-11-20 Kui Kam Lam Bonding apparatus having a plurality of rotary transfer arms for transferring electronic devices for bonding
KR102121467B1 (ko) * 2016-01-22 2020-06-10 캡콘 리미티드 부품 패키징 장치 및 그 방법
SG11201807973RA (en) * 2016-03-14 2018-10-30 Capcon Ltd Chip packaging apparatus and method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339771A (zh) * 2011-09-30 2012-02-01 中南大学 一种双焊线头引线键合装置
CN104183527A (zh) * 2013-05-28 2014-12-03 北京中电科电子装备有限公司 工件键合系统
CN104701199A (zh) * 2015-03-20 2015-06-10 北京中电科电子装备有限公司 一种倒装芯片键合设备

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11774935B2 (en) 2016-10-08 2023-10-03 Capcon Limited Apparatus, control method and control device of semiconductor packaging
CN112466801A (zh) * 2021-01-29 2021-03-09 四川晶辉半导体有限公司 一种贴片二极管引线框架输送装置
CN112466801B (zh) * 2021-01-29 2021-04-20 四川晶辉半导体有限公司 一种贴片二极管引线框架输送装置

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