WO2017154893A1 - 電極接続構造、リードフレーム及び電極接続構造の形成方法 - Google Patents
電極接続構造、リードフレーム及び電極接続構造の形成方法 Download PDFInfo
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- WO2017154893A1 WO2017154893A1 PCT/JP2017/008970 JP2017008970W WO2017154893A1 WO 2017154893 A1 WO2017154893 A1 WO 2017154893A1 JP 2017008970 W JP2017008970 W JP 2017008970W WO 2017154893 A1 WO2017154893 A1 WO 2017154893A1
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- electrode
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- 238000000034 method Methods 0.000 title claims description 66
- 238000007747 plating Methods 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 41
- 230000000694 effects Effects 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005304 joining Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
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Definitions
- the present invention relates to an electrode connection structure for plating and connecting an electronic device electrode and / or a substrate electrode and a lead of a lead frame.
- Patent Document 1 As techniques for connecting electrodes by plating, techniques disclosed in Patent Documents 1 to 3 are disclosed.
- the technique shown in Patent Document 1 includes a lead for plating connection with a semiconductor electrode provided with a protrusion of the same material or electric conductor having a height of 5 to 200 ⁇ m by plating or bending at the tip of the lead, and a protrusion at the tip of the lead. Place the electrode on the semiconductor element at the same position and contact and fix it so that electrical continuity is obtained, soak it in a plating bath, or place it in a plating solution spray, and the electrode on the semiconductor element Are connected by plated metal
- Patent Document 2 The technique shown in Patent Document 2 is configured such that the plating 4 grows radially around the protrusion 3 between the semiconductor element 1 and the metal plate 2.
- Patent Document 1 the technique shown in Patent Document 1 is to provide a protrusion at the tip of the lead and connect it to the electrode by plating, and a longitudinal side surface of the lead in which a plurality of long leads are arranged in parallel. This is not applicable to the case where the electrode is connected by plating.
- the technique shown in Patent Document 2 is a technique of performing plating around a protrusion between a semiconductor element and a metal plate.
- the region where the metal plate is parallel is wide, and in such a region, the plating process speed varies, and voids may occur. Further, even if only the region where the semiconductor element and the metal plate are not parallel (only the protruding portion) is plated, the plating is insufficient and the thermal conductivity is poor and practical connection cannot be made.
- Patent Document 3 discloses a technique for plating the side surface portion of the copper wire and the copper plate, only the periphery of the contact portion between the arc portion on the side surface of the copper wire and the copper plate is plated. Although it is possible to prevent the generation of voids and the like, there is a problem that the thermal conductivity is lowered.
- the present invention provides an electrode connection structure or the like for connecting a long side surface of a lead having a plurality of long leads arranged in parallel and the electrode with high quality by plating.
- the electrode connection structure according to the present invention is an electrode connection structure in which an electronic device electrode and / or a substrate electrode and a lead of a lead frame are connected by plating, and a plurality of elongated leads in the lead frame are arranged in parallel.
- a longitudinal side surface of each lead and the electronic device electrode and / or the substrate electrode are plated and connected, and the electronic device electrode and / or the first connection surface of the substrate electrode connected to the lead;
- the connecting portion with the second connecting surface on the side surface in the longitudinal direction of the lead connected to the first connecting surface In the connecting portion with the second connecting surface on the side surface in the longitudinal direction of the lead connected to the first connecting surface, the outer side of the second connecting surface from the edge portion of the second connecting surface that contacts the first connecting surface The distance between the first connection surface and the second connection surface continuously increases toward the portion.
- the electronic device electrode and / or the substrate electrode and the lead frame in which a plurality of long leads are arranged in parallel are arranged on the side surface in the longitudinal direction of the lead.
- the first connection is made at the connection portion between the first connection surface of the electronic device electrode and / or the substrate electrode and the second connection surface on the side surface in the longitudinal direction of the lead connected to the first connection surface.
- the electronic device electrode and / or Alternatively it is possible to sufficiently distribute the plating solution between the substrate electrode and the side surface in the longitudinal direction of the lead, and there is an effect that high-quality plating connection can be realized without generating voids or the like.
- region from the edge part of the 2nd connection surface which contacts a 1st connection surface to the outer part of the said 2nd connection surface can be plated in a wide range, the connection excellent in thermal conductivity is performed. There is an effect that can be.
- the lead is thinned from the edge portion of the second connection surface toward the outer portion of the second connection surface.
- the longitudinal side surface of the lead is thinned from the edge portion of the second connection surface toward the outer portion of the second connection surface.
- the plating solution can be sufficiently circulated between the substrate electrode and the longitudinal side surface of the lead, and there is an effect that high-quality plating connection can be realized without generating voids or the like.
- the electrode connection structure according to the present invention is such that the edge portion is formed at the center in the longitudinal direction of the second connection surface.
- the edge portion is formed at the center in the longitudinal direction of the second connection surface, so that the wide region from the edge portion toward the outer side of the second connection surface can be obtained. It is possible to distribute the plating solution sufficiently and evenly, and there is an effect that a high-quality plating connection can be realized.
- a plurality of the edge portions are formed at predetermined intervals in the short direction of the second connection surface, and the short sides of the second connection surface are formed between the edge portions.
- a concave groove-like air gap penetrating in the direction is formed.
- the plurality of edge portions are formed at predetermined intervals in the short direction of the second connection surface, and the second connection surface is formed between the edge portions. Since a concave groove-shaped gap is formed that penetrates in the short direction, the plating process can be performed in a state where the plating solution is sufficiently distributed around the edge, realizing high-quality plating connection There is an effect that can be done. Further, by forming the concave groove-like gap, it is possible to disperse the stress applied in the longitudinal direction, and it is possible to prevent breakage of the lead and the like.
- the electrode connection structure according to the present invention is such that a continuous or discontinuous groove-like void is formed in the longitudinal direction of the second connection surface.
- the continuous or discontinuous concave groove-like voids are formed in the longitudinal direction of the second connection surface, so that the stress applied in the short direction can be dispersed. There is an effect that breakage of the lead and the like can be more reliably prevented.
- the electrode connection structure according to the present invention includes a third connection surface on the back surface side of the second connection surface, and the fourth connection surface of the electronic device electrode and / or the substrate electrode connected to the third connection surface.
- the distance between the fourth connection surface and the third connection surface is continuous from the edge portion of the third connection surface in contact with the fourth connection surface toward the outer portion of the third connection surface. Is increasing.
- the third connection surface on the back surface side of the second connection surface, the electronic device electrode connected to the third connection surface, and / or the fourth connection surface of the substrate electrode In the connecting portion, the distance between the fourth connecting surface and the third connecting surface continuously increases from the edge portion of the third connecting surface in contact with the fourth connecting surface toward the outer portion of the third connecting surface. Therefore, the electronic device electrode and / or the substrate electrode and the lead frame can be formed in multiple layers by high-quality plating connection.
- the plating connection is plating with a metal or alloy having a melting point of 700 ° C. or higher, preferably Ni or Ni alloy.
- the plating connection is plating with a metal or alloy having a melting point of 700 ° C. or higher, preferably Ni or Ni alloy, so that plating is performed in a plating solution at 100 ° C. or lower. Processing is performed, and an effect is obtained that damage due to stress or heat at the time of connection can be reduced.
- the plating process is performed with a high melting point metal or alloy, there is an effect that an accurate operation can be ensured even in a high temperature state.
- an angle formed by the electronic device electrode and / or the substrate electrode and the longitudinal side surface of the lead at the edge portion of the lead is 3 degrees to 15 degrees.
- the angle formed between the electronic device electrode and / or the substrate electrode and the longitudinal side surface of the lead at the edge portion of the lead is 3 degrees to 15 degrees,
- the electrode width can be increased with a short plating time, and the manufacturing efficiency can be improved.
- the edge portion is formed by pressing or etching.
- the edge portion is formed by pressing or etching, it is possible to efficiently form a high-quality electrode connection structure with a simplified manufacturing process. There is an effect that can be done.
- a method for forming an electrode connection structure according to the present invention is a method for forming an electrode connection structure for connecting an electronic device electrode and / or a substrate electrode and leads of a lead frame, wherein the lead frame has a plurality of elongated leads. Are arranged in parallel and have an edge portion on the side surface in the longitudinal direction of the lead, and the ultrasonic wave in a state where the electronic device electrode and / or the substrate electrode and the edge portion of the lead are in contact with each other. Vibration is applied to buckle the tip of the edge portion, and the electronic device electrode and / or substrate electrode and the lead are ultrasonically bonded.
- the method for forming an electrode connection structure is a method for forming an electrode connection structure for connecting an electronic device electrode and / or a substrate electrode and leads of a lead frame, wherein the lead frame has a plurality of lengths.
- the scale-shaped leads are arranged in parallel, and have an edge portion on the side surface in the longitudinal direction, and the electronic device electrode and / or the substrate electrode and the edge portion of the lead are brought into contact with each other.
- the edge portion is used and the lead is highly bonded. It is possible to join the electrode and the electrode.
- a plating bonding process is performed in a state where the electronic device electrode and / or the substrate electrode and the lead of the lead frame are temporarily fixed by the ultrasonic bonding.
- the plating bonding process is performed.
- it is not necessary to use an auxiliary jig when positioning the plating joint there is an effect that a simple and low-cost manufacturing method can be realized by omitting the process of attaching and removing the jig. .
- an angle formed between an edge portion of the lead and the electronic device electrode and / or the substrate electrode is 3 degrees to 15 degrees.
- the angle formed between the edge portion of the lead and the electronic device electrode and / or the substrate electrode is set to 3 to 15 degrees. Can be formed thick, and the manufacturing efficiency can be improved.
- the buckling width at the tip of the edge portion is set to 1 ⁇ m to 50 ⁇ m.
- the buckling width of the tip of the edge portion is set to 1 ⁇ m to 50 ⁇ m, the tip portion of the edge is buckled at the time of joining, and joining on a minute surface is performed. While realizing, there is an effect that it is possible to prevent damage to the electrode at the joining destination at the tip of the edge portion.
- the method for forming an electrode connection structure according to the present invention is such that the frequency of the ultrasonic vibration is 15 kHz to 150 kHz.
- the frequency of the ultrasonic vibration is 15 kHz to 150 kHz, it is possible to efficiently destroy an unnecessary oxide film or the like on the bonding surface and efficiently at the bonding portion. Energy can be propagated, and the energy efficiency can be improved.
- connection structure of the lead frame and semiconductor chip which are used with the electrode connection structure which concerns on 1st Embodiment It is a 1st enlarged view in case the 1st connection surface and 2nd connection surface in an electrode connection structure concerning a 1st embodiment are plated. It is a 2nd enlarged view in case the 1st connection surface and 2nd connection surface in the electrode connection structure which concern on 1st Embodiment are plated. It is a perspective view which shows the shape of the lead
- FIG. 7 is a diagram showing a modification of the lead shown in FIG. 6. It is a front view which shows the electrode connection structure which concerns on 3rd Embodiment. It is a figure which shows the application example of the electrode connection structure shown in FIG. It is a figure which shows the formation method of the electrode connection structure which concerns on 4th Embodiment. It is a figure which shows the cross-sectional shape and external appearance of the lead frame used in the Example. It is a figure which shows the result of having connected the lead frame and the electrode of the semiconductor chip by Ni plating.
- electrode connection structure and a method for forming the electrode connection structure when a semiconductor chip is used as an example of an electronic device will be described. It can also be applied to electrode connection structures such as MEMS, LEDs, and batteries.
- FIG. 1 is a diagram showing a lead frame and semiconductor chip connection structure used in the electrode connection structure according to the present embodiment.
- 1A is a bottom view when the semiconductor chip and the lead frame are connected
- FIG. 1B is a side cross-sectional view when the semiconductor chip and the lead frame are connected.
- the electrode connection structure according to the present embodiment has a semiconductor chip and a longitudinal side surface of each lead 11 in a lead frame 10 in which a plurality of long leads 11 are arranged in parallel in a ladder shape. Twelve electrodes are connected by plating.
- the electrode surface of the semiconductor chip 12 connected in direct contact with the lead frame 10 is referred to as a first connection surface 13, and the longitudinal side surface of the lead 11 in contact with the first connection surface 13 is referred to as a second connection surface 14.
- the semiconductor chip 12 and the lead frame 10 are electrically connected by plating the first connection surface 13 and the second connection surface 14 and joining them.
- FIG. 2 is a first enlarged view in the case where the first connection surface and the second connection surface in the electrode connection structure according to the present embodiment are plated.
- the plating process is performed in a state where the first connection surface 13 and the second connection surface 14 are in close contact with each other, the plating solution is sufficiently circulated between the first connection surface 13 and the second connection surface 14. In some cases, voids or other defects may be formed, leading to a decrease in quality. Therefore, in the present embodiment, in order to sufficiently distribute the plating solution between the first connection surface 13 and the second connection surface 14, the edge portion 15 is provided on the second connection surface 14, and this edge portion.
- each surface (the first connection surface 13 and the second connection surface) is directed from the edge portion 15 toward the outer side portion 16 (the end portion of the second connection surface) of the second connection surface 14.
- the gap 17 is formed so that the distance of the connecting surface 14) increases continuously.
- the lead 11 has a rectangular cross section.
- the lead 11 has a parallelogram. May be a positive direction, rhombus, trapezoid, or other polygon.
- the shape is rectangular or square as shown in FIG.
- the edge part 15 is formed in a part of edge part of the 2nd connection surface 14 as shown in FIG. 2, it goes to the outer part 16 except the location in which the said edge part 15 is formed.
- the gap 17 is formed so that the distance between the respective surfaces increases continuously.
- FIG. 3 is a second enlarged view when the first connection surface and the second connection surface in the electrode connection structure according to the present embodiment are plated.
- FIG. 3A shows the first connection by having the edge portion 15 on the outer side portion 16a on one end side of the second connection surface 14 and reducing the thickness of the lead 11 toward the outer side portion 16b on the other end side.
- a gap 17 is formed so that the distance between the surface 13 and the second connection surface 14 continuously increases from the edge portion 15 toward the outer portion 16b.
- This thinning process can be performed by, for example, pressing, etching, or cutting.
- 3B has an edge portion 15 at the longitudinal center on the second connection surface 14, and the lead 11 is thinned toward the outer portions 16a and 16b at both ends, whereby the first connection is achieved.
- a gap 17 is formed so that the distance between the surface 13 and the second connection surface 14 continuously increases from the edge portion 15 toward the outer portions 16a and 16b. This thinning process can be performed by, for example, pressing, etching, or cutting.
- the gap 17 can be formed by reducing the thickness of the second connection surface 14 of the lead 11 from the edge portion 15 toward the outer side portion 16 of the lead 11.
- the plating solution can sufficiently flow through the gap 17 so that the first connection surface 13 and the second connection surface 14 can be plated and connected without generating voids or the like.
- the second connecting surface 14 can be widely filled with plating.
- connection structure between the lead frame 10 and the electrode of the semiconductor chip 11 has been described.
- the same electrode connection structure technique can be applied to the connection between the lead frame 10 and the substrate electrode.
- the edge portion 15 is provided on the side surface in the longitudinal direction of the lead 11, and the edge portion 15 extends to the outer portion 16 of the lead 11.
- the plating solution is formed between the first connection surface 13 and the second connection surface 14 by forming the gap 17 so that the distance between the first connection surface 13 and the second connection surface 14 continuously increases. Can be sufficiently distributed, high-quality plating connection can be performed without causing voids and other defects, and the first connection surface 13 and the second connection surface 14 are widely plated. It becomes possible to fill with.
- the thermal conductivity can be increased.
- Electrode connection structure according to this embodiment will be described with reference to FIGS.
- a plurality of edge portions 15 are formed at predetermined intervals in the short direction of the second connection surface 14 on the side surface in the longitudinal direction of the lead 11.
- the description which overlaps with the said 1st Embodiment is abbreviate
- FIG. 4 is a perspective view showing the shape of a lead in the electrode connection structure according to this embodiment
- FIG. 5 is a view showing the connection structure of the lead frame and the semiconductor chip in the electrode connection structure according to this embodiment.
- a plurality of narrow edge portions 15 are formed in the short direction on the second connection surface 14 of the lead 11, and the short direction of the second connection surface is formed between the edge portions 15.
- a concave groove-like air gap 17 is formed so as to penetrate through.
- the plating process is performed with the edge portion 15 of the lead 11 in contact with the semiconductor chip 12 (or substrate electrode).
- 5A is a side view showing the connection structure between the lead frame and the semiconductor chip
- FIG. 5B is a front view showing the connection structure between the lead frame and the semiconductor chip
- FIG. It is a bottom view which shows a connection structure.
- the lead 11 is formed with a concave groove-like gap 17 between the edge portions 15, so that the plating solution is sufficiently distributed around the edge portion 15, and the first embodiment described above. As in the case of, high-quality plating can be performed centering on the edge portion 15.
- a plurality of gaps 17 are formed between the edge portions 15, stress applied in the longitudinal direction can be dispersed to prevent breakage of the leads 11.
- FIG. 6 shows a further improvement of the shape of the lead 11 shown in FIG. 6A is a view in which a concave groove-like air gap 17a discontinuous in the longitudinal direction is further formed in the shape of the lead 11 shown in FIG. 4, and FIG.
- the formed edge portion 15 is formed in a mountain shape. As shown in FIG. 6 (A), a part of the edge portion 15 is cut to form a concave groove-like air gap 17a that is discontinuous in the longitudinal direction, thereby dispersing the stress applied in the lateral direction. The breakage of the lead 11 can be prevented.
- a concave groove-like gap continuous in the longitudinal direction is formed in the edge portion 15, so that the case of FIG. Similarly, the stress applied in the short direction can be dispersed to prevent the lead 11 from being damaged.
- the edge portion 15 of FIG. 6 (A) is processed so as to have a mountain shape when viewed from the longitudinal direction of the lead 11.
- the stress applied to the lead 11 can be dispersed as described above to prevent the lead 11 from being damaged and the like, and an extremely high quality plating process can be achieved by distributing the plating solution more effectively.
- the discontinuous gap 17a may not be formed in the longitudinal direction.
- FIG. 7 shows a modification of the lead shown in FIG.
- a plurality of narrower edge portions 15 are formed in the lateral direction than in the case of FIG.
- the concave groove-like air gap 17 penetrating in the short direction is not an R shape but an acute concave groove shape (FIG. 7A).
- a part of the edge portion 15 is cut to form a concave groove-shaped gap 17 a continuous in the longitudinal direction.
- the stress applied in the direction can be dispersed to prevent the lead 11 from being damaged (FIG. 7B).
- the edge portion 15 is processed so as to have a mountain shape when viewed from the longitudinal direction of the lead 11, so that the plating solution can be distributed more effectively and extremely high quality plating can be performed. Processing can be performed.
- the electrode connection structure according to this embodiment includes a third connection surface on the back surface side of the second connection surface on the side surface in the longitudinal direction of the lead 11, and an electrode surface (or substrate electrode surface) of the semiconductor chip 12 connected to the third connection surface.
- the fourth connection surface and the fourth connection surface, the fourth connection surface and the third connection from the edge portion of the third connection surface in contact with the fourth connection surface toward the outer side of the third connection surface.
- the distance to the surface is continuously increasing.
- the description which overlaps with each said embodiment is abbreviate
- FIG. 8 is a front view showing an electrode connection structure according to the present embodiment.
- the second connecting surface 14 on the upper surface side of the lead 11 has an edge portion 15a
- the third connecting surface 18 on the lower surface side has an edge portion 15b.
- high-quality plating connection is possible as demonstrated in each said embodiment.
- high-quality plating connection is also possible in the connection between the third connection surface 18 and the fourth connection surface 19 which is the electrode surface (or substrate electrode surface) of the semiconductor chip 12 connected to the third connection surface 18. Is possible.
- the fourth connection surface 19 and the third connection are directed from the edge 15 b toward the outer portion 16 of the third connection surface 18. Since the gap 17 is formed by continuously increasing the distance to the surface 18, a high-quality plating connection in which a plating solution is sufficiently passed through the gap 17 to eliminate voids and the like is possible. Yes.
- the semiconductor chips 12 can be stacked in multiple layers, and high-quality plating connection is realized. At the same time, the process of laminating the semiconductor chips 12 can be simplified and the working efficiency can be remarkably improved.
- FIG. 9 in the electrode connection structure according to this embodiment, the lead 11 described in each of the above embodiments can be used.
- FIG. 9A is an application of the electrode connection structure in FIG. 3
- FIG. 9B is an application of the electrode connection structure in FIG.
- the plating connection is preferably plating with a metal or alloy having a melting point of 700 ° C. or higher, and particularly preferably Ni (nickel) or a Ni alloy.
- a metal or alloy having a melting point of 700 ° C. or higher and particularly preferably Ni (nickel) or a Ni alloy.
- Ni or Ni alloy it is possible to perform plating processing at 100 ° C or less, and it is possible to maintain high quality without damaging semiconductor chips, substrates, lead frames, etc. due to stress or heat during plating processing. It becomes.
- the first connection surface 13 and the edge portion 15 on the second connection surface 14 are joined by ultrasonic vibration.
- Ultrasonic bonding is used, for example, for bonding wire bonding, and by reducing the distance between molecules while removing unnecessary films (for example, oxide films) on the surface of the bonding surface by ultrasonic vibration. Bonding at the molecular level. Ultrasonic bonding has extremely difficulty in bonding between surfaces, but can be satisfactorily bonded to a planar electrode in the edge portion 15 as in wire bonding or the present invention.
- FIG. 10 is a diagram showing a state in which the above electrode connection structure is formed using ultrasonic bonding.
- FIG. 10A is a diagram in which the first connection surface 13 and the second connection surface 14 are bonded by ultrasonic bonding, and the third connection surface 18 and the fourth connection surface 19 are bonded.
- 10 (B) is a diagram when the plating process is performed in the state of FIG. 10 (A). That is, in FIG. 10A, the semiconductor chip 12 and the lead 11 are temporarily fixed by ultrasonic bonding, and the plating process shown in FIG. By temporarily fixing by ultrasonic bonding, the subsequent plating process can be stably performed with high accuracy.
- ultrasonic vibration can be applied in the longitudinal direction and width direction of the lead 11, but in the longitudinal direction, that is, in the direction in which the edge extends on the line in FIG.
- an object that hinders bonding such as an oxide on the surface of the bonded surface
- the edge portions 15a and 15b may be deformed before the oxide film is destroyed, and the bonding property may be deteriorated.
- ultrasonic vibration is applied at a frequency of 15 kHz to 150 kHz. By doing so, it is possible to efficiently propagate energy while destroying the oxide film before the edge portions 15a and 15b are deformed.
- the temperature for ultrasonic bonding can be room temperature, but it is desirable to heat it to about 180 ° C. or less where oxidation does not easily occur. Furthermore, in order to suppress oxidation, it is effective to keep the atmosphere of the joint portion inert with nitrogen gas or the like.
- the ultrasonic vibrations are adjusted so that the buckling width d of the edge portions 15a and 15b is about 1 ⁇ m to 50 ⁇ m. It is desirable that the application time, the magnitude of pressurization, and the energy are adjusted. Further, the tip portions of the edge portions 15a and 15b have an angle ⁇ of the tip portion (for example, from the most distal portion of the edge portions 15a and 15b to a position of about 50 ⁇ m) in order to facilitate deformation joining by ultrasonic vibration. 1 may be an acute angle of ⁇ 1 ⁇ 90 degrees.
- the lead 11 and the semiconductor chip 12 are temporarily fixed by the above ultrasonic bonding, and an electrode connection structure as shown in FIG. 10B is formed by performing plating in this state.
- the positioning of the plating bonding can be easily performed, and the edge tip The void residue after plating in the non-contact region of the part can be reduced.
- it is not necessary to use an auxiliary jig when positioning the plating joint it is possible to realize a simple and low-cost manufacturing method by omitting the process of attaching and removing the jig.
- the angle formed by the first connection surface 13 and the second connection surface 14 and the angle ⁇ 2 formed by the third connection surface 18 and the fourth connection surface 19 (see, for example, FIG. 10). Is preferably 3 to 15 degrees. That is, for example, when used as a power device, since a large amount of current is passed, it is necessary to improve thermal conductivity. Therefore, it is necessary to increase the width of the electrode to some extent, but if the angle formed by each connection surface is larger than 15 degrees, it is necessary to perform a plating process for a long time in order to form a large width of the electrode, In some cases, the production efficiency may deteriorate. By making the angle formed by each connection surface to about 3 to 15 degrees, it becomes possible to increase the width of the electrode with a small amount of plating metal, and it becomes possible to greatly reduce the plating time and increase the production efficiency. .
- the electrode connection structure using ultrasonic bonding and the method for forming the electrode connection structure in the present embodiment can be applied to the technology according to each of the embodiments.
- FIG. 11 is a diagram showing the cross-sectional shape and appearance of the lead frame used in this example.
- FIG. 12 shows the result of connecting the lead frame of FIG. 11 and the electrodes of the semiconductor chip 12 by Ni plating.
- 12A is an appearance photograph when the lead frame and the semiconductor chip are joined
- FIG. 12B is a joint cross-sectional photograph when the lead frame and the semiconductor chip are joined
- FIG. 12C is FIG. It is the photograph which expanded a part of joining sectional drawing of B).
- the lead 11 and the electrode of the semiconductor chip 12 are connected by Ni plating without causing a defect such as a void.
- the plating from the edge portion 15 of the lead 11 to the outer portion 16 of the lead 11 is sufficiently filled with Ni plating, and an extremely high quality and high thermal conductivity plating connection can be realized.
- the electrode connection structure according to the present invention enables extremely high-quality plating connection.
- the interposer and the semiconductor chip can be directly joined, and high heat resistance, high thermal conductivity, and low inductance can be realized.
- heat treatment is not required, the effects of residual stress and oxidation during the process can be suppressed, and high reliability can be realized by improving the mechanical strength by plating mounting.
- high productivity can be realized because processes such as die bonding and wire bonding can be performed collectively in the plating process.
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Abstract
Description
本実施形態に係る電極接続構造について、図1ないし図3を用いて説明する。図1は、本実施形態に係る電極接続構造で用いるリードフレーム及び半導体チップの接続構造を示す図である。図1(A)は、半導体チップとリードフレームとを接続した場合の下面図、図1(B)は、半導体チップとリードフレームとを接続した場合の側断面図である。図1に示すように、本実施形態に係る電極接続構造は、複数の長尺状のリード11が梯子状に並列して配設されたリードフレーム10における各リード11の長手方向側面と半導体チップ12の電極とをめっき接続する。リードフレーム10と直接接触して接続される半導体チップ12の電極面を第1接続面13とし、この第1接続面13に接触するリード11の長手方向側面を第2接続面14とする。第1接続面13と第2接続面14との間をめっき処理して接合することで、半導体チップ12とリードフレーム10とを電気的に接続する。
本実施形態に係る電極接続構造について、図4ないし図7を用いて説明する。本実施形態に係る電極接続構造は、リード11の長手方向側面の第2接続面14の短手方向に複数のエッジ部15が所定の間隔を空けて形成されているものである。なお、本実施形態において前記第1の実施形態と重複する説明は省略する。
本実施形態に係る電極接続構造について、図8及び図9を用いて説明する。本実施形態に係る電極接続構造は、リード11の長手方向側面の第2接続面の裏面側の第3接続面と、当該第3接続面と接続する半導体チップ12の電極面(又は基板電極面でもよい)である第4接続面と、の接続部分において、第4接続面と接触する第3接続面のエッジ部分から当該第3接続面の外側部に向かって第4接続面と第3接続面との距離が連続的に増加しているものである。なお、本実施形態において前記各実施形態と重複する説明は省略する。
本実施形態に係る電極接続構造の形成方法について、図10を用いて説明する。本実施形態に係る電極接続構造の形成方法は、第1接続面13と第2接続面14上のエッジ部15とを超音波振動により接合するものである。超音波接合は、例えばワイヤボンディングの接合等に利用されているものであり、超音波振動により接合面表面の不要な膜(例えば、酸化膜等)を除去しながら分子間の距離を縮めることで、分子レベルで接合するものである。超音波接合は、面同士での接合では極めて困難性を有するが、ワイヤボンディングや本発明のようなエッジ部15においては、平面電極に対して良好に接合することが可能である。
11 リード
12 半導体チップ
13 第1接続面
14 第2接続面
15(15a,15b) エッジ部
16(16a,16b) 外側部
17(17a) 空隙
18 第3接続面
19 第4接続面
Claims (23)
- 電子デバイス電極及び/又は基板電極とリードフレームのリードとをめっき接続する電極接続構造において、
前記リードフレームにおける複数の長尺状のリードが並列して配設されており、各リードの長手方向側面と前記電子デバイス電極及び/又は前記基板電極とがめっき接続され、
前記リードに接続される前記電子デバイス電極及び/又は前記基板電極の第1接続面と、当該第1接続面に接続される前記リードの長手方向側面における第2接続面と、の接続部分において、前記第1接続面と接触する前記第2接続面のエッジ部分から当該第2接続面の外側部に向かって前記第1接続面と前記第2接続面との距離が連続的に増加していることを特徴とする電極接続構造。 - 請求項1に記載の電極接続構造において、
前記第2接続面のエッジ部分から当該第2接続面の外側部に向かって、前記リードが減肉加工されていることを特徴とする電極接続構造。 - 請求項2に記載の電極接続構造において、
前記第2接続面における長手方向中心部に前記エッジ部分が形成されていることを特徴とする電極接続構造。 - 請求項1ないし3のいずれかに記載の電極接続構造において、
前記第2接続面における短手方向に複数の前記エッジ部が所定の間隔を空けて形成されており、当該エッジ部の間に前記第2接続面の短手方向に貫通する凹溝状の空隙が形成されていることを特徴とする電極接続構造。 - 請求項1ないし4のいずれかに記載の電極接続構造において、
前記第2接続面における長手方向に連続又は不連続の凹溝状の空隙が形成されていることを特徴とする電極接続構造。 - 請求項1ないし5のいずれかに記載の電極接続構造において、
前記第2接続面の裏面側の第3接続面と、当該第3接続面と接続する前記電子デバイス電極及び/又は前記基板電極の第4接続面と、の接続部分において、前記第4接続面と接触する前記第3接続面のエッジ部分から当該第3接続面の外側部に向かって前記第4接続面と前記第3接続面との距離が連続的に増加していることを特徴とする電極接続構造。 - 電子デバイス電極及び/又は基板電極とリードフレームのリードとをめっき接続する電極接続構造において、
前記リードフレームにおける複数の長尺状のリードが並列して配設されており、各リードの長手方向側面と前記電子デバイス電極及び/又は前記基板電極とがめっき接続され、
前記リードに接続される前記電子デバイス電極及び/又は前記基板電極の第1接続面と、当該第1接続面に接続される前記リードの長手方向側面における第2接続面と、の接続部分において、前記第2接続面における短手方向に複数の前記エッジ部が所定の間隔を空けて形成されており、当該エッジ部の間に前記第2接続面の短手方向に貫通する凹溝状の空隙が形成されていることを特徴とする電極接続構造。 - 請求項1ないし7のいずれかに記載の電極接続構造において、
前記めっき接続が、融点が700℃以上の金属又は合金によるめっきであることを特徴とする電極接続構造。 - 請求項8に記載の電極接続構造において、
前記金属又は前記合金が、Ni又はNi合金であることを特徴とする電極接続構造。 - 請求項1ないし9のいずれかに記載の電極接続構造において、
前記リードのエッジ部分における、前記電子デバイス電極及び/又は基板電極と前記リードの長手方向側面とのなす角度が3度~15度であることを特徴とする電極接続構造。 - 請求項3に記載の電極接続構造の形成方法であって、
前記エッジ部がプレス加工又はエッチング加工により形成されることを特徴とする電極接続構造の形成方法。 - 電子デバイス電極及び/又は基板電極とめっき接続するリードフレームにおいて、
前記複数の長尺状のリードが並列して配設されており、
前記電子デバイス電極及び/又は前記基板電極に接合される前記リードの長手方向側面に前記電子デバイス電極及び/又は前記基板電極と接触するエッジ部を有することを特徴とするリードフレーム。 - 請求項12に記載のリードフレームにおいて、
前記エッジ部分から当該エッジ部を有する接続面の外側部に向かって、前記リードが減肉加工されていることを特徴とするリードフレーム。 - 請求項13に記載のリードフレームにおいて、
前記接続面における長手方向中心部に前記エッジ部分が形成されていることを特徴とするリードフレーム。 - 請求項12ないし14のいずれかに記載のリードフレームにおいて、
前記接続面における短手方向に複数の前記エッジ部が所定の間隔を空けて形成されており、当該エッジ部の間に前記接続面の短手方向に貫通する凹溝状の空隙が形成されていることを特徴とするリードフレーム。 - 請求項12ないし15のいずれかに記載のリードフレームにおいて、
前記接続面における長手方向に連続又は不連続の凹溝状の空隙が形成されていることを特徴とするリードフレーム。 - 請求項12ないし16のいずれかに記載のリードフレームにおいて、
前記エッジ部が形成されている接続面の裏面側の前記リードの長手方向側面に他のエッジ部が形成されていることを特徴とするリードフレーム。 - 請求項12ないし17のいずれかに記載のリードフレームにおいて、
前記リードのエッジ部分が、接合される前記電子デバイス電極及び/又は前記基板電極の面に対して3度~15度の角度で形成されていることを特徴とするリードフレーム。 - 電子デバイス電極及び/又は基板電極とリードフレームのリードとを接続する電極接続構造の形成方法であって、
前記リードフレームは複数の長尺状のリードが並列して配設されると共に、当該リードの長手方向側面にはエッジ部分を有しており、
前記電子デバイス電極及び/又は基板電極と前記リードのエッジ部分とを接触させた状態で超音波振動を付加して前記エッジ部分の先端を座屈させ、前記電子デバイス電極及び/又は基板電極と前記リードとを超音波接合する電極接続構造の形成方法。 - 請求項19に記載の電極接続構造の形成方法において、
前記電子デバイス電極及び/又は基板電極とリードフレームのリードとが前記超音波接合で仮止めされた状態でめっき接合処理が行われることを特徴とする電極接続構造の形成方法。 - 請求項19又は20に記載の電極接続構造の形成方法において、
前記リードのエッジ部分と前記電子デバイス電極及び/又は基板電極とのなす角度が3度~15度であることを特徴とする電極接続構造の形成方法。 - 請求項19ないし21のいずれかに記載の電極接続構造の形成方法において、
前記エッジ部分の先端の座屈幅が1μm~50μmであることを特徴とする電極接続構造の形成方法。 - 請求項19ないし22のいずれかに記載の電極接続構造の形成方法において、
前記超音波振動の周波数が15kHz~150kHzであることを特徴とする電極接続構造の形成方法。
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US6762067B1 (en) * | 2000-01-18 | 2004-07-13 | Fairchild Semiconductor Corporation | Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails |
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