WO2017154422A1 - 接続基板 - Google Patents
接続基板 Download PDFInfo
- Publication number
- WO2017154422A1 WO2017154422A1 PCT/JP2017/003554 JP2017003554W WO2017154422A1 WO 2017154422 A1 WO2017154422 A1 WO 2017154422A1 JP 2017003554 W JP2017003554 W JP 2017003554W WO 2017154422 A1 WO2017154422 A1 WO 2017154422A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- main surface
- conductor
- glass
- hole
- open
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/26—Cleaning or polishing of the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
- H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
- H05K2203/0793—Aqueous alkaline solution, e.g. for cleaning or etching
Definitions
- the present invention relates to an electrical connection substrate in which a through conductor such as a via conductor is formed in a through hole.
- a substrate for mounting an electronic device such as a SAW filter
- a substrate (via substrate) having a structure in which a through hole is provided in an insulating substrate such as ceramic and the hole is filled with a conductor to form a through electrode is used.
- insulating substrate such as ceramic
- the via substrate which is a component, is also required to be thin. It has been.
- the wiring on the substrate surface needs to be miniaturized for miniaturization, it is required to reduce the diameter of the through electrode and to increase the accuracy of the position. Furthermore, since these fine wirings are formed by photolithography or plating, it is particularly required that the through electrodes be dense and have high water tightness in order to prevent problems caused by the ingress of chemicals in the resist coating process and plating process. ing.
- Patent Document 1 discloses a method of preventing the resist solution from entering by forming a conductive protective film on the surface of a porous through electrode.
- the insulating substrate is thin, the air permeability of the through electrode is increased, so that the strength of the conductive protective film is insufficient and does not function as a protective film.
- Patent Document 2 discloses a method of filling a void with a second conductor after forming a porous first conductor as a through electrode.
- a ceramic substrate is used, cracks and warpage of the substrate are likely to occur when the substrate is thinned due to the difference in thermal expansion between the metal that is the conductive material and the ceramic.
- Patent Document 3 discloses a method in which an active metal layer is formed between a ceramic substrate and a through electrode by filling the through hole of the ceramic substrate with a metal containing an active metal, thereby densifying the ceramic substrate.
- a metal containing an active metal since the metal brazing containing the active metal has a very high viscosity, it cannot be filled well if the through electrode diameter is small.
- Patent Document 4 discloses a method of using a conductive paste containing an expansion material when forming a through electrode. However, it is difficult to fill all the cavities with only the expansion material, and the denseness of the through electrode cannot be obtained particularly when the plate is thinned.
- Patent Document 5 discloses a method of filling a glass paste after disposing a granular conductive material in each through hole of a ceramic substrate.
- cracks and warpage due to the difference in thermal expansion between the ceramic and the spherical conductive material are likely to occur.
- the through hole is small, it is difficult to arrange the spherical conductive material.
- An object of the present invention is to provide a microstructure capable of improving the water-tightness of a through hole when manufacturing a connection board including a ceramic substrate and a through conductor provided in the through hole.
- the connection substrate according to the present invention includes a ceramic substrate provided with a through hole, and a through conductor provided in the through hole, the through conductor having a first main surface and a second main surface.
- the through conductor is formed in the first porous hole, the metal porous body provided with the first open hole communicating with the first main surface and the second open hole communicating with the second main surface.
- the first glass phase, the second glass phase formed in the second open pores, the first void provided in the first open pores, and the first glass phase provided in the first open pores Two gaps are provided.
- the first space is a closed space that does not communicate with the first main surface
- the second space is an open space that communicates with the second main surface.
- a through conductor is obtained by supplying a metal paste to a through hole of a ceramic substrate and baking it.
- the microstructure of such through conductors is uniform throughout.
- the thickness of the ceramic substrate became extremely small, it was considered that a part of the open pores communicated between both main surfaces of the penetrating conductor and a small amount of liquid leakage occurred.
- the present inventor also studied to reduce the pores of the metal porous body constituting the through conductor.
- the thermal expansion difference between the through conductor and the ceramic is large, so that peeling at the interface is likely to occur, and water tightness is impaired through this peeling portion.
- the present inventor paid attention to the microstructure of the porous metal body mainly constituting the through conductor.
- the metal porous body included a first open pore communicating with the first main surface and a second open pore communicating with the second main surface.
- the present inventor has the first open pores communicating with the first main surface when suppressing peeling due to a difference in thermal expansion between the through conductor and the ceramic by generating a glass phase in each pore.
- the air gap was closed by the glass phase, and thereby the water tightness function was mainly supported on the first open pore side of the through conductor.
- the clad layer is not blocked by the glass phase, and the void is communicated with the second open pore. Accordingly, the penetration conductor and the ceramic are hardly peeled as a whole while maintaining the water tightness of the through conductor itself, and the water tightness is also maintained in this respect.
- FIG. (A) is a top view which shows typically the ceramic base material 1 in which the through-hole 2 was arranged
- (b) is a cross-sectional view of the ceramic base material 1.
- FIG. (A) shows a state in which the metal paste 3 is filled in the through-holes of the ceramic substrate 1
- (b) shows a state in which the metal paste 3 is baked to form the metal porous body 4
- (c) The state which formed the glass layer 9 on the 1st main surface 1a of the ceramic base material 1 is shown
- (d) shows the state which removed the glass layer 9.
- FIG. FIG. 2A is a plan view schematically showing the connection substrate 10 in which the through conductor 11 is formed in the through hole 2 ⁇ / b> A
- 2B is a cross-sectional view of the connection substrate 10. It is a schematic diagram which shows the structure of the metal porous body 4 produced
- the ceramic substrate 1 is provided with one main surface 1a and the other main surface 1b, and a large number of through holes 2 penetrating between the main surfaces 1a and 1b are formed. Yes.
- the through hole 2 has an opening 2a on the first main surface 1a side and an opening 2b on the second main surface 1b side.
- a metal paste 3 is filled in the opening 2 of the ceramic substrate 1. Then, by heating the metal paste 3, the metal paste is baked to form a porous metal body 4 in the through hole 2 as shown in FIG.
- Reference numeral 5 denotes a first main surface of the metal porous body 4, and 6 denotes a second main surface of the metal porous body 4.
- a glass paste is applied on the first main surface 1a of the ceramic substrate 1 to form a glass paste layer.
- the glass paste is melted by heating and baking the glass paste.
- the glass layer 9 is formed on the 1st main surface 1a of the ceramic base material 1.
- the molten glass is impregnated into the open pores of the metal porous body to generate a glass phase, thereby generating the through conductor 7 in the through hole.
- Reference numeral 8 denotes a first main surface of the through conductor 8.
- the through conductor is exposed on the first main surface side of the ceramic base material to obtain a connection substrate.
- the first main surface 1a of the ceramic base material 1 is further polished to form a polished surface 1c as shown in FIG.
- the through conductors 11 are filled in the through holes 2A.
- 11 a is a first main surface of the through conductor 11
- 11 b is a second main surface of the through conductor 11.
- the metal porous body 4 is formed in the through hole 2 by baking the metal paste.
- the metal porous body 4 extends from the first main surface 1a of the ceramic substrate 1 to the second main surface 1b.
- 5 is the first main surface of the porous metal body, and 6 is the other main surface.
- the metal porous body 4 includes a metal matrix 20 and pores 16A, 16B, 16C, and 16D.
- the pores generated in the matrix include the first open pores 16A and 16D that open on the first main surface 5, the second open pore 16B that opens on the second main surface 6, and the main surfaces 5 and 6.
- the open pores 16A are open to the first main surface 5 in the cross section of FIG.
- the open pores 16D are not opened in the first main surface 5 in the cross section of FIG. 4, but are opened in the first main surface 5 along a route that does not appear in the cross section.
- the open pores 16A and 16D are distinguished.
- the air gap 33 is a closed air gap that does not communicate with the main surface, and the air gap 32 is an open air gap that opens in the second main surface 6.
- the glass paste is applied so as to cover the open pores 16A and 16D opened in the first main surface 5.
- the glass layer 18 is formed on the first main surface 1a, and at the same time, the molten glass is impregnated, and the glass phase 19 is formed in the open pores 16A and 16D.
- the glass phase 17 originally present in the porous metal body may be mixed with the glass phase 19 generated by impregnation and baking of the glass paste.
- the polishing surface 1c is formed on the ceramic substrate 1A, and the thickness of the ceramic substrate 1A is smaller than that before polishing.
- a through conductor 11 is formed in the through hole 2A.
- the first open holes 16A and 16D communicate with the first main surface 11a of the through conductor. Further, the second open hole 16B communicates with the second main surface 11b. 16C is a closed pore that does not communicate with either of the main surfaces 11a and 11b.
- the glass phase 17 derived from the metal paste, the glass phase 19 derived from the glass impregnated later, and the void 30 that does not open in the main surface 11a remain.
- the glass phase 17A derived from the metal paste and the voids 33 that do not open on the main surface remain.
- the glass phase 17B derived from the metal paste the void 32 communicating with the main surface 11b, and the void 31 not opening in the main surfaces 11a and 11b. And remains.
- the first gap 30 remaining in the first open pores 16A and 16D is closed by the glass phases 17 and 19, thereby forming a closed gap that does not communicate with the first main surface 11b. This prevents liquid leakage between the main surfaces through the first open pores and the second open pores.
- the second gap 32 in the second open pore is an open gap communicating with the second main surface 11b.
- the glass phase is generated in the first open pores by impregnating the molten glass from the first main surface side of the through conductor, whereby the first voids are the first main holes. I tried not to communicate with the surface.
- the present invention is not limited to this manufacturing method.
- the through-conductor having a microstructure as in the present invention can be manufactured by changing the paste composition between the upper half and the lower half of the through-hole.
- the area ratio of the porous metal body is 30 to 70% in the cross section of the through conductor. If the area ratio of the metal porous body is too high, the thermal stress between the through conductor and the ceramic increases, and if this area ratio is too low, the conductivity is low. From this viewpoint, the area ratio of the metal porous body is 30 to 70%, more preferably 40 to 65%, and particularly preferably 45 to 60%.
- the area ratio (total value) of the glass phase is 10 to 50%, and particularly preferably 20 to 40%.
- the total value of the void area ratio in the cross section of the through conductor is preferably 5 to 60%, and more preferably 5 to 40%.
- the measurement of the area ratio of these porous metal bodies, glass, and voids is performed by taking a SEM (1000 times) image of the cross section of the through conductor. It is possible to identify each material by photographing with the SEM by changing the color tone according to each material. Thereafter, the conductor portion to be measured is divided into a grid having a side of 5 ⁇ m, and the material occupying the most area is determined for each grid. The area ratio can be calculated by comparing the number of lattices determined for each material.
- the thickness of the ceramic substrate is 25 to 150 ⁇ m, and the diameter W of the through hole is 20 to 60 ⁇ m.
- the present invention is particularly useful for such a small and thin connection substrate.
- the diameter W of the through hole formed in the ceramic substrate is more preferably 25 ⁇ m or more from the viewpoint of ease of forming.
- the distance D (distance between the nearest through holes) between adjacent through holes 2 is preferably 50 ⁇ m or more, and more preferably 100 ⁇ m or more, from the viewpoint of suppressing breakage and cracks.
- the distance D between the adjacent through holes 2 is preferably 1000 ⁇ m or less, and more preferably 500 ⁇ m or less, from the viewpoint of improving the density of the through holes.
- the method for forming the through hole in the ceramic substrate is not particularly limited.
- a through hole can be formed in a green sheet of a ceramic substrate by pins or laser processing.
- a through-hole can also be formed in a blank substrate by laser processing.
- the laser oscillation source CO 2 , YAG (yttrium / aluminum garnet), or the like can be used.
- Ceramics constituting the ceramic substrate include aluminum oxide, yttrium oxide, YAG, zirconium oxide, and aluminum nitride.
- aluminum oxide, particularly high-purity aluminum oxide having a purity of 99.9% or more is particularly useful because it has a high Young's modulus of 400 GPa or more and excellent shape stability when thinned.
- a metal paste is supplied to the through hole, and a metal porous body is generated by heating.
- the metal that is the main component constituting such a metal paste include Ag, Au, Cu, Pd, or a mixture thereof.
- glass components include B 2 O 3 , SiO 2 , ZnO, PbO, Li 2 O, Na 2 O, K 2 O, MgO, CaO, SrO, BaO, Bi 2 O 3 , Al 2 O 3 , Gd 2.
- the baking temperature of the metal paste is appropriately selected depending on the type of paste, and can be set to 500 to 900 ° C., for example.
- a glass paste is applied to the first main surface of the metal porous body, and the open pores of the metal porous body are impregnated with the glass paste.
- the glass paste can be applied over the entire first main surface of the ceramic substrate.
- the glass paste may be applied only on the first main surface of the porous metal body by screen printing or the like, and the glass paste may not be applied on the other ceramic surfaces.
- the glass paste is melted by heating to form a glass layer on the main surface of the porous metal body, and the molten glass is impregnated into the open pores to form a glass phase.
- the baking temperature of the glass paste is appropriately selected depending on the type of paste, and can be set to 500 to 900 ° C., for example.
- connection substrate having a ceramic substrate and a through conductor provided in the through hole is obtained.
- the first main surface of the ceramic substrate is preferably polished.
- predetermined wiring, a pad, etc. are formed in each main surface 11a, 11b of a ceramic substrate.
- the ceramic substrate is an integral relay substrate.
- the ceramic substrate is preferably precision polished.
- CMP Chemical Mechanical Polishing
- polishing slurry a slurry in which abrasive grains having a particle size of 30 nm to 200 nm are dispersed in an alkali or neutral solution is used.
- the abrasive material include silica, alumina, diamond, zirconia, and ceria, which are used alone or in combination.
- a hard urethane pad, a nonwoven fabric pad, and a suede pad can be illustrated as a polishing pad.
- Example 1 A connection substrate was fabricated as described with reference to FIGS. Specifically, first, a slurry in which the following components were mixed was prepared.
- (Raw material powder) Specific surface area 3.5 to 4.5 m 2 / g, ⁇ -alumina powder having an average primary particle size of 0.35 to 0.45 ⁇ m (alumina purity 99.99%) 100 parts by mass • MgO (magnesia) 250 pppm ⁇ ZrO 2 (zirconia) 400ppm ⁇ Y 2 O 3 (yttria) 15ppm (Dispersion medium) ⁇ 45 parts by weight of 2-ethylhexanol (binder) ⁇ PVB (polyvinyl butyral) resin 4 parts by weight (dispersant) ⁇ Polymer surfactant 3 parts by weight (plasticizer) ⁇ DOP 0.1 parts by weight
- this slurry is formed into a tape shape so as to be 300 ⁇ m in terms of the thickness after firing, and converted into a size after firing so that it becomes a square of 100 mm in length ⁇ 100 mm in width. Disconnected.
- the obtained powder compact is calcined at 1240 ° C. in the atmosphere (preliminary firing), and then the substrate is placed on a molybdenum plate and heated at a rate of 1300 ° C. to 1550 ° C. in an atmosphere of hydrogen 3: nitrogen 1. Was kept at 1550 ° C. for 2.5 hours and baked to obtain a blank substrate.
- the blank substrate was laser processed under the following conditions to form through holes having the following dimensions.
- CO 2 laser wavelength 10.6 ⁇ m
- Pulse 1000Hz- On time 5 ⁇ s
- Laser mask diameter 0.9 mm
- Number of shots 40 times Through-hole diameter
- W Table 0.06 mm
- Through hole spacing D: 0.12 mm
- the melt (dross) adhering to the substrate surface was removed by grinding with a grinder, and then annealed at 1300 ° C. in the atmosphere for 5 hours to obtain a ceramic substrate having a thickness of 200 ⁇ m.
- Glass paste Solid content: 95% by weight
- Glass composition Bi-Zn-B viscosity: 50 Pa ⁇ s
- Mask # 360 mesh, 30um thickness
- Squeegee angle 70 degrees
- Squeegee speed 5mm / sec
- Number of squeegees 1
- Drying conditions 95 ° C x 30 minutes
- connection substrate the glass layer remaining on the surface was removed by polishing to obtain a connection substrate. Specifically, after grinding with a grinder while the substrate was attached to an alumina plate, lapping with diamond slurry was performed on both sides. The particle size of diamond was 3 ⁇ m. Finally, CMP processing using SiO 2 abrasive grains and diamond abrasive grains was performed. Thereafter, the substrate was peeled off from the alumina plate, the same processing was performed on the main surface on the opposite side, and washing was performed to obtain a connection substrate.
- the water tightness of the through conductor of the obtained connection board was confirmed by a method described with reference to FIG. That is, the porous plate 21 was fixed to the pedestal 22, the dust-free paper 23 was placed on the pedestal 22, and the ceramic substrate sample 24 was placed thereon. Water 26 was dropped onto the through hole of the ceramic substrate 24 and sucked at ⁇ 80 kPa as indicated by an arrow A. Then, it was confirmed whether or not moisture was observed on the dust-free paper.
- the number of through conductors in which liquid leakage was observed was 1 for 30000 through conductors provided on one ceramic substrate.
- Examples 2 to 7 A connection board was produced in the same manner as in Example 1. However, the area ratio of the metal porous body and the area ratio (total) of the glass phase in the cross section of the through conductor were changed as shown in Table 1. These parameters were changed by adjusting the solid content concentration of the Ag-Pd paste, the ratio of Ag, Pd and glass frit, the firing temperature, the melting and impregnation temperature and time of the glass paste.
- Example 1 An Ag paste was embedded in each through-hole of the same ceramic substrate as in Example 1.
- the Ag paste used is the same as in Example 1. Then, it baked at 700 degreeC and formed the metal porous body in the through-hole.
- both main surfaces of the ceramic base material were precision-polished without carrying out a step of printing the glass paste on the first main surface of the ceramic base material to obtain a connection substrate.
- each parameter indicating the microstructure is as follows. Number of first air gaps in the first open pores opening in the main surface 11a: 5 Number of second air gaps in the second open air holes opening in the main surface 11b: 6 through conductors Area ratio of porous metal body in cross section: 60% Area ratio of glass phase in cross section of through conductor (total): 20%
- Example 2 Next, a water tightness test was performed in the same manner as in Example 1. As a result, liquid leakage was observed in almost all the 30,000 through conductors provided on one ceramic substrate.
Abstract
Description
好適な実施形態においては、貫通導体の横断面において、金属多孔体の面積比率が30~70%である。金属多孔体の面積比率が高すぎると、貫通導体とセラミックスとの間の熱応力が増大し、この面積比率が低すぎると、導電性が低い。この観点からは、金属多孔体の面積比率を30~70%とするが、40~65%がより好ましく、45~60%が特に好ましい。
図1~図6を参照しつつ説明したようにして接続基板を作製した。
具体的には、まず以下の成分を混合したスラリーを調製した。
(原料粉末)
・比表面積3.5~4.5m2/g、
平均一次粒子径0.35~0.45μmのα-アルミナ粉末
(アルミナ純度99.99%) 100質量部
・MgO(マグネシア) 250pppm
・ZrO2(ジルコニア) 400ppm
・Y2O3(イットリア) 15ppm
(分散媒)
・2-エチルヘキサノール 45重量部
(結合剤)
・PVB(ポリビニルブチラール)樹脂 4重量部
(分散剤)
・高分子界面活性剤 3重量部
(可塑剤)
・DOP 0.1重量部
CO2レーザー:波長 10.6μm
パルス:1000Hz- On time 5μs
レーザーマスク径: 0.9 mm
ショット回数: 40回
貫通孔径W: 表0.06 mm、裏0.02mm
貫通孔の間隔D: 0.12 mm
貫通孔の数 : 30,000個/枚
[Ag-Pdペースト]
固形分濃度: 95 重量%
固形分組成=Ag:Pd:ガラスフリット=91:3:6 (重量比)
粘度:200 Pa・s
[印刷条件]
マスク:使用せず(ペーストを直接基板にのせ、スキージ(squeegee)で貫通孔にペーストを押し込んだ)。
スキージ角度:20度
スキージ速度:5mm/sec
スキージ回数:10回
[乾燥条件]
95℃×30分
[焼成条件]
600℃×40分
[ガラスペースト]
固形分濃度: 95 重量%
ガラス組成: Bi-Zn-B系
粘度:50 Pa・s
[印刷条件]
マスク:#360メッシュ、30um厚
スキージ角度:70度
スキージ速度:5mm/sec
スキージ回数:1回
[乾燥条件]
95℃×30分
[溶融、含浸条件]
570℃×3時間
貫通導体の横断面における金属多孔体の面積比率: 60%
貫通導体の横断面におけるガラス相の面積比率(合計): 30%
すなわち、台座22に多孔体板21を固定し、台座22上に無塵紙23を載置し、その上にセラミック基板のサンプル24を設置した。セラミック基板24の貫通孔上に水26を滴下し、矢印Aのように-80kPaで吸引した。そして、無塵紙に水分の付着が見られるかどうかを確認した。
実施例1と同様にして接続基板を作製した。
ただし、貫通導体の横断面における金属多孔体の面積比率、ガラス相の面積比率(合計)を、表1に示すように変更した。これらのパラメーターを変更するには、Ag-Pdペーストの固形分濃度、AgとPdとガラスフリットの比率、焼成温度、ガラスペーストの溶融、含浸の温度および時間を調整することで行った。
実施例1と同じセラミック基材の各貫通孔にAgペースト埋め込みを行った。使用したAgペーストは実施例1と同じである。その後、700℃にて焼成を行い、貫通孔中に金属多孔体を形成した。
第一の開気孔中の第一の空隙が主面11aに開口している個数:5個
第二の開気孔中の第二の空隙が主面11bに開口している個数:6個
貫通導体の横断面における金属多孔体の面積比率: 60%
貫通導体の横断面におけるガラス相の面積比率(合計): 20%
Claims (4)
- 貫通孔が設けられているセラミック基板、および
前記貫通孔中に設けられた貫通導体であって、第一の主面と第二の主面とを有する貫通導体を備える接続基板であって、
前記貫通導体が、
前記第一の主面に連通する第一の開気孔および前記第二の主面に連通する第二の開気孔が設けられた金属多孔体、
前記第一の開気孔内に形成された第一のガラス相、
前記第二の開気孔内に形成された第二のガラス相、
前記第一の開気孔内に設けられた第一の空隙、および
前記第二の開気孔内に設けられた第二の空隙
を有しており、前記第一の空隙が前記第一の主面に連通しない閉空隙であり、前記第二の空隙が前記第二の主面に連通する開空隙であることを特徴とする、接続基板。 - 前記貫通導体の横断面において、前記金属多孔体の面積比率が30~70%であることを特徴とする、請求項1記載の接続基板。
- 前記金属多孔体に閉気孔が設けられており、この閉気孔中に第三のガラス相が存在することを特徴とする、請求項1または2記載の接続基板。
- 前記セラミック基板の厚さが25~150μmであり、前記貫通孔の径が20μm~60μmであることを特徴とする、請求項1~3のいずれか一つの請求項に記載の接続基板。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201780011941.7A CN108781506B (zh) | 2016-03-11 | 2017-02-01 | 连接基板 |
KR1020187024055A KR20180121507A (ko) | 2016-03-11 | 2017-02-01 | 접속 기판 |
DE112017001274.0T DE112017001274T5 (de) | 2016-03-11 | 2017-02-01 | Verbindungssubstrat |
JP2018504052A JP6918774B2 (ja) | 2016-03-11 | 2017-02-01 | 接続基板 |
US16/108,339 US10257941B2 (en) | 2016-03-11 | 2018-08-22 | Connection substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-048165 | 2016-03-11 | ||
JP2016048165 | 2016-03-11 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/108,339 Continuation US10257941B2 (en) | 2016-03-11 | 2018-08-22 | Connection substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017154422A1 true WO2017154422A1 (ja) | 2017-09-14 |
Family
ID=59789214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2017/003554 WO2017154422A1 (ja) | 2016-03-11 | 2017-02-01 | 接続基板 |
Country Status (7)
Country | Link |
---|---|
US (1) | US10257941B2 (ja) |
JP (1) | JP6918774B2 (ja) |
KR (1) | KR20180121507A (ja) |
CN (1) | CN108781506B (ja) |
DE (1) | DE112017001274T5 (ja) |
TW (1) | TWI720123B (ja) |
WO (1) | WO2017154422A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019068015A (ja) * | 2017-10-05 | 2019-04-25 | 日本電気硝子株式会社 | ガラスセラミックス積層板、その製造方法、電子部品パッケージ、及びその製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102020201868A1 (de) * | 2020-02-14 | 2021-08-19 | Robert Bosch Gesellschaft mit beschränkter Haftung | Schaltungsträger mit einem wärmeleitfähigen gedruckten Metall-Inlay |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06291435A (ja) * | 1993-04-05 | 1994-10-18 | Ngk Spark Plug Co Ltd | 導体ペースト及びそれによって導体を形成したセラミック配線基板並びにそのセラミック配線基板の製造方法 |
JP2005093105A (ja) * | 2003-09-12 | 2005-04-07 | Asahi Glass Co Ltd | 導電性構造体およびその製造方法 |
JP2013165265A (ja) * | 2012-01-13 | 2013-08-22 | Zycube:Kk | 貫通/埋込電極構造及びその製造方法 |
WO2014106925A1 (ja) * | 2013-01-07 | 2014-07-10 | 株式会社アライドマテリアル | セラミック配線基板、半導体装置、およびセラミック配線基板の製造方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62296496A (ja) | 1986-06-17 | 1987-12-23 | 富士通株式会社 | 多層セラミツク回路基板の製造方法 |
US5614043A (en) | 1992-09-17 | 1997-03-25 | Coors Ceramics Company | Method for fabricating electronic components incorporating ceramic-metal composites |
JP3754748B2 (ja) | 1995-05-19 | 2006-03-15 | ニッコー株式会社 | スルーホール充填用導体ペースト、セラミック回路基板及びパッケージ基板 |
US5698015A (en) | 1995-05-19 | 1997-12-16 | Nikko Company | Conductor paste for plugging through-holes in ceramic circuit boards and a ceramic circuit board having this conductor paste |
JPH10308565A (ja) * | 1997-05-02 | 1998-11-17 | Shinko Electric Ind Co Ltd | 配線基板 |
JP4688379B2 (ja) | 2001-09-26 | 2011-05-25 | 福田金属箔粉工業株式会社 | 回路基板及びその製造方法ならびに電子装置 |
JP4154913B2 (ja) | 2002-04-01 | 2008-09-24 | 株式会社村田製作所 | 電子部品およびその製造方法 |
JP2005063708A (ja) * | 2003-08-20 | 2005-03-10 | Daiken Kagaku Kogyo Kk | 導電性ペースト |
US7528006B2 (en) * | 2005-06-30 | 2009-05-05 | Intel Corporation | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
JP5098646B2 (ja) * | 2005-12-12 | 2012-12-12 | パナソニック株式会社 | 回路基板の製造方法 |
US20100096178A1 (en) | 2008-10-17 | 2010-04-22 | Sumsung Electro-Mechanics Co., Ltd. | Non-shirinkage ceramic substrate and manufacturing method thereof |
JP2011091185A (ja) * | 2009-10-22 | 2011-05-06 | Shinko Electric Ind Co Ltd | 導電フィルムおよびその製造方法、並びに半導体装置およびその製造方法 |
JP2011151185A (ja) * | 2010-01-21 | 2011-08-04 | Shinko Electric Ind Co Ltd | 配線基板及び半導体装置 |
JP5381800B2 (ja) | 2010-02-23 | 2014-01-08 | 旭硝子株式会社 | 発光素子搭載用基板およびこの基板を用いた発光装置 |
JP5497504B2 (ja) * | 2010-03-23 | 2014-05-21 | 株式会社日立製作所 | 電子部品 |
JP5566271B2 (ja) | 2010-11-24 | 2014-08-06 | 京セラ株式会社 | 配線基板およびその製造方法 |
US9282638B2 (en) | 2012-01-13 | 2016-03-08 | Zycube Co., Ltd. | Electrode, electrode material, and electrode formation method |
JP2013153051A (ja) * | 2012-01-25 | 2013-08-08 | Tokuyama Corp | メタライズドセラミックスビア基板及びその製造方法 |
JP6155551B2 (ja) | 2012-04-10 | 2017-07-05 | セイコーエプソン株式会社 | 電子デバイス、電子機器および電子デバイスの製造方法 |
US9403023B2 (en) * | 2013-08-07 | 2016-08-02 | Heraeus Deutschland GmbH & Co. KG | Method of forming feedthrough with integrated brazeless ferrule |
JP6365111B2 (ja) | 2013-11-12 | 2018-08-01 | セイコーエプソン株式会社 | 配線基板の製造方法、配線基板、素子収納用パッケージ、電子デバイス、電子機器および移動体 |
WO2015141344A1 (ja) | 2014-03-19 | 2015-09-24 | 株式会社アライドマテリアル | セラミック配線基板および半導体装置 |
CN105322909A (zh) * | 2014-06-06 | 2016-02-10 | 精工爱普生株式会社 | 电子器件封装用基板、电子器件封装、电子器件及制造方法 |
JP2015231009A (ja) | 2014-06-06 | 2015-12-21 | セイコーエプソン株式会社 | 電子デバイスパッケージ用基板および電子デバイスパッケージ用基板の製造方法 |
JP6336829B2 (ja) | 2014-06-19 | 2018-06-06 | 京セラ株式会社 | 配線基板、パッケージおよび電子機器 |
JP5922739B2 (ja) | 2014-10-27 | 2016-05-24 | 株式会社トクヤマ | セラミックスビア基板、メタライズドセラミックスビア基板、これらの製造方法 |
JP6291435B2 (ja) | 2015-02-20 | 2018-03-14 | 日本電信電話株式会社 | プログラムおよびクラスタシステム |
-
2017
- 2017-02-01 DE DE112017001274.0T patent/DE112017001274T5/de not_active Withdrawn
- 2017-02-01 WO PCT/JP2017/003554 patent/WO2017154422A1/ja active Application Filing
- 2017-02-01 CN CN201780011941.7A patent/CN108781506B/zh not_active Expired - Fee Related
- 2017-02-01 JP JP2018504052A patent/JP6918774B2/ja active Active
- 2017-02-01 KR KR1020187024055A patent/KR20180121507A/ko unknown
- 2017-02-07 TW TW106103921A patent/TWI720123B/zh not_active IP Right Cessation
-
2018
- 2018-08-22 US US16/108,339 patent/US10257941B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06291435A (ja) * | 1993-04-05 | 1994-10-18 | Ngk Spark Plug Co Ltd | 導体ペースト及びそれによって導体を形成したセラミック配線基板並びにそのセラミック配線基板の製造方法 |
JP2005093105A (ja) * | 2003-09-12 | 2005-04-07 | Asahi Glass Co Ltd | 導電性構造体およびその製造方法 |
JP2013165265A (ja) * | 2012-01-13 | 2013-08-22 | Zycube:Kk | 貫通/埋込電極構造及びその製造方法 |
WO2014106925A1 (ja) * | 2013-01-07 | 2014-07-10 | 株式会社アライドマテリアル | セラミック配線基板、半導体装置、およびセラミック配線基板の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019068015A (ja) * | 2017-10-05 | 2019-04-25 | 日本電気硝子株式会社 | ガラスセラミックス積層板、その製造方法、電子部品パッケージ、及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN108781506B (zh) | 2021-06-29 |
JP6918774B2 (ja) | 2021-08-11 |
DE112017001274T5 (de) | 2019-01-10 |
JPWO2017154422A1 (ja) | 2019-01-17 |
US10257941B2 (en) | 2019-04-09 |
US20180359866A1 (en) | 2018-12-13 |
TWI720123B (zh) | 2021-03-01 |
CN108781506A (zh) | 2018-11-09 |
KR20180121507A (ko) | 2018-11-07 |
TW201743369A (zh) | 2017-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6831832B2 (ja) | 接続基板 | |
TWI345938B (en) | Multi-layered ceramic substrate and its production method, and electronic device comprising same | |
US5464950A (en) | Aluminum nitride circuit board and method of producing same | |
JPWO2007083811A1 (ja) | 導体ペースト、多層セラミック基板及び多層セラミック基板の製造方法 | |
JP4557417B2 (ja) | 低温焼成セラミック配線基板の製造方法 | |
WO2017154422A1 (ja) | 接続基板 | |
JP5877932B1 (ja) | 貫通孔を有する絶縁基板 | |
KR20100005143A (ko) | 비아홀용 전기 전도성 조성물 | |
CN111096090A (zh) | 陶瓷基板的制造方法、陶瓷基板以及模块 | |
JP3652196B2 (ja) | セラミック配線基板の製造方法 | |
JP6918773B2 (ja) | 接続基板の製造方法 | |
JPH04283994A (ja) | セラミックプリント配線板及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2018504052 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20187024055 Country of ref document: KR Kind code of ref document: A |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17762767 Country of ref document: EP Kind code of ref document: A1 |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17762767 Country of ref document: EP Kind code of ref document: A1 |