WO2017148018A1 - 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Download PDF

Info

Publication number
WO2017148018A1
WO2017148018A1 PCT/CN2016/082968 CN2016082968W WO2017148018A1 WO 2017148018 A1 WO2017148018 A1 WO 2017148018A1 CN 2016082968 W CN2016082968 W CN 2016082968W WO 2017148018 A1 WO2017148018 A1 WO 2017148018A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
clock signal
potential
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/082968
Other languages
English (en)
French (fr)
Inventor
王博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/539,124 priority Critical patent/US10074315B2/en
Publication of WO2017148018A1 publication Critical patent/WO2017148018A1/zh
Priority to US16/052,570 priority patent/US10438541B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the shift register includes a plurality of shift register units, and each shift register unit corresponds to one row of pixel units.
  • the progressive scan driving of the pixel unit of the display device is implemented by a plurality of shift register units to display an image.
  • the shift register unit controls the level of the potential of the circuit output signal through a plurality of transistors and capacitors.
  • the circuit structure of each shift register unit is complicated, and the control process is cumbersome.
  • Embodiments of the present invention provide a shift register unit, a driving method, a gate driving circuit, and a display device.
  • a shift register unit comprising: a control module, a first output module, and a second output module;
  • the first output module is respectively connected to the first signal end, the first node and the output end, and configured to output, from the output of the first signal end, the first signal end to the output end under the control of the first node a control signal;
  • the second output module is respectively connected to the output end, the second node, the first clock signal end and the second signal end, and is configured to be at the second node and the first clock signal end a second control signal from the second signal end is output to the output terminal under control of a clock signal;
  • the control module is respectively connected to the first node, the second node, the first signal end, the second signal end, the first clock signal end, the second clock signal end, and the input end, and is Configuring to use the first control signal from the first signal end, The second control signal from the second signal terminal, a first clock signal from the first clock signal terminal, a second clock signal from the second clock signal terminal, and an input signal from the input terminal And controlling the potentials of the first node and the second node.
  • control module includes: a pull-down sub-module, a first pull-up sub-module, a control sub-module, and a second pull-up sub-module;
  • the pull-down sub-module is respectively connected to the second signal end, the first clock signal end, the third node, and the fourth node, and configured to be at the third node and from the first clock signal Controlling, by the first clock signal of the terminal, the second control signal of the second signal end to the fourth node;
  • the first pull-up sub-module is coupled to the input, the first clock signal end, the third node, and the fourth node, respectively, and configured to be at the input from the input And outputting, by the control of the first clock signal from the first clock signal end, the first clock signal to the third node and the fourth node, respectively;
  • the control submodule is respectively connected to the second clock signal end, the input end, the fourth node, the first node, and the second node, and configured to be from the second Controlling, by the second clock signal of the clock signal end, the input signal from the input terminal to the first node, and outputting the potential of the fourth node to the second node;
  • the second pull-up sub-module is respectively connected to the first signal end, the first node, and the second node, and configured to be in a second state under the control of the first node
  • the node outputs the first control signal from the first signal terminal.
  • the pull-down sub-module includes: a first transistor, a second transistor, and a first capacitor; wherein
  • a first pole of the first transistor is coupled to the second signal terminal, a second pole of the first transistor is coupled to the third node, and a third pole of the first transistor is coupled to the first Clock signal terminal connection;
  • a first pole of the second transistor is coupled to the second signal terminal, a second pole of the second transistor is coupled to the fourth node, and a third pole of the second transistor is coupled to the third Node connection
  • a first pole of the first capacitor is coupled to the third node, and a second pole of the first capacitor is coupled to the second signal terminal.
  • the first pull-up sub-module includes: a third transistor, a fourth transistor, a second capacitor, and a fifth transistor;
  • a first pole of the third transistor is connected to the input end, a second pole of the third transistor is connected to a fifth node, and a third pole of the third transistor is connected to the first clock signal end ;
  • a first pole of the fourth transistor is coupled to the first clock signal terminal, a second pole of the fourth transistor is coupled to the third node, and a third pole of the fourth transistor is coupled to the third Five-node connection;
  • a first pole of the second capacitor is connected to the fifth node, and a second pole of the second capacitor is connected to the fourth node;
  • a first pole of the fifth transistor is coupled to the first clock signal terminal, a second pole of the fifth transistor is coupled to the fourth node, and a third pole of the fifth transistor is coupled to the third Five-node connection.
  • control submodule includes: a sixth transistor and a seventh transistor; wherein
  • a first pole of the sixth transistor is coupled to the input terminal, a second pole of the sixth transistor is coupled to the first node, and a third pole of the sixth transistor is coupled to the second clock signal End connection
  • a first pole of the seventh transistor is connected to the fourth node, a second pole of the seventh transistor is connected to the second node, and a third pole of the seventh transistor is opposite to the second clock Signal terminal connection.
  • the second pull-up sub-module includes: an eighth transistor;
  • a first pole of the eighth transistor is coupled to the first signal terminal, a second pole of the eighth transistor is coupled to the second node, and a third pole of the eighth transistor is coupled to the first Node connection.
  • the first output module includes: a ninth transistor and a third capacitor; wherein
  • a first pole of the ninth transistor is connected to the first signal end, a second pole of the ninth transistor is connected to the output end, and a third pole of the ninth transistor is connected to the first node connection;
  • a first pole of the third capacitor is coupled to a first pole of the ninth transistor, and a second pole of the third capacitor is coupled to a third pole of the ninth transistor.
  • the second output module includes: a tenth transistor and a fourth capacitor; in
  • a first pole of the tenth transistor is coupled to the second signal terminal, a second pole of the tenth transistor is coupled to the output terminal, and a third pole of the tenth transistor is coupled to the second node connection;
  • a first pole of the fourth capacitor is coupled to a third pole of the tenth transistor, and a second pole of the fourth capacitor is coupled to the first clock signal terminal.
  • the transistors are all P-type transistors.
  • a driving method of a shift register unit for driving a shift register unit according to the first aspect comprising: a control module, a first output module And a second output module, wherein the method comprises:
  • the input signal input to the input terminal is the second potential
  • the first clock signal input by the first clock signal terminal is the second potential
  • the second clock signal input by the second clock signal terminal is the first potential
  • the two nodes maintain a second potential
  • the second output module outputs a second control signal from the second signal terminal to the output terminal, the potential of the second control signal being the second potential ;
  • the input signal input by the input terminal is a second potential
  • the first clock signal input by the first clock signal end is a first potential
  • the second clock signal input by the second clock signal end is a second clock signal.
  • the control module outputs an input signal from the input to the first node
  • the first output module outputs the first control to the output under control of the first node a signal
  • the potential of the first control signal is a first potential
  • the input signal input by the input terminal is a first potential
  • the first clock signal input by the first clock signal end is a second potential
  • the second clock signal input by the second clock signal end is a second clock signal.
  • the input signal input by the input terminal is a first potential
  • the first clock signal input by the first clock signal end is a first potential
  • the second clock signal input by the second clock signal end is a second clock signal.
  • Controlling, by the second potential, the second control signal from the second signal end to the second node, and the second output module is directed to the output under the control of the second node
  • the terminal outputs the second control signal.
  • control module includes: a pull-down sub-module, a first pull-up sub-module, and a control a sub-module and a second pull-up sub-module; and wherein the method comprises:
  • the first clock signal input by the first clock signal terminal is a second potential
  • the pull-down sub-module outputs a second control signal from the second signal terminal to the fourth node
  • the input signal input by the input terminal is a second potential
  • the first clock signal input by the first clock signal end is a first potential
  • the first pull-up sub-module is respectively The third node and the fourth node output the first clock signal
  • the second clock signal input by the second clock signal terminal is a second potential
  • the control submodule outputs the interface from the input terminal to the first node. Transmitting an input signal, and outputting a potential of the fourth node to the second node;
  • the first node is a second potential
  • the second pull-up sub-module outputs the first from the first signal end to the second node control signal.
  • the pull-down sub-module includes: a first transistor, a second transistor, and a first capacitor; and wherein the method includes:
  • the first clock signal input by the first clock signal terminal is a second potential
  • the second control signal input by the second signal terminal is a second potential
  • the first transistor and the second transistor are turned on, the first capacitor stores a second potential, and the second transistor outputs the second control signal from the second signal terminal to the fourth node ;
  • the second stage of the second transistor maintains a second potential, the second transistor is turned on, and the second transistor outputs the second signal end to the fourth node
  • the second control signal is described.
  • the first pull-up sub-module includes: a third transistor, a fourth transistor, a second capacitor, and a fifth transistor; and wherein the method includes:
  • the input signal input by the input terminal is a second potential
  • the first clock signal input by the first clock signal terminal is a second potential
  • the third transistor, the fourth transistor, and the Said fifth transistor is turned on, said second capacitor stores a second potential, said fourth transistor outputs said first clock signal from said first clock signal terminal to said third node, and said fifth transistor is The fourth node outputs the first clock signal;
  • the input signal input by the input terminal is a second potential
  • the first clock signal input by the first clock signal terminal is a first potential
  • the third transistor is turned off
  • the fourth transistor and the fifth transistor are turned on, the fourth transistor outputs the first clock signal from the first clock signal terminal to the third node, and the fifth The transistor outputs the first clock signal to the fourth node.
  • control submodule includes: a sixth transistor and a seventh transistor; and wherein the method comprises:
  • the second clock signal input by the second clock signal terminal is a second potential
  • the sixth transistor and the seventh transistor are turned on
  • the A six transistor outputs the input signal from the input to the first node
  • the seventh transistor outputs a potential of the fourth node to the second node.
  • the second pull-up sub-module includes: an eighth transistor; and wherein the method includes:
  • the first node is a second potential
  • the eighth transistor is turned on
  • the eighth transistor outputs the first signal from the second node The first control signal of the terminal.
  • the first output module includes: a ninth transistor and a third capacitor; and wherein the method comprises:
  • the control module outputs the input signal from the input terminal to a first node, the input signal is at a second potential, the ninth transistor is turned on, and the third capacitor stores a second potential, and the ninth transistor outputs the first control signal from the first signal end to an output terminal;
  • the first node maintains a second potential
  • the ninth transistor is turned on, and the ninth transistor outputs the first control signal from the first signal terminal to an output terminal.
  • the second output module includes: a tenth transistor and a fourth capacitor; and wherein the method comprises:
  • the control module outputs the second control signal from the second signal end to the second node, the second control signal is a second potential, and the tenth transistor is turned on.
  • the fourth capacitor stores a second potential, and the tenth transistor outputs the second control signal from the second signal terminal to an output terminal;
  • the second node maintains a second potential
  • the tenth transistor is turned on, and the tenth transistor outputs the second control signal from the second signal terminal to an output terminal.
  • the transistors are all P-type transistors.
  • the first potential is at a high potential relative to the second potential.
  • an embodiment of the present disclosure provides a gate driving circuit including at least two cascaded shift register units as described in the first aspect.
  • an embodiment of the present disclosure provides a display device including the gate driving circuit of the third aspect.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram showing potential changes of an input terminal, a first clock signal terminal, a second clock signal terminal, and an output terminal in various embodiments of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the transistor employed in the embodiments of the present disclosure mainly functions as a switching transistor in accordance with its role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present disclosure, the source of the transistor is referred to as a first stage, and the drain is referred to as a second stage, and the gate is referred to as a second stage. It is the third pole. In the drawing, it is prescribed that the middle end of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain.
  • the switching transistor employed in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor.
  • the P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the plurality of signals in the various embodiments of the present disclosure correspond to the first potential and the second potential, which only represents that the potential of one signal has two state quantities, and does not represent that the first potential or the second potential has a specific value.
  • the first control signal can be a high potential signal and the second control signal can be a low potential signal.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit may include a control module 110, a first output module 120, and a second output module 130.
  • the first output module 120 is respectively connected to the first signal terminal VGH, the first node A and the output terminal OUT, and is configured to output the output signal from the first signal terminal VGH to the output terminal OUT under the control of the first node A. a first control signal, the potential of the first control signal being a first potential.
  • the second output module 130 is connected to the output terminal OUT, the second node B, the first clock signal terminal CK and the second signal terminal VGL, respectively, and is configured for the second node B and the first clock signal terminal CK. Under the control of a clock signal, a second control signal from the second signal terminal VGL is output to the output terminal OUT, and the potential of the second control signal is a second potential.
  • the control module 110 is respectively connected to the first node A, the second node B, the first signal terminal VGH, the second signal terminal VGL, the first clock signal terminal CK, the second clock signal terminal CKB, and the input terminal STV, and is configured.
  • the potentials of the first node A and the second node B are controlled under the control of the second clock signal of the terminal CKB and the input signal from the input terminal STV.
  • a shift register unit provided by an embodiment of the present disclosure includes: a control module, a first output module, and a second output module, wherein the shift register unit can pass the control module, the first output module, and the The two output modules are used to control the level of the output of the output terminal.
  • the circuit structure and the control process of the shift register unit provided by the embodiments of the present disclosure are relatively simple.
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • the shift register unit adds additional components to the shift register unit shown in FIG. 1, so that the shift register unit provided by the embodiment of the present disclosure has good performance.
  • the control module 110 includes a pull-down sub-module 111, a first pull-up sub-module 112, a control sub-module 113, and a second pull-up sub-module 114.
  • the pull-down sub-module 111 is respectively connected to the second signal terminal VGL, the first clock signal terminal CK, the third node C and the fourth node D, and is configured to be at the third node C and from the first clock signal terminal CK
  • the second control signal of the second signal terminal VGL is output to the fourth node D under the control of the first clock signal.
  • the first pull-up sub-module 112 is connected to the input terminal STV, the first clock signal terminal CK, the third node C and the fourth node D, respectively, and is configured for input signals from the input terminal STV and from the first clock signal Under the control of the first clock signal of the terminal CK, the first clock signal is output to the third node C and the fourth node D, respectively.
  • the control sub-module 113 is respectively connected to the second clock signal terminal CKB, the input terminal STV, the fourth node D, the first node A and the second node B, and is configured for the second clock from the second clock signal terminal CKB Under the control of the signal, the input signal from the input terminal STV is output to the first node A, and the potential of the fourth node D is output to the second node B.
  • the second pull-up sub-module 114 is respectively connected to the first signal end VGH, the first node A and the second node B, and is configured to output the first signal from the second node B under the control of the first node A The first control signal of the terminal VGH.
  • FIG. 3 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • the pull-down sub-module 111 includes a first transistor M1, a second transistor M2, and a first capacitor C1.
  • the first pole of the first transistor M1 is connected to the second signal terminal VGL, the second pole of the first transistor M1 is connected to the third node C, and the third pole of the first transistor M1 is connected to the first clock signal terminal CK.
  • the first pole of the second transistor M2 is connected to the second signal terminal VGL
  • the second pole of the second transistor M2 is connected to the fourth node D
  • the third pole of the second transistor M2 is connected to the third node C.
  • the first pole of the first capacitor C1 is connected to the third node C, and the second pole of the first capacitor C1 is connected to the second signal terminal VGL.
  • the first pull-up sub-module 112 includes: a third transistor M3, The fourth transistor M4, the second capacitor C2, and the fifth transistor M5.
  • the first electrode of the third transistor M3 is connected to the input terminal STV, the second electrode of the third transistor M3 is connected to the fifth node E, and the third electrode of the third transistor M3 is connected to the first clock signal terminal CK.
  • the first pole of the fourth transistor M4 is connected to the first clock signal terminal CK, the second pole of the fourth transistor M4 is connected to the third node C, and the third pole of the fourth transistor M4 is connected to the fifth node E.
  • the first pole of the second capacitor C2 is connected to the fifth node E, and the second pole of the second capacitor C2 is connected to the fourth node D.
  • the first pole of the fifth transistor M5 is connected to the first clock signal terminal CK, the second pole of the fifth transistor M5 is connected to the fourth node D, and the third pole of the fifth transistor M5 is connected to the fifth node E.
  • control sub-module 113 includes a sixth transistor M6 and a seventh transistor M7.
  • the first pole of the sixth transistor M6 is connected to the input terminal STV, the second pole of the sixth transistor M6 is connected to the first node A, and the third pole of the sixth transistor M6 is connected to the second clock signal terminal CKB.
  • the first pole of the seventh transistor M7 is connected to the fourth node D
  • the second pole of the seventh transistor M7 is connected to the second node B
  • the third pole of the seventh transistor M7 is connected to the second clock signal terminal CKB.
  • the second pull-up sub-module 114 includes an eighth transistor M8.
  • the first pole of the eighth transistor M8 is connected to the first signal terminal VGH, the second pole of the eighth transistor M8 is connected to the second node B, and the third pole of the eighth transistor M8 is connected to the first node A.
  • the first output module 120 includes: a ninth transistor M9 and a third capacitor C3.
  • the first pole of the ninth transistor M9 is connected to the first signal terminal VGH, the second pole of the ninth transistor M9 is connected to the output terminal OUT, and the third pole of the ninth transistor M9 is connected to the first node A.
  • the first pole of the third capacitor C3 is connected to the first pole of the ninth transistor M9, and the second pole of the third capacitor C3 is connected to the third pole of the ninth transistor M9.
  • the second output module 130 includes: a tenth transistor M10. And a fourth capacitor C4.
  • the first pole of the tenth transistor M10 is connected to the second signal terminal VGL, the second pole of the tenth transistor M10 is connected to the output terminal OUT, and the third pole of the tenth transistor M10 is connected to the second node B.
  • the first pole of the fourth capacitor C4 is connected to the third pole of the tenth transistor M10, and the second pole of the fourth capacitor C4 is connected to the first clock signal terminal CK.
  • the shift register unit provided by the embodiment of the present disclosure completes the control of the potential of the output terminal by ten transistors and four capacitors, thereby simplifying the structure of the shift register unit and achieving the effect of reducing the area of the shift register layout. And is advantageous for the manufacture of high resolution display devices.
  • FIG. 4 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure.
  • the structure of the shift register unit can be as shown in FIG.
  • the shift register unit may include a control module 110, a first output module 120, and a second output module 130.
  • the shift register unit driving method includes the following steps.
  • the first stage is described at step 401.
  • the input signal input by the input terminal STV is the second potential
  • the first clock signal input by the first clock signal terminal CK is the second potential
  • the second clock signal input by the second clock signal terminal CKB is the first a second node B maintains a second potential
  • the second output module 130 outputs a second control signal from the second signal terminal VGL to the output terminal OUT, the second control signal
  • the potential is the second potential.
  • the second phase is described at step 402.
  • the input signal input by the input terminal STV is the second potential
  • the first clock signal input by the first clock signal terminal CK is the first potential
  • the second clock signal input by the second clock signal terminal CKB is a second potential
  • the control module 110 outputs an input signal from the input terminal to the first node A
  • the first output module 120 outputs the first control signal to the output terminal OUT under the control of the first node A
  • the potential of the first control signal is a first potential.
  • the third stage is described at step 403.
  • the input signal input by the input terminal STV is a first potential
  • the first clock signal input by the first clock signal terminal CK is a second potential
  • the second clock signal input by the second clock signal terminal CKB is Is a first potential
  • the first node A maintains a second potential
  • the first output module 120 outputs the first control signal to the output terminal OUT.
  • the fourth stage is described at step 404.
  • the input STV loses The input signal is the first potential; the first clock signal input by the first clock signal terminal CK is the first potential; the second clock signal input by the second clock signal terminal CKB is the second potential; the control module 110 The second node B outputs the second control signal from the second signal terminal VGL, and the second output module 130 outputs the second control signal to the output terminal OUT under the control of the second node B.
  • the fifth stage is described at step 405.
  • the input terminal STV maintains the first potential
  • the fourth phase is periodically repeated such that: the first node A maintains the first potential, the second node B maintains the second potential, and the output terminal OUT maintains the second potential .
  • the fifth stage described above is the low potential maintenance stage. That is, the shift register unit driving method provided by the embodiment of the present disclosure can control the level of the output of the output terminal OUT by controlling the sustaining time of the input terminal STV at the first potential and the second potential.
  • the first node A of the shift register unit can always maintain the first potential, and the second node B can always maintain the second potential, so that the second output module 130 continues to the output terminal OUT.
  • a second control signal from the second signal terminal VGL is output.
  • the shift register unit driving method provided by the embodiment of the present disclosure can control the level of the output of the output terminal through the control module, the first output module, and the second output module in the shift register unit, and the shift The control process of the bit register unit driving method is relatively simple.
  • control module 110 includes: a pull-down sub-module 111, a first pull-up sub-module 112, a control sub-module 113, and a second pull-up sub-module 114.
  • the first clock signal input by the first clock signal terminal CK is the second potential
  • the pull-down sub-module 111 outputs the fourth signal terminal VGL from the fourth node D.
  • the second control signal is the first clock signal input by the first clock signal terminal CK.
  • the input signal input by the input terminal STV is a second potential
  • the first clock signal input by the first clock signal terminal CK is a first potential
  • the first pull-up sub-module 112 respectively The third node C and the fourth node D output the first clock signal.
  • the second clock signal input by the second clock signal terminal CKB is a second potential; the control sub-module 113 outputs an input signal from the input terminal STV to the first node A. And outputting the potential of the fourth node D to the second node B.
  • the first node A is at a second potential
  • the second pull-up sub-module 114 outputs a first control signal from the first signal terminal VGH to the second node B.
  • the pull-down sub-module 111 includes: a first transistor M1, a second transistor M2, and a first capacitor C1.
  • the first clock signal input by the first clock signal terminal CK is the second potential
  • the second control signal input by the second signal terminal VGL is the second potential.
  • the first transistor M1 and the second transistor M2 are turned on, the first capacitor C1 stores the second potential, and the second transistor M2 outputs the second control signal from the second signal terminal VGL to the fourth node D.
  • the second stage of the second transistor M2 can continue to maintain the second potential in the fourth phase. Therefore, the second transistor M2 is turned on, and the second signal terminal VGL outputs the second control signal to the fourth node D.
  • the first pull-up sub-module 112 includes: a third transistor M3, a fourth transistor M4, a second capacitor C2, and a fifth transistor M5.
  • the first clock signal input by the first clock signal terminal CK is the second potential, and the third transistor M3 is turned on.
  • the third transistor M3 outputs an input signal from the input terminal STV to the fifth node 4.
  • the input signal is at the second potential, and thus the fourth transistor M4 and the fifth transistor M5 are turned on.
  • the second capacitor C2 stores the second potential, and the fourth transistor M4 outputs a first clock signal from the first clock signal terminal CK to the third node C, while the fifth transistor M5 outputs the first clock signal to the fourth node D. .
  • the first clock signal is at the second potential.
  • the input signal input to the input terminal STV is the second potential
  • the third transistor M3 is turned off. Since the second capacitor stores a low potential in the first phase, the fifth node E can continue to maintain the second potential in the second phase.
  • the fourth transistor M4 and the fifth transistor M5 are turned on, and the fourth transistor M4 outputs the first clock signal from the first clock signal terminal CK to the third node C; meanwhile, the fifth transistor M5 outputs the same to the fourth node D.
  • the first clock signal is at the first potential. Since the third pole of the second transistor M2 in the pull-down sub-module 111 is connected to the third node C, the second transistor M2 is turned off, so that the fourth node D can stably maintain the first potential.
  • control submodule 113 includes: a sixth transistor M6. And a seventh transistor M7.
  • the second clock signal input by the second clock signal terminal CKB is a second potential, and thus the sixth transistor M6 and the seventh transistor M7 is turned on.
  • the sixth transistor M6 outputs an input signal from the input terminal STV to the first node A
  • the seventh transistor M7 outputs the potential of the fourth node D to the second node B.
  • the signal output by the sixth transistor M6 to the first node A is at the second potential.
  • the signal output by the seventh transistor M7 to the second node B is at a first potential.
  • the first output module 120 outputs a first control signal from the first signal terminal VGH to the output terminal.
  • the signal output by the sixth transistor M6 to the first node A is at the first potential.
  • the signal output by the seventh transistor M7 to the second node B is at the second potential.
  • the second output module 130 outputs a second control signal from the second signal terminal VGL to the output terminal.
  • the second pull-up sub-module 114 includes an eighth transistor M8.
  • the first node A is at the second potential, and thus the eighth transistor M8 is turned on.
  • the eighth transistor M8 outputs the first control signal from the first signal terminal VGH to the second node B, and the potential of the first control signal is a first potential, so in the second phase and the third phase
  • the tenth transistor M10 in the second output module 130 is in an off state.
  • the first output module 120 includes: a ninth transistor M9 and a third capacitor C3.
  • the control module 110 outputs the input signal from the input terminal STV to the first node A, and the input signal is at the second potential, so the ninth transistor M9 is turned on, and the first The three capacitor C3 stores the second potential.
  • the ninth transistor M9 outputs the first control signal from the first signal terminal VGH to the output terminal OUT.
  • the first control signal is at the first potential. Therefore, the potential of the output signal outputted by the output terminal OUT is the first potential.
  • the first node A maintains a second potential, and thus the ninth transistor M9 is turned on.
  • the ninth transistor M9 outputs the first control signal from the first signal terminal VGH to the output terminal OUT. Therefore, the potential of the output signal outputted from the output terminal OUT at this time is the first potential.
  • the second output module 130 includes a tenth transistor M10 and a fourth capacitor C4.
  • the control module 110 outputs the second control signal from the second signal terminal VGL to the second node B, and the second control signal is the second potential, so the first The ten transistor M10 is turned on, and the fourth capacitor C4 stores the second potential.
  • the tenth transistor M10 outputs the second control signal from the second signal terminal VGL to the output terminal OUT, and the potential of the second control signal is the second potential. Therefore, the potential of the output signal outputted by the output terminal OUT is Two potentials.
  • the second node B maintains the second potential, so the tenth transistor M10 is turned on, and the tenth transistor M10 outputs the second control signal from the second signal terminal VGL to the output terminal OUT.
  • the operating voltages of the first signal terminal VGH and the second signal terminal VGL are both DC voltages.
  • the operating voltage of the first signal terminal VGH may be 7 volts (V), and the operating voltage of the second signal terminal VGL may be -7V.
  • first clock signal terminal CK, the second clock signal terminal CKB, the input terminal STV, and the output terminal OUT involved in various embodiments of the present disclosure are in the first phase T1, the second phase T2, the third phase T3, and the fourth
  • the potential change of the phase T4 and the fifth phase T5 can be referred to FIG.
  • the horizontal axis represents time and the vertical axis represents potential.
  • the shift register unit provided by the embodiment of the present disclosure may cyclically execute the driving method shown in the first to fifth stages described above.
  • the shift register unit driving method provided by the embodiment of the present disclosure can control the potential level of the output of the output terminal through the control module, the first output module, and the second output module in the shift register unit, and thus the shift register unit driving method
  • the control process is relatively simple.
  • the ninth transistor M9 and the tenth transistor M10 are P-type transistors, and the first potential is high and the second potential is low.
  • the first to tenth transistors may also employ N-type transistors.
  • the first potential is low and the second potential is high.
  • the potential change of the first clock signal terminal CK, the second clock signal terminal CKB, and the input terminal STV may be opposite to the potential change shown in FIG. 5 (that is, the phase difference between the two is 180 degrees).
  • Embodiments of the present disclosure provide a gate drive circuit that can include at least two cascaded shift register cells as shown in FIG. 1, FIG. 2, or FIG.
  • inventions of the present disclosure also provide a display device including a gate driving circuit.
  • the gate drive circuit can include at least two cascaded shift register units as shown in FIG. 1, FIG. 2 or FIG.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。该移位寄存器单元包括：控制模块（110）、第一输出模块（120）和第二输出模块（130），其中该第一输出模块（120）分别与第一信号端（VGH）、第一节点（A）和输出端（OUT）连接；该第二输出模块（130）分别与该输出端（OUT）、第二节点（B）、第一时钟信号端（CK）和第二信号端（VGL）连接；该控制模块（110）分别与该第一节点（A）、该第二节点（B）、该第一信号端（VGH）、该第二信号端（VGL）、第一时钟信号端（CK）、第二时钟信号端（CKB）和输入端（STV）连接，用于控制该第一节点（A）和该第二节点（B）的电位。所述移位寄存单元解决了移位寄存器单元电路结构复杂，控制过程较为繁琐的问题，达到了简化移位寄存器单元电路结构和控制过程的目的。

Description

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 技术领域
本公开涉及显示技术的领域，特别地涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
背景技术
显示装置在显示图像时，需要利用移位寄存器对像素单元进行扫描。移位寄存器包括多个移位寄存单元，并且每个移位寄存单元对应一行像素单元。由多个移位寄存器单元实现对显示装置的像素单元的逐行扫描驱动，以显示图像。
随着像素数目的提高，移位寄存器(栅极开关电路)在一帧时间内所需扫描的行数增加，这就要求移位寄存器单元的版图面积要更小以及电路结构更简单。通常，移位寄存器单元通过多个晶体管和电容器来控制电路输出信号的电位的高低。但是，在这种情况下，每个移位寄存器单元的电路结构较为复杂，并且控制过程较为繁琐。
发明内容
本发明的实施例提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
根据本公开的第一方面，提供了一种移位寄存器单元，所述移位寄存器单元包括：控制模块、第一输出模块和第二输出模块；其中
所述第一输出模块分别与第一信号端、第一节点和输出端连接，并且被配置用于在所述第一节点的控制下，向所述输出端输出来自所述第一信号端的第一控制信号；
所述第二输出模块分别与所述输出端、第二节点、第一时钟信号端和第二信号端连接，并且被配置用于在所述第二节点和来自所述第一时钟信号端的第一时钟信号的控制下，向所述输出端输出来自所述第二信号端的第二控制信号；
所述控制模块分别与所述第一节点、所述第二节点、所述第一信号端、所述第二信号端、第一时钟信号端、第二时钟信号端和输入端连接，并且被配置用于在来自所述第一信号端的所述第一控制信号、 来自所述第二信号端的所述第二控制信号、来自所述第一时钟信号端的第一时钟信号、来自所述第二时钟信号端的第二时钟信号和来自所述输入端的输入信号的控制下，控制所述第一节点和所述第二节点的电位。
可选地，所述控制模块包括：下拉子模块、第一上拉子模块、控制子模块和第二上拉子模块；其中
所述下拉子模块分别与所述第二信号端、所述第一时钟信号端、第三节点和第四节点连接，并且被配置用于在所述第三节点和来自所述第一时钟信号端的所述第一时钟信号的控制下，向所述第四节点输出所述第二信号端的所述第二控制信号；
所述第一上拉子模块分别与所述输入端、所述第一时钟信号端、所述第三节点和所述第四节点连接，并且被配置用于在来自所述输入端的所述输入信号和来自所述第一时钟信号端的所述第一时钟信号的控制下，分别向所述第三节点和所述第四节点输出所述第一时钟信号；
所述控制子模块分别与所述第二时钟信号端、所述输入端、所述第四节点、所述第一节点和所述第二节点连接，并且被配置用于在来自所述第二时钟信号端的所述第二时钟信号的控制下，向所述第一节点输出来自所述输入端的所述输入信号，并向所述第二节点输出所述第四节点的电位；
所述第二上拉子模块分别与所述第一信号端、所述第一节点和所述第二节点连接，并且被配置用于在所述第一节点的控制下，向所述第二节点输出来自所述第一信号端的所述第一控制信号。
可选地，所述下拉子模块包括：第一晶体管、第二晶体管和第一电容器；其中
所述第一晶体管的第一极与所述第二信号端连接，所述第一晶体管的第二极与所述第三节点连接，并且所述第一晶体管的第三极与所述第一时钟信号端连接；
所述第二晶体管的第一极与所述第二信号端连接，所述第二晶体管的第二极与所述第四节点连接，并且所述第二晶体管的第三极与所述第三节点连接；
所述第一电容器的第一极与所述第三节点连接，并且所述第一电容器的第二极与所述第二信号端连接。
可选地，所述第一上拉子模块包括：第三晶体管、第四晶体管、第二电容器和第五晶体管；其中
所述第三晶体管的第一极与所述输入端连接，所述第三晶体管的第二极与第五节点连接，并且所述第三晶体管的第三极与所述第一时钟信号端连接；
所述第四晶体管的第一极与所述第一时钟信号端连接，所述第四晶体管的第二极与所述第三节点连接，并且所述第四晶体管的第三极与所述第五节点连接；
所述第二电容器的第一极与所述第五节点连接，并且所述第二电容器的第二极与所述第四节点连接；
所述第五晶体管的第一极与所述第一时钟信号端连接，所述第五晶体管的第二极与所述第四节点连接，并且所述第五晶体管的第三极与所述第五节点连接。
可选地，所述控制子模块包括：第六晶体管和第七晶体管；其中
所述第六晶体管的第一极与所述输入端连接，所述第六晶体管的第二极与所述第一节点连接，并且所述第六晶体管的第三极与所述第二时钟信号端连接；
所述第七晶体管的第一极与所述第四节点连接，所述第七晶体管的第二极与所述第二节点连接，并且所述第七晶体管的第三极与所述第二时钟信号端连接。
可选地，所述第二上拉子模块包括：第八晶体管；其中
所述第八晶体管的第一极与所述第一信号端连接，所述第八晶体管的第二极与所述第二节点连接，并且所述第八晶体管的第三极与所述第一节点连接。
可选地，所述第一输出模块包括：第九晶体管和第三电容器；其中
所述第九晶体管的第一极与所述第一信号端连接，所述第九晶体管的第二极与所述输出端连接，并且所述第九晶体管的第三极与所述第一节点连接；
所述第三电容器的第一极与所述第九晶体管的第一极连接，并且所述第三电容器的第二极与所述第九晶体管的第三极连接。
可选地，所述第二输出模块包括：第十晶体管和第四电容器；其 中
所述第十晶体管的第一极与所述第二信号端连接，所述第十晶体管的第二极与所述输出端连接，并且所述第十晶体管的第三极与所述第二节点连接；
所述第四电容器的第一极与所述第十晶体管的第三极连接，并且所述第四电容器的第二极与所述第一时钟信号端连接。
可选地，所述晶体管均为P型晶体管。
根据本发明的第二方面，提供了一种移位寄存器单元的驱动方法，用于驱动根据第一方面所述的移位寄存器单元，所述移位寄存器单元包括：控制模块、第一输出模块和第二输出模块，其中所述方法包括：
在第一阶段中，输入端输入的输入信号为第二电位，第一时钟信号端输入的第一时钟信号为第二电位，第二时钟信号端输入的第二时钟信号为第一电位，第二节点保持第二电位，并且在所述第二节点的控制下，所述第二输出模块向输出端输出来自第二信号端的第二控制信号，所述第二控制信号的电位为第二电位；
在第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第二时钟信号端输入的第二时钟信号为第二电位，所述控制模块向第一节点输出来自所述输入端的输入信号，并且在所述第一节点的控制下，所述第一输出模块向所述输出端输出所述第一控制信号，所述第一控制信号的电位为第一电位；
在第三阶段中，所述输入端输入的输入信号为第一电位，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第二时钟信号端输入的第二时钟信号为第一电位，所述第一节点保持第二电位，并且在所述第一节点的控制下，所述第一输出模块向所述输出端输出所述第一控制信号；
在第四阶段中，所述输入端输入的输入信号为第一电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第二时钟信号端输入的第二时钟信号为第二电位，控制所述控制模块向第二节点输出来自所述第二信号端的所述第二控制信号，并且在所述第二节点的控制下，所述第二输出模块向所述输出端输出所述第二控制信号。
可选地，所述控制模块包括：下拉子模块、第一上拉子模块、控 制子模块和第二上拉子模块；并且其中所述方法包括：
在所述第三阶段中，所述第一时钟信号端输入的第一时钟信号为第二电位，并且所述下拉子模块向第四节点输出来自所述第二信号端的第二控制信号；
在所述第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，并且所述第一上拉子模块分别向第三节点和所述第四节点输出所述第一时钟信号；
在所述第二阶段和所述第四阶段中，所述第二时钟信号端输入的第二时钟信号为第二电位，所述控制子模块向所述第一节点输出来自所述输入端的所述输入信号，并向所述第二节点输出所述第四节点的电位；
所述第二阶段和所述第三阶段中，所述第一节点为第二电位，并且所述第二上拉子模块向所述第二节点输出来自所述第一信号端的所述第一控制信号。
可选地，所述下拉子模块包括：第一晶体管、第二晶体管和第一电容器；并且其中所述方法包括：
在所述第一阶段和所述第三阶段中，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第二信号端输入的所述第二控制信号为第二电位，所述第一晶体管和所述第二晶体管开启，所述第一电容器存储第二电位，并且所述第二晶体管向所述第四节点输出来自所述第二信号端的所述第二控制信号；
在所述第四阶段中，所述第二晶体管的第二级保持第二电位，所述第二晶体管开启，并且所述第二晶体管向所述第四节点输出来自所述第二信号端的所述第二控制信号。
可选地，所述第一上拉子模块包括：第三晶体管、第四晶体管、第二电容器和第五晶体管；并且其中所述方法包括：
在所述第一阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第三晶体管、第四晶体管和所述第五晶体管开启，所述第二电容器存储第二电位，所述第四晶体管向所述第三节点输出来自所述第一时钟信号端的所述第一时钟信号，并且所述第五晶体管向所述第四节点输出所述第一时钟信号；
在所述第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第三晶体管关断，第五节点保持第二电位，所述第四晶体管和所述第五晶体管开启，所述第四晶体管向所述第三节点输出来自所述第一时钟信号端的所述第一时钟信号，并且所述第五晶体管向所述第四节点输出所述第一时钟信号。
可选地，所述控制子模块包括：第六晶体管和第七晶体管；并且其中所述方法包括：
在所述第二阶段和所述第四阶段中，所述第二时钟信号端输入的所述第二时钟信号为第二电位，所述第六晶体管和所述第七晶体管开启，所述第六晶体管向所述第一节点输出来自所述输入端的所述输入信号，并且所述第七晶体管向所述第二节点输出所述第四节点的电位。
可选地，所述第二上拉子模块包括：第八晶体管；并且其中所述方法包括：
在所述第二阶段和所述第三阶段中，所述第一节点为第二电位，所述第八晶体管开启，并且所述第八晶体管向所述第二节点输出来自所述第一信号端的所述第一控制信号。
可选地，所述第一输出模块包括：第九晶体管和第三电容器；并且其中所述方法包括：
在所述第二阶段中，所述控制模块向第一节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第九晶体管开启，所述第三电容器存储第二电位，并且所述第九晶体管向输出端输出来自所述第一信号端的所述第一控制信号；
在所述第三阶段中，所述第一节点保持第二电位，所述第九晶体管开启，并且所述第九晶体管向输出端输出来自所述第一信号端的所述第一控制信号。
可选地，所述第二输出模块包括：第十晶体管和第四电容器；并且其中所述方法包括：
在所述第四阶段中，所述控制模块向所述第二节点输出来自所述第二信号端的所述第二控制信号，所述第二控制信号为第二电位，所述第十晶体管开启，所述第四电容器存储第二电位，并且所述第十晶体管向输出端输出来自所述第二信号端的所述第二控制信号；
在所述第一阶段中，所述第二节点保持第二电位，所述第十晶体管开启，并且所述第十晶体管向输出端输出来自所述第二信号端的所述第二控制信号。
可选地，所述晶体管均为P型晶体管。
可选地，所述第一电位相对于所述第二电位为高电位。
根据本公开的第三方面，本公开的实施例提供了一种栅极驱动电路，所述栅极驱动电路包括至少两个级联的如第一方面所述的移位寄存器单元。
根据本公开的第四方面，本公开的实施例提供了一种显示装置，所述显示装置包括第三方面所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开的实施例中的技术方案，下面参考附图描述了本发明的非限制性和非穷举性实施例，其中
图1是本公开的实施例提供的一种移位寄存器单元的结构示意图；
图2是本公开的实施例提供的另一种移位寄存器单元的结构示意图；
图3是本公开的实施例提供的又一种移位寄存器单元的结构示意图；
图4是本公开的实施例提供的一种移位寄存器单元的驱动方法的流程图；
图5是本公开的各个实施例中的输入端、第一时钟信号端、第二时钟信号端和输出端的电位变化示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开的实施例作进一步地详细描述。
本公开的所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据其在电路中的作用，本公开的实施例所采用的晶体管主要作为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开的实施例中，将晶体管的源极称为第一级，漏极称为第二级，栅极称 为第三极。在附图中，规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开的实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管。P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开的各个实施例中的多个信号都对应有第一电位和第二电位，这仅代表一个信号的电位有2个状态量，不代表第一电位或第二电位具有特定的数值。第一控制信号可以为高电位信号，第二控制信号可以为低电位信号。
图1是本公开的实施例提供的一种移位寄存器单元的结构示意图。移位寄存器单元可以包括：控制模块110、第一输出模块120和第二输出模块130。
第一输出模块120分别与第一信号端VGH、第一节点A和输出端OUT连接，并且被配置用于在第一节点A的控制下，向输出端OUT输出来自该第一信号端VGH的第一控制信号，该第一控制信号的电位为第一电位。
第二输出模块130分别与输出端OUT、第二节点B、第一时钟信号端CK和第二信号端VGL连接，并且被配置用于在第二节点B和来自第一时钟信号端CK的第一时钟信号的控制下，向该输出端OUT输出来自该第二信号端VGL的第二控制信号，该第二控制信号的电位为第二电位。
控制模块110分别与第一节点A、第二节点B、第一信号端VGH、第二信号端VGL、第一时钟信号端CK、第二时钟信号端CKB和输入端STV连接，并且被配置用于在来自该第一信号端VGH的该第一控制信号、来自该第二信号端VGL的该第二控制信号、来自该第一时钟信号端CK的第一时钟信号、来自该第二时钟信号端CKB的第二时钟信号和来自该输入端STV的输入信号的控制下，控制该第一节点A和该第二节点B的电位。
综上所述，本公开的实施例提供的一种移位寄存器单元包括：控制模块、第一输出模块和第二输出模块，该移位寄存器单元能够通过该控制模块、第一输出模块和第二输出模块来控制输出端输出的电位高低，本公开的实施例提供的移位寄存器单元的电路结构和控制过程均较为简单。
图2为本公开的实施例提供的另一种移位寄存器单元的结构示意图。该移位寄存器单元在图1所示的移位寄存器单元的基础上增加了附加的部件，从而使得本公开的实施例提供的移位寄存器单元具有良好的性能。如图2所示，该控制模块110包括：下拉子模块111、第一上拉子模块112、控制子模块113和第二上拉子模块114。
下拉子模块111分别与第二信号端VGL、第一时钟信号端CK、第三节点C和第四节点D连接，并且被配置用于在该第三节点C和来自该第一时钟信号端CK的第一时钟信号的控制下，向该第四节点D输出该第二信号端VGL的第二控制信号。
第一上拉子模块112分别与输入端STV、第一时钟信号端CK、第三节点C和第四节点D连接，并且被配置用于在来自输入端STV的输入信号和来自第一时钟信号端CK的第一时钟信号的控制下，分别向第三节点C和第四节点D输出第一时钟信号。
控制子模块113分别与第二时钟信号端CKB、输入端STV、第四节点D、第一节点A和第二节点B连接，并且被配置用于在来自第二时钟信号端CKB的第二时钟信号的控制下，向第一节点A输出来自输入端STV的输入信号，并向第二节点B输出第四节点D的电位。
第二上拉子模块114分别与第一信号端VGH、第一节点A和第二节点B连接，并且被配置用于在第一节点A的控制下，向第二节点B输出来自第一信号端VGH的第一控制信号。
图3是本公开的实施例提供的又一种移位寄存器单元的结构示意图。如图3所示，下拉子模块111包括：第一晶体管M1、第二晶体管M2和第一电容器C1。
第一晶体管M1的第一极与第二信号端VGL连接，第一晶体管M1的第二极与第三节点C连接，第一晶体管M1的第三极与第一时钟信号端CK连接。
第二晶体管M2的第一极与第二信号端VGL连接，第二晶体管M2的第二极与第四节点D连接，第二晶体管M2的第三极与第三节点C连接。
第一电容器C1的第一极与第三节点C连接，第一电容器C1的第二极与第二信号端VGL连接。
可选地，如图3所示，第一上拉子模块112包括：第三晶体管M3、 第四晶体管M4、第二电容器C2和第五晶体管M5。
第三晶体管M3的第一极与输入端STV连接，第三晶体管M3的第二极与第五节点E连接，第三晶体管M3的第三极与第一时钟信号端CK连接。
第四晶体管M4的第一极与第一时钟信号端CK连接，第四晶体管M4的第二极与第三节点C连接，第四晶体管M4的第三极与第五节点E连接。
第二电容器C2的第一极与第五节点E连接，第二电容器C2的第二极与第四节点D连接。
第五晶体管M5的第一极与第一时钟信号端CK连接，第五晶体管M5的第二极与第四节点D连接，第五晶体管M5的第三极与第五节点E连接。
可选地，如图3所示，控制子模块113包括：第六晶体管M6和第七晶体管M7。
第六晶体管M6的第一极与输入端STV连接，第六晶体管M6的第二极与第一节点A连接，第六晶体管M6的第三极与第二时钟信号端CKB连接。
第七晶体管M7的第一极与第四节点D连接，第七晶体管M7的第二极与第二节点B连接，第七晶体管M7的第三极与第二时钟信号端CKB连接。
可选地，如图3所示，第二上拉子模块114包括：第八晶体管M8。
第八晶体管M8的第一极与第一信号端VGH连接，第八晶体管M8的第二极与第二节点B连接，第八晶体管M8的第三极与第一节点A连接。
可选地，如图3所示，第一输出模块120包括：第九晶体管M9和第三电容器C3。
第九晶体管M9的第一极与第一信号端VGH连接，第九晶体管M9的第二极与输出端OUT连接，第九晶体管M9的第三极与第一节点A连接。
第三电容器C3的第一极与第九晶体管M9的第一极连接，第三电容器C3的第二极与第九晶体管M9的第三极连接。
可选地，如图3所示，第二输出模块130包括：第十晶体管M10 和第四电容器C4。
第十晶体管M10的第一极与第二信号端VGL连接，第十晶体管M10的第二极与输出端OUT连接，第十晶体管M10的第三极与第二节点B连接。
第四电容器C4的第一极与第十晶体管M10的第三极连接，第四电容器C4的第二极与第一时钟信号端CK连接。
本公开的实施例提供的移位寄存器单元，通过十个晶体管和四个电容器完成了对输出端电位高低的控制，从而简化了移位寄存器单元结构，达到了减小移位寄存器版图面积的效果，并且有利于高分辨率显示装置的制造。
图4是本公开的实施例提供的一种移位寄存器单元的驱动方法的流程图。移位寄存器单元的结构可以如图1所示。该移位寄存器单元可以包括：控制模块110、第一输出模块120和第二输出模块130。该移位寄存器单元驱动方法包括以下步骤。
在步骤401处描述了第一阶段。在第一阶段中，输入端STV输入的输入信号为第二电位；第一时钟信号端CK输入的第一时钟信号为第二电位；第二时钟信号端CKB输入的第二时钟信号为第一电位；第二节点B保持第二电位，并且在该第二节点B的控制下，第二输出模块130向输出端OUT输出来自第二信号端VGL的第二控制信号，该第二控制信号的电位为第二电位。
在步骤402处描述了第二阶段。在第二阶段中，该输入端STV输入的输入信号为第二电位；该第一时钟信号端CK输入的第一时钟信号为第一电位；该第二时钟信号端CKB输入的第二时钟信号为第二电位；该控制模块110向第一节点A输出来自该输入端的输入信号，并且在该第一节点A的控制下，该第一输出模块120向输出端OUT输出该第一控制信号，该第一控制信号的电位为第一电位。
在步骤403处描述了第三阶段。在第三阶段中，该输入端STV输入的输入信号为第一电位；该第一时钟信号端CK输入的第一时钟信号为第二电位；该第二时钟信号端CKB输入的第二时钟信号为第一电位；该第一节点A保持第二电位，并且在该第一节点A的控制下，该第一输出模块120向输出端OUT输出该第一控制信号。
在步骤404处描述了第四阶段。在第四阶段中，该输入端STV输 入的输入信号为第一电位；该第一时钟信号端CK输入的第一时钟信号为第一电位；该第二时钟信号端CKB输入的第二时钟信号为第二电位；该控制模块110向第二节点B输出来自该第二信号端VGL的该第二控制信号，并且在该第二节点B的控制下，该第二输出模块130向输出端OUT输出该第二控制信号。
在步骤405处描述了第五阶段。在第五阶段中，输入端STV保持第一电位，并且周期性重复第四阶段，使得：第一节点A保持第一电位，第二节点B保持第二电位，以及输出端OUT保持第二电位。
上述第五阶段为低电位维持阶段。也就是说，本公开的实施例提供的移位寄存器单元驱动方法，可以通过控制输入端STV在第一电位和第二电位的维持时间来控制输出端OUT输出的电位高低。
需要说明的是，在初始化阶段，该移位寄存器单元的第一节点A可以一直保持第一电位，以及第二节点B可以一直保持第二电位，使得该第二输出模块130持续向输出端OUT输出来自第二信号端VGL的第二控制信号。在输入端STV、第一时钟信号端CK和第二时钟信号端CKB被输入信号后，该移位寄存器单元可以循环执行上述第一阶段至第五阶段所示的驱动方法。
综上所述，本公开的实施例提供的移位寄存器单元驱动方法能够通过移位寄存器单元中的控制模块、第一输出模块和第二输出模块来控制输出端输出的电位高低，并且该移位寄存器单元驱动方法的控制过程较为简单。
可选地，如图2所示，控制模块110包括：下拉子模块111、第一上拉子模块112、控制子模块113和第二上拉子模块114。
在这种情况下，在所述第三阶段中，该第一时钟信号端CK输入的第一时钟信号为第二电位，并且下拉子模块111向第四节点D输出来自该第二信号端VGL的第二控制信号。
在所述第二阶段中，该输入端STV输入的输入信号为第二电位；该第一时钟信号端CK输入的第一时钟信号为第一电位；以及该第一上拉子模块112分别向第三节点C和该第四节点D输出该第一时钟信号。
在所述第二阶段和第四阶段中，该第二时钟信号端CKB输入的第二时钟信号为第二电位；该控制子模块113向该第一节点A输出来自该输入端STV的输入信号，并向第二节点B输出该第四节点D的电位。
在所述第二阶段和第三阶段中，该第一节点A为第二电位，该第二上拉子模块114向该第二节点B输出来自第一信号端VGH的第一控制信号。
可选地，如图3所示，该下拉子模块111包括：第一晶体管M1、第二晶体管M2和第一电容器C1。
在这种情况下，在所述第一阶段和第三阶段中，第一时钟信号端CK输入的第一时钟信号为第二电位，第二信号端VGL输入的第二控制信号为第二电位，第一晶体管M1和第二晶体管M2开启，第一电容器C1存储第二电位，第二晶体管M2向该第四节点D输出来自第二信号端VGL的第二控制信号。
在所述第四阶段中，由于第三阶段中第一电容器C1存储有第二电位，使得该第四阶段中，第二晶体管M2的第二级能够继续保持第二电位。因此，该第二晶体管M2开启，该第二信号端VGL向该第四节点D输出该第二控制信号。
可选地，如图3所示，第一上拉子模块112包括：第三晶体管M3、第四晶体管M4、第二电容器C2和第五晶体管M5。
在这种情况下，在所述第一阶段中，第一时钟信号端CK输入的第一时钟信号为第二电位，该第三晶体管M3开启。第三晶体管M3向第五节点4输出来自输入端STV的输入信号。此时该输入信号为第二电位，因此第四晶体管M4和第五晶体管M5开启。第二电容器C2存储该第二电位，并且第四晶体管M4向第三节点C输出来自第一时钟信号端CK的第一时钟信号，同时第五晶体管M5向第四节点D输出该第一时钟信号。此时，该第一时钟信号为第二电位。
在所述第二阶段中，输入端STV输入的输入信号为第二电位，并且第三晶体管M3关断。由于第二电容器在第一阶段中存储有低电位，使得第二阶段中该第五节点E能够继续保持第二电位。此时，第四晶体管M4和第五晶体管M5开启，第四晶体管M4向第三节点C输出来自第一时钟信号端CK的第一时钟信号；同时，第五晶体管M5向第四节点D输出该第一时钟信号。此时，该第一时钟信号为第一电位。由于下拉子模块111中第二晶体管M2的第三极与第三节点C连接，因此该第二晶体管M2关断，使得该第四节点D能够稳定保持第一电位。
可选地，如图3所示，该控制子模块113包括：第六晶体管M6 和第七晶体管M7。
在这种情况下，在所述第二阶段和该第四阶段中，所述第二时钟信号端CKB输入的该第二时钟信号为第二电位，因此该第六晶体管M6和该第七晶体管M7开启。此时，该第六晶体管M6向该第一节点A输出来自该输入端STV的输入信号，并且该第七晶体管M7向该第二节点B输出该第四节点D的电位。
在第二阶段中，由于该输入端STV输入的输入信号为第二电位，并且第四节点D的电位为第一电位，因此第六晶体管M6向第一节点A输出的信号处于第二电位，第七晶体管M7向该第二节点B输出的信号处于第一电位。此时，第一输出模块120向输出端输出来自该第一信号端VGH的第一控制信号。
在第四阶段中，由于该输入端STV输入的输入信号为第一电位，并且第四节点D的电位为第二电位，因此第六晶体管M6向第一节点A输出的信号处于第一电位，并且第七晶体管M7向该第二节点B输出的信号处于第二电位。此时，第二输出模块130向输出端输出来自该第二信号端VGL的第二控制信号。
可选地，如图3所示，该第二上拉子模块114包括：第八晶体管M8。
在这种情况下，在第二阶段和该第三阶段中，该第一节点A为第二电位，因此该第八晶体管M8开启。该第八晶体管M8向该第二节点B输出来自该第一信号端VGH的该第一控制信号，并且该第一控制信号的电位为第一电位，因此在该第二阶段和第三阶段中，第二输出模块130中的第十晶体管M10处于关断状态。
可选地，如图3所示，该第一输出模块120包括：第九晶体管M9和第三电容器C3。
在这种情况下，在第二阶段中，控制模块110向第一节点A输出来自输入端STV的该输入信号，并且该输入信号处于第二电位，因此该第九晶体管M9开启，并且该第三电容器C3存储第二电位。该第九晶体管M9向输出端OUT输出来自该第一信号端VGH的该第一控制信号，该第一控制信号为第一电位，故此时输出端OUT输出的输出信号的电位为第一电位。
在第三阶段中，该第一节点A保持第二电位，因此该第九晶体管 M9开启。该第九晶体管M9向输出端OUT输出来自该第一信号端VGH的该第一控制信号，故此时输出端OUT输出的输出信号的电位为第一电位。
可选地，如图3所示，该第二输出模块130包括：第十晶体管M10和第四电容器C4。
在这种情况下，在第四阶段中，控制模块110向该第二节点B输出来自该第二信号端VGL的该第二控制信号，并且该第二控制信号为第二电位，因此该第十晶体管M10开启，并且该第四电容器C4存储第二电位。该第十晶体管M10向输出端OUT输出来自该第二信号端VGL的该第二控制信号，并且该第二控制信号的电位为第二电位，故此时输出端OUT输出的输出信号的电位为第二电位。
在第一阶段中，该第二节点B保持第二电位，因此该第十晶体管M10开启，并且该第十晶体管M10向输出端OUT输出来自该第二信号端VGL的该第二控制信号。
需要说明的是，在本公开的实施例中，该第一信号端VGH和第二信号端VGL的工作电压均为直流电压。第一信号端VGH的工作电压可以为7伏特(V)，且该第二信号端VGL的工作电压可以为-7V。
此外，本公开的各个实施例中涉及的第一时钟信号端CK、第二时钟信号端CKB、输入端STV和输出端OUT在第一阶段T1、第二阶段T2、第三阶段T3、第四阶段T4和第五阶段T5的电位变化可以参照图5。在图5中，横轴代表时间，纵轴代表电位。
进一步地，如图5所示，本公开的实施例提供的移位寄存器单元可以循环执行上述第一阶段至第五阶段所示的驱动方法。
本公开的实施例提供的移位寄存器单元驱动方法能够通过移位寄存器单元中的控制模块、第一输出模块和第二输出模块来控制输出端输出的电位高低，因此该移位寄存器单元驱动方法的控制过程较为简单。
需要说明的是，上述实施例均是以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10为P型晶体管，以及第一电位为高电位且第二电位为低电位为例进行说明。当然，该第一至第十晶体管还可以采用N型晶体管。当该 第一至第十晶体管采用N型晶体管时，该第一电位为低电位并且该第二电位为高电位。此时，该第一时钟信号端CK、第二时钟信号端CKB和输入端STV的电位变化可以与图5所示的电位变化相反(即二者的相位差为180度)。
本公开的实施例提供了一种栅极驱动电路，该栅极驱动电路可以包括至少两个级联的如图1、图2或图3所示的移位寄存器单元。
另外，本公开的实施例还提供一种显示装置，该显示装置包括栅极驱动电路。该栅极驱动电路可以包括至少两个级联的如图1、图2或图3所示的移位寄存器单元。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本发明的可选实施例，并不用以限制本发明。在本发明的精神和原则之内，所作的任何修改、等同替换、改进等均应包含在本发明的保护范围之内。

Claims (21)

  1. 一种移位寄存器单元，包括：控制模块、第一输出模块和第二输出模块，其中：
    所述第一输出模块分别与第一信号端、第一节点和输出端连接，并且被配置用于在所述第一节点的控制下，向所述输出端输出来自所述第一信号端的第一控制信号；
    所述第二输出模块分别与所述输出端、第二节点、第一时钟信号端和第二信号端连接，并且被配置用于在所述第二节点和来自所述第一时钟信号端的第一时钟信号的控制下，向所述输出端输出来自所述第二信号端的第二控制信号；
    所述控制模块分别与所述第一节点、所述第二节点、所述第一信号端、所述第二信号端、所述第一时钟信号端、第二时钟信号端和输入端连接，并且被配置用于在来自所述第一信号端的所述第一控制信号、来自所述第二信号端的所述第二控制信号、来自所述第一时钟信号端的第一时钟信号、来自所述第二时钟信号端的第二时钟信号和来自所述输入端的输入信号的控制下，控制所述第一节点和所述第二节点的电位。
  2. 根据权利要求1所述的移位寄存器单元，其中所述控制模块包括：下拉子模块、第一上拉子模块、控制子模块和第二上拉子模块；并且
    所述下拉子模块分别与所述第二信号端、所述第一时钟信号端、第三节点和第四节点连接，并且被配置用于在所述第三节点和来自所述第一时钟信号端的所述第一时钟信号的控制下，向所述第四节点输出所述第二信号端的所述第二控制信号；
    所述第一上拉子模块分别与所述输入端、所述第一时钟信号端、所述第三节点和所述第四节点连接，并且被配置用于在来自所述输入端的所述输入信号和来自所述第一时钟信号端的所述第一时钟信号的控制下，分别向所述第三节点和所述第四节点输出所述第一时钟信号；
    所述控制子模块分别与所述第二时钟信号端、所述输入端、所述第四节点、所述第一节点和所述第二节点连接，并且被配置用于在来自所述第二时钟信号端的所述第二时钟信号的控制下，向所述第一节 点输出来自所述输入端的所述输入信号，并向所述第二节点输出所述第四节点的电位；
    所述第二上拉子模块分别与所述第一信号端、所述第一节点和所述第二节点连接，并且被配置用于在所述第一节点的控制下，向所述第二节点输出来自所述第一信号端的所述第一控制信号。
  3. 根据权利要求2所述的移位寄存器单元，其中所述下拉子模块包括：第一晶体管、第二晶体管和第一电容器；并且
    所述第一晶体管的第一极与所述第二信号端连接，所述第一晶体管的第二极与所述第三节点连接，并且所述第一晶体管的第三极与所述第一时钟信号端连接；
    所述第二晶体管的第一极与所述第二信号端连接，所述第二晶体管的第二极与所述第四节点连接，并且所述第二晶体管的第三极与所述第三节点连接；
    所述第一电容器的第一极与所述第三节点连接，并且所述第一电容器的第二极与所述第二信号端连接。
  4. 根据权利要求2所述的移位寄存器单元，其中所述第一上拉子模块包括：第三晶体管、第四晶体管、第二电容器和第五晶体管；并且
    所述第三晶体管的第一极与所述输入端连接，所述第三晶体管的第二极与第五节点连接，并且所述第三晶体管的第三极与所述第一时钟信号端连接；
    所述第四晶体管的第一极与所述第一时钟信号端连接，所述第四晶体管的第二极与所述第三节点连接，并且所述第四晶体管的第三极与所述第五节点连接；
    所述第二电容器的第一极与所述第五节点连接，并且所述第二电容器的第二极与所述第四节点连接；
    所述第五晶体管的第一极与所述第一时钟信号端连接，所述第五晶体管的第二极与所述第四节点连接，并且所述第五晶体管的第三极与所述第五节点连接。
  5. 根据权利要求2所述的移位寄存器单元，其中所述控制子模块包括：第六晶体管和第七晶体管；并且
    所述第六晶体管的第一极与所述输入端连接，所述第六晶体管的 第二极与所述第一节点连接，并且所述第六晶体管的第三极与所述第二时钟信号端连接；
    所述第七晶体管的第一极与所述第四节点连接，所述第七晶体管的第二极与所述第二节点连接，并且所述第七晶体管的第三极与所述第二时钟信号端连接。
  6. 根据权利要求2所述的移位寄存器单元，其中所述第二上拉子模块包括：第八晶体管；并且
    所述第八晶体管的第一极与所述第一信号端连接，所述第八晶体管的第二极与所述第二节点连接，并且所述第八晶体管的第三极与所述第一节点连接。
  7. 根据权利要求1所述的移位寄存器单元，其中所述第一输出模块包括：第九晶体管和第三电容器；并且
    所述第九晶体管的第一极与所述第一信号端连接，所述第九晶体管的第二极与所述输出端连接，并且所述第九晶体管的第三极与所述第一节点连接；
    所述第三电容器的第一极与所述第九晶体管的第一极连接，并且所述第三电容器的第二极与所述第九晶体管的第三极连接。
  8. 根据权利要求1所述的移位寄存器单元，其中所述第二输出模块包括：第十晶体管和第四电容器；
    所述第十晶体管的第一极与所述第二信号端连接，所述第十晶体管的第二极与所述输出端连接，并且所述第十晶体管的第三极与所述第二节点连接；
    所述第四电容器的第一极与所述第十晶体管的第三极连接，并且所述第四电容器的第二极与所述第一时钟信号端连接。
  9. 根据权利要求3至8任一所述的移位寄存器单元，其中所述晶体管均为P型晶体管。
  10. 一种移位寄存器单元的驱动方法，用于驱动权利要求1至9任一所述的移位寄存器单元，所述移位寄存器单元包括：控制模块、第一输出模块和第二输出模块，其中所述方法包括：
    在第一阶段中，输入端输入的输入信号为第二电位，第一时钟信号端输入的第一时钟信号为第二电位，第二时钟信号端输入的第二时钟信号为第一电位，第二节点保持第二电位，并且在所述第二节点的 控制下，所述第二输出模块向输出端输出来自第二信号端的第二控制信号，所述第二控制信号的电位为第二电位；
    在第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第二时钟信号端输入的第二时钟信号为第二电位，所述控制模块向第一节点输出来自所述输入端的输入信号，并且在所述第一节点的控制下，所述第一输出模块向所述输出端输出所述第一控制信号，所述第一控制信号的电位为第一电位；
    在第三阶段中，所述输入端输入的输入信号为第一电位，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第二时钟信号端输入的第二时钟信号为第一电位，所述第一节点保持第二电位，并且在所述第一节点的控制下，所述第一输出模块向所述输出端输出所述第一控制信号；
    在第四阶段中，所述输入端输入的输入信号为第一电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第二时钟信号端输入的第二时钟信号为第二电位，控制所述控制模块向第二节点输出来自所述第二信号端的所述第二控制信号，并且在所述第二节点的控制下，所述第二输出模块向所述输出端输出所述第二控制信号。
  11. 根据权利要求10所述的方法，其中所述控制模块包括：下拉子模块、第一上拉子模块、控制子模块和第二上拉子模块；并且其中所述方法包括：
    在所述第三阶段中，所述第一时钟信号端输入的第一时钟信号为第二电位，并且所述下拉子模块向第四节点输出来自所述第二信号端的第二控制信号；
    在所述第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，并且所述第一上拉子模块分别向第三节点和所述第四节点输出所述第一时钟信号；
    在所述第二阶段和所述第四阶段中，所述第二时钟信号端输入的第二时钟信号为第二电位，所述控制子模块向所述第一节点输出来自所述输入端的所述输入信号，并向所述第二节点输出所述第四节点的电位；
    所述第二阶段和所述第三阶段中，所述第一节点为第二电位，并 且所述第二上拉子模块向所述第二节点输出来自所述第一信号端的所述第一控制信号。
  12. 根据权利要求11所述的方法，其中所述下拉子模块包括：第一晶体管、第二晶体管和第一电容器；并且其中所述方法包括：
    在所述第一阶段和所述第三阶段中，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第二信号端输入的所述第二控制信号为第二电位，所述第一晶体管和所述第二晶体管开启，所述第一电容器存储第二电位，并且所述第二晶体管向所述第四节点输出来自所述第二信号端的所述第二控制信号；
    在所述第四阶段中，所述第二晶体管的第二级保持第二电位，所述第二晶体管开启，并且所述第二晶体管向所述第四节点输出来自所述第二信号端的所述第二控制信号。
  13. 根据权利要求11所述的方法，其中所述第一上拉子模块包括：第三晶体管、第四晶体管、第二电容器和第五晶体管；并且其中所述方法包括：
    在所述第一阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第二电位，所述第三晶体管、第四晶体管和所述第五晶体管开启，所述第二电容器存储第二电位，所述第四晶体管向所述第三节点输出来自所述第一时钟信号端的所述第一时钟信号，并且所述第五晶体管向所述第四节点输出所述第一时钟信号；
    在所述第二阶段中，所述输入端输入的输入信号为第二电位，所述第一时钟信号端输入的第一时钟信号为第一电位，所述第三晶体管关断，第五节点保持第二电位，所述第四晶体管和所述第五晶体管开启，所述第四晶体管向所述第三节点输出来自所述第一时钟信号端的所述第一时钟信号，并且所述第五晶体管向所述第四节点输出所述第一时钟信号。
  14. 根据权利要求11所述的方法，其中所述控制子模块包括：第六晶体管和第七晶体管；并且其中所述方法包括：
    在所述第二阶段和所述第四阶段中，所述第二时钟信号端输入的所述第二时钟信号为第二电位，所述第六晶体管和所述第七晶体管开启，所述第六晶体管向所述第一节点输出来自所述输入端的所述输入 信号，并且所述第七晶体管向所述第二节点输出所述第四节点的电位。
  15. 根据权利要求11所述的方法，其中所述第二上拉子模块包括：第八晶体管；并且其中所述方法包括：
    在所述第二阶段和所述第三阶段中，所述第一节点为第二电位，所述第八晶体管开启，并且所述第八晶体管向所述第二节点输出来自所述第一信号端的所述第一控制信号。
  16. 根据权利要求10所述的方法，其中所述第一输出模块包括：第九晶体管和第三电容器；并且其中所述方法包括：
    在所述第二阶段中，所述控制模块向第一节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第九晶体管开启，所述第三电容器存储第二电位，并且所述第九晶体管向输出端输出来自所述第一信号端的所述第一控制信号；
    在所述第三阶段中，所述第一节点保持第二电位，所述第九晶体管开启，并且所述第九晶体管向输出端输出来自所述第一信号端的所述第一控制信号。
  17. 根据权利要求10所述的方法，其中所述第二输出模块包括：第十晶体管和第四电容器；并且其中所述方法包括：
    在所述第四阶段中，所述控制模块向所述第二节点输出来自所述第二信号端的所述第二控制信号，所述第二控制信号为第二电位，所述第十晶体管开启，所述第四电容器存储第二电位，并且所述第十晶体管向输出端输出来自所述第二信号端的所述第二控制信号；
    在所述第一阶段中，所述第二节点保持第二电位，所述第十晶体管开启，并且所述第十晶体管向输出端输出来自所述第二信号端的所述第二控制信号。
  18. 根据权利要求12至17任一所述的方法，其中，所述晶体管均为P型晶体管。
  19. 根据权利要求18所述的方法，其中，所述第一电位相对于所述第二电位为高电位。
  20. 一种栅极驱动电路，其中所述栅极驱动电路包括至少两个级联的如权利要求1至9任一所述的移位寄存器单元。
  21. 一种显示装置，其中所述显示装置包括权利要求20所述的栅极驱动电路。
PCT/CN2016/082968 2016-03-02 2016-05-23 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Ceased WO2017148018A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/539,124 US10074315B2 (en) 2016-03-02 2016-05-23 Shift register unit, driving method, gate driving circuit and display device
US16/052,570 US10438541B2 (en) 2016-03-02 2018-08-01 Shift register unit, driving method, gate driving circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610119070.8A CN105513531B (zh) 2016-03-02 2016-03-02 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN201610119070.8 2016-03-02

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US15/539,124 A-371-Of-International US10074315B2 (en) 2016-03-02 2016-05-23 Shift register unit, driving method, gate driving circuit and display device
US16/052,570 Continuation US10438541B2 (en) 2016-03-02 2018-08-01 Shift register unit, driving method, gate driving circuit and display device

Publications (1)

Publication Number Publication Date
WO2017148018A1 true WO2017148018A1 (zh) 2017-09-08

Family

ID=55721466

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/082968 Ceased WO2017148018A1 (zh) 2016-03-02 2016-05-23 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Country Status (3)

Country Link
US (2) US10074315B2 (zh)
CN (1) CN105513531B (zh)
WO (1) WO2017148018A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304057B (zh) * 2015-12-09 2018-11-30 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN105575328B (zh) * 2016-03-01 2018-03-06 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN105513531B (zh) 2016-03-02 2018-04-10 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
KR102735537B1 (ko) * 2017-02-20 2024-12-02 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
CN106601190B (zh) * 2017-03-06 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN107154234B (zh) * 2017-07-20 2020-01-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110197697B (zh) * 2018-02-24 2021-02-26 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路以及显示设备
CN108447437B (zh) * 2018-04-02 2021-09-07 上海天马有机发光显示技术有限公司 发射控制电路及其驱动方法、发射控制器、显示装置
CN108492763B (zh) * 2018-04-10 2020-03-13 上海天马有机发光显示技术有限公司 一种移位寄存器、驱动电路及驱动方法、显示装置
CN112424856B (zh) * 2019-06-03 2023-03-14 京东方科技集团股份有限公司 像素电路、像素电路的驱动方法、显示装置及其驱动方法
CN111508433B (zh) * 2020-05-28 2021-08-31 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
CN113053293B (zh) * 2021-04-07 2022-07-19 北京京东方技术开发有限公司 移位寄存器单元、栅极驱动电路、显示面板
WO2026065365A1 (zh) * 2024-09-30 2026-04-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079682A1 (en) * 2006-09-01 2008-04-03 Au Optronics Corp. Control circuit for releasing residual charges
CN104809978A (zh) * 2015-05-21 2015-07-29 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN104900189A (zh) * 2015-06-19 2015-09-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN105304013A (zh) * 2015-06-30 2016-02-03 上海天马有机发光显示技术有限公司 移位寄存器、移位寄存电路和显示装置
CN205050536U (zh) * 2015-10-23 2016-02-24 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN105513531A (zh) * 2016-03-02 2016-04-20 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485065B (zh) * 2014-12-30 2017-02-22 上海天马有机发光显示技术有限公司 移位寄存器、驱动方法、栅极驱动电路
CN104835450B (zh) * 2015-05-22 2017-01-25 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动电路、显示装置
CN104933990B (zh) * 2015-06-30 2017-03-22 上海天马有机发光显示技术有限公司 一种移位寄存单元及驱动方法、栅极驱动电路
CN105096858B (zh) * 2015-07-28 2017-08-22 上海天马有机发光显示技术有限公司 一种移位寄存器及驱动方法、栅极驱动电路
CN105047124B (zh) * 2015-09-18 2017-11-17 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN105304057B (zh) * 2015-12-09 2018-11-30 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN105632560B (zh) * 2016-01-04 2019-08-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN105679248B (zh) * 2016-01-04 2017-12-08 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN205950536U (zh) 2016-08-24 2017-02-15 中国航天科技集团公司长征机械厂 具有可调定位功能的夹具

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079682A1 (en) * 2006-09-01 2008-04-03 Au Optronics Corp. Control circuit for releasing residual charges
CN104809978A (zh) * 2015-05-21 2015-07-29 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN104900189A (zh) * 2015-06-19 2015-09-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN105304013A (zh) * 2015-06-30 2016-02-03 上海天马有机发光显示技术有限公司 移位寄存器、移位寄存电路和显示装置
CN205050536U (zh) * 2015-10-23 2016-02-24 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN105513531A (zh) * 2016-03-02 2016-04-20 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Also Published As

Publication number Publication date
CN105513531B (zh) 2018-04-10
CN105513531A (zh) 2016-04-20
US20180342209A1 (en) 2018-11-29
US10438541B2 (en) 2019-10-08
US10074315B2 (en) 2018-09-11
US20180082623A1 (en) 2018-03-22

Similar Documents

Publication Publication Date Title
WO2017148018A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN105632560B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US10210791B2 (en) Shift register unit, driving method, gate driver on array and display device
CN104809978B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US9747854B2 (en) Shift register, gate driving circuit, method for driving display panel and display device
US9293223B2 (en) Shift register unit, gate driving circuit and display device
CN106098101B (zh) 一种移位寄存器、栅极驱动电路及显示装置
CN106782285B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
EP3675128B1 (en) Shift register, drive method thereof, drive control circuit, and display device
CN105741744B (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
WO2017118014A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
WO2018161528A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN107093414B (zh) 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN107342038B (zh) 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
US12198772B2 (en) Shift register and driving method thereof, gate driving circuit, and display device
CN106228927A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US10403210B2 (en) Shift register and driving method, driving circuit, array substrate and display device
CN104934071B (zh) 一种移位寄存器、栅极驱动电路及显示装置
US10535414B2 (en) Shift register element, method for driving the same, and display device
CN106057116A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
WO2018201791A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11183103B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US10115363B2 (en) Gate driving circuits and the liquid crystal devices thereof
CN110930951A (zh) 栅极驱动电路、显示面板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15539124

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16892206

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16892206

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 13/05/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 16892206

Country of ref document: EP

Kind code of ref document: A1