WO2017147974A1 - 阵列基板的制作方法及制得的阵列基板 - Google Patents

阵列基板的制作方法及制得的阵列基板 Download PDF

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Publication number
WO2017147974A1
WO2017147974A1 PCT/CN2016/078878 CN2016078878W WO2017147974A1 WO 2017147974 A1 WO2017147974 A1 WO 2017147974A1 CN 2016078878 W CN2016078878 W CN 2016078878W WO 2017147974 A1 WO2017147974 A1 WO 2017147974A1
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Prior art keywords
layer
hole
source
drain
passivation layer
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Ceased
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PCT/CN2016/078878
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English (en)
French (fr)
Inventor
甘启明
王勐
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/105,582 priority Critical patent/US10103173B2/en
Publication of WO2017147974A1 publication Critical patent/WO2017147974A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and an array substrate obtained.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel comprises a CF (Color Filter) substrate, a Thin Film Transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • CF Color Filter
  • TFT Thin Film Transistor
  • LC liquid crystal sandwiched between the color filter substrate and the thin film transistor array substrate
  • sealant a sealant.
  • the composition of the box (Sealant).
  • FIG. 1 is a schematic diagram of a method for fabricating an array substrate according to the prior art.
  • the method for fabricating the array substrate includes the following steps:
  • Step 1 providing a base substrate 100, sequentially forming a gate (not shown), a gate insulating layer 200, an active layer (not shown), and a source/drain 300 on the base substrate 100;
  • Step 2 forming a first passivation layer 400 on the source/drain 300 and the gate insulating layer 200, and patterning the first passivation layer 400 to obtain a first passivation layer 400.
  • Step 3 forming a flat layer 500 on the first passivation layer 400, and patterning the flat layer 500 to obtain a second via hole 510 located in the first via hole 410; Annealing treatment;
  • Step 4 forming a common electrode 600 on the flat layer 500;
  • Step 5 forming a second passivation layer 700 on the common electrode 600 and the flat layer 500, and patterning the second passivation layer 700 to obtain a third via 710 located in the second via 510. ;
  • Step 6 forming a pixel electrode 800 on the second passivation layer 700 , and the pixel electrode 800 is in contact with the source/drain 300 via the third via 710 .
  • step 3 of the method for fabricating the above array substrate when the planarization layer 500 is annealed, the photoresist material of the planarization layer 500 located in the first via hole 410 reacts with the metal material of the source/drain electrodes 300 to generate no
  • the conductive complex 550 blocks the conduction of the pixel electrode 800 from the source/drain 300, resulting in the inability of the data signal to be transmitted to the pixel electrode 300, thereby having a fatal effect on the performance of the array substrate.
  • An object of the present invention is to provide a method for fabricating an array substrate, which effectively blocks the contact between the flat layer and the source/drain during the annealing process of each film layer, thereby preventing the two from reacting, reducing the number of masks, and reducing the processing time. reduce manufacturing cost.
  • the present invention provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a substrate, sequentially forming a gate, a gate insulating layer, an active layer, and a source/drain on the substrate;
  • Step 2 forming a first passivation layer on the source/drain and gate insulating layers, forming a flat layer on the first passivation layer, and performing pattern processing on the flat layer to obtain a source corresponding to the source a first via above the drain;
  • Step 3 using the flat layer as a mask, etching the first passivation layer to form a second via hole corresponding to the first via hole;
  • Step 4 depositing a first transparent conductive layer on the flat layer, and patterning the first transparent conductive layer to form a common electrode and a conductive connection layer spaced apart from the common electrode, the conductive a connection layer covering the hole walls of the first through hole and the second through hole, and a source/drain exposed at the second through hole;
  • Step 5 forming a second passivation layer on the common electrode and the flat layer, and performing a hole treatment on a portion of the second passivation layer located in the first through hole and the second through hole to obtain a second a third via hole on the passivation layer, the third via hole exposing a portion of the conductive connection layer;
  • Step 6 depositing a second transparent conductive layer on the second passivation layer, and patterning the second transparent conductive layer to form a pixel electrode, wherein the pixel electrode and the conductive connection layer are via the third via hole In contact with each other, the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain.
  • the step 2 further includes: annealing the flat layer after forming the first via hole on the flat layer.
  • the step 3 further includes: annealing the common electrode and the conductive connection layer; and the step 6 further comprises: annealing the pixel electrode.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, and the first through hole and the second through hole have a diameter of 7-12 ⁇ m, and the diameter of the third through hole is 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a flat layer on the first passivation layer, a common electrode and a conductive connection layer disposed on the flat layer, and a second passivation layer disposed on the common electrode, the conductive connection layer, and the flat layer, And a pixel electrode disposed on the second passivation layer;
  • a portion of the second passivation layer located in the first through hole and the second through hole is provided with a third through hole, the third through hole exposing a portion of the conductive connection layer;
  • the three-via hole is in contact with the conductive connection layer, and the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, and the first through hole and the second through hole have a diameter of 7-12 ⁇ m, and the diameter of the third through hole is 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a flat layer on the first passivation layer, a common electrode and a conductive connection layer disposed on the flat layer, and disposed on the common electrode and the conductive connection a bonding layer, a second passivation layer on the planar layer, and a pixel electrode disposed on the second passivation layer;
  • a portion of the second passivation layer located in the first through hole and the second through hole is provided with a third through hole, the third through hole exposing a portion of the conductive connection layer;
  • the three-via hole is in contact with the conductive connection layer, and the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain;
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the first passivation layer
  • the film thickness of the second passivation layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the method for fabricating an array substrate provided by the present invention can realize the opening treatment of the flat layer and the first passivation layer by using a photomask, which can save a mask compared with the prior art. , saving production cost and reducing process time; forming a conductive connection layer covering the first via hole on the flat layer and the second via hole on the first passivation layer while forming the common electrode, thereby avoiding source/drain and The flat layer is exposed to the environment, which eliminates the possibility of reaction between the two, and is beneficial to improving the electrical performance of the array substrate and achieving signal conduction.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.
  • FIG. 1 is a schematic view showing a method of fabricating an array substrate of the prior art
  • FIG. 2 is a schematic view showing the first step of the method for fabricating the array substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an array substrate of the present invention
  • step 3 is a schematic diagram of step 3 of the method for fabricating an array substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of the method for fabricating an array substrate of the present invention.
  • step 5 is a schematic diagram of step 5 of the method for fabricating an array substrate of the present invention.
  • FIG. 7 is a schematic view showing the step 6 of the method for fabricating the array substrate of the present invention and the invention is prepared Schematic diagram of the structure of the array substrate.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 10 is provided, and a gate electrode 15, a gate insulating layer 20, an active layer 25, and source/drain electrodes 30 are sequentially formed on the substrate 10.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • Step 2 As shown in FIG. 3, a first passivation layer 40 is formed on the source/drain 30 and the gate insulating layer 20, and a flat layer 50 is formed on the first passivation layer 40.
  • the flat layer 50 is exposed and developed by the cover to pattern the flat layer 50 to obtain a first through hole 51 corresponding to the upper side of the source/drain 30.
  • the material of the flat layer 50 is a positive photoresist.
  • the step 2 further includes: after the first through hole 51 is formed on the flat layer 50, the flat layer 50 is subjected to an annealing treatment to be heat-cured.
  • the flat layer 50 is annealed, since the first passivation layer 40 is provided between the flat layer 50 and the source/drain electrodes 30, it is impossible to contact, and thus no reaction occurs to form a complex.
  • Step 3 As shown in FIG. 4, the first passivation layer 40 is etched by using the flat layer 50 as a mask to form a second via hole 41 corresponding to the first via hole 51.
  • the etching process of the first passivation layer 40 is a dry etching process.
  • the step 2-3 only uses a mask to realize the opening treatment of the flat layer 50 and the first passivation layer 40. Compared with the prior art, the utility model can save a light mask, save production cost and reduce process time. . However, after the etching process of the step 2-3, the flat layer 50 and the source/drain 30 are exposed to the air at the first through hole 51 and the second through hole 41, respectively, and thus there is still a reaction. Possible.
  • Step 4 depositing a first transparent conductive layer on the flat layer 50, and collecting The first transparent conductive layer is patterned by a photolithography process to form a common electrode 60 and a conductive connection layer 65 spaced apart from the common electrode 60.
  • the conductive connection layer 65 covers the first The hole walls of the through hole 51 and the second through hole 41, and the source/drain 30 exposed at the second through hole 41, thereby preventing the source/drain 30 and the flat layer 50 from being exposed to the environment, eliminating the occurrence of both The possibility of reaction.
  • the material of the common electrode 60 and the conductive connection layer 65 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 4 further comprises: annealing the common electrode 60 and the conductive connection layer 65 to heat-solidify and crystallize the transparent conductive metal oxide therein, thereby improving the film quality of the common electrode 60 and the conductive connection layer 65.
  • the structure reduces the sheet resistance, making the structure more stable and longer.
  • the first via hole 51 and the second via hole 41 are covered by the conductive connection layer 65, so that the source/drain 30 and the flat layer 50 cannot be exposed. In the environment, the possibility of a reaction between the two is eliminated.
  • Step 5 as shown in FIG. 6, a second passivation layer 70 is formed on the common electrode 60 and the flat layer 50, and the first pass hole 51 is located on the second passivation layer 70 by a photolithography process.
  • a portion of the second via hole 41 is subjected to an opening process to obtain a third via hole 71 on the second passivation layer 70, and the third via hole 71 exposes a portion of the conductive connection layer 65.
  • the etching process in the photolithography process of the second passivation layer 70 is a dry etching process.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the third through hole 71 is smaller than the size of the first through hole 51 and the second through hole 41.
  • the first through hole 51, the second through hole 41, and the third through hole 71 are all circular holes, and the first through hole 51 and the second through hole 41 have a diameter of 7-12 ⁇ m.
  • the diameter of the third through hole 71 is 3-5 ⁇ m.
  • Step 6 depositing a second transparent conductive layer on the second passivation layer 70, and patterning the second transparent conductive layer by a photolithography process to form a pixel electrode 80.
  • the pixel electrode 80 is in contact with the conductive connection layer 65 via the third via 71, and the conductive connection layer 65 is in contact with the source/drain 30, thereby achieving conduction between the pixel electrode 80 and the source/drain 30.
  • the material of the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 6 further comprises: annealing the pixel electrode 80 to heat-solidify the transparent conductive metal oxide therein, thereby improving the film structure of the pixel electrode 80, reducing the sheet resistance, and making the structure more Stable and long lasting.
  • the present invention further provides an array substrate, comprising a substrate 10, a gate electrode 15 disposed on the substrate 10, a gate insulating layer 20 disposed on the gate electrode 15 and the substrate 10, and An active layer 25 on the gate insulating layer 20, a source/drain 30 provided on the active layer 25 and the gate insulating layer 20, and the source/drain 30 and the active layer 25 And a first passivation layer 40 on the gate insulating layer 20, a flat layer 50 disposed on the first passivation layer 40, and a common electrode 60 disposed on the flat layer 50 and spaced apart from each other and electrically connected a layer 65, a second passivation layer 70 disposed on the common electrode 60, the conductive connection layer 65, and the flat layer 50, and a pixel electrode 80 disposed on the second passivation layer 70;
  • a first via hole 51 and a second via hole 41 corresponding to the source/drain 30 are respectively formed on the flat layer 50 and the first passivation layer 40, and the conductive connection layer 65 covers the a hole wall of the first through hole 51 and the second through hole 41, and a source/drain 30 exposed at the second through hole 41;
  • a portion of the second passivation layer 70 in the first through hole 51 and the second through hole 41 is provided with a third through hole 71, the third through hole 71 exposes a portion of the conductive connection layer 65;
  • the pixel electrode 80 is in contact with the conductive connection layer 65 via the third via 71, and the conductive connection layer 65 is in contact with the source/drain 30, thereby achieving conduction between the pixel electrode 80 and the source/drain 30.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • the material of the flat layer 50 is a positive photoresist.
  • the material of the common electrode 60, the conductive connection layer 65, and the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the third through hole 71 is smaller than the size of the first through hole 51 and the second through hole 41.
  • the first through hole 51, the second through hole 41, and the third through hole 71 are all circular holes, and the first through hole 51 and the second through hole 41 have a diameter of 7-12 ⁇ m.
  • the diameter of the third through hole 71 is 3-5 ⁇ m.
  • the method for fabricating an array substrate can realize the opening treatment of the flat layer and the first passivation layer by using a photomask, which can save a photomask compared with the prior art. Saving production cost and reducing process time; forming a conductive connection layer covering the first via hole on the flat layer and the second via hole on the first passivation layer while forming the common electrode, thereby avoiding source/drain and flatness
  • the layer is exposed to the environment, which eliminates the possibility of reaction between the two, and is beneficial to improving the electrical performance of the array substrate and achieving signal conduction.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.

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Abstract

一种阵列基板的制作方法及制得的阵列基板，通过采用一道光罩来实现平坦层（50）与第一钝化层（40）的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间；在形成公共电极（60）的同时形成包覆平坦层上的第一通孔（51）与第一钝化层上的第二通孔（41）的导电连接层（65），从而避免源/漏极（30）与平坦层裸露于环境中，消除了二者发生反应的可能，有利于提高阵列基板的电学性能，实现信号导通。该阵列基板，信号传导畅通，具有良好的电学性能。

Description

阵列基板的制作方法及制得的阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及制得的阵列基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
图1为现有的一种阵列基板的制作方法的示意图，该阵列基板的制作方法包括如下步骤：
步骤1、提供一衬底基板100，在所述衬底基板100上依次形成栅极(未图示)、栅极绝缘层200、有源层(未图示)、及源/漏极300；
步骤2、在所述源/漏极300及栅极绝缘层200上形成第一钝化层400，并对该第一钝化层400进行图形化处理，得到位于第一钝化层400上的第一过孔410；
步骤3、在所述第一钝化层400上形成平坦层500，并对该平坦层500进行图形化处理，得到位于第一过孔410中的第二过孔510；之后对平坦层500进行退火处理；
步骤4、在所述平坦层500上形成公共电极600；
步骤5、在所述公共电极600、平坦层500上形成第二钝化层700，并对该第二钝化层700进行图形化处理，得到位于第二过孔510内的第三过孔710；
步骤6、在所述第二钝化层700上形成像素电极800，所述像素电极800经由第三过孔710与源/漏极300相接触。
上述阵列基板的制作方法步骤3中，在对平坦层500进行退火处理时，位于第一过孔410中的平坦层500的光阻材料会与源/漏极300的金属材料发生反应，生成不导电的络合物550，从而阻隔所述像素电极800与源/漏极300的导通，导致数据(Data)信号无法传输至像素电极300，从而对阵列基板的性能造成致命性的影响。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，在各膜层的退火过程中有效阻隔平坦层与源/漏极的接触，防止二者发生反应，同时减少光罩数量，减少制程时间，降低生产成本。
本发明的目的还在于提供一种阵列基板，信号传导畅通，具有良好的电学性能。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成栅极、栅极绝缘层、有源层、及源/漏极；
步骤2、在所述源/漏极及栅极绝缘层上形成第一钝化层，在所述第一钝化层上形成平坦层，对所述平坦层进行图形化处理，得到对应于源/漏极上方的第一通孔；
步骤3、以所述平坦层为掩模，对所述第一钝化层进行蚀刻，形成对应于所述第一通孔的第二通孔；
步骤4、在所述平坦层上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极、以及与所述公共电极间隔设置的导电连接层，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
步骤5、在所述公共电极、平坦层上形成第二钝化层，对所述第二钝化层上位于第一通孔与第二通孔内的部分进行开孔处理，得到位于第二钝化层上的第三通孔，所述第三通孔暴露出部分导电连接层；
步骤6、在所述第二钝化层上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极，所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电极与源/漏极的导通。
所述步骤2还包括：在所述平坦层上形成第一通孔后，对所述平坦层进行退火处理。
所述步骤3还包括：对所述公共电极与导电连接层进行退火处理；所述步骤6还包括：对所述像素电极进行退火处理。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078878-appb-000001
所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔与第二通孔的直径为7-12μm，所述第三通孔的直径为3-5μm。
本发明还提供一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上且间隔设置的公共电极与导电连接层、设于所述公共电极、导电连接层、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
所述平坦层与第一钝化层上分别设有对应于源/漏极上方且相贯通的第一通孔与第二通孔，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
所述第二钝化层上位于所述第一通孔与第二通孔内的部分上设有第三通孔，所述第三通孔暴露出部分导电连接层；所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电极与源/漏极的导通。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078878-appb-000002
所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔与第二通孔的直径为7-12μm，所述第三通孔的直径为3-5μm。
本发明还提供一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上且间隔设置的公共电极与导电连接层、设于所述公共电极、导电连 接层、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
所述平坦层与第一钝化层上分别设有对应于源/漏极上方且相贯通的第一通孔与第二通孔，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
所述第二钝化层上位于所述第一通孔与第二通孔内的部分上设有第三通孔，所述第三通孔暴露出部分导电连接层；所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电极与源/漏极的导通；
其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078878-appb-000003
其中，所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
本发明的有益效果：本发明提供的一种阵列基板的制作方法，通过采用一道光罩来实现平坦层与第一钝化层的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间；在形成公共电极的同时形成包覆平坦层上的第一通孔与第一钝化层上的第二通孔的导电连接层，从而避免源/漏极与平坦层裸露于环境中，消除了二者发生反应的可能，有利于提高阵列基板的电学性能，实现信号导通。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种阵列基板的制作方法的示意图；
图2为本发明的阵列基板的制作方法的步骤1的示意图；
图3为本发明的阵列基板的制作方法的步骤2的示意图；
图4为本发明的阵列基板的制作方法的步骤3的示意图；
图5为本发明的阵列基板的制作方法的步骤4的示意图；
图6为本发明的阵列基板的制作方法的步骤5的示意图；
图7为本发明的阵列基板的制作方法的步骤6的示意图暨本发明制得 的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2-7，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供一基板10，在所述基板10上依次形成栅极15、栅极绝缘层20、有源层25、及源/漏极30。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indium gallium zinc oxide)。
步骤2、如图3所示，在所述源/漏极30及栅极绝缘层20上形成第一钝化层40，在所述第一钝化层40上形成平坦层50，采用一道光罩对所述平坦层50进行曝光、显影，以对所述平坦层50进行图形化处理，得到对应于源/漏极30上方的第一通孔51。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述步骤2还包括：在所述平坦层50上形成第一通孔51后，对所述平坦层50进行退火(anneal)处理，使其加热固化。在对平坦层50进行退火处理时，由于平坦层50与源/漏极30之间设有第一钝化层40，不能够相接触，因此不会发生反应生成络合物。
步骤3、如图4所示，以所述平坦层50为掩模，对所述第一钝化层40进行蚀刻，形成对应于所述第一通孔51的第二通孔41。
具体的，所述步骤3中，所述第一钝化层40的蚀刻制程为干蚀刻制程。
所述步骤2-3仅采用一道光罩即实现所述平坦层50与第一钝化层40的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间。但是，经过所述步骤2-3的蚀刻制程之后，所述平坦层50与源/漏极30又分别在第一通孔51与第二通孔41处暴露于空气中，因此还存在发生反应的可能。
步骤4、如图5所示，在所述平坦层50上沉积第一透明导电层，并采 用一道光刻制程对所述第一透明导电层进行图形化处理，形成公共电极60、以及与所述公共电极60间隔设置的导电连接层65，所述导电连接层65包覆所述第一通孔51与第二通孔41的孔壁、以及暴露于第二通孔41处的源/漏极30，从而避免源/漏极30与平坦层50裸露于环境中，消除了二者发生反应的可能。
具体的，所述公共电极60与导电连接层65的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤4还包括：对所述公共电极60与导电连接层65进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善公共电极60与导电连接层65的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。在对公共电极60与导电连接层65进行退火处理的过程中，由于导电连接层65包覆所述第一通孔51与第二通孔41，使得源/漏极30与平坦层50无法裸露于环境中，消除了二者发生反应的可能。
步骤5、如图6所示，在所述公共电极60、平坦层50上形成第二钝化层70，采用一道光刻制程对所述第二钝化层70上位于第一通孔51与第二通孔41内的部分进行开孔处理，得到位于第二钝化层70上的第三通孔71，所述第三通孔71暴露出部分导电连接层65。
具体的，所述步骤5中，所述第二钝化层70的光刻制程中的蚀刻制程为干蚀刻制程。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
Figure PCTCN2016078878-appb-000004
具体的，所述第三通孔71的尺寸小于所述第一通孔51与第二通孔41的尺寸。
优选的，所述第一通孔51、第二通孔41、及第三通孔71均为圆形孔，所述第一通孔51与第二通孔41的直径为7-12μm，所述第三通孔71的直径为3-5μm。
步骤6、如图7所示，在所述第二钝化层70上沉积第二透明导电层，并采用一道光刻制程对所述第二透明导电层进行图形化处理，形成像素电极80，所述像素电极80经由第三通孔71与导电连接层65相接触，由于导电连接层65与源/漏极30相接触，从而实现像素电极80与源/漏极30的导通。
具体的，所述像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤6还包括：对所述像素电极80进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善像素电极80的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。
请参阅图7，本发明还提供一种阵列基板，包括基板10、设于所述基板10上的栅极15、设于所述栅极15及基板10上的栅极绝缘层20、设于所述栅极绝缘层20上的有源层25、设于所述有源层25及栅极绝缘层20上的源/漏极30、设于所述源/漏极30、有源层25、及栅极绝缘层20上的第一钝化层40、设于所述第一钝化层40上的平坦层50、设于所述平坦层50上且间隔设置的公共电极60与导电连接层65、设于所述公共电极60、导电连接层65、及平坦层50上的第二钝化层70、及设于所述第二钝化层70上的像素电极80；
所述平坦层50与第一钝化层40上分别设有对应于源/漏极30上方且相贯通的第一通孔51与第二通孔41，所述导电连接层65包覆所述第一通孔51与第二通孔41的孔壁、以及暴露于第二通孔41处的源/漏极30；
所述第二钝化层70上位于所述第一通孔51与第二通孔41内的部分上设有第三通孔71，所述第三通孔71暴露出部分导电连接层65；所述像素电极80经由第三通孔71与导电连接层65相接触，由于导电连接层65与源/漏极30相接触，从而实现像素电极80与源/漏极30的导通。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indium gallium zinc oxide)。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述公共电极60、导电连接层65、及像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
Figure PCTCN2016078878-appb-000005
具体的，所述第三通孔71的尺寸小于所述第一通孔51与第二通孔41的尺寸。
优选的，所述第一通孔51、第二通孔41、及第三通孔71均为圆形孔，所述第一通孔51与第二通孔41的直径为7-12μm，所述第三通孔71的直径为3-5μm。
综上所述，本发明提供的一种阵列基板的制作方法，通过采用一道光罩来实现平坦层与第一钝化层的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间；在形成公共电极的同时形成包覆平坦层上的第一通孔与第一钝化层上的第二通孔的导电连接层，从而避免源/漏极与平坦层裸露于环境中，消除了二者发生反应的可能，有利于提高阵列基板的电学性能，实现信号导通。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上依次形成栅极、栅极绝缘层、有源层、及源/漏极；
    步骤2、在所述源/漏极及栅极绝缘层上形成第一钝化层，在所述第一钝化层上形成平坦层，对所述平坦层进行图形化处理，得到对应于源/漏极上方的第一通孔；
    步骤3、以所述平坦层为掩模，对所述第一钝化层进行蚀刻，形成对应于所述第一通孔的第二通孔；
    步骤4、在所述平坦层上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极、以及与所述公共电极间隔设置的导电连接层，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
    步骤5、在所述公共电极、平坦层上形成第二钝化层，对所述第二钝化层上位于第一通孔与第二通孔内的部分进行开孔处理，得到位于第二钝化层上的第三通孔，所述第三通孔暴露出部分导电连接层；
    步骤6、在所述第二钝化层上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极，所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电极与源/漏极的导通。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤2还包括：在所述平坦层上形成第一通孔后，对所述平坦层进行退火处理。
  3. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤4还包括：对所述公共电极与导电连接层进行退火处理；所述步骤6还包括：对所述像素电极进行退火处理。
  4. 如权利要求1所述的阵列基板的制作方法，其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078878-appb-100001
  5. 如权利要求1所述的阵列基板的制作方法，其中，所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
  6. 如权利要求5所述的阵列基板的制作方法，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔与第二通孔的直径为7-12 μm，所述第三通孔的直径为3-5μm。
  7. 一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上且间隔设置的公共电极与导电连接层、设于所述公共电极、导电连接层、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
    所述平坦层与第一钝化层上分别设有对应于源/漏极上方且相贯通的第一通孔与第二通孔，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
    所述第二钝化层上位于所述第一通孔与第二通孔内的部分上设有第三通孔，所述第三通孔暴露出部分导电连接层；所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电极与源/漏极的导通。
  8. 如权利要求7所述的阵列基板，其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078878-appb-100002
  9. 如权利要求7所述的阵列基板，其中，所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
  10. 如权利要求9所述的阵列基板，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔与第二通孔的直径为7-12μm，所述第三通孔的直径为3-5μm。
  11. 一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上且间隔设置的公共电极与导电连接层、设于所述公共电极、导电连接层、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
    所述平坦层与第一钝化层上分别设有对应于源/漏极上方且相贯通的第一通孔与第二通孔，所述导电连接层包覆所述第一通孔与第二通孔的孔壁、以及暴露于第二通孔处的源/漏极；
    所述第二钝化层上位于所述第一通孔与第二通孔内的部分上设有第三通孔，所述第三通孔暴露出部分导电连接层；所述像素电极经由第三通孔与导电连接层相接触，由于导电连接层与源/漏极相接触，从而实现像素电 极与源/漏极的导通；
    其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078878-appb-100003
    其中，所述第三通孔的尺寸小于所述第一通孔与第二通孔的尺寸。
  12. 如权利要求11所述的阵列基板，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔与第二通孔的直径为7-12μm，所述第三通孔的直径为3-5μm。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098614A (zh) * 2016-08-16 2016-11-09 昆山龙腾光电有限公司 在多层绝缘薄膜上开接触孔的制作方法
CN106054472B (zh) * 2016-08-22 2019-09-10 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管阵列基板及其制作方法、液晶面板
CN107490911B (zh) * 2017-08-15 2021-07-13 昆山龙腾光电股份有限公司 阵列基板及其制作方法和显示面板
CN108155196B (zh) * 2017-12-28 2020-11-03 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN108400140B (zh) * 2018-02-08 2020-05-05 武汉华星光电技术有限公司 阵列基板及其制造方法
US10901282B2 (en) 2018-02-08 2021-01-26 Wuhan China Star Optoelectronics Technology Co., Ltd. Thin film transistor substrate and manufacturing method thereof
CN108646487B (zh) * 2018-05-15 2020-12-25 Tcl华星光电技术有限公司 Ffs型阵列基板的制作方法及ffs型阵列基板
CN110224006B (zh) * 2019-05-13 2021-06-01 武汉华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN110164871A (zh) * 2019-05-15 2019-08-23 深圳市华星光电技术有限公司 Tft阵列基板及其制造方法
CN110690168A (zh) * 2019-09-25 2020-01-14 南京中电熊猫平板显示科技有限公司 一种液晶显示面板的制造方法
CN211236526U (zh) * 2019-11-22 2020-08-11 京东方科技集团股份有限公司 显示装置及其显示面板、阵列基板
CN111129033B (zh) * 2019-12-19 2024-01-19 武汉华星光电技术有限公司 阵列基板及其制备方法
CN111063700B (zh) * 2020-01-03 2023-01-24 京东方科技集团股份有限公司 阵列基板及其制备方法
CN111244116B (zh) * 2020-03-23 2022-06-28 京东方科技集团股份有限公司 半过孔结构及其制造方法、阵列基板、显示面板
CN111564457B (zh) * 2020-05-28 2022-08-05 武汉华星光电技术有限公司 一种阵列基板及其制备方法、显示面板
CN112711157B (zh) * 2021-01-05 2023-11-28 武汉华星光电技术有限公司 一种阵列基板、阵列基板制程方法及显示面板
CN114122019B (zh) * 2021-11-22 2025-10-31 昆山龙腾光电股份有限公司 薄膜晶体管阵列基板及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103003743A (zh) * 2010-07-21 2013-03-27 夏普株式会社 有源矩阵基板及其制造方法和液晶显示面板
CN103413898A (zh) * 2013-08-29 2013-11-27 深圳市华星光电技术有限公司 有机发光二极管阳极连接结构及其制作方法
CN103531593A (zh) * 2013-10-29 2014-01-22 京东方科技集团股份有限公司 像素结构、阵列基板、显示装置及像素结构的制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831623B2 (en) * 1996-10-22 2004-12-14 Seiko Epson Corporation Liquid crystal panel substrate, liquid crystal panel, and electronic equipment and projection type display device both using the same
KR101423970B1 (ko) * 2008-04-15 2014-08-01 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101921164B1 (ko) * 2011-07-27 2018-11-23 엘지디스플레이 주식회사 횡전계방식 액정표시장치용 어레이기판의 제조방법
KR102104356B1 (ko) * 2012-12-24 2020-04-24 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및 이의 제조 방법
JP6347937B2 (ja) * 2013-10-31 2018-06-27 株式会社ジャパンディスプレイ 液晶表示装置
CN105093747B (zh) * 2015-08-11 2018-06-01 武汉华星光电技术有限公司 低温多晶硅阵列基板的修补方法
CN105097675B (zh) * 2015-09-22 2018-01-30 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN105336745B (zh) * 2015-09-30 2019-01-22 深圳市华星光电技术有限公司 低温多晶硅tft基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103003743A (zh) * 2010-07-21 2013-03-27 夏普株式会社 有源矩阵基板及其制造方法和液晶显示面板
CN103413898A (zh) * 2013-08-29 2013-11-27 深圳市华星光电技术有限公司 有机发光二极管阳极连接结构及其制作方法
CN103531593A (zh) * 2013-10-29 2014-01-22 京东方科技集团股份有限公司 像素结构、阵列基板、显示装置及像素结构的制造方法

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