WO2017147968A1 - 互补型薄膜晶体管及其制造方法 - Google Patents

互补型薄膜晶体管及其制造方法 Download PDF

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Publication number
WO2017147968A1
WO2017147968A1 PCT/CN2016/078749 CN2016078749W WO2017147968A1 WO 2017147968 A1 WO2017147968 A1 WO 2017147968A1 CN 2016078749 W CN2016078749 W CN 2016078749W WO 2017147968 A1 WO2017147968 A1 WO 2017147968A1
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layer
type
thin film
transistor region
semiconductor layer
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French (fr)
Inventor
曾勉
萧祥志
张盛东
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
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    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body

Definitions

  • the present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to a complementary thin film transistor and a method of fabricating the same.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • NMOS N-type MOSFETs
  • PMOS P-channel MOS semiconductors
  • CMOS complementary metal oxide semiconductor image sensing devices and other digital logic circuits in a typical process. That is, CMOS consists of a P-channel metal oxide semiconductor and N Type channel metal oxide semiconductors are formed together, and CMOS circuits are used as basic circuit structures in integrated circuits.
  • FIG. 1 is a complementary thin film transistor (Continuous Time Fourier). Transform, a CTFT) circuit diagram of the inverter, the complementary thin film transistor is electrically connected to a power supply voltage VDD and a common voltage VSS, and the complementary thin film transistor has a P-type thin film transistor 11 and an N-type thin film transistor 12, The N-type thin film transistor 12 is an active component and is formed on the substrate (not shown) and has an input terminal Vin and an output terminal Vout.
  • PEN plastic substrates
  • the traditional LCD Liquid Crystal Display
  • the driver chip (IC) and glass substrate do not have an integrated separate design, low temperature polysilicon (LTPS, Low Temperature In the technique of Poly-silicon, a semiconductor layer of a region of the P-type thin film transistor 11 and a region of the N-type thin film transistor 12 in a CTFT circuit is separately prepared by using different types of doping, and the CTFT circuit is prepared.
  • the process includes complex processes such as laser annealing and ion implantation, and the manufacturing cost is high.
  • an object of the present invention is to provide a complementary thin film transistor which can be formed into a double gate by forming an N-type thin film crystal in the N-type transistor region and forming a P-type thin film crystal in the P-type transistor region. Structure, used to improve device characteristics.
  • Another object of the present invention is to provide a method of fabricating a complementary thin film transistor in which an N-type thin film crystal is formed in an N-type transistor region by an N-type semiconductor layer forming step, and a P-type semiconductor layer forming step is formed in a P-type transistor region. Thin film crystals reduce process preparation and reduce manufacturing costs.
  • an embodiment of the present invention provides a complementary thin film transistor including a substrate, an N-type semiconductor layer, and a P-type semiconductor layer; An N-type transistor region and a P-type transistor region; the N-type semiconductor layer is disposed above the substrate and located in the N-type transistor region, wherein the N-type semiconductor layer comprises a metal oxide material; The P-type semiconductor layer is disposed over the substrate and in the P-type transistor region, wherein the P-type semiconductor layer comprises an organic semiconductor material.
  • the complementary thin film transistor further includes a first gate layer and an insulating layer, wherein the first gate layer is formed on the substrate and located in the N-type transistor region And the P-type transistor region, the insulating layer is formed on the first gate layer and the substrate, wherein the N-type semiconductor layer and the P-type semiconductor layer are formed on the insulating layer They are separated from each other.
  • the complementary thin film transistor further includes an etch stop layer formed on the N-type semiconductor layer and the insulating layer and located in the N-type transistor region.
  • the complementary thin film transistor further includes an electrode metal layer formed on the insulating layer and located in the N-type transistor region and the P-type transistor region, wherein the electrode A metal layer is formed on the N-type semiconductor layer, and the P-type semiconductor layer is formed on the electrode metal layer.
  • the complementary thin film transistor further includes: a passivation layer formed on the electrode metal layer and the insulating layer and located in the N-type transistor region and the P-type transistor And a second gate layer formed on the passivation layer and located in the N-type transistor region and the P-type transistor region.
  • the metal oxide material of the N-type semiconductor layer is selected from the group consisting of indium gallium zinc oxide, indium zinc oxide, or zinc tin oxide.
  • the organic semiconductor material of the P-type semiconductor layer is selected from the group consisting of pentacene, triphenylamine, fullerene, phthalocyanine, Anthraquinone derivatives or cyanines.
  • an embodiment of the present invention provides a method of fabricating a complementary thin film transistor, the manufacturing method including a first gate layer forming step, an insulating layer forming step, and an N-type semiconductor layer forming a step of forming an electrode metal layer, a step of forming a P-type semiconductor layer;
  • the step of forming the first gate layer is to define an adjacent N-type transistor region and a P-type transistor region on a substrate, and a first gate layer is formed on the substrate and located in the N-type transistor region and the P-type transistor region;
  • the insulating layer forming step is to form an insulating layer on the first gate layer and On the substrate;
  • the N-type semiconductor layer forming step is to form an N-type semiconductor layer on the insulating layer and located in the N-type transistor region, wherein the N-type semiconductor layer comprises a metal oxide material;
  • the electrode metal layer forming step is to form an electrode metal layer on the N-type semiconductor layer and the insulating layer and in the
  • the manufacturing method further includes an etch barrier layer forming step after the N-type semiconductor layer forming step, forming an etch barrier layer on the N-type semiconductor layer and the insulating layer On the layer and in the N-type transistor region.
  • the manufacturing method further includes a second gate layer forming step after the P-type semiconductor layer forming step, forming a passivation layer on the electrode metal layer and the An insulating layer is disposed in the N-type transistor region and the P-type transistor region, and then a second gate layer is formed on the passivation layer and located in the N-type transistor region and the P-type transistor In the district.
  • the complementary thin film transistor of the present invention utilizes an N-type thin film crystal in the N-type transistor region to form a P-type thin film crystal in the P-type transistor region, and adopts a simple process preparation process at a low cost while utilizing
  • the P-type thin film crystal and the N-type thin film crystal structure are prepared into a double gate structure, which can reduce the process preparation process and be used to improve device characteristics.
  • FIG. 1 is a circuit diagram of a conventional complementary thin film transistor inverter.
  • FIG. 2 is a cross-sectional view of a complementary thin film transistor in accordance with a first preferred embodiment of the present invention.
  • Figure 3 is a cross-sectional view of a complementary thin film transistor in accordance with a second preferred embodiment of the present invention.
  • FIG. 4 is a flow chart showing a method of fabricating a complementary thin film transistor according to a first preferred embodiment of the present invention.
  • Figure 5 is a flow chart showing a method of fabricating a complementary thin film transistor according to a second preferred embodiment of the present invention.
  • a complementary thin film transistor 100 according to a first preferred embodiment of the present invention, wherein the complementary thin film transistor 100 comprises a substrate 2, an N-type semiconductor layer 31, and a P-type semiconductor layer 32. a first gate layer 41, an insulating layer 5, an electrode metal layer 6, a passivation layer 7, and a second gate layer 42.
  • the substrate 2 defines an adjacent N-type transistor region 101 and a P-type transistor region 102.
  • the substrate 2 is a glass substrate, but in other embodiments, it may be a plastic substrate (PEN).
  • the N-type semiconductor layer 31 is disposed above the substrate 2 and located in the N-type transistor region 101, wherein the N-type semiconductor layer 31 comprises a metal oxide material.
  • the metal oxide material of the N-type semiconductor layer 31 is selected from the group consisting of indium gallium zinc oxide, indium zinc oxide, or zinc tin oxide.
  • the P-type semiconductor layer 32 is disposed above the substrate 2 and located in the P-type transistor region 102, wherein the P-type semiconductor layer 32 comprises an organic semiconductor material.
  • the organic semiconductor material of the P-type semiconductor layer 32 is selected from the group consisting of pentacene, triphenylamine, fullerene, and phthalocyanine. Anthraquinone derivatives or cyanines.
  • the first gate layer 41 is formed on the substrate 2, and the first gate layer 41 is respectively formed with two portions in the N-type transistor region 101 and the P-type. In the transistor region 102.
  • the first gate layer 41 is a metal material such as aluminum, manganese, copper or titanium and alloys thereof.
  • the insulating layer 5 is formed on the first gate layer 41 and the substrate 2, wherein the N-type semiconductor layer 31 and the P-type semiconductor layer 32 are formed in the The insulating layer 5 is spaced apart from each other. In the embodiment, the insulating layer 5 is used to insulate the first gate layer 41.
  • the electrode metal layer 6 is formed on the insulating layer 5 and located in the N-type transistor region 101 and the P-type transistor region 102, wherein the electrode metal layer 6 is formed in the On the N-type semiconductor layer 31, the P-type semiconductor layer 32 is formed on the electrode metal layer 6.
  • the electrode metal layer 6 is a metal material such as aluminum, manganese, copper or titanium and an alloy thereof. Further, the N-type semiconductor layer 31 is exposed, developed, etched, and stripped.
  • Organic organic thin film transistor
  • Oxide metal oxide thin film transistor
  • the passivation layer 7 is formed on the electrode metal layer 6 and the insulating layer 5 and is located in the N-type transistor region 101 and the P-type transistor region 102.
  • the second gate layer 42 is formed on the passivation layer 7, and the second gate layer 42 is respectively formed with two portions in the N-type transistor region 101 and the In the P-type transistor region 102.
  • the N-type semiconductor layer 31 and the P-type semiconductor layer 32 are disposed over the substrate 2, so that the complementary thin film transistor 100 forms an N-type film in the N-type transistor region 101, respectively.
  • Organic organic thin film transistor
  • Oxide oxide thin film transistor
  • a dual gate structure is prepared by using a P-type thin film transistor and the N-type thin film transistor structure, which can reduce the process preparation process and improve device characteristics, such as increasing the on-state current (Ion) and reducing the off-state current (Ioff). ) and improve Vth offset, etc., without adding extra cost.
  • the complementary thin film transistor 100 of the present invention forms an N-type thin film transistor in the N-type transistor region 101, and a P-type thin film transistor in the P-type transistor region 102, which adopts a simple process preparation process and is low.
  • the cost while using a P-type thin film transistor and the N-type thin film transistor structure to form a dual gate structure, can reduce the process preparation process and improve device characteristics, such as increasing the on-state current (Ion) and reducing the off-state current. (Ioff) and improve Vth offset.
  • a complementary thin film transistor 100' is similar to the first embodiment of the present invention and substantially uses the same component name and figure number, wherein the complementary thin film transistor 100' includes a substrate 2, an N-type semiconductor layer 31, a P-type semiconductor layer 32, a first gate layer 41, an insulating layer 5, an electrode metal layer 6, a passivation layer 7, and a second gate. Polar layer 42.
  • the second embodiment of the present invention is characterized in that the complementary thin film transistor 100 ′ further includes an etch stop layer 8 , wherein the etch stop layer 8 is formed on the N-type semiconductor layer 31 and the insulating layer.
  • the etch stop layer 8 is located in the N-type transistor region 101 to protect the N-type semiconductor layer 31 as an N-type channel. Further, the etch stop layer 8 is formed in the On the insulating layer 5 of the N-type semiconductor layer 31 and the edge of the N-type semiconductor layer 31, the etch stop layer 8 on the portion of the N-type semiconductor layer 31 forms a vacant groove for forming the electrode metal layer. 6. A portion of the N-type semiconductor layer 31 can be electrically connected to the electrode metal layer 6.
  • the complementary thin film transistor 100' of the present invention forms an N-type thin film transistor (Ntype) in the N-type transistor region 101, respectively.
  • TFT TFT
  • Ptype P-type thin film transistor
  • the etching stopper layer 8 is provided on the N-type semiconductor layer 31, and the N-type semiconductor layer 31 which is an N-type channel can be protected.
  • FIG. 4 and FIG. 2 it is a flowchart of a method for fabricating a complementary thin film transistor according to a first preferred embodiment of the present invention, wherein the method for fabricating the complementary thin film transistor includes a first gate
  • the first gate layer forming step S201 defines an adjacent N-type transistor region 101 and a P-type transistor region 102 on a substrate 2, and a first A gate layer 41 is formed on the substrate 2 and is located in the N-type transistor region 101 and the P-type transistor region 102.
  • the insulating layer forming step S202 is performed by forming an insulating layer 5 on the first gate layer 41 and the substrate 2.
  • the N-type semiconductor layer forming step S203 is formed by forming an N-type semiconductor layer 31 on the insulating layer 5 and located in the N-type transistor region 101, wherein the N-type The semiconductor layer 31 comprises a metal oxide material.
  • the electrode metal layer forming step S204 is to form an electrode metal layer 6 on the N-type semiconductor layer 31 and the insulating layer 5, and is located in the N-type transistor.
  • the region 101 and the P-type transistor region 102 are included.
  • the P-type semiconductor layer forming step S205 is to form a P-type semiconductor layer 32 on the insulating layer 5 and the electrode metal layer 6, and is located in the P-type.
  • the P-type semiconductor layer 32 comprises an organic semiconductor material
  • the N-type semiconductor layer 31 and the P-type semiconductor layer 32 are spaced apart from each other.
  • the second gate layer forming step S206 is to form a passivation layer 7 on the electrode metal layer 6 and the insulating layer 5, and is located in the N-type.
  • a second gate layer 42 is then formed on the passivation layer 7 and in the N-type transistor region 101 and the P-type transistor region 102.
  • an N-type thin film transistor is formed in the N-type transistor region 101, and a P-type thin film transistor is formed in the P-type transistor region 102, which adopts a simple process preparation process and is low in cost, and utilizes a P-type film.
  • the transistor and the N-type thin film transistor structure are fabricated into a double gate structure, which can reduce the process preparation process and improve device characteristics, such as increasing on-state current (Ion), reducing off-state current (Ioff), and improving Vth bias. shift.
  • the semiconductor characteristics of the N-type thin film transistor can be ensured to be unaffected by the process. .
  • FIG. 5 and FIG. 3 it is a flowchart of a method for fabricating a complementary thin film transistor according to a second preferred embodiment of the present invention, wherein the method for fabricating the complementary thin film transistor includes a first gate a layer forming step S201, an insulating layer forming step S202, an N-type semiconductor layer forming step S203, an etch stop layer forming step S207, an electrode metal layer forming step S204, a P-type semiconductor layer forming step S205, and a second gate.
  • the pole layer formation step S206 The pole layer formation step S206.
  • the first gate layer forming step S201 defines an adjacent N-type transistor region 101 and a P-type transistor region 102 on a substrate 2, and a first A gate layer 41 is formed on the substrate 2 and is located in the N-type transistor region 101 and the P-type transistor region 102.
  • the insulating layer forming step S202 is performed by forming an insulating layer 5 on the first gate layer 41 and the substrate 2.
  • the N-type semiconductor layer forming step S203 is formed by forming an N-type semiconductor layer 31 on the insulating layer 5 and located in the N-type transistor region 101, wherein the N-type The semiconductor layer 31 comprises a metal oxide material.
  • the etch barrier layer forming step S207 is to form an etch stop layer 8 on the N-type semiconductor layer 31 and the insulating layer 5 and located in the N-type transistor. In area 101.
  • the electrode metal layer forming step S204 is to form an electrode metal layer 6 on the N-type semiconductor layer 31 and the insulating layer 5, and is located in the N-type transistor.
  • the region 101 and the P-type transistor region 102 are included.
  • the P-type semiconductor layer forming step S205 is formed by forming a P-type semiconductor layer 32 on the insulating layer 5 and the electrode metal layer 6, and is located in the P-type.
  • the P-type semiconductor layer 32 comprises an organic semiconductor material
  • the N-type semiconductor layer 31 and the P-type semiconductor layer 32 are spaced apart from each other.
  • the second gate layer forming step S206 is to form a passivation layer 7 on the electrode metal layer 6 and the insulating layer 5, and is located in the N-type.
  • a second gate layer 42 is then formed on the passivation layer 7 and in the N-type transistor region 101 and the P-type transistor region 102.
  • an N-type thin film transistor is formed in the N-type transistor region 101, and a P-type thin film transistor is formed in the P-type transistor region 102, which adopts a simple process preparation process and is low in cost, and utilizes a P-type film.
  • the transistor and the N-type thin film transistor structure are fabricated in a dual gate structure, which reduces the process preparation process and is used to improve device characteristics.
  • the etching stopper layer 8 is provided on the N-type semiconductor layer 31, and the N-type semiconductor layer 31 which is an N-type channel can be protected.

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种互补型薄膜晶体管及其制造方法，该互补型薄膜晶体管（100）包含一基板（2）、一N型半导体层（31）及一P型半导体层（32）；该基板定义有相邻的一N型晶体管区（101）及一P型晶体管区（102），该N型半导体层设置在该基板上方且位于该N型晶体管区中，且该N型半导体层包含一金属氧化物材料，该P型半导体层设置在该基板上方且位于该P型晶体管区中，且该P型半导体层包含一有机半导体材料。

Description

互补型薄膜晶体管及其制造方法 技术领域
本发明是有关于一种薄膜晶体管及其制造方法，特别是有关于一种互补型薄膜晶体管及其制造方法。
 背景技术
互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor, CMOS)是一种集成电路的设计制程，可以在硅质晶圆模板上制出N 型沟道金属氧化物半导体(n-type MOSFET, NMOS)和P型沟道金属氧化物半导体 (p-type MOSFET, PMOS)的基本组件，由于NMOS与PMOS在物理特性上为互补性，因此被称为CMOS。CMOS在一般的制程上，可用来制作静态随机存储器、微控制器、微处理器、以及互补式金属氧化物半导体图像传感装置与其他数位逻辑电路系统。也就是说，CMOS由P型沟道金属氧化物半导体和N 型沟道金属氧化物半导体共同构成，而CMOS电路是作为集成电路中的基本电路结构。
目前显示面板中的基板大部分为玻璃基板或塑料基板(PEN)等，如图1所示，为一种互补型薄膜晶体管(Continuous Time Fourier Transform, CTFT)反相器的电路图，所述互补型薄膜晶体管电性连接一电源电压VDD及一公共电压VSS，且所述互补型薄膜晶体管具有一P型薄膜晶体管11，及一N型薄膜晶体管12，其中所述N型薄膜晶体管12为主动组件且形成在所述基板(未绘示)上，并具有一输入端Vin及一输出端Vout。
然而，传统的LCD(Liquid Crystal Display)显示器的驱动芯片(IC)与玻璃基板为不具有集成的分离式设计，在低温多晶硅(LTPS, Low Temperature Poly-silicon)的技术中，通过采用不同类型的掺杂来分别制备CTFT电路中所述P型薄膜晶体管11的区域及所述N型薄膜晶体管12的区域的半导体层，所述CTFT电路的制备工艺包括激光退火、离子注入等复杂工艺，制造成本较高。
 技术问题
有鉴于此，本发明的目的在于提供一种互补型薄膜晶体管，利用在所述N型晶体管区形成N型薄膜晶体，在所述P型晶体管区形成P型薄膜晶体，可制备成双栅极结构，用以来改善器件特性。
本发明的另一目的在于提供一种互补型薄膜晶体管的制造方法，利用N型半导体层形成步骤在N型晶体管区形成N型薄膜晶体，及P型半导体层形成步骤在P型晶体管区形成P型薄膜晶体，可减少工艺制备流程并降低制造成本。
 技术解决方案
为达成本发明的前述目的，本发明一实施例提供一种互补型薄膜晶体管，所述互补型薄膜晶体管包含一基板、一N型半导体层及一P型半导体层；所述基板定义有相邻的一N型晶体管区及一P型晶体管区；所述N型半导体层设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；所述P型半导体层设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区及所述P型晶体管区中，所述绝缘层形成在所述第一栅极层及所述基板上，其中所述N型半导体层及所述P型半导体层形成在所述绝缘层上且彼此相间隔。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一刻蚀阻挡层，形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区中。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一电极金属层，形成在所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
在本发明的一实施例中，所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
在本发明的一实施例中，所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
在本发明的一实施例中，所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、 茈衍生物或花菁。
为达成本发明的前述目的，本发明一实施例提供一种互补型薄膜晶体管的制造方法，所述制造方法包含一第一栅极层形成步骤、一绝缘层形成步骤、一N型半导体层形成步骤、一电极金属层形成步骤、一P型半导体层形成步骤；所述第一栅极层形成步骤是在一基板上定义相邻的一N型晶体管区及一P型晶体管区，并将一第一栅极层形成在所述基板上并位于所述N型晶体管区及所述P型晶体管区中；所述绝缘层形成步骤是将一绝缘层形成在所述第一栅极层及所述基板上；所述N型半导体层形成步骤是将一N型半导体层形成在绝缘层上且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；所述电极金属层形成步骤是将一电极金属层形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；所述P型半导体层形成步骤是将一P型半导体层形成在所述绝缘层及所述电极金属层上且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料，且所述N型半导体层及所述P型半导体层彼此相间隔。
在本发明的一实施例中，所述制造方法还包含在所述N型半导体层形成步骤之后的一刻蚀阻挡层形成步骤，将一刻蚀阻挡层形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区中。
在本发明的一实施例中，所述制造方法还包含在所述P型半导体层形成步骤之后的一第二栅极层形成步骤，将一钝化层形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，接着将一第二栅极层形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
 有益效果
如上所述，本发明互补型薄膜晶体管利用在所述N型晶体管区形成N型薄膜晶体，在所述P型晶体管区形成P型薄膜晶体，所采用简单工艺制备流程且较低成本，同时利用P型薄膜晶体和所述N型薄膜晶体结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性。
附图说明
图1是一现有的互补型薄膜晶体管反相器的电路图。
图2是根据本发明一第一优选实施例的互补型薄膜晶体管的一剖视图。
图3是根据本发明一第二优选实施例的互补型薄膜晶体管的一剖视图。
图4是本发明所述第一优选实施例的互补型薄膜晶体管的制造方法的一流程图。
图5是本发明所述第二优选实施例的互补型薄膜晶体管的制造方法的一流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图2所示，是根据本发明一第一优选实施例的互补型薄膜晶体管100，其中所述互补型薄膜晶体管100包含一基板2、一N型半导体层31、一P型半导体层32、一第一栅极层41、一绝缘层5、一电极金属层6、一钝化层7及一第二栅极层42。本发明将于下文详细说明各实施例上述各组件的细部构造、组装关系及其运作原理。
续参照图2所示，所述基板2定义有相邻的一N型晶体管区101及一P型晶体管区102。在本实施例中，所述基板2为玻璃基板，但在其他实施例中，也可为塑料基板(PEN)。
续参照图2所示，所述N型半导体层31设置在所述基板2上方且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。在本实施例中，所述N型半导体层31的金属氧化物材料是选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
续参照图2所示，所述P型半导体层32设置在所述基板2上方且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料。在本实施例中，所述P型半导体层32的有机半导体材料是选自于并五苯、三苯基胺、富勒烯、酞菁、 茈衍生物或花菁。
续参照图2所示，所述第一栅极层41形成在所述基板2上，且所述第一栅极层41分别形成两个部分位于所述N型晶体管区101及所述P型晶体管区102中。在本实施例中，所述第一栅极层41为金属材料，例如铝、锰、铜或钛以及其合金。
续参照图2所示，所述绝缘层5形成在所述第一栅极层41及所述基板2上，其中所述N型半导体层31及所述P型半导体层32是形成在所述绝缘层5上，且彼此相间隔。在本实施例中，所述绝缘层5用以绝缘所述第一栅极层41。
续参照图2所示，所述电极金属层6形成在所述绝缘层5上且位于所述N型晶体管区101及所述P型晶体管区102中，其中所述电极金属层6形成在所述N型半导体层31上，所述P型半导体层32形成在所述电极金属层6上。在本实施例中，所述电极金属层6为金属材料，例如铝、锰、铜或钛以及其合金；进一步说明的是，所述N型半导体层31是通过曝光、显影、刻蚀、剥离等工序而形成在所述绝缘层5上，并在所述N型半导体层31上溅射一层所述电极金属层6，接着再涂布一层所述P型半导体层32(有机半导体层)，通过所述N型半导体层31及P型半导体层32设置在不同层，使有机薄膜晶体管(Organic TFT)作为P型薄膜晶体管的区域结构，以金属氧化物薄膜晶体管(Oxide TFT)作为N型薄膜晶体管的区域结构，进而能够制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性。
续参照图2所示，所述钝化层7形成在所述电极金属层6及所述绝缘层5上且位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图2所示，所述第二栅极层42形成在所述钝化层7上，且所述第二栅极层42分别形成两个部分位于所述N型晶体管区101及所述P型晶体管区102中。
依据上述的结构，通过在所述基板2上方设置所述N型半导体层31及所述P型半导体层32，使所述互补型薄膜晶体管100分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，进而能够以有机薄膜晶体管(Organic TFT)作为P型薄膜晶体管的区域结构，也就是使用P型有机半导体材料制备所述P型半导体层32，又以金属氧化物薄膜晶体管(Oxide TFT)作为N型薄膜晶体管的区域结构，也就是使用氧化物材料制备所述N型半导体层31。同时利用P型薄膜晶体管和所述N型薄膜晶体管结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性，例如增大开态电流(Ion)，减小关态电流(Ioff)及改善Vth偏移等，而不用增加额外的成本。
利用上述的设计，本发明互补型薄膜晶体管100分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，所采用简单工艺制备流程且较低成本，同时利用P型薄膜晶体管和所述N型薄膜晶体管结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性，例如增大开态电流(Ion)，减小关态电流(Ioff)及改善Vth偏移。
请参照图3所示，是根据本发明一第二优选实施例的互补型薄膜晶体管100’，相似于本发明第一实施例并大致沿用相同组件名称及图号，其中所述互补型薄膜晶体管100’包含一基板2、一N型半导体层31、一P型半导体层32、一第一栅极层41、一绝缘层5、一电极金属层6、一钝化层7、一第二栅极层42。但本发明第二实施例的差异特征在于：所述互补型薄膜晶体管100’还包含一刻蚀阻挡层8，其中所述刻蚀阻挡层8形成在所述N型半导体层31及所述绝缘层5上，且所述刻蚀阻挡层8位于所述N型晶体管区101中，以保护作为N型沟道的N型半导体层31，进一步说明的是，所述刻蚀阻挡层8形成在所述N型半导体层31及靠近所述N型半导体层31的边缘的绝缘层5上，同时部分的N型半导体层31上的刻蚀阻挡层8形成缺槽，用以形成所述电极金属层6，使部分的N型半导体层31能够与所述电极金属层6电性连接。
利用上述的设计，本发明互补型薄膜晶体管100’分别在所述N型晶体管区101形成N型薄膜晶体管(Ntype TFT)，在所述P型晶体管区102形成P型薄膜晶体管(Ptype TFT)，所采用简单工艺制备流程且较低成本，同时利用P型薄膜晶体管和所述N型薄膜晶体管结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性。另外，将所述刻蚀阻挡层8设置在所述N型半导体层31上，能够保护作为N型沟道的N型半导体层31。
请参照图4并配合图2所示，是依照本发明所述第一优选实施例的互补型薄膜晶体管的制造方法的流程图，其中所述互补型薄膜晶体管的制造方法包含一第一栅极层形成步骤S201、一绝缘层形成步骤S202、一N型半导体层形成步骤S203、一电极金属层形成步骤S204、一P型半导体层形成步骤S205及一第二栅极层形成步骤S206。
续参照图4并配合图2所示，所述第一栅极层形成步骤S201是在一基板2上定义相邻的一N型晶体管区101及一P型晶体管区102，并将一第一栅极层41形成在所述基板2上，并位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图4并配合图2所示，所述绝缘层形成步骤S202是将一绝缘层5形成在所述第一栅极层41及所述基板2上。
续参照图4并配合图2所示，所述N型半导体层形成步骤S203是将一N型半导体层31形成在绝缘层5上且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。
续参照图4并配合图2所示，所述电极金属层形成步骤S204是将一电极金属层6形成在所述N型半导体层31及所述绝缘层5上，且位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图4并配合图2所示，所述P型半导体层形成步骤S205是将一P型半导体层32形成在所述绝缘层5及所述电极金属层6上，且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料，且所述N型半导体层31及所述P型半导体层32彼此相间隔。
续参照图4并配合图2所示，所述第二栅极层形成步骤S206是将一钝化层7形成在所述电极金属层6及所述绝缘层5上，且位于所述N型晶体管区101及所述P型晶体管区102中，接着将一第二栅极层42形成在所述钝化层7上且位于所述N型晶体管区101及所述P型晶体管区102中。
利用上述的设计，分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，所采用简单工艺制备流程且较低成本，同时利用P型薄膜晶体管和所述N型薄膜晶体管结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性，例如增大开态电流(Ion)，减小关态电流(Ioff)及改善Vth偏移。利用将P型薄膜晶体管制程的所述P型半导体层形成步骤S205实施于N型薄膜晶体管制程的所述N型半导体层形成步骤S203之后，可确保N型薄膜晶体管的半导体特性不受制程的影响。
请参照图5并配合图3所示，是依照本发明所述第二优选实施例的互补型薄膜晶体管的制造方法的流程图，其中所述互补型薄膜晶体管的制造方法包含一第一栅极层形成步骤S201、一绝缘层形成步骤S202、一N型半导体层形成步骤S203、一刻蚀阻挡层形成步骤S207、一电极金属层形成步骤S204、一P型半导体层形成步骤S205及一第二栅极层形成步骤S206。
续参照图5并配合图3所示，所述第一栅极层形成步骤S201是在一基板2上定义相邻的一N型晶体管区101及一P型晶体管区102，并将一第一栅极层41形成在所述基板2上，并位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图5并配合图3所示，所述绝缘层形成步骤S202是将一绝缘层5形成在所述第一栅极层41及所述基板2上。
续参照图5并配合图3所示，所述N型半导体层形成步骤S203是将一N型半导体层31形成在绝缘层5上且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。
续参照图5并配合图3所示，所述刻蚀阻挡层形成步骤S207是将一刻蚀阻挡层8形成在所述N型半导体层31及所述绝缘层5上且位于所述N型晶体管区101中。
续参照图5并配合图3所示，所述电极金属层形成步骤S204是将一电极金属层6形成在所述N型半导体层31及所述绝缘层5上，且位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图5并配合图3所示，所述P型半导体层形成步骤S205是将一P型半导体层32形成在所述绝缘层5及所述电极金属层6上，且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料，且所述N型半导体层31及所述P型半导体层32彼此相间隔。
续参照图5并配合图3所示，所述第二栅极层形成步骤S206是将一钝化层7形成在所述电极金属层6及所述绝缘层5上，且位于所述N型晶体管区101及所述P型晶体管区102中，接着将一第二栅极层42形成在所述钝化层7上且位于所述N型晶体管区101及所述P型晶体管区102中。
利用上述的设计，分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，所采用简单工艺制备流程且较低成本，同时利用P型薄膜晶体管和所述N型薄膜晶体管结构制备成双栅极结构，可减少工艺制备流程，并用来改善器件特性。另外，将所述刻蚀阻挡层8设置在所述N型半导体层31上，能够保护作为N型沟道的N型半导体层31。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (19)

  1. 一种互补型薄膜晶体管，其中：所述互补型薄膜晶体管包含：
    一基板，定义有相邻的一N型晶体管区及一P型晶体管区；
    一N型半导体层，设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料，且所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物；及
    一P型半导体层，设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料，且所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
  2. 如权利要求1所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区及所述P型晶体管区中，所述绝缘层形成在所述第一栅极层及所述基板上，其中所述N型半导体层及所述P型半导体层形成在所述绝缘层上且彼此相间隔。
  3. 如权利要求2所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  4. 如权利要求2所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
  5. 如权利要求2所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一刻蚀阻挡层，形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区中。
  6. 如权利要求5所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  7. 如权利要求5所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
  8. 一种互补型薄膜晶体管，其中：所述互补型薄膜晶体管包含：
    一基板，定义有相邻的一N型晶体管区及一P型晶体管区；
    一N型半导体层，设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；及
    一P型半导体层，设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料。
  9. 如权利要求8所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区及所述P型晶体管区中，所述绝缘层形成在所述第一栅极层及所述基板上，其中所述N型半导体层及所述P型半导体层形成在所述绝缘层上且彼此相间隔。
  10. 如权利要求9所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  11. 如权利要求9所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
  12. 如权利要求9所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一刻蚀阻挡层，形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区中。
  13. 如权利要求12所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  14. 如权利要求12所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
  15. 如权利要求8所述的互补型薄膜晶体管，其中：所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
  16. 如权利要求8所述的互补型薄膜晶体管，其中：所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
  17. 一种互补型薄膜晶体管的制造方法，其中：所述制造方法包含步骤：
    一第一栅极层形成步骤，在一基板上定义相邻的一N型晶体管区及一P型晶体管区，并将一第一栅极层形成在所述基板上并位于所述N型晶体管区及所述P型晶体管区中；
    一绝缘层形成步骤，将一绝缘层形成在所述第一栅极层及所述基板上；
    一N型半导体层形成步骤，将一N型半导体层形成在绝缘层上且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；
    一电极金属层形成步骤，将一电极金属层形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中；及
    一P型半导体层形成步骤，将一P型半导体层形成在所述绝缘层及所述电极金属层上且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料，且所述N型半导体层及所述P型半导体层彼此相间隔。
  18. 如权利要求17所述的制造方法，其中：所述制造方法还包含在所述N型半导体层形成步骤之后的一刻蚀阻挡层形成步骤，将一刻蚀阻挡层形成在所述N型半导体层及所述绝缘层上且位于所述N型晶体管区中。
  19. 如权利要求17所述的制造方法，其中：所述制造方法还包含在所述P型半导体层形成步骤之后的一第二栅极层形成步骤，将一钝化层形成在所述电极金属层及所述绝缘层上且位于所述N型晶体管区及所述P型晶体管区中，接着将一第二栅极层形成在所述钝化层上且位于所述N型晶体管区及所述P型晶体管区中。
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