WO2017128772A1 - 移位寄存单元及驱动方法、移位寄存器、栅极驱动电路和显示装置 - Google Patents

移位寄存单元及驱动方法、移位寄存器、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017128772A1
WO2017128772A1 PCT/CN2016/102130 CN2016102130W WO2017128772A1 WO 2017128772 A1 WO2017128772 A1 WO 2017128772A1 CN 2016102130 W CN2016102130 W CN 2016102130W WO 2017128772 A1 WO2017128772 A1 WO 2017128772A1
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WIPO (PCT)
Prior art keywords
module
pull
voltage signal
transistor
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/102130
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English (en)
French (fr)
Inventor
封宾
王俊伟
田明
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/512,639 priority Critical patent/US10262749B2/en
Publication of WO2017128772A1 publication Critical patent/WO2017128772A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display devices, and in particular to a shift register unit, a method of driving the shift register unit, a shift register including the shift register unit, and a gate including the shift register A driving circuit and a display device including the gate driving circuit.
  • the shift register unit includes a pull-up transistor T1, a storage capacitor C, a clock signal input terminal CLK, and a signal output terminal OUT.
  • the pull-up transistor T1 is turned on, thereby outputting the valid signal input through the clock signal input terminal CLK to the signal output terminal OUT.
  • the shift register unit duty cycle for example, the reset phase of the shift register unit
  • the gate-to-source voltage difference is zero.
  • An object of the present disclosure is to provide a shift register unit, a drive method of the shift register unit, a shift register including the shift register unit, a gate drive circuit including the shift register, and a A display device including the gate drive circuit, thereby at least alleviating or even eliminating the above-mentioned drawbacks of the prior art.
  • a shift register unit includes a pull-up module, a clock signal input terminal, a memory module, and a signal output terminal. An input end of the pull-up module is electrically connected to the clock signal input end, An output end of the pull-up module is electrically connected to the signal output end, and one end of the storage module is electrically connected to the signal output end.
  • the shift register unit further includes a control voltage signal input terminal and a leakage suppression module.
  • An output end of the leakage suppression module is connected to a control end of the pull-up module, a first input end of the leakage suppression module is connected to the control voltage signal input end, and a second input end of the leakage suppression module Connected to the other end of the storage module.
  • the leakage suppression module is configured to selectively output an output of the leakage suppression module and a first input or a second of the leakage suppression module under control of a voltage signal input from a control terminal of the leakage suppression module
  • the input end is turned on, and when the output end of the leakage suppression module is electrically connected to the first input end of the leakage suppression module, the input end and the output end of the pull-up module are disconnected, when the leakage suppression module
  • the output end is electrically connected to the second input end of the leakage suppression module, the input end and the output end of the pull-up module are turned on.
  • the pull-up module is configured to: when the absolute value of the voltage difference between the voltage received by the control terminal of the pull-up module and the voltage received by the input terminal of the pull-up module is not greater than a preset value, The input end and the output end of the pull-up module are turned on.
  • control end of the leakage suppression module is formed integrally with the second input of the leakage suppression module and is connected to the other end of the storage module.
  • control terminal of the leakage suppression module is formed integrally with the second input terminal of the leakage suppression module
  • the same terminal of the leakage suppression module is multiplexed into the control terminal and the second input
  • the terminal may also mean that the control terminal and the second input terminal of the leakage suppression module input the same signal, and are connected to the same terminal (ie, the other end of the storage module).
  • the leakage suppression module includes a first switching element and a second switching element.
  • a control end of the first switching element is connected to a control end of the leakage suppression module, an input end of the first switching element is connected to a first input end of the leakage suppression module, and the first switching element is The output is connected to the output of the leakage suppression module.
  • the first switching element is configured to turn on an input end and an output end of the first switching element when the control terminal of the leakage suppression module receives an invalid voltage signal.
  • invalid voltage signal refers to a signal that is capable of disconnecting the input and output of the pull-up module.
  • effective voltage signal refers to a signal that enables the input and output of the pull-up module to conduct.
  • An input end of the second switching element is connected to a control end of the leakage suppression module, and an output end of the second switching element is connected to an output end of the leakage suppression module.
  • the second switching element is configured to conduct an input end and an output end of the second switching element when the control terminal of the leakage suppression module receives the effective voltage signal.
  • the first switching element comprises a first transistor.
  • a control electrode of the first transistor serves as a control terminal of the first switching element, a first pole of the first transistor serves as an input of the first switching element, and a second pole of the first transistor acts as An output of the first switching element.
  • the second switching element comprises a second transistor.
  • a control electrode of the second transistor is coupled to the first pole and serves as an input of the second switching element, and a second pole of the second transistor serves as an output of the second switching element.
  • the first transistor is a P-type transistor and the second transistor is an N-type transistor.
  • the first transistor is an N-type transistor and the second transistor is a P-type transistor.
  • the pull up module comprises a pull up transistor.
  • a gate of the pull-up transistor acts as a control terminal of the pull-up module, a first pole of the pull-up transistor acts as an input of the pull-up module, and a second pole of the pull-up transistor acts as The output of the pull-up module.
  • the pull-up transistor is an N-type transistor.
  • the memory module includes a storage capacitor.
  • a shift register including a cascaded multi-stage shift register unit, wherein the shift register unit is any one of the above-described shifts provided by the present disclosure Bit register unit.
  • a gate driving circuit including a shift register, wherein the shift register is the above shift register provided by the present disclosure.
  • a display device including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present disclosure.
  • each duty cycle of the driving method includes:
  • a first voltage signal is provided to the clock signal input, a control voltage signal is provided to the control voltage signal input, and an invalid voltage signal is provided to a control terminal of the leakage suppression module.
  • the polarity of the control voltage signal is the same as the polarity of the first voltage signal, and the absolute value of the control voltage signal is greater than the absolute value of the first voltage signal.
  • the pull-up module when the pull-up module includes the pull-up transistor and the pull-up transistor is an N-type transistor, the first voltage signal is -8V, input through the control voltage signal input terminal The control voltage signal is -12 ⁇ -16V.
  • the control voltage signal input from the control voltage signal input terminal can be provided to the control terminal of the pull-up module through the leakage suppression module, and the control voltage signal input terminal ensures the input.
  • the control voltage signal that is pulled up by the pull-up module ensures that the input of the pull-up module is disconnected from the signal output to prevent leakage current.
  • Figure 1 is a schematic illustration of a portion of a prior art shift register unit
  • FIG. 2 is a schematic diagram of a portion of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a portion of a shift register unit provided by an embodiment of the present disclosure
  • the shift register unit includes a pull-up module 100, a clock signal input terminal CLK, a memory module 200, and a signal output terminal OUT.
  • the input end of the pull-up module 100 is electrically connected to the clock signal input terminal CLK
  • the output end of the pull-up module 100 is electrically connected to the signal output terminal OUT
  • one end of the memory module 100 is electrically connected to the signal output terminal OUT.
  • the shift register unit further includes a control voltage signal input terminal VGL and a leakage suppression module 300.
  • the output end of the leakage suppression module 300 is connected to the control end of the pull-up module 100, the first input end of the leakage suppression module 300 is connected to the control voltage signal input terminal VGL, and the second input end of the leakage suppression module 300 and the storage module 200 The other end is connected.
  • the leakage suppression module 300 is configured to selectively output the output of the leakage suppression module 300 and the first input or the second input of the leakage suppression module 300 under the control of the voltage signal received by the control terminal of the leakage suppression module 300. Turn on.
  • the leakage suppression module 300 is further configured to disconnect the input end and the output end of the pull-up module when the output end of the leakage suppression module is electrically connected to the first input end of the leakage suppression module, when the leakage The input end and the output end of the pull-up module are turned on when the output end of the suppression module is electrically connected to the second input end of the leakage suppression module.
  • the input terminal and the output terminal of the pull-up module 100 Turn on.
  • a control voltage signal is supplied to the control voltage signal input terminal VGL.
  • the other end of the memory module 200 serves as a pull-up node PU of the shift register unit.
  • the control voltage signal input terminal VGL is electrically connected to the control terminal of the pull-up module 100.
  • the invalid voltage signal can be input through the control voltage signal input terminal VGL, so that the input terminal and the output terminal of the pull-up module 100 are disconnected.
  • the pull-up node PU When the second input end of the leakage suppression module 300 is electrically connected to the output end of the leakage suppression module 300, the pull-up node PU is electrically connected to the control end of the pull-up module 100. If the level of the pull-up node PU is sufficiently high, the input and output of the pull-up module 100 can be turned on.
  • the leakage suppression module 300 By controlling the time when the first input end and the output end of the leakage suppression module 300 are turned on, And by designing the size of the control voltage signal input by the control voltage signal input terminal VGL, the voltage received by the control terminal of the pull-up module 100 can be controlled, thereby controlling the on/off of the pull-up module 100.
  • a control voltage signal is input to the control voltage signal input terminal VGL.
  • the polarity of the control voltage signal is the same as the polarity of the invalid clock signal, and the absolute value of the control voltage signal is greater than the absolute value of the invalid clock signal.
  • the shift register unit includes a signal input terminal.
  • the signal timing diagram indicated by IN is the timing of the signal input through the signal input terminal.
  • an invalid clock signal (herein referred to as a first voltage signal) is supplied to the clock signal input terminal CLK.
  • the effective voltage signal is stored in the memory module 200 through the signal input terminal IN such that the potential of the pull-up node PU is equal to the potential of the effective voltage signal.
  • an effective voltage signal can be provided to the control terminal of the leakage suppression module 300, thereby turning on the second input end of the leakage suppression module 300 and the output end of the leakage suppression module 300, that is, pulling up the node PU and pulling up
  • the control terminal of module 100 is turned on. Since the potential of the pull-up node PU at this time is equal to the potential of the effective voltage signal, the input terminal and the output terminal of the pull-up module 100 are turned on, so that the signal output terminal OUT outputs an invalid clock signal.
  • a valid clock signal (herein referred to as a second voltage signal) is input through the clock signal input terminal CLK, and the input terminal of the shift register unit is disconnected from the memory module 200.
  • the voltage at the pull-up node PU is still an effective voltage that enables the input and output terminals of the pull-up module 100 to conduct.
  • an effective signal is provided to the control terminal of the leakage suppression module 300 such that the second input of the leakage suppression module 300 is electrically connected to the output of the leakage suppression module 300. Therefore, the control terminal of the pull-up module 100 is input with an effective voltage signal.
  • the input end of the pull-up module 100 is turned on with the signal output terminal OUT, so that the signal output terminal OUT outputs a valid clock signal.
  • an invalid voltage signal may be provided to the control terminal of the leakage suppression module 300, so that the first signal input end of the leakage suppression module 300 is electrically connected to the output end of the leakage suppression module 300, and thus through the control voltage signal input terminal VGL input control
  • the voltage signal is input to the control terminal of the pull-up module 100, so that the input terminal and the output terminal of the pull-up module 100 can be disconnected, and the leakage current affecting the normal output signal between the input terminal and the output terminal of the pull-up module 100 is prevented. , so that the occurrence of abnormal display can be prevented.
  • the control voltage signal input by the control voltage signal input terminal VGL can be provided to the control end of the pull-up module 100 through the leakage suppression module 300 during the output pull-down phase.
  • the control voltage signal input terminal VGL inputs a control voltage signal that ensures that the pull-up module 100 is turned off, thereby ensuring that the input terminal of the pull-up module 100 is disconnected from the signal output terminal to prevent leakage current from being generated.
  • the leakage suppression module 300 can take any suitable form.
  • the control end of the leakage suppression module 300 is formed integrally with the second input end of the leakage suppression module 300, and is both connected to the other end of the storage module 200 (ie, the pull-up node PU).
  • FIG. 3 illustrates a schematic diagram of a portion of a shift register unit in accordance with an embodiment of the present disclosure.
  • the leakage suppression module 300 includes a first switching element T3 and a second switching element T2.
  • the control end of the first switching element T3 is connected to the control end of the leakage suppression module 300, the input end of the first switching element T3 is connected to the first input end of the leakage suppression module 300, and the output end of the first switching element T3 and the leakage suppression The outputs of module 300 are connected.
  • the first switching element T3 is configured to conduct the input terminal and the output terminal of the first switching element T3 when the control terminal of the leakage suppression module 300 receives the invalid voltage signal.
  • the input end of the second switching element T2 is connected to the control end of the leakage suppression module 300, and the output end of the second switching element T2 is connected to the output end of the leakage suppression module 300.
  • the second switching element T2 is configured to conduct the input terminal and the output terminal of the second switching element T2 when the control terminal of the leakage suppression module 300 receives the effective voltage signal.
  • the first switching element T3 When receiving the effective voltage signal, the first switching element T3 is turned off, and the second switching element T2 is turned on; when the invalid voltage signal is received, the first switching element T3 is turned on, and the second The switching element T2 is turned off.
  • the first switching element T3 includes a first transistor, and a gate electrode of the first transistor serves as a control terminal of the first switching element, and a first pole of the first transistor serves as the first An input terminal of the switching element T3, and the second electrode of the first transistor serves as an output terminal of the first switching element T3.
  • the first transistor may be a P-type transistor.
  • the second switching element T2 can take any suitable form.
  • the second switching element T2 may be a diode.
  • the anode of the second switching element T2 is connected to the pull-up node PU, and the cathode of the second switching element T2 is connected to the control terminal of the pull-up module 100.
  • the second switching element T2 may include a second transistor.
  • the gate of the second transistor is coupled to the first pole and serves as the input of the second switching element T2, and the second pole of the second transistor serves as the output of the second switching element T2.
  • the gate of the second transistor is coupled to the first pole to form a diode connection.
  • the second transistor may be an N-type transistor; when the effective voltage signal is a low level signal, the second transistor may be a P-type transistor.
  • the types of the two are different. If the first transistor is a P-type transistor, the second transistor is an N-type transistor. If the first transistor is an N-type transistor, the second transistor is a P-type transistor.
  • the pull up module 100 can take any suitable form.
  • the pull-up module 100 includes a pull-up transistor T1.
  • the gate of the pull-up transistor T1 acts as the control terminal of the pull-up module 100
  • the first pole of the pull-up transistor T1 acts as the input of the pull-up module 100
  • the second pole of the pull-up transistor T1 acts as the output of the pull-up module 100 end.
  • the control electrode of the pull-up transistor T1 is connected to the output terminal of the leakage suppression module 300, the first electrode of the pull-up transistor T1 is connected to the clock signal input terminal CLK, and the second electrode of the pull-up transistor T1 is The signal output terminal OUT is connected.
  • the pull-up transistor T1 is an N-type transistor
  • the gate-source voltage difference of the pull-up transistor T1 ie, the voltage difference between the gate and the second pole of the pull-up transistor T1
  • the pull-up is Transistor T1 is off.
  • pull-up transistor can be used The control terminal voltage of T1 is set to a lower voltage, so that the gate-source voltage difference of the pull-up transistor T1 can be made smaller than 0, thereby ensuring that the pull-up transistor T1 is turned off and the generation of leakage current is avoided.
  • a voltage of less than -8 V can be supplied to the control voltage signal input terminal VGL.
  • a voltage between -16V and -12V may be supplied to the control voltage signal input terminal VGL to ensure that the pull-up transistor T1 can be turned off.
  • the pull-up transistor T1 is an N-type transistor.
  • the effective voltage signal is a high level signal and the invalid voltage signal is a low level signal.
  • the second transistor can be an N-type transistor and the first transistor can be a P-type transistor.
  • the memory module 200 can take any suitable form as long as it is capable of storing charge during the charging phase and ensuring that the level of the pull-up node PU is at the level of the effective voltage signal during the output phase.
  • the memory module 200 includes a storage capacitor C.
  • One end of the storage capacitor C serves as one end of the memory module 200, and the other end of the storage capacitor C serves as the other end of the memory module 200.
  • a shift register includes a cascaded multi-stage shift register unit, wherein the shift register unit is any one of the above-described shift register units provided by the present disclosure.
  • a gate driving circuit including a shift register, wherein the shift register is the above shift register provided by the present disclosure.
  • a display device including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present invention.
  • An embodiment of the present disclosure further provides a driving method of a shift register unit, wherein the shift register unit is any one of the above-described shift register units provided by the present disclosure.
  • each duty cycle of the driving method includes the following stages.
  • a first voltage signal (ie, an invalid clock signal) is supplied to the clock signal input terminal CLK, a control voltage signal is supplied to the control voltage signal input terminal, and an effective voltage signal is supplied to the control terminal of the leakage suppression module.
  • a second voltage signal (ie, a valid clock signal) is supplied to the clock signal input terminal CLK, and a control voltage signal is supplied to the control voltage signal input terminal, and And providing an effective voltage signal to the control terminal of the leakage suppression module;
  • a first voltage signal is supplied to the clock signal input terminal, a control voltage signal is supplied to the control voltage signal input terminal, and an invalid voltage signal is supplied to the control terminal of the leakage suppression module.
  • the polarity of the control voltage signal is the same as the polarity of the first voltage signal, and the absolute value of the control voltage signal is greater than the absolute value of the first voltage signal.
  • the leakage suppression module 300 includes a P-type first transistor T3 and an N-type second transistor T2, and the control terminal and the second input terminal of the leakage suppression module 300 are formed integrally, and are connected to the pull-up node PU. Connected.
  • the pull-up module 100 includes an N-type pull-up transistor T1
  • the memory module 200 includes a storage capacitor C.
  • a first voltage signal is supplied to the clock signal input terminal CLK, and the storage capacitor C is charged through the signal input terminal IN such that the potential of the pull-up node PU is equal to the potential of the effective voltage signal. Therefore, the first transistor T3 is turned off, and the second transistor T2 is turned on, thereby turning on the pull-up node PU and the control electrode of the pull-up transistor T1, thereby turning on the first pole and the second pole of the pull-up transistor T1. Therefore, in the charging phase, the signal output terminal OUT outputs an invalid clock signal (ie, the first voltage signal).
  • an invalid voltage signal is supplied to the storage capacitor C through the signal input terminal IN, and a second voltage signal is supplied through the clock signal input terminal CLK. Therefore, the storage capacitor C is bootstrapped to pull the potential of the pull-up phase PU higher. Therefore, the first transistor T3 is turned off, and the second transistor T2 is turned on, thereby turning on the pull-up node PU and the control electrode of the pull-up transistor T1, thereby causing the first pole and the second pole of the pull-up transistor T1 to be turned on. Therefore, in the output stage, the signal output terminal OUT outputs a valid clock signal (ie, a second voltage signal).
  • an invalid voltage signal is supplied to the storage capacitor through the signal input terminal IN, and the first voltage signal is supplied through the clock signal input terminal CLK. Since the storage capacitor C is discharged at the output stage t2, the potential of the pull-up node PU is the potential of the invalid voltage signal. At this time, the first transistor T3 is turned on, and the second transistor T2 is turned off, thereby supplying the control voltage input to the control voltage signal input terminal VGL to the gate electrode of the pull-up transistor T1.
  • the gate voltage of the pull-up transistor T1 is smaller than the first pole of the pull-up transistor. Voltage, which ensures the pull-up The body tube T1 is completely cut off at this stage, thereby avoiding the generation of leakage current.
  • an invalid clock signal input through the clock signal input terminal is -8V, and passes through The control voltage signal input to the control voltage signal input terminal is -12 to -16V.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位寄存单元及驱动方法、移位寄存器、栅极驱动电路和显示装置。该移位寄存单元包括上拉模块（100）、时钟信号输入端（CLK）、存储模块（200）、信号输出端（OUT）、控制电压信号输入端（VGL）和漏电抑制模块（300）。漏电抑制模块（300）的输出端与上拉模块（100）的控制端相连，漏电抑制模块（300）的第一输入端与控制电压信号输入端（VGL）相连，并且漏电抑制模块（300）的第二输入端与存储模块（200）的另一端相连。

Description

移位寄存单元及驱动方法、移位寄存器、栅极驱动电路和显示装置
相关申请
本申请要求享有2016年1月29日提交的中国专利申请No.201610065078.0的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示装置领域，具体地，涉及一种移位寄存单元、该移位寄存单元的驱动方法，一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示装置。
背景技术
图1中所示的是移位寄存单元的一部分，如图所示，所述移位寄存单元包括上拉晶体管T1、存储电容C、时钟信号输入端CLK和信号输出端OUT。在移位寄存单元的输出阶段，上拉晶体管T1导通，从而将通过时钟信号输入端CLK输入的有效信号输出至信号输出端OUT。在移位寄存单元工作周期的某些阶段(例如，移位寄存单元的复位阶段)，需要控制上拉晶体管T1截止，以避免在此阶段信号输出端存在输出，因此需要使得上拉晶体管T1的栅源电压差为0。
但是，随着显示装置的使用，存在上拉晶体管T1无法正常截止的情况，从而会导致异常显示。
发明内容
本公开的目的在于提供一种移位寄存单元、该移位寄存单元的驱动方法，一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示装置，从而至少缓解或甚至消除以上提到的现有技术的缺陷。
为了实现上述目的，作为本公开的一个方面，提供一种移位寄存单元。所述移位寄存单元包括上拉模块、时钟信号输入端、存储模块和信号输出端。所述上拉模块的输入端与所述时钟信号输入端电连接， 所述上拉模块的输出端与所述信号输出端电连接，并且所述存储模块的一端与所述信号输出端电连接。所述移位寄存单元还包括控制电压信号输入端和漏电抑制模块。所述漏电抑制模块的输出端与所述上拉模块的控制端相连，所述漏电抑制模块的第一输入端与所述控制电压信号输入端相连，并且所述漏电抑制模块的第二输入端与所述存储模块的另一端相连。所述漏电抑制模块被配置成在所述漏电抑制模块的控制端输入的电压信号的控制下选择性地将所述漏电抑制模块的输出端与所述漏电抑制模块的第一输入端或第二输入端导通，并且当所述漏电抑制模块的输出端与所述漏电抑制模块的第一输入端导通时使所述上拉模块的输入端和输出端断开，当所述漏电抑制模块的输出端与所述漏电抑制模块的第二输入端导通时使所述上拉模块的输入端和输出端导通。
根据一些实施例中，所述上拉模块被配置成当上拉模块的控制端接收到的电压与上拉模块的输入端接收到的电压的压差的绝对值不大于预设值时，将所述上拉模块的输入端和输出端导通。
根据一些实施例，所述漏电抑制模块的控制端与所述漏电抑制模块的第二输入端形成为一体且与所述存储模块的另一端相连。
如本文所使用的，“所述漏电抑制模块的控制端与所述漏电抑制模块的第二输入端形成为一体”可以是指漏电抑制模块的同一个端子被复用为控制端和第二输入端，也可以是指漏电抑制模块的控制端和第二输入端输入相同的信号，并且连接到相同的端子(即所述存储模块的另一端)。
根据一些实施例，所述漏电抑制模块包括第一开关元件和第二开关元件。
所述第一开关元件的控制端与所述漏电抑制模块的控制端相连，所述第一开关元件的输入端与所述漏电抑制模块的第一输入端相连，并且所述第一开关元件的输出端与所述漏电抑制模块的输出端相连。所述第一开关元件被配置成在所述漏电抑制模块的控制端接收到无效电压信号时将所述第一开关元件的输入端和输出端导通。
如本文中所使用的，术语“无效电压信号”是指能够使得上拉模块的输入端和输出端断开的信号。相反地，术语“有效电压信号”是指能够使得上拉模块的输入端和输出端导通的信号。
所述第二开关元件的输入端与所述漏电抑制模块的控制端相连，并且所述第二开关元件的输出端与所述漏电抑制模块的输出端相连。所述第二开关元件被配置成在所述漏电抑制模块的控制端接收到有效电压信号时将所述第二开关元件的输入端和输出端导通。
根据一些实施例，所述第一开关元件包括第一晶体管。所述第一晶体管的控制极充当所述第一开关元件的控制端，所述第一晶体管的第一极充当所述第一开关元件的输入端，并且所述第一晶体管的第二极充当所述第一开关元件的输出端。
根据一些实施例，所述第二开关元件包括第二晶体管。所述第二晶体管的控制极和第一极相连，并充当所述第二开关元件的输入端，并且所述第二晶体管的第二极充当所述第二开关元件的输出端。
根据一些实施例，所述第一晶体管为P型晶体管，并且所述第二晶体管为N型晶体管。
根据一些实施例，所述第一晶体管为N型晶体管，并且所述第二晶体管为P型晶体管。
根据一些实施例，所述上拉模块包括上拉晶体管。所述上拉晶体管的控制极充当所述上拉模块的控制端，所述上拉晶体管的第一极充当所述上拉模块的输入端，并且所述上拉晶体管的第二极充当所述上拉模块的输出端。
根据一些实施例，所述上拉晶体管为N型晶体管。
根据一些实施例，所述存储模块包括存储电容器。
作为本公开的另一个方面，提供一种移位寄存器，所述移位寄存器包括级联的多级移位寄存单元，其中，所述移位寄存单元为本公开所提供的上述任一种移位寄存单元。
作为本公开的还一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括移位寄存器，其中，所述移位寄存器为本公开所提供的上述移位寄存器。
作为本公开的又一个方面，提供一种显示装置，所述显示装置包括栅极驱动电路，其中，所述栅极驱动电路为本公开所提供的上述栅极驱动电路。
作为本公开的再一个方面，提供一种移位寄存单元的驱动方法，其中，所述移位寄存单元为本公开所提供的上述任一种移位寄存单元。 所述驱动方法的每个工作周期都包括：
在充电阶段，向时钟信号输入端提供第一电压信号，向控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供有效电压信号；
在输出阶段，向所述时钟信号输入端提供第二电压信号，向所述控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块控制端提供有效电压信号；
在输出下拉阶段，向所述时钟信号输入端提供第一电压信号，向所述控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供无效电压信号。
所述控制电压信号的极性与第一电压信号的极性相同，且所述控制电压信号的绝对值大于第一电压信号的绝对值。
根据一些实施例，当所述上拉模块包括所述上拉晶体管、且所述上拉晶体管为N型晶体管时，所述第一电压信号为-8V，通过所述控制电压信号输入端输入的控制电压信号为-12～-16V。
在本公开所提供的移位寄存单元工作时，在输出下拉阶段，可以通过漏电抑制模块将控制电压信号输入端输入的控制电压信号提供至上拉模块的控制端，并且控制电压信号输入端输入确保上拉模块断开的控制电压信号，从而可以确保上拉模块的输入端与信号输出端断开，以防止漏电流的产生。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是现有的移位寄存单元的一部分的示意图；
图2是本公开的实施例所提供的移位寄存单元的一部分的示意图；
图3是本公开的实施例所提供的移位寄存单元的一部分的示意图；
图4是本公开的实施例所提供的移位寄存单元在工作时，各个信号的时序图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
作为本公开的一个方面，提供一种移位寄存单元。如图2所示，所述移位寄存单元包括上拉模块100、时钟信号输入端CLK、存储模块200和信号输出端OUT。上拉模块100的输入端与时钟信号输入端CLK电连接，上拉模块100的输出端与信号输出端OUT电连接，并且存储模块100的一端与信号输出端OUT电连接。所述移位寄存单元还包括控制电压信号输入端VGL和漏电抑制模块300。该漏电抑制模块300的输出端与上拉模块100的控制端相连，漏电抑制模块300的第一输入端与控制电压信号输入端VGL相连，并且漏电抑制模块300的第二输入端与存储模块200的另一端相连。漏电抑制模块300被配置成在漏电抑制模块300的控制端所接收到的电压信号的控制下选择性地将漏电抑制模块300的输出端与漏电抑制模块300的第一输入端或第二输入端导通。漏电抑制模块300进一步被配置成当所述漏电抑制模块的输出端与所述漏电抑制模块的第一输入端导通时使所述上拉模块的输入端和输出端断开，当所述漏电抑制模块的输出端与所述漏电抑制模块的第二输入端导通时使所述上拉模块的输入端和输出端导通。
在一些实施例中，当上拉模块100的控制端接收到的电压与上拉模块100的输入端接收到的电压的压差不大于预设值时，上拉模块100的输入端和输出端导通。
当本公开的实施例所提供的移位寄存单元用于显示装置中时，向控制电压信号输入端VGL提供控制电压信号。并且，存储模块200的另一端充当该移位寄存单元的上拉节点PU。
当漏电抑制模块300的第一输入端与漏电抑制模块300的输出端导通时，控制电压信号输入端VGL与上拉模块100的控制端导通。此时，可以通过控制电压信号输入端VGL输入无效电压信号，使得上拉模块100的输入端和输出端断开。
当漏电抑制模块300的第二输入端与漏电抑制模块300的输出端导通时，上拉节点PU与上拉模块100的控制端导通。如果上拉节点PU的电平足够高，那么上拉模块100的输入端和输出端则可以导通。
通过控制漏电抑制模块300的第一输入端与输出端导通的时间、 以及通过设计控制电压信号输入端VGL输入的控制电压信号的大小，则可以实现对上拉模块100的控制端接收到的电压的控制，进而实现控制上拉模块100的通断。
当本公开实施例所提供的移位寄存单元用于显示装置中时，结合图4中的信号时序图对本公开实施例所提供的移位寄存单元的工作周期进行详细的介绍。
当移位寄存单元工作时，向控制电压信号输入端VGL输入控制电压信号。该控制电压信号的极性与无效的时钟信号的极性相同，且控制电压信号的绝对值大于无效的时钟信号的绝对值。
容易理解的是，所述移位寄存单元包括信号输入端，在图4中，IN表示的信号时序图即为通过所述信号输入端输入的信号的时序。
在充电阶段t1，向时钟信号输入端CLK提供无效时钟信号(在本文中，称为第一电压信号)。此时，通过信号输入端IN将有效电压信号存储在存储模块200中，使得上拉节点PU的电位等于有效电压信号的电位。在此阶段，可以向漏电抑制模块300的控制端提供有效电压信号，从而将漏电抑制模块300的第二输入端与漏电抑制模块300的输出端导通，即，将上拉节点PU与上拉模块100的控制端导通。由于上拉节点PU此时的电位等于有效电压信号的电位，因此，上拉模块100的输入端和输出端导通，使得信号输出端OUT输出无效的时钟信号。
在输出阶段t2，通过时钟信号输入端CLK输入有效的时钟信号(在本文中，称为第二电压信号)，并且将移位寄存单元的输入端与存储模块200断开。在存储模块200的自举作用下，使得上拉节点PU处的电压仍然为能够使得上拉模块100的输入端和输出端导通的有效电压。在此阶段，向漏电抑制模块300的控制端提供有效信号，使得漏电抑制模块300的第二输入端与漏电抑制模块300的输出端导通。因此，上拉模块100的控制端被输入有效电压信号。此时，上拉模块100的输入端与信号输出端OUT导通，使得信号输出端OUT输出有效的时钟信号。
在输出下拉阶段t3，可以向漏电抑制模块300的控制端提供无效电压信号，从而使得漏电抑制模块300的第一信号输入端与漏电抑制模块300的输出端导通，因而通过控制电压信号输入端VGL输入的控 制电压信号被输入至上拉模块100的控制端，从而可以确保上拉模块100的输入端和输出端断开，防止上拉模块100的输入端与输出端之间出现影响正常输出信号的漏电流，从而可以防止非正常显示的出现。
由此可知，在本公开实施例所提供的移位寄存单元工作时，在输出下拉阶段，可以通过漏电抑制模块300将控制电压信号输入端VGL输入的控制电压信号提供至上拉模块100的控制端，控制电压信号输入端VGL输入确保上拉模块100断开的控制电压信号，从而可以确保上拉模块100的输入端与信号输出端断开，以防止漏电流的产生。
在本公开中，漏电抑制模块300可以采取任何合适的形式。例如，如图2所示，漏电抑制模块300的控制端与该漏电抑制模块300的第二输入端形成为一体，并且都与存储模块200的另一端(即，上拉节点PU)相连。
图3图示了根据本公开的实施例的移位寄存单元的部分的示意图。如图3中所示，漏电抑制模块300包括第一开关元件T3和第二开关元件T2。
第一开关元件T3的控制端与漏电抑制模块300的控制端相连，第一开关元件T3的输入端与漏电抑制模块300的第一输入端相连，并且第一开关元件T3的输出端与漏电抑制模块300的输出端相连。第一开关元件T3被配置成在漏电抑制模块300的控制端接收到无效电压信号时将该第一开关元件T3的输入端和输出端导通。
第二开关元件T2的输入端与漏电抑制模块300的控制端相连，并且第二开关元件T2的输出端与漏电抑制模块300的输出端相连。第二开关元件T2被配置成在漏电抑制模块300的控制端接收到有效电压信号时将该第二开关元件T2的输入端和输出端导通。
当接收到有效电压信号时，第一开关元件T3是断开的，并且第二开关元件T2是导通的；当接收到无效电压信号时，第一开关元件T3是导通的，并且第二开关元件T2是断开的。
在示例性实施例中，如图3中所示，第一开关元件T3包括第一晶体管，第一晶体管的控制极充当该第一开关元件的控制端，第一晶体管的第一极充当该第一开关元件T3的输入端，并且第一晶体管的第二极充当该第一开关元件T3的输出端。
容易理解的是，当第一开关元件T3的控制端接收到有效电压信号 时，该第一开关元件T3的输入端和输出端之间是断开的；当第一开关元件T3的控制端接收到无效电压信号时，该第一开关元件T3的输入端和输出端导通。例如，当有效电压信号为高电平信号时，第一晶体管可以为P型晶体管。
在本公开中，第二开关元件T2可以采取任何合适的形式。例如，第二开关元件T2可以为二极管。当有效电压信号为高电平信号时，第二开关元件T2的阳极与上拉节点PU相连，第二开关元件T2的阴极与上拉模块100的控制端相连。
可替换地，第二开关元件T2可以包括第二晶体管。第二晶体管的控制极和第一极相连，并充当该第二开关元件T2的输入端，并且第二晶体管的第二极充当该第二开关元件T2的输出端。第二晶体管的控制极和第一极相连，从而形成为二极管连接。
容易理解的是，当第二开关元件T2的控制端接收到有效电压信号时，第二开关元件T2的输入端与输出端导通；当第二开关元件T2的控制端接收到无效电压信号时，第二开关元件T2的输入端与输出端断开。当有效电压信号为高电平信号时，第二晶体管可以为N型晶体管；当有效电压信号为低电平信号时，第二晶体管则可以为P型晶体管。
由此可知，当第一开关元件T3和第二开关元件T2均包括晶体管时，二者的类型是不相同的。如果第一晶体管为P型晶体管，第二晶体管则为N型晶体管。如果第一晶体管为N型晶体管，第二晶体管则为P型晶体管。
在本公开中，上拉模块100可以采取任何合适的形式。例如，如图3中所示，上拉模块100包括上拉晶体管T1。该上拉晶体管T1的控制极充当上拉模块100的控制端，上拉晶体管T1的第一极充当上拉模块100的输入端，并且上拉晶体管T1的第二极充当上拉模块100的输出端。
如图3中所示，上拉晶体管T1的控制极与漏电抑制模块300的输出端相连，上拉晶体管T1的第一极与时钟信号输入端CLK相连，并且上拉晶体管T1的第二极与信号输出端OUT相连。
当上拉晶体管T1为N型晶体管时，理论上，当上拉晶体管T1的栅源压差(即，上拉晶体管T1的栅极和第二极之间的压差)为0时，上拉晶体管T1是截止的。为了避免漏电流的产生，可以将上拉晶体管 T1的控制端电压设置成更低的电压，从而可以使得上拉晶体管T1的栅源压差小于0，从而可以确保上拉晶体管T1截止，避免漏电流的产生。
例如，当通过时钟信号输入端CLK输入的时钟信号的低电平电压为-8V时，可以向控制电压信号输入端VGL提供小于-8V的电压。例如，可以向控制电压信号输入端VGL提供-16V～-12V之间的电压，以确保上拉晶体管T1能够截止。
作为本公开的一种实施方式，上拉晶体管T1为N型晶体管。相应地，有效电压信号为高电平信号，无效电压信号为低电平信号。相应地，第二晶体管可以是N型晶体管，第一晶体管可以是P型晶体管。
在本公开中，存储模块200可以采取任何适当的形式，只要能够在充电阶段存储电荷、在输出阶段保证上拉节点PU的电平处于有效电压信号的电平即可。例如，存储模块200包括存储电容器C。存储电容器C的一端充当存储模块200的一端，并且存储电容器C的另一端充当存储模块200的另一端。
作为本公开的另一个方面，提供一种移位寄存器。所述移位寄存器包括级联的多级移位寄存单元，其中，所述移位寄存单元为本公开所提供的上述任一种移位寄存单元。
作为本公开的还一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括移位寄存器，其中，所述移位寄存器为本公开所提供的上述移位寄存器。
作为本公开的又一个方面，提供一种显示装置，所述显示装置包括栅极驱动电路，其中，所述栅极驱动电路为本发明所提供的上述栅极驱动电路。
本公开的实施例还提供一种移位寄存单元的驱动方法，其中，所述移位寄存单元为本公开所提供的上述任一种移位寄存单元。如图4所示，所述驱动方法的每个工作周期都包括以下阶段。
在充电阶段t1，向时钟信号输入端CLK提供第一电压信号(即无效的时钟信号)，向控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供有效电压信号。
在输出阶段t2，向时钟信号输入端CLK提供第二电压信号(即有效的时钟信号)，向所述控制电压信号输入端提供控制电压信号，并 且向所述漏电抑制模块控制端提供有效电压信号；
在输出下拉阶段t3，向所述时钟信号输入端提供第一电压信号，向所述控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供无效电压信号。
所述控制电压信号的极性与第一电压信号的极性相同，且所述控制电压信号的绝对值大于第一电压信号的绝对值。
下面结合图3中的具体电路结构描述本公开实施例所提供的驱动方法。如图3中所示，漏电抑制模块300包括P型的第一晶体管T3和N型的第二晶体管T2，漏电抑制模块300的控制端和第二输入端形成为一体，且与上拉节点PU相连。上拉模块100包括N型的上拉晶体管T1，并且存储模块200包括存储电容器C。
在充电阶段t1，向时钟信号输入端CLK提供第一电压信号，并且通过信号输入端IN向存储电容器C充电，使得上拉节点PU的电位等于有效电压信号的电位。因此，第一晶体管T3截止，第二晶体管T2导通，从而将上拉节点PU与上拉晶体管T1的控制极导通，进而使得上拉晶体管T1的第一极与第二极导通。因此，在充电阶段，信号输出端OUT输出无效时钟信号(即，第一电压信号)。
在输出阶段t2，通过信号输入端IN向存储电容器C提供无效电压信号，并且通过时钟信号输入端CLK提供第二电压信号。因此，存储电容器C发生自举作用，将上拉阶段PU的电位拉至更高。因而，第一晶体管T3截止，并且第二晶体管T2导通，从而将上拉节点PU与上拉晶体管T1的控制极导通，进而使得上拉晶体管T1的第一极与第二极导通。因此，在输出阶段，信号输出端OUT输出有效时钟信号(即，第二电压信号)。
在输出下拉阶段t3，通过信号输入端IN向存储电容提供无效电压信号，通过时钟信号输入端CLK提供第一电压信号。由于在输出阶段t2，存储电容器C放电，因此，上拉节点PU的电位为无效电压信号的电位。此时，第一晶体管T3导通，第二晶体管T2截止，从而将控制电压信号输入端VGL输入的控制电压提供至上拉晶体管T1的控制极。由于控制电压信号VGL的极性与无效的时钟信号相同，并且控制电压信号VGL的绝对值小于无效的时钟信号的绝对值，因此，上拉晶体管T1的控制极电压小于上拉晶体管的第一极电压，从而可以确保上拉晶 体管T1在此阶段彻底截止，从而避免了漏电流的产生。
本领域技术人员应当理解的是，在移位寄存单元中，存在与时钟信号输入端CLK输入的时钟信号相位互补的时钟信号输入端CLKB，如何设置该时钟信号输入端CLKB是本领域技术人员所公知的，这里不再赘述。
在示例性实施例中，如上文中所述，当上拉模块包括上拉晶体管，且上拉晶体管为N型晶体管时，通过所述时钟信号输入端输入的无效时钟信号为-8V，并且通过所述控制电压信号输入端输入的控制电压信号为-12～-16V。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种移位寄存单元，包括上拉模块、时钟信号输入端、存储模块和信号输出端，所述上拉模块的输入端与所述时钟信号输入端电连接，所述上拉模块的输出端与所述信号输出端电连接，并且所述存储模块的一端与所述信号输出端电连接，其中，所述移位寄存单元还包括控制电压信号输入端和漏电抑制模块，所述漏电抑制模块的输出端与所述上拉模块的控制端相连，所述漏电抑制模块的第一输入端与所述控制电压信号输入端相连，并且所述漏电抑制模块的第二输入端与所述存储模块的另一端相连，
    所述漏电抑制模块被配置成在所述漏电抑制模块的控制端输入的电压信号的控制下选择性地将所述漏电抑制模块的输出端与所述漏电抑制模块的第一输入端或第二输入端导通，并且当所述漏电抑制模块的输出端与所述漏电抑制模块的第一输入端导通时使所述上拉模块的输入端和输出端断开，当所述漏电抑制模块的输出端与所述漏电抑制模块的第二输入端导通时使所述上拉模块的输入端和输出端导通。
  2. 根据权利要求1所述的移位寄存单元，其中所述上拉模块被配置成当上拉模块的控制端接收到的电压与上拉模块的输入端接收到的电压的压差的绝对值不大于预设值时，将所述上拉模块的输入端和输出端导通。
  3. 根据权利要求1所述的移位寄存单元，其中，所述漏电抑制模块的控制端与所述漏电抑制模块的第二输入端形成为一体且与所述存储模块的另一端相连。
  4. 根据权利要求3所述的移位寄存单元，其中，所述漏电抑制模块包括第一开关元件和第二开关元件，
    所述第一开关元件的控制端与所述漏电抑制模块的控制端相连，所述第一开关元件的输入端与所述漏电抑制模块的第一输入端相连，并且所述第一开关元件的输出端与所述漏电抑制模块的输出端相连，所述第一开关元件被配置成在所述漏电抑制模块的控制端接收到无效电压信号时将所述第一开关元件的输入端和输出端导通；
    所述第二开关元件的输入端与所述漏电抑制模块的控制端相连，并且所述第二开关元件的输出端与所述漏电抑制模块的输出端相连， 所述第二开关元件被配置成在所述漏电抑制模块的控制端接收到有效电压信号时将所述第二开关元件的输入端和输出端导通。
  5. 根据权利要求4所述的移位寄存单元，其中，所述第一开关元件包括第一晶体管，所述第一晶体管的控制极充当所述第一开关元件的控制端，所述第一晶体管的第一极充当所述第一开关元件的输入端，并且所述第一晶体管的第二极充当所述第一开关元件的输出端。
  6. 根据权利要求5所述的移位寄存单元，其中，所述第二开关元件包括第二晶体管，所述第二晶体管的控制极和第一极相连，并充当所述第二开关元件的输入端，并且所述第二晶体管的第二极充当所述第二开关元件的输出端。
  7. 根据权利要求6所述的移位寄存单元，其中，所述第一晶体管为P型晶体管，并且所述第二晶体管为N型晶体管。
  8. 根据权利要求6所述的移位寄存单元，其中，所述第一晶体管为N型晶体管，并且所述第二晶体管为P型晶体管。
  9. 根据权利要求1至8中任意一项所述的移位寄存单元，其中，所述上拉模块包括上拉晶体管，所述上拉晶体管的控制极充当所述上拉模块的控制端，所述上拉晶体管的第一极充当所述上拉模块的输入端，并且所述上拉晶体管的第二极充当所述上拉模块的输出端。
  10. 根据权利要求9所述的移位寄存单元，其中，所述上拉晶体管为N型晶体管。
  11. 根据权利要求1至10中任意一项所述的移位寄存单元，其中，所述存储模块包括存储电容器。
  12. 一种移位寄存器，所述移位寄存器包括级联的多级移位寄存单元，其中，所述移位寄存单元为权利要求1至11中任意一项所述的移位寄存单元。
  13. 一种栅极驱动电路，所述栅极驱动电路包括移位寄存器，其中，所述移位寄存器为权利要求12所述的移位寄存器。
  14. 一种显示装置，所述显示装置包括栅极驱动电路，其中，所述栅极驱动电路为权利要求13所述的栅极驱动电路。
  15. 一种移位寄存单元的驱动方法，其中，所述移位寄存单元为权利要求1至11中任意一项所述的移位寄存单元，所述驱动方法的每个工作周期都包括：
    在充电阶段，向时钟信号输入端提供第一电压信号，向控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供有效电压信号；
    在输出阶段，向所述时钟信号输入端提供第二电压信号，向所述控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块控制端提供有效电压信号；
    在输出下拉阶段，向所述时钟信号输入端提供第一电压信号，向所述控制电压信号输入端提供控制电压信号，并且向所述漏电抑制模块的控制端提供无效电压信号，其中，
    所述控制电压信号的极性与第一电压信号的极性相同，且所述控制电压信号的绝对值大于第一电压信号的绝对值。
  16. 根据权利要求15所述的驱动方法，其中，所述上拉模块包括上拉晶体管，所述上拉晶体管的控制极充当所述上拉模块的控制端，所述上拉晶体管的第一极充当所述上拉模块的输入端，并且所述上拉晶体管的第二极充当所述上拉模块的输出端，所述上拉晶体管为N型晶体管，所述第一电压信号为-8V，通过所述控制电压信号输入端输入的控制电压信号为-12～-16V。
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