WO2017118013A1 - 防静电器件及其制造方法、基板 - Google Patents

防静电器件及其制造方法、基板 Download PDF

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WO2017118013A1
WO2017118013A1 PCT/CN2016/094107 CN2016094107W WO2017118013A1 WO 2017118013 A1 WO2017118013 A1 WO 2017118013A1 CN 2016094107 W CN2016094107 W CN 2016094107W WO 2017118013 A1 WO2017118013 A1 WO 2017118013A1
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Prior art keywords
layer
conductive layer
insulating layer
antistatic device
conductive
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PCT/CN2016/094107
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English (en)
French (fr)
Inventor
任兴凤
汪森林
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/629,975 priority Critical patent/US10025152B2/en
Publication of WO2017118013A1 publication Critical patent/WO2017118013A1/zh
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
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    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
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    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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Definitions

  • the present invention relates to an antistatic device, a method of manufacturing an antistatic device, and a substrate including the antistatic device.
  • the array substrate of the liquid crystal display includes a pixel unit and a thin film transistor that drives the pixel unit.
  • a thin film transistor that drives the pixel unit.
  • static electricity is generated on different conductive layers of the thin film transistor due to friction, etc., and static electricity breakdown occurs when static electricity is accumulated to a certain extent, which causes a pixel circuit on the array substrate. Short circuit and damage.
  • FIG. 1 shows a cross-sectional view of an antistatic device of the prior art.
  • the antistatic device mainly includes a first conductive layer 11 , a first insulating layer 12 formed on the first conductive layer 11 , and a second conductive layer 15 formed on the first insulating layer 12 .
  • a second insulating layer 16 on the second conductive layer 15 a via 02 formed in the second insulating layer 16, a via 03 penetrating the second insulating layer 16 and the first insulating layer 12, and a second insulating layer
  • the second conductive layer 15 of the antistatic device is electrically connected to the third conductive layer 17 via the via 02
  • the third conductive layer 17 is connected to the first conductive layer 11 via the via 03 .
  • Electrical connection. Therefore, in the prior art, the second conductive layer 15 and the first conductive layer 11 are electrically isolated from each other before the third conductive layer 17 is formed. Therefore, before the third conductive layer 17 is formed, there is a voltage difference between the second conductive layer 15 and the first conductive layer 11 (because the second conductive layer 15 and the first layer are caused during the manufacturing process, such as friction or the like) Static electricity is present on a conductive layer 11, and electrostatic breakdown occurs when static electricity is accumulated to a certain extent. When the voltage difference is sufficiently high, the second conductive layer 15 and the first conductive layer 11 are broken. An insulating layer 12, which causes the pixel circuits on the array substrate to be damaged by a short circuit.
  • Electrostatic breakdown can cause damage to the pixel circuits on the array substrate in the display device, which can lead to array bases in severe cases.
  • the pixel circuit on the board is shorted and the array substrate is not working properly.
  • the via 03 electrically connecting the third conductive layer 17 and the first conductive layer 11 needs to penetrate through the first insulating layer 12 and the second insulating layer 16, which results in the via 03 The length is long and difficult to make.
  • the actually formed via 03 cannot completely penetrate the first insulating layer 12 and the second insulating layer 16, which may cause the third conductive layer 17 not to be electrically connected to the first conductive layer 11, and the third conductive layer 17 and the first layer are added.
  • an antistatic device which is capable of eliminating a potential difference between different conductive layers and effectively preventing electrostatic breakdown between different conductive layers.
  • an antistatic device is provided that is capable of reducing the length of vias that bridge two conductive layers, effectively reducing the probability of electrical disconnection between the two conductive layers.
  • an antistatic device comprising: a first conductive layer; a first insulating layer formed on the first conductive layer; and an active layer formed on the first insulating layer; Etching a barrier layer formed on the active layer; a second conductive layer formed on the etch stop layer and including first and second portions spaced apart from each other; and a second insulating layer formed at the On the second conductive layer; and a third conductive layer formed on the second insulating layer, the first portion and the second portion of the second conductive layer respectively passing through the first portion formed in the etch barrier layer
  • the via hole and the second via hole are electrically connected to the active layer, and are electrically connected to the third conductive layer through a third via hole and a fourth via hole formed in the second insulating layer, respectively, One of the first portion and the second portion of the second conductive layer is electrically connected to the first conductive layer through a fifth via hole penetrating the etch stop layer and the first insulating layer.
  • an array substrate comprising the aforementioned antistatic device is provided.
  • a method of manufacturing the aforementioned antistatic device comprising the steps of:
  • first portion and the second portion of the second conductive layer are electrically connected to the active layer through the first via and the second via, respectively, One of the first portion and the second portion of the second conductive layer is electrically connected to the first conductive layer through the fifth via;
  • the second conductive layer is electrically connected to the first conductive layer through a single via hole, and the second conductive layer and the first conductive layer in the production process can be eliminated in time.
  • the potential difference effectively prevents electrostatic breakdown during the production process.
  • the foregoing antistatic device may be formed simultaneously while manufacturing a thin film transistor to avoid electrostatic breakdown between different conductive layers during the process of fabricating the thin film transistor.
  • the vias spanning the two conductive layers only need to penetrate through an insulating layer, thereby reducing the length of the via vias and reducing the occurrence between the two conductive layers. The probability of electrical disconnection.
  • Figure 1 shows a cross-sectional view of an antistatic device of the prior art
  • FIG. 2 shows a cross-sectional view of an antistatic device in accordance with an exemplary embodiment of the present invention.
  • FIGS 3a-3h show the process of making the antistatic device shown in Figure 2.
  • an antistatic device comprising: a first conductive layer; a first insulating layer formed on the first conductive layer; and an active layer formed on the first insulating layer An etch barrier layer formed on the active layer; a second conductive layer including first and second portions spaced apart from each other, formed on the etch stop layer;
  • the first portion and the second portion of the second conductive layer are electrically connected to the active layer through first and second via holes formed in the etch barrier layer, respectively;
  • One of the first portion and the second portion of the second conductive layer is electrically connected to the first conductive layer through a fifth via hole penetrating the etch stop layer and the first insulating layer.
  • the first conductive layer and the second conductive layer can be electrically connected before the third conductive layer is disposed, thereby eliminating the potential difference between the two different conductive layers, effectively Prevent electrostatic breakdown between different conductive layers.
  • a second insulating layer formed on the second conductive layer, and a third conductive layer formed on the second insulating layer are further disposed.
  • the first portion and the second portion of the second conductive layer are electrically connected to the third conductive layer through third vias and fourth vias formed in the second insulating layer, respectively.
  • FIG. 2 shows a cross-sectional view of an antistatic device in accordance with an exemplary embodiment of the present invention.
  • an antistatic device mainly includes a first conductive layer 110, a first insulating layer 120, an active layer 130, an etch stop layer 140, a second conductive layer 150, a second insulating layer 160, and a third conductive layer. Layer 170.
  • the first insulating layer 120 is formed on the first conductive layer 110.
  • the active layer 130 is formed on the first insulating layer 120 by a patterning process.
  • An etch barrier layer 140 is formed on the active layer 130.
  • the second conductive layer 150 is formed on the etch barrier layer 140, and the second conductive layer 150 includes a first portion 151 and a second portion 152 that are formed once by a single patterning process. The first portion 151 and the second portion 152 are spaced apart from each other.
  • the second insulating layer 160 is formed on the second conductive layer 150.
  • the third conductive layer 170 is formed on the second insulating layer 160.
  • the first portion 151 and the second portion 152 of the second conductive layer 150 pass through the first via 10 and the second via 20 formed in the etch stop layer 140, respectively. Electrically connected to the active layer 130, and the first portion 151 and the second portion 152 of the second conductive layer 150 are respectively formed in the second The third via 30 and the fourth via 40 in the edge layer 160 are electrically connected to the third conductive layer 170.
  • one of the first portion 151 and the second portion 152 of the second conductive layer 150 passes through the first through the etch barrier layer 140 and the first insulating layer 120.
  • the five vias 50 are electrically connected to the first conductive layer 110.
  • the first portion 151 of the second conductive layer 150 is electrically coupled to the first conductive layer 110 by a fifth via 50 extending through the etch stop layer 140 and the first insulating layer 120.
  • the present invention is not limited to the illustrated embodiment, for example, the positions of the first portion 151 and the second portion 152 of the second conductive layer 150 in FIG. 2 may be interchanged.
  • the third conductive layer 170 may be a transparent conductive layer made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first insulating layer 120 and the second insulating layer 160 may be a passivation protective layer made of an inorganic insulating material.
  • the first insulating layer 120 and the second insulating layer 160 may be made of silicon dioxide SiO 2 , silicon nitride SiN x , silicon oxynitride SiO x N y , aluminum oxide Al 2 O 3 or titanium oxide TiO x .
  • the active layer 130 may be a semiconductive layer made of an oxide semiconductor material.
  • the active layer 130 may be made of indium gallium zinc oxide IGZO, indium gallium tin oxide oxide IGTO, or indium zinc oxide IZO.
  • a substrate including the aforementioned antistatic device is provided, the substrate further including an array substrate portion having a thin film transistor array.
  • Figures 3a-3h show the process of making the antistatic device shown in Figure 2.
  • FIG. 2 A method of manufacturing the antistatic device shown in FIG. 2 will be described in detail below with reference to FIG. 3, which mainly includes the following steps:
  • S150 forming a second conductive layer 150 on the etch barrier layer 140. As shown in FIG. 3e, the first portion 151 and the second portion 152 of the second conductive layer 150 pass through the first via hole 10 and the second via hole 20, respectively.
  • the active layer 130 is electrically connected, and one of the first portion 151 and the second portion 152 of the second conductive layer 150 is electrically connected to the first conductive layer 110 through the fifth via 50;
  • S180 forming a third conductive layer 170 on the second insulating layer 160. As shown in FIG. 3h, the third conductive layer 170 passes through the third via 30 and the fourth via 40 and the first portion 151 of the second conductive layer 150, respectively. The second portion 152 is electrically connected.
  • an antistatic device as shown in Fig. 2 can be manufactured.
  • the first portion 151 and the second portion 152 of the second conductive layer 150 pass through the first via 10 and the second via 20, respectively.
  • the active layer 130 is electrically connected, and one of the first portion 151 and the second portion 152 of the second conductive layer 150 is electrically connected to the first conductive layer 110 through the fifth via 50.
  • the first portion 151 of the second conductive layer 150 is electrically coupled to the first conductive layer 110 through a separate fifth via 50, and thus, the first portion 151 of the second conductive layer 150 and the first conductive layer
  • the layer 110 is at the same potential.
  • the active layer 130 is turned on, which causes the second conductive layer 150 to
  • the first portion 151, the second portion 152, and the first conductive layer 110 are all at the same potential, thereby eliminating the potential difference between the second conductive layer 150 and the first conductive layer 110, thereby effectively preventing electrostatic discharge during production. Wear phenomenon.
  • the foregoing antistatic device may be formed simultaneously while manufacturing a thin film transistor to avoid electrostatic breakdown between different conductive layers during the process of manufacturing the thin film transistor, for example, Electrostatic breakdown between the source and drain layers of the thin film transistor and the gate during the fabrication of the thin film transistor is avoided.
  • the bridging vias 30, 40 bridging the third conductive layer 170 and the second conductive layer 150 need only penetrate through the second insulating layer 160. There is no need to penetrate the first insulating layer 140 and the second insulating layer 160, thereby reducing the length of the bridging vias 30, 40 across the third conductive layer 170 and the second conductive layer 150 (far less than that shown in FIG. 1)
  • the length of the vias 03 in the prior art reduces the probability of electrical disconnection of the third conductive layer.
  • the length of the fifth via 50 electrically connecting the second conductive layer 150 and the first conductive layer 110 is small (far less than that shown in FIG. 1).
  • the length of the via hole 03 in the prior art is therefore easy to form, which reduces manufacturing difficulty and ensures reliable electrical connection between the second conductive layer 150 and the first conductive layer 110.
  • the first via hole 10 and the second via hole 20 are etched from the top surface of the etch barrier layer 140 to the active layer 130, and the fifth via hole 50 is The top surface of the etch stop layer 140 is always Etching to the top surface of the first conductive layer 110.
  • the first portion 151 and the second portion 152 of the second conductive layer 150 pass through the first via 10, the second The bidirectional conduction circuit formed by the via 20 and the fifth via 50 is electrically connected to the first conductive layer 110, thereby eliminating the potential difference between the second conductive layer 150 and the first conductive layer 110, thereby effectively preventing the production process. Electrostatic breakdown occurs.

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Abstract

一种防静电器件及其制造方法、基板；防静电器件包括：第一导电层（110）；第一绝缘层（120），形成在第一导电层（110）上；有源层（130），形成在第一绝缘层（120）上；刻蚀阻挡层（140），形成在有源层（130）上；第二导电层（150），形成在刻蚀阻挡层（140）上，包括相互隔开的第一部分（151）和第二部分（152）；第二导电层（150）的第一部分（151）和第二部分（152）分别通过形成在刻蚀阻挡层（140）中的第一过孔（10）和第二过孔（20）与有源层（130）电连接；第二导电层（150）的第一部分（151）和第二部分（152）中的一个通过贯穿刻蚀阻挡层（140）和第一绝缘层（120）的第五过孔（50）与第一导电层（110）电连接；由于第二导电层（150）通过单独的过孔与第一导电层（110）电连接，因此，可以及时消除第一导电层（110）和第二导电层（150）之间的电位差，有效防止在生产过程中出现静电击穿现象。

Description

防静电器件及其制造方法、基板
本申请要求于2016年01月05日递交的、申请号为201610005081.3、发明名称为“防静电器件及其制造方法、基板”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明涉及一种防静电器件、防静电器件的制造方法以及包括该防静电器件的基板。
背景技术
液晶显示器的阵列基板包括像素单元和驱动该像素单元的薄膜晶体管。通常，在生产薄膜晶体管时，由于摩擦等原因，会在薄膜晶体管的不同的导电层上产生静电，当静电积累到一定程度就会出现静电击穿现象，这会导致阵列基板上的像素电路因短路而受损。
为了防止出现静电击穿现象，一般需要在制造薄膜晶体管的同时形成一个防静电器件，以避免在不同的导电层之间出现静电击穿现象。图1显示现有技术中的一种防静电器件的剖视图。如图1所示，该防静电器件主要包括第一导电层11、形成在第一导电层11上的第一绝缘层12、形成在第一绝缘层12上的第二导电层15、形成在第二导电层15上的第二绝缘层16、形成在第二绝缘层16中的过孔02、贯穿第二绝缘层16和第一绝缘层12的过孔03、和形成在第二绝缘层16上的第三导电层17。
如图1所示，在现有技术中，该防静电器件的第二导电层15经由过孔02与第三导电层17电连接，第三导电层17经由过孔03与第一导电层11电连接。因此，在现有技术中，在形成第三导电层17之前，第二导电层15与第一导电层11之间是相互电隔离开的。因此，在形成第三导电层17之前，在第二导电层15与第一导电层11之间存在电压差(因为在制造的过程中，例如摩擦等原因，会导致第二导电层15和第一导电层11上存在静电，当静电积累到一定程度就会出现静电击穿现象)，当该电压差足够高时，就会击穿第二导电层15与第一导电层11之间的第一绝缘层12，这会导致阵列基板上的像素电路因短路而受损。
因此，在现有技术中，在制造薄膜晶体管的过程中，依然会出现静电击穿现象。静电击穿会导致显示装置中的阵列基板上的像素电路受损，严重时会导致阵列基 板上的像素电路短路，阵列基板无法正常工作。
此外，如图1所示，在现有技术中，电连接第三导电层17和第一导电层11的过孔03需要贯穿第一绝缘层12和第二绝缘层16，这导致过孔03的长度较长，难以制作。有时实际形成的过孔03不能完全贯穿第一绝缘层12和第二绝缘层16，这会导致第三导电层17不能电连接到第一导电层11，增加了第三导电层17与第一导电层11之间电断开(OPEN)的概率。
发明内容
本发明的目的旨在解决现有技术中存在的上述问题和缺陷的至少一个方面。
根据本发明的一个目的，提供一种防静电器件，其能够消除不同导电层之间的电位差，有效地防止在不同导电层之间出现静电击穿现象。
根据本发明的另一个目的，提供一种防静电器件，其能够减小跨接两个导电层的过孔的长度，有效降低了两个导电层之间出现电断开的概率。
根据本发明的一个方面，提供一种防静电器件，包括：第一导电层；第一绝缘层，形成在所述第一导电层上；有源层，形成在所述第一绝缘层上；刻蚀阻挡层，形成在所述有源层上；第二导电层，形成在所述刻蚀阻挡层上，并且包括相互隔开的第一部分和第二部分；第二绝缘层，形成在所述第二导电层上；和第三导电层，形成在所述第二绝缘层上，所述第二导电层的第一部分和第二部分分别通过形成在所述刻蚀阻挡层中的第一过孔和第二过孔与所述有源层电连接，并且分别通过形成在所述第二绝缘层中的第三过孔和第四过孔与所述第三导电层电连接，所述第二导电层的第一部分和第二部分中的一个通过贯穿所述刻蚀阻挡层和所述第一绝缘层的第五过孔与所述第一导电层电连接。
根据本发明的另一个方面，提供一种阵列基板，包括前述防静电器件。
根据本发明的另一个方面，提供一种制造前述防静电器件的方法，包括以下步骤：
在所述第一导电层上形成第一绝缘层；
在所述第一绝缘层上形成有源层；
在所述有源层上形成刻蚀阻挡层；
形成贯穿所述刻蚀阻挡层的第一过孔和第二过孔和形成贯穿所述刻蚀阻挡层和所述第一绝缘层的第五过孔；
在所述刻蚀阻挡层上形成第二导电层，其中所述第二导电层的第一部分和第二部分分别通过所述第一过孔和第二过孔与所述有源层电连接，所述第二导电层的第一部分和第二部分中的一个通过所述第五过孔与所述第一导电层电连接；
在所述第二导电层上形成第二绝缘层；
形成贯穿所述第二绝缘层的第三过孔和第四过孔；和
在所述第二绝缘层上形成第三导电层，所述第三导电层分别通过所述第三过孔和第四过孔与所述第二导电层的第一部分和第二部分电连接。
在根据本发明的前述各个实施例的防静电器件中，第二导电层通过一个单独的过孔与第一导电层电连接，可以及时消除生产过程中第二导电层与第一导电层之间的电位差，有效防止了在生产过程中出现静电击穿现象。
在本发明的一个实例性的实施例中，前述防静电器件可以在制造薄膜晶体管的同时同步形成，以避免在制造薄膜晶体管的过程中在不同的导电层之间出现静电击穿。
此外，在本发明的前述各个实施例中，跨接两个导电层的过孔只需贯穿一层绝缘层，因此，减小了跨接过孔的长度，降低了两个导电层之间出现电断开的概率。
通过下文中参照附图对本发明所作的描述，本发明的其它目的和优点将显而易见，并可帮助对本发明有全面的理解。
附图说明
图1显示现有技术中的一种防静电器件的剖视图；
图2显示根据本发明的一个实例性的实施例的防静电器件的剖视图；和
图3a-3h显示制造图2所示的防静电器件的过程。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
根据本发明的一个总体技术构思，提供一种防静电器件，包括：第一导电层；第一绝缘层，形成在所述第一导电层上；有源层，形成在所述第一绝缘层上；刻蚀阻挡层，形成在所述有源层上；第二导电层，包括相互隔开的第一部分和第二部分，形成在所述刻蚀阻挡层上；
其中，所述第二导电层的第一部分和第二部分分别通过形成在所述刻蚀阻挡层中的第一过孔和第二过孔与所述有源层电连接；
所述第二导电层的第一部分和第二部分中的一个通过贯穿所述刻蚀阻挡层和所述第一绝缘层的第五过孔与所述第一导电层电连接。
基于上述结构，相对于现有技术，第一导电层和第二导电层在未设置第三导电层之前即可实现电连接，进而能够消除上述两个不同导电层之间的电位差，有效地防止在不同导电层之间出现静电击穿现象。
在上述提供的结构之上，进一步设置形成在所述第二导电层上的第二绝缘层，；和形成在所述第二绝缘层上的第三导电层。所述第二导电层的第一部分和第二部分分别通过形成在所述第二绝缘层中的第三过孔和第四过孔与所述第三导电层电连接。
如此设置，结合前述结构中的第二导电层与第一导电层的电连接结构，以及第二导电层与第三导电层的电连接结构，替换将现有技术中第一导电层和第三导电层直接贯通的电连接结构，避免了形成长度较大的过孔，降低了第三导电层与第一导电层断路的概率。
图2显示根据本发明的一个实例性的实施例的防静电器件的剖视图。
在本发明的一个实例性的实施例中，公开了一种防静电器件。如图2所示，该防静电器件主要包括第一导电层110、第一绝缘层120、有源层130、刻蚀阻挡层140、第二导电层150、第二绝缘层160和第三导电层170。
如图2所示，在图示的实施例中，第一绝缘层120形成在第一导电层110上。有源层130通过构图工艺形成在第一绝缘层120上。刻蚀阻挡层140形成在有源层130上。第二导电层150形成在刻蚀阻挡层140上，该第二导电层150包括通过单次构图工艺一次性地形成的第一部分151和第二部分152。第一部分151和第二部分152相互隔开。第二绝缘层160形成在第二导电层150上。第三导电层170形成在第二绝缘层160上。
请继续参见图2，在图示的实施例中，第二导电层150的第一部分151和第二部分152分别通过形成在刻蚀阻挡层140中的第一过孔10和第二过孔20与有源层130电连接，并且第二导电层150的第一部分151和第二部分152分别通过形成在第二绝 缘层160中的第三过孔30和第四过孔40与第三导电层170电连接。
在本发明的一个实例性的实施例中，如图2所示，第二导电层150的第一部分151和第二部分152中的一个通过贯穿刻蚀阻挡层140和第一绝缘层120的第五过孔50与第一导电层110电连接。在图示的实施例中，第二导电层150的第一部分151通过贯穿刻蚀阻挡层140和第一绝缘层120的第五过孔50与第一导电层110电连接。但是，本发明不局限于图示的实施例，例如，图2中的第二导电层150的第一部分151和第二部分152的位置可以互换。
在本发明的一个实施例中，如图2所示，第三导电层170可以为由铟锡氧化物(ITO)制成的透明导电层。
在本发明的一个实施例中，如图2所示，第一绝缘层120和第二绝缘层160可以为由无机绝缘材料制成的钝化保护层。例如，第一绝缘层120和第二绝缘层160可以由二氧化硅SiO2、氮化硅SiNx、氮氧化硅SiOxNy，氧化铝Al2O3或氧化钛TiOx制成。
在本发明的一个实施例中，如图2所示，有源层130可以为由氧化物半导体材料制成的半导电层。例如，有源层130可以由铟镓锌氧化物IGZO、铟镓锡氧化物氧化IGTO或铟锌氧化物IZO制成。
尽管未图示，根据本发明的另一个总体技术构思，提供一种包括前述防静电器件的基板，该基板还包括具有薄膜晶体管阵列的阵列基板部分。图3a-3h显示制造图2所示的防静电器件的过程。
下面将参照图3来详细说明制造图2所示的防静电器件的方法，该方法主要包括以下步骤：
S110：在第一导电层110上形成第一绝缘层120，如图3a所示；
S120：在第一绝缘层120上形成有源层130，如图3b所示；
S130：在有源层130上形成刻蚀阻挡层140，如图3c所示；
S140：形成贯穿刻蚀阻挡层140的第一过孔10和第二过孔20和形成贯穿刻蚀阻挡层140和第一绝缘层120的第五过孔50，如图3d所示；
S150：在刻蚀阻挡层140上形成第二导电层150，如图3e所示，第二导电层150的第一部分151和第二部分152分别通过第一过孔10和第二过孔20与有源层130电连接，第二导电层150的第一部分151和第二部分152中的一个通过第五过孔50与第一导电层110电连接；
S160：在第二导电层150上形成第二绝缘层160，如图3f所示；
S170：形成贯穿第二绝缘层160的第三过孔30和第四过孔40，如图3g所示；和
S180：在第二绝缘层160上形成第三导电层170，如图3h所示，第三导电层170分别通过第三过孔30和第四过孔40与第二导电层150的第一部分151和第二部分152电连接。
这样，就可以制造出一个如图2所示的防静电器件。
在前述制造过程中，如图3e所示，一旦形成第二导电层150之后，第二导电层150的第一部分151和第二部分152就分别通过第一过孔10和第二过孔20与有源层130电连接，第二导电层150的第一部分151和第二部分152中的一个通过第五过孔50与第一导电层110电连接。在图示的实施例中，第二导电层150的第一部分151通过一个独立的第五过孔50与第一导电层110电连接，因此，第二导电层150的第一部分151和第一导电层110处于相同的电位，此时，如果第二导电层150的第一部分151与第二部分152之间存在电位差，有源层130就会导通，这就会使得第二导电层150的第一部分151、第二部分152以及第一导电层110都处于相同的电位，从而消除了第二导电层150与第一导电层110之间的电位差，有效防止了在生产过程中出现静电击穿现象。
在本发明的一个实例性的实施例中，前述防静电器件可以在制造薄膜晶体管的同时同步形成，以避免在制造薄膜晶体管的过程中在不同的导电层之间出现静电击穿，例如，以避免在制造薄膜晶体管的过程中在薄膜晶体管的源漏极层与栅极之间出现静电击穿。
在本发明的前述各个实施例中，如图3g和图3h所示，跨接第三导电层170和第二导电层150的跨接过孔30、40只需贯穿第二绝缘层160，而无需贯穿第一绝缘层140和第二绝缘层160，因此，减小了跨接第三导电层170和第二导电层150的跨接过孔30、40的长度(远小于图1所示的现有技术中的过孔03的长度)，降低了第三导电层出现电断开的概率。
在本发明的前述各个实施例中，如图3d和图3e所示，由于电连接第二导电层150和第一导电层110的第五过孔50的长度较小(远小于图1所示的现有技术中的过孔03的长度)，因此，第五过孔50容易形成，降低了制造难度，能够确保第二导电层150与第一导电层110之间可靠电连接。
在本发明的前述实施例中，如图3d所示，第一过孔10和第二过孔20从刻蚀阻挡层140的顶面一直刻蚀至有源层130，第五过孔50从刻蚀阻挡层140的顶面一直 刻蚀至第一导电层110的顶面。这样，在形成第二导电层150的第一部分151和第二部分152之后，如图3e所示，第二导电层150的第一部分151和第二部分152通过由第一过孔10、第二过孔20和第五过孔50构成的双向导通电路与第一导电层110电连接，从而消除了第二导电层150与第一导电层110之间的电位差，有效防止了在生产过程中出现静电击穿现象。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
虽然结合附图对本发明进行了说明，但是附图中公开的实施例旨在对本发明优选实施方式进行示例性说明，而不能理解为对本发明的一种限制。
虽然本总体发明构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离本总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本发明的范围以权利要求和它们的等同物限定。
应注意，措词“包括”不排除其它元件或步骤，措词“一”或“一个”不排除多个。另外，权利要求的任何元件标号不应理解为限制本发明的范围。

Claims (13)

  1. 一种防静电器件，包括：
    第一导电层(110)；
    第一绝缘层(120)，形成在所述第一导电层(110)上；
    有源层(130)，形成在所述第一绝缘层(120)上；
    刻蚀阻挡层(140)，形成在所述有源层(130)上；
    第二导电层(150)，形成在所述刻蚀阻挡层(140)上并且包括相互隔开的第一部分(151)和第二部分(152)；
    其中，所述第二导电层(150)的第一部分(151)和第二部分(152)分别通过形成在所述刻蚀阻挡层(140)中的第一过孔(10)和第二过孔(20)与所述有源层(130)电连接；
    所述第二导电层(150)的第一部分(151)和第二部分(152)中的一个通过贯穿所述刻蚀阻挡层(140)和所述第一绝缘层(120)的第五过孔(50)与所述第一导电层(110)电连接。
  2. 根据权利要求1所述的防静电器件，还包括：
    第二绝缘层(160)，形成在所述第二导电层(150)上；和
    第三导电层(170)，形成在所述第二绝缘层(160)上，
    所述第二导电层(150)的第一部分(151)和第二部分(152)分别通过形成在所述第二绝缘层(150)中的第三过孔(30)和第四过孔(40)与所述第三导电层(170)电连接。
  3. 根据权利要求2所述的防静电器件，其中，
    所述第三导电层(170)为由铟锡氧化物制成的透明导电层。
  4. 根据权利要求2所述的防静电器件，其中，
    所述第一绝缘层(120)和所述第二绝缘层(160)为由无机绝缘材料制成的钝化保护层。
  5. 根据权利要求4所述的防静电器件，其中，
    所述第一绝缘层(120)和所述第二绝缘层(160)由二氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛制成。
  6. 根据权利要求1所述的防静电器件，其中，
    所述有源层(130)为由氧化物半导体材料制成的半导电层。
  7. 根据权利要求6所述的防静电器件，其中，
    所述有源层(130)由铟镓锌氧化物、铟镓锡氧化物氧化或铟锌氧化物制成。
  8. 根据权利要求1-7中任一项所述的防静电器件，其中，所述防静电器件设置于包括薄膜晶体管的基板上。
  9. 一种基板，包括权利要求1至8任一项所述的防静电器件。
  10. 一种制造权利要求1至7任一项所述的防静电器件的方法，包括以下步骤：
    在所述第一导电层(110)上形成第一绝缘层(120)；
    在所述第一绝缘层(120)上形成有源层(130)；
    在所述有源层(130)上形成刻蚀阻挡层(140)；
    形成贯穿所述刻蚀阻挡层(140)的第一过孔(10)和第二过孔(20)和形成贯穿所述刻蚀阻挡层(140)和所述第一绝缘层(120)的第五过孔(50)；
    在所述刻蚀阻挡层(140)上形成第二导电层(150)，其中所述第二导电层(150)的第一部分(151)和第二部分(152)分别通过所述第一过孔(10)和第二过孔(20)与所述有源层(130)电连接，所述第二导电层(150)的第一部分(151)和第二部分(152)中的一个通过所述第五过孔(50)与所述第一导电层(110)电连接。
  11. 根据权利要求10所述的方法，还包括：
    在所述第二导电层(150)上形成第二绝缘层(160)；
    形成贯穿所述第二绝缘层(160)的第三过孔(30)和第四过孔(40)；和
    在所述第二绝缘层(160)上形成第三导电层(170)，其中所述第三导电层(170)分别通过所述第三过孔(30)和第四过孔(40)与所述第二导电层(150)的第一部分(151)和第二部分(152)电连接。
  12. 根据权利要求10所述的方法，其中，
    所述第二导电层(150)的第一部分(151)和第二部分(152)通过一次构图工艺一次性地形成在所述刻蚀阻挡层(140)上。
  13. 根据权利要求10-12中任一项所述的方法，其中，
    所述防静电器件在制造薄膜晶体管的同时同步形成。
PCT/CN2016/094107 2016-01-05 2016-08-09 防静电器件及其制造方法、基板 Ceased WO2017118013A1 (zh)

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