WO2017117845A1 - 栅极驱动电路和使用栅极驱动电路的液晶显示器 - Google Patents

栅极驱动电路和使用栅极驱动电路的液晶显示器 Download PDF

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Publication number
WO2017117845A1
WO2017117845A1 PCT/CN2016/074462 CN2016074462W WO2017117845A1 WO 2017117845 A1 WO2017117845 A1 WO 2017117845A1 CN 2016074462 W CN2016074462 W CN 2016074462W WO 2017117845 A1 WO2017117845 A1 WO 2017117845A1
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Prior art keywords
electrically connected
transistor
output
control
control node
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/916,261 priority Critical patent/US10068542B2/en
Publication of WO2017117845A1 publication Critical patent/WO2017117845A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to a liquid crystal display, in particular to a gate driver (Gate driver on A liquid crystal display of an array, GOA) circuit.
  • GOA gate driver on A liquid crystal display of an array
  • the GOA circuit uses a thin film transistor liquid crystal display Array process to fabricate a gate driver with a thin film transistor (Thin film). Transistor, TFT) on the substrate of the array to implement a progressive scan driving method.
  • the GOA circuit contains several GOA circuit units.
  • a conventional GOA circuit unit outputs a scan signal by controlling a gate voltage of an output transistor (that is, a voltage at a Q point).
  • the prior art precharges the output transistor such that the Q point voltage is at the output transistor. It is charged to the high level before the high level signal is passed.
  • the prior art utilizes a capacitor to store the Q point voltage.
  • the capacitor is still electrically connected to other transistors in the GOA circuit unit, and thus the charge stored in the capacitor flows out through other transistors, resulting in leakage. This causes the voltage at the Q point to drop, so that the output transistor cannot be fully turned on, causing the output transistor to not fully turn on the high level signal to form an incomplete scan signal pulse.
  • the technical solution of the present invention provides a gate driving circuit including a plurality of GOA circuit units, a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is used according to the first two stages of the GOA circuit unit.
  • the output scan signal, the first clock signal, and the second clock signal output a scan signal at the output end.
  • Each level of the GOA circuit unit includes: an input control module, configured to be turned on when receiving the scan signal output by the first two stages of the GOA circuit unit; and a latching module electrically connected to the input control module and the first control node, And a voltage stabilizing module electrically connected to the latch module for preventing leakage; and an output control module electrically connected to the first control node for applying Controlling the output of the scan signal by the voltage of the first control node; the pull-up module is electrically connected to the second control node, and configured to: when the second clock signal is received, the second control node is a high level; a pull-down maintaining module electrically connected to the input control module, the latch module, the output control module, the pull-up module, and the voltage stabilizing module for maintaining the second control node a low level during the non-scan period, and maintaining a low level of the scan signal; and a driving module electrically connecting the output end and the second transistor for outputting a pulse of the scan signal Outputting the driving signal to turn on said second
  • the latching module includes: a first transistor electrically connected to the input control module, a first input end electrically connected to the first fixed voltage, and a first output end electrically connected to the first control node a second transistor, the second control terminal is electrically connected to the driving signal, the second input end is electrically connected to the first output end of the first transistor, and the second output end is electrically connected to the first control node; And a third transistor, wherein the third control terminal and the third output terminal are electrically connected to the first control node, and the third input terminal is electrically connected to the input control module.
  • the voltage stabilizing module includes a fourth transistor, wherein a fourth control electrode is electrically connected to the first fixed voltage, and a fourth input electrode is electrically connected to the first control electrode of the first transistor The fourth output is electrically connected to the second control node.
  • the pull-up module includes a fifth transistor, the fifth control electrode is electrically connected to the second clock signal, and the fifth input is electrically connected to the first fixed voltage, and the fifth The output is electrically connected to the second control node.
  • the pull-down maintaining module includes: a sixth transistor, the sixth control electrode is electrically connected to the second clock signal, and the sixth input is electrically connected to the fourth output of the fourth transistor a sixth transistor electrically connected to the second fixed voltage; a seventh transistor having a seventh control electrode electrically connected to the fourth output electrode of the fourth transistor, wherein the seventh input is electrically connected to the fourth input a second control node, wherein the seventh output is electrically connected to the second fixed voltage; the eighth transistor has an eighth control electrode electrically connected to the second control node, and an eighth input is electrically connected to the second a control node, an eighth output of which is electrically connected to the second fixed voltage; a ninth transistor whose ninth control electrode is electrically connected to the second control node, and a ninth input of which is electrically connected to the output end The ninth output is electrically connected to the second fixed voltage; and the first capacitor is electrically connected to the second control node and the second fixed voltage at both ends.
  • the input control module includes a tenth transistor, and the tenth control electrode and the tenth input electrode are electrically connected to the scan signal output by the first two stages of the GOA circuit unit, and the tenth output is electrically Connecting the first control electrode of the first transistor.
  • the output control module includes an eleventh transistor, and an eleventh control electrode is electrically connected to the first control node, and an eleventh input electrode is electrically connected to the first clock signal, Its eleventh output is electrically connected to the output terminal.
  • the drive circuit is an inverter for inverting the scan signal of the output to output as the drive signal.
  • the driving circuit is a NOR circuit electrically connected to the output end and the second control node for using the scan signal and the second control node according to the scan signal.
  • the voltage performs a NAND operation to output the drive signal.
  • the driving circuit comprises: a twelfth transistor, wherein the twelfth control electrode and the twelfth input electrode are electrically connected to the first fixed voltage, and the twelfth output is electrically connected The second control electrode of the second transistor; and the thirteenth transistor, wherein the thirteenth control electrode is electrically connected to the output end, and the thirteenth input electrode is electrically connected to the second transistor
  • the second control electrode has a thirteenth output pole electrically connected to the second fixed voltage.
  • the driving circuit further includes a fourteenth transistor, wherein the fourteenth control electrode is electrically connected to the second control node, and the fourteenth input terminal is electrically connected to the second transistor
  • the second control electrode has a fourteenth output pole electrically connected to the second fixed voltage.
  • the gate driving circuit further includes a second capacitor electrically connected to the first control node and the output end.
  • the technical solution of the present invention further provides a liquid crystal display including a source driver and a gate driving circuit as described above, wherein the gate driving circuit outputs a scan signal such that a plurality of the transistors are turned on, and the source driver outputs corresponding The data signal is applied to a plurality of said pixel units to display gray scales.
  • the GOA circuit unit of the present invention replaces the capacitor with a latch module. Because the second transistor of the latch module is turned on when the scan signal does not generate a pulse, the first transistor and the third transistor can latch the voltage of the first control node. At the same time, since the transistor forms a DC path between the first control node and the first fixed voltage, the voltage of the first control node does not change due to leakage. In addition, since the second capacitor couples the voltage of the first control node, the pulse of the scan signal output by the GOA circuit unit has a desired level.
  • the eighth transistor is turned on by the voltage of the second control node, so that the output control module is turned off because the voltage of the first control node is pulled down, so the scan signal output by the GOA circuit unit is at a low level. Therefore, the present invention solves the technical problem that the GOA circuit unit using the capacitor in the prior art is prone to leakage, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.
  • Figure 1 is a functional block diagram of a liquid crystal display of the present invention.
  • Fig. 2 is a circuit diagram of a GOA circuit unit of the first embodiment of the present invention.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2.
  • Figure 4 is a circuit diagram of a GOA circuit unit of a second embodiment of the present invention.
  • Figure 5 is a circuit diagram of a GOA circuit unit of a third embodiment of the present invention.
  • Figure 6 is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 5.
  • Fig. 7 is a circuit diagram of a GOA circuit unit of a fourth embodiment of the present invention.
  • FIG. 1 is a functional block diagram of a liquid crystal display device 10 of the present invention.
  • the liquid crystal display 10 includes a glass substrate 14, a timing controller 30, and a source driver (source) Driver)16.
  • a plurality of pixels arranged in a matrix and a gate driving (GOA) circuit 12 are disposed on the glass substrate 14, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • the timing controller 30 is used to generate the clock signals CK1-CK4 and the start signals STV1, STV2.
  • the GOA circuit 12 outputs the scan signals at regular intervals such that the transistors 22 of each row are sequentially turned on, while the source driver 16 outputs corresponding data signals to an entire column of pixel cells 20 to charge them to respective required voltages. Show different gray levels.
  • the GOA circuit 12 turns off the scan signal of the row, and then the GOA circuit 12 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 charges the pixel unit 20 of the next row. Discharge. This is continued until all the pixel units 20 are fully charged, and charging starts from the first line.
  • the GOA circuit 12 shown in FIG. The control includes N GOA circuit units SR(1), ..., SR(N), N equal to 768.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n) according to a first embodiment of the present invention.
  • the GOA circuit 12 is provided on both sides of the glass substrate 14.
  • the GOA circuit 12 includes a plurality of cascade-connected GOA circuit units SR(n).
  • the two GOA circuits 12 respectively include GOA circuit units SR(1), SR(3), ..., SR for generating odd scan signals G(1), G(3), ..., G(767).
  • each stage of the GOA circuit unit SR(n) is used to output the scan signal G(n-2), the first clock signal CKV1, and the second clock signal CKV2 according to the first two stages of the GOA circuit unit SR(n-2).
  • the scan signal G(n) is output at the output terminal OUT.
  • the first clock signal CKV1 and the second clock signal CKV2 represent two of the four clock signals CK1-CK4, respectively.
  • the four clock signals CK1-CK4 generate pulses in turn, and the times at which pulses are generated from each other do not overlap each other.
  • the GOA circuit units SR(1), SR(5), ..., SR(N-3) are based on the clock signals CK1 and CK2 (representing the first clock signal CKV1 and the second clock signal CKV2 of FIG. 2, respectively).
  • the scan signals G(1), G(5), ..., G(N-3) are generated; the GOA circuit units SR(2), SR(6), ..., SR(N-2) are based on the clock signals CK2 and CK3 (Respectively indicating the first clock signal CKV1 and the second clock signal CKV2 of FIG. 2) generating scan signals G(2), G(6), ..., G(N-2); GOA circuit units SR(3), SR( 7), ..., SR(N-1) generates scan signals G(3), G(7), ... according to clock signals CK3 and CK4 (representing first clock signal CKV1 and second clock signal CKV2 of Fig. 2, respectively).
  • GOA circuit units SR(4), SR(8), ..., SR(N) are based on clock signals CK4 and CK1 (representing the first clock signal CKV1 and the second clock signal of Fig. 2, respectively) CKV2) generates scan signals G(4), G(8), ..., G(N).
  • Each stage of the GOA circuit unit SR(n) includes an input control module 100, a latch module 200, an output control module 300, a voltage stabilizing module 400, a pull-up module 500, a pull-down maintaining module 600, and a driving module 700.
  • the input control module 100 is configured to be turned on when receiving the scan signal G(n-2) output by the first two stages of the GOA circuit unit SR(n-2).
  • the latch module 200 is electrically connected to the input control module 100 and the first control node Q(n) for latching the level of the first control node Q(n).
  • the output control module 300 is electrically connected to the first control node Q(n) for controlling the output scan signal G(n) according to the voltage applied to the first control node Q(n).
  • the voltage stabilizing module 400 is electrically connected to the latch module 200 for preventing leakage.
  • the pull-up module 500 is electrically connected to the second control node P(n) for causing the second control node P(n) to be at a high level when receiving the second clock signal CKV2.
  • the pull-down maintaining module 600 is electrically connected to the input control module 100, the latch module 200, the output control module 300, the pull-up module 500, and the voltage stabilizing module 400 for maintaining low power of the second control node P(n) during non-scanning. Flat, and maintain the low level of the scan signal G(n).
  • the driving module 700 is electrically connected to the output terminal OUT and the second transistor T2 for outputting the driving signal TR1 to turn on the second transistor T2 when the pulse of the scanning signal G(n) is output.
  • the latch module 200 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the first control terminal of the first transistor T1 is electrically connected to the input control module 100, and the first input end thereof is electrically connected to the first fixed voltage V1, and the first output end thereof is electrically connected to the first control node Q(n).
  • the second control terminal of the second transistor T2 is electrically connected to the driving signal TR1, the second input end thereof is electrically connected to the first output end of the first transistor T1, and the second output end thereof is electrically connected to the first control node Q(n) .
  • the third control terminal and the third output terminal of the third transistor T3 are electrically connected to the first control node Q(n), and the third input terminal is electrically connected to the input control module 100.
  • the voltage stabilizing module 400 includes a fourth transistor T4.
  • the fourth control electrode of the fourth transistor T4 is electrically connected to the first fixed voltage V1
  • the fourth input pole is electrically connected to the first control electrode of the first transistor T1
  • the fourth output thereof is electrically connected to the second control node P ( n).
  • the pull-up module 500 includes a fifth transistor T5.
  • the fifth control electrode of the fifth transistor T5 is electrically connected to the second clock signal CKV2, the fifth input pole is electrically connected to the first fixed voltage V1, and the fifth output pole is electrically connected to the second control node P(n).
  • the pull-down maintaining module 600 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a first capacitor C1.
  • the sixth control electrode of the sixth transistor T6 is electrically connected to the second clock signal CKV2, the sixth input terminal thereof is electrically connected to the fourth output electrode of the fourth transistor T4, and the sixth output electrode thereof is electrically connected to the second fixed voltage V2.
  • the seventh control electrode of the seventh transistor T7 is electrically connected to the fourth output electrode of the fourth transistor T4, the seventh input terminal is electrically connected to the second control node P(n), and the seventh output is electrically connected to the second fixed electrode. Voltage V2.
  • the eighth control electrode of the eighth transistor T8 is electrically connected to the second control node P(n), and the eighth input is electrically connected to the first control node Q(n), and the eighth output is electrically connected to the second fixed voltage. V2.
  • the ninth control electrode of the ninth transistor T9 is electrically connected to the second control node P(n), the ninth input of which is electrically connected to the output terminal OUT, and the ninth output of which is electrically connected to the second fixed voltage V2. Both ends of the first capacitor C1 are electrically connected to the second control node P(n) and the second fixed voltage V2.
  • the input control module 100 includes a tenth transistor T10.
  • the tenth control electrode and the tenth input pole of the tenth transistor T10 are electrically connected to the scan signal G(n-2) outputted by the first two stages of the GOA circuit unit SR(n-2), and the tenth output is electrically connected first.
  • the output control module 300 includes an eleventh transistor T11.
  • the eleventh control electrode of the eleventh transistor T11 is electrically connected to the first control node Q(n), the eleventh input pole is electrically connected to the first clock signal CKV1, and the eleventh output pole is electrically connected to the output end OUT .
  • the drive circuit 700 is an inverter for inverting the scan signal G(n) of the output terminal OUT to output the drive signal TR1.
  • the driving circuit 700 includes a twelfth transistor T12 and a thirteenth transistor T13.
  • the twelfth control electrode and the twelfth input electrode of the twelfth transistor T12 are electrically connected to the first fixed voltage V1, and the twelfth output pole is electrically
  • the second control electrode of the second transistor T2 is connected.
  • the thirteenth control electrode of the thirteenth transistor T13 is electrically connected to the output terminal OUT, and the thirteenth input terminal is electrically connected to the second control electrode of the second transistor T2, and the thirteenth output electrode is electrically connected to the second fixed voltage. V2.
  • the gate driving circuit SR(n) further includes a second capacitor C2. Both ends of the second capacitor C2 are electrically connected to the first control node Q(n) and the output terminal OUT.
  • All the transistors of the GOA circuit unit SR(n) of FIG. 2 are N-type metal oxides. Semiconductor, NMOS) transistor.
  • the control, input and output terminals of all of the transistors T1-T13 are the gate, the drain and the source of the transistors T1-T13, respectively, the first fixed voltage V1 is at a high level, and the second fixed voltage V2 is Low level.
  • the input and output terminals of transistors T1-T13 may also be the source and drain of the transistor, respectively.
  • FIG. 3 is a timing diagram of various input signals, output signals and node voltages shown in FIG.
  • the period during which each of the GOA circuit units SR(n) outputs the scanning signal G(n), that is, t3 shown in FIG. 3, is referred to as a scanning period, and the remaining time is referred to as a non-scanning period.
  • the non-scanning period is further divided into a pre-charging period t1-t2 and an idle period t5.
  • the following embodiment is exemplified by the GOA circuit unit SR(n) employing the clock signals CK1 and CK2 (representing the first clock signal CKV1 and the second clock signal CKV2 of FIG. 2, respectively).
  • the transistor T10 transmits the high-level scan signal G(n-2) to the first control of the transistor T1.
  • the pole is such that the transistor T1 is turned on.
  • the sixth control electrode of the transistor T6 turns on the high-level scan signal G(n-2) to the ninth control electrode of the transistor T9 by receiving the first fixed voltage V1 of the high level. Therefore, the transistor T9 turns on the second fixed voltage V2 of the low level to the second control node P(n).
  • the transistor T5 turns on the first clock signal CKV1 of the low level to the output terminal OUT, so the scan signal G(n) is at the low level.
  • the driving module 700 inverts the scanning signal G(n) to output the driving signal TR1 of the high level, the transistor T2 is turned on.
  • the transistors T1 and T2 are both turned on, and the first fixed voltage V1 of the high level is turned on to the first control node Q(n).
  • the transistors T1 and T9 are not turned on, and at this time, the voltages of the first control node Q(n) are held at a high level by the transistors T1 and T3 of the latch module 200. Since the transistors T1, T2 form a direct current path between the first control node Q(n) and the first fixed voltage V1 of the high level, the voltage of the first control node Q(n) is not lowered by the leakage. At this time, the transistor T5 turns on the first clock signal CKV1 of the low level to the output terminal OUT, so the scan signal G(n) is at the low level. The low level scan signal G(n) outputs a high level drive signal TR1, causing transistor T2 to turn on.
  • the first clock signal CKV1 of the high level is turned on to the output terminal OUT to form a scan.
  • the high level scan signal G(n) outputs a low level drive signal TR1, causing transistor T2 to turn off. Therefore, the second capacitor C2 couples the voltage of the first control node Q(n) such that the level of the scan signal G(n) pulse rises with the voltage of the first control node Q(n), achieving an ideal high power. level.
  • the high-level scan signal G(n) outputs a low-level drive signal TR1, so that the transistor T2 is turned off.
  • the transistors T5 and T6 are turned on by the second clock signal CKV2 of the high level, and the first fixed voltage V1 of the high level is transmitted to the second control node P(n).
  • the eighth control electrode of the eighth transistor T8 and the ninth control electrode of the transistor T9 are turned on because the second control node P(n) is at a high level, so that the first control node Q(n) and the output terminal OUT are both pulled down to be stable. Low level.
  • the scanning signal G(n) is at a low level.
  • the low level scan signal G(n) outputs a high level drive signal TR1, causing transistor T2 to turn on.
  • FIG. 4 is a circuit diagram of a GOA circuit unit SR(n) according to a second embodiment of the present invention.
  • all of the transistors of the GOA circuit unit SR(n) of FIG. 4 are P-type MOSs (P-type).
  • the connection and operation modes of the components are the same as those of FIG. 5, the level of the signal for driving the PMOS transistor and the output signal of the PMOS transistor are exactly opposite to those of the NMOS transistor, which is well known to those skilled in the art, and is not otherwise Narration.
  • those skilled in the art can replace all or part of the NMOS transistors with PMOS transistors in accordance with the circuit of the present invention to achieve the same function of the GOA circuit unit.
  • the GOA circuit unit SR(n) of the present invention replaces the capacitor with the latch module 200. Since the second transistor T2 of the latch module 200 is turned on when the scan signal G(n) does not generate a pulse, the first transistor T1 and the third transistor T3 can latch the voltage of the first control node Q(n). At the same time, since the transistors T1, T2 form a direct current path between the first control node Q(n) and the first fixed voltage V1, the voltage of the first control node Q(n) does not change due to leakage. In addition, since the second capacitor C2 couples the voltage of the first control node Q(n), the pulse of the output scan signal G(n) has a desired level. Therefore, the present invention solves the technical problem that the GOA circuit unit using the capacitor in the prior art is prone to leakage, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.
  • FIG. 5 is a circuit diagram of a GOA circuit unit SR(n) according to a third embodiment of the present invention.
  • the GOA circuit unit SR(n) shown in FIG. 2 has the same numbered components as the GOA circuit unit SR(n) shown in FIG. 5, and its function and operation are the same, and will not be further described herein.
  • the second control terminal of the second transistor T2 of the GOA circuit unit SR(n) of the present embodiment is electrically connected to the driving signal TR2, and the driving module 800 is a NOR gate (NOR).
  • the driving circuit 800 includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.
  • the twelfth control electrode and the twelfth input electrode of the twelfth transistor T12 are electrically connected to the first fixed voltage V1, and the twelfth output electrode is electrically connected to the second control electrode of the second transistor T2.
  • the thirteenth control electrode of the thirteenth transistor T13 is electrically connected to the output terminal OUT, and the thirteenth input terminal is electrically connected to the second control electrode of the second transistor T2, and the thirteenth output electrode is electrically connected to the second fixed voltage. V2.
  • the fourteenth control electrode of the fourteenth transistor T14 is electrically connected to the second control node P(n), and the fourteenth input pole is electrically connected to the second control electrode of the second transistor T2, and the fourteenth output pole is electrically A second fixed voltage V2 is connected.
  • All of the transistors of the GOA circuit unit SR(n) of FIG. 5 are N-type metal oxides. Semiconductor, NMOS) transistor.
  • the control, input and output terminals of all of the transistors T1-T14 are the gate, the drain and the source of the transistors T1-T14, respectively, the first fixed voltage V1 is at a high level, and the second fixed voltage V2 is Low level.
  • the input and output terminals of transistors T1-T14 can also be the source and drain of the transistor, respectively.
  • FIG. 6 is a timing diagram of various input signals, output signals and node voltages shown in FIG.
  • the period during which each of the GOA circuit units SR(n) outputs the scanning signal G(n), that is, t3 shown in FIG. 6, is referred to as a scanning period, and the remaining time is referred to as a non-scanning period.
  • the non-scanning period is further divided into a pre-charging period t1-t2 and an idle period t5.
  • the following embodiment is exemplified by the GOA circuit unit SR(n) employing the clock signals CK1 and CK2 (representing the first clock signal CKV1 and the second clock signal CKV2 of FIG. 2, respectively).
  • the transistor T10 transmits the high-level scan signal G(n-2) to the first control of the transistor T1.
  • the pole is such that the transistor T1 is turned on.
  • the sixth control electrode of the transistor T6 turns on the high-level scan signal G(n-2) to the ninth control electrode of the transistor T9 by receiving the first fixed voltage V1 of the high level. Therefore, the transistor T9 turns on the second fixed voltage V2 of the low level to the second control node P(n).
  • the transistor T5 turns on the first clock signal CKV1 of the low level to the output terminal OUT, so the scan signal G(n) is at the low level.
  • the driving module 800 performs a non-operation and outputs a high level driving signal TR2, so the transistor T2 is turned on. At this time, the transistors T1 and T2 are both turned on, and the first fixed voltage V1 of the high level is turned on to the first control node Q(n).
  • the transistors T1 and T9 are not turned on, and at this time, the voltages of the first control node Q(n) are held at a high level by the transistors T1 and T3 of the latch module 200. Since the transistors T1, T2 form a direct current path between the first control node Q(n) and the first fixed voltage V1 of the high level, the voltage of the first control node Q(n) is not lowered by the leakage. At this time, the transistor T5 turns on the first clock signal CKV1 of the low level to the output terminal OUT, so the scan signal G(n) is at the low level. Because the scan signal G(n) The voltage applied to the second control node P(n) is also at a low level, so the driving module 800 performs a non-operation and outputs a high level driving signal TR2, so the transistor T2 is turned on.
  • the first clock signal CKV1 of the high level is turned on to the output terminal OUT to form a scan. Pulse of signal G(n).
  • the high level scan signal G(n) outputs a low level drive signal TR2, causing transistor T2 to turn off. Therefore, the second capacitor C2 couples the voltage of the first control node Q(n) such that the level of the scan signal G(n) pulse rises with the voltage of the first control node Q(n), achieving an ideal high power. level.
  • the driving module 800 performs a non-operation and outputs a low level driving signal TR2, so the transistor T2 is turned off and not turned on. .
  • the transistors T5 and T6 are turned on by the second clock signal CKV2 of the high level, and the first fixed voltage V1 of the high level is transmitted to the second control node P(n).
  • the eighth control electrode of the eighth transistor T8 and the ninth control electrode of the transistor T9 are turned on because the second control node P(n) is at a high level, so that the first control node Q(n) and the output terminal OUT are both pulled down to be stable. Low level.
  • the eighth transistor T8 and the ninth transistor T9 are turned on by the voltage of the second control node P(n), so that the output control module 300 is due to the first control node Q(n)
  • the voltage is turned off by a second fixed voltage V2 that is pulled down to a low level.
  • the ninth transistor T9 is turned on to turn on the second fixed voltage V2 of the low level to the output terminal OUT, so the scan signal G(n) will be a stable low level.
  • FIG. 7 is a circuit diagram of a GOA circuit unit SR(n) according to a fourth embodiment of the present invention.
  • all the transistors of the GOA circuit unit SR(n) of FIG. 7 are P-type MOSs (P-type).
  • the level of the signal for driving the PMOS transistor and the output signal of the PMOS transistor are exactly opposite to those of the NMOS transistor, which is well known to those skilled in the art, and is not otherwise Narration.
  • those skilled in the art can replace all or part of the NMOS transistors with PMOS transistors in accordance with the circuit of the present invention to achieve the same function of the GOA circuit unit.
  • the GOA circuit unit SR(n) of the present invention replaces the capacitor with the latch module 200. Since the second transistor T2 of the latch module 200 is turned on when the scan signal G(n) does not generate a pulse, the first transistor T1 and the third transistor T3 can latch the voltage of the first control node Q(n). At the same time, since the transistors T1, T2 form a direct current path between the first control node Q(n) and the first fixed voltage V1, the voltage of the first control node Q(n) does not change due to leakage. In addition, since the second capacitor C2 couples the voltage of the first control node Q(n), the pulse of the output scan signal G(n) has a desired level.
  • the eighth transistor T8 is turned on by the voltage of the second control node P(n), so that the output control module 300 is turned off due to the voltage of the first control node Q(n) being pulled down, so the scan signal G (n) is low. Therefore, the present invention solves the technical problem that the GOA circuit unit using the capacitor in the prior art is prone to leakage, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.

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Abstract

一种栅极驱动电路(12)，其包含数个GOA电路单元(SR(1)~SR(N))。GOA电路单元(SR(n))利用锁存模块(200)取代电容。因为锁存模块(200)的第二晶体管(T2)在扫描信号(G(n))没有产生脉冲时开启，使得第一晶体管(T1)和第三晶体管(T3)能将第一控制节点(Q(n))的电压锁存。同时，因为第一晶体管(T1)和第二晶体管(T2)在第一控制节点(Q(n))和第一固定电压(V1)之间形成直流通路，因此第一控制节点(Q(n))的电压不会因漏电而变化。另外，由于第二电容(C2)会耦合第一控制节点(Q(n))的电压，使得GOA电路单元(SR(n))输出的扫描信号(G(n))的脉冲具有理想电平。该栅极驱动电路(12)解决了现有技术容易发生漏电的技术问题，提升了扫描信号(G(n))的稳定性。

Description

栅极驱动电路和使用栅极驱动电路的液晶显示器 技术领域
本发明是有关于一种液晶显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的液晶显示器。
 背景技术
GOA电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个GOA电路单元。传统的GOA电路单元通过控制输出晶体管的栅极电压(亦即Q点电压)来输出扫描信号。为了确保该输出晶体管能准确地由漏极导通高电平的信号脉冲至源极，以形成扫描信号脉冲，现有技术是对该输出晶体管预充电，使得该Q点电压在该输出晶体管导通该高电平的信号之前就先充电至高电平。为了让该Q点电压维持在高电平至少两个时钟脉冲的时间，现有技术是利用电容来存储Q点电压。但是该电容仍电性连接GOA电路单元内的其它晶体管，因此会导致存储于该电容的电荷经由其它晶体管流出，导致漏电。这会造成Q点电压下降，使得该输出晶体管无法完全开启，导致该输出晶体管无法完全导通该高电平的信号而形成不完整的扫描信号脉冲。
因此有必要对现有技术采用电容存储Q点电压的方式进行改良，以避免Q点漏电的现象。
 技术问题
本发明的目的是提供一种栅极驱动电路和使用栅极驱动电路的液晶显示器，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前两级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号。每一级GOA电路单元包含：输入控制模块，用来于接收所述前两级GOA电路单元输出的扫描信号时导通；锁存模块，电性连接所述输入控制模块和第一控制节点，用来锁存所述第一控制节点的电平；稳压模块，电性连接所述锁存模块，用来防止漏电；输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；上拉模块，电性连接第二控制节点，用来于接收所述第二时钟信号时，使得所述第二控制节点处于高电平；下拉维持模块，电性连接所述输入控制模块、所述锁存模块、所述输出控制模块、所述上拉模块和所述稳压模块，用来维持所述第二控制节点在非扫描期间的低电平，以及维持所述扫描信号的低电平；及驱动模块，电性连接所述输出端及所述第二晶体管，用来于输出所述扫描信号的脉冲时，输出所述驱动信号以开启所述第二晶体管。锁存模块包含：第一晶体管，其第一控制端电性连接所述输入控制模块，其第一输入端电性连接第一固定电压，其第一输出端电性连接所述第一控制节点；第二晶体管，其第二控制端电性连接驱动信号，其第二输入端电性连接所述第一晶体管的第一输出端，其第二输出端电性连接所述第一控制节点；以及第三晶体管，其第三控制端和第三输出端皆电性连接所述第一控制节点，其第三输入端电性连接所述输入控制模块。
依据本发明的实施例，所述稳压模块包含第四晶体管，其第四控制极电性连接所述第一固定电压，其第四输入极电性连接所述第一晶体管的第一控制极，其第四输出极电性连接所述第二控制节点。
依据本发明的实施例，所述上拉模块包含第五晶体管，其第五控制极电性连接所述第二时钟信号，其第五输入极电性连接所述第一固定电压，其第五输出极电性连接所述第二控制节点。
依据本发明的实施例，所述下拉维持模块包含：第六晶体管，其第六控制极电性连接所述第二时钟信号，其第六输入极电性连接所述第四晶体管的第四输出极，其第六输出极电性连接所述第二固定电压；第七晶体管，其第七控制极电性连接所述第四晶体管的第四输出极，其第七输入极电性连接所述第二控制节点，其第七输出极电性连接所述第二固定电压；第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述第一控制节点，其第八输出极电性连接所述第二固定电压；第九晶体管，其第九控制极电性连接所述第二控制节点，其第九输入极电性连接所述输出端，其第九输出极电性连接所述第二固定电压；及第一电容，其两端电性连接所述第二控制节点和所述第二固定电压。
依据本发明的实施例，所述输入控制模块包含第十晶体管，其第十控制极和第十输入极电性连接所述前两级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一晶体管的第一控制极。
依据本发明的实施例，所述输出控制模块包含第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端。
依据本发明的实施例，所述驱动电路是反相器，其用来反相所述输出端的所述扫描信号以输出为所述驱动信号。
依据本发明的实施例，所述驱动电路是或非门电路，其电性连接所述输出端和所述第二控制节点，用来依据所述扫描信号和施加于所述第二控制节点的电压执行或非运算以输出所述驱动信号。
依据本发明的实施例，所述驱动电路包含：第十二晶体管，其第十二控制极和第十二输入极皆电性连接所述第一固定电压，其第十二输出极电性连接所述第二晶体管的所述第二控制极；及第十三晶体管，其第十三控制极电性连接所述输出端，其第十三输入极电性连接所述第二晶体管的所述第二控制极，其第十三输出极电性连接所述第二固定电压。
依据本发明的实施例，所述驱动电路另包含第十四晶体管，其第十四控制极电性连接所述第二控制节点，其第十四输入极电性连接所述第二晶体管的所述第二控制极，其第十四输出极电性连接所述第二固定电压。
依据本发明的实施例，所述栅极驱动电路另包含第二电容，其两端电性连接所述第一控制节点和所述输出端。
本发明的技术方案又提供一种液晶显示器包含源极驱动器以及如上述的栅极驱动电路，所述栅极驱动电路输出扫描信号使得数个所述晶体管开启，同时所述源极驱动器输出对应的数据信号至数个所述像素单元使其显示灰阶。
 有益效果
相较于现有技术，本发明的GOA电路单元利用锁存模块取代电容。因为锁存模块的第二晶体管在所述扫描信号没有产生脉冲时开启，使得第一晶体管和第三晶体管能将第一控制节点的电压锁存。同时因为晶体管在第一控制节点和第一固定电压之间形成直流通路，因此第一控制节点的电压不会因漏电而变化。另外，由于第二电容会耦合(couple)第一控制节点的电压，使得GOA电路单元输出的扫描信号的脉冲具有理想电平。此外，在非扫描期间，第八晶体管因第二控制节点的电压而开启，使得输出控制模块因第一控制节点的电压被下拉而关闭，因此GOA电路单元输出的扫描信号为低电平。因此本发明解决现有技术采用电容的GOA电路单元容易发生漏电的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
 附图说明
图1是本发明的液晶显示器的功能方块图。
图2是本发明第一实施例的GOA电路单元的电路图。
图3是图2所示各种输入信号、输出信号和节点电压的时序图。
图4是本发明第二实施例的GOA电路单元的电路图。
图5是本发明第三实施例的GOA电路单元的电路图。
图6是图5所示各种输入信号、输出信号和节点电压的时序图。
图7是本发明第四实施例的GOA电路单元的电路图。
 本发明的最佳实施方式
请参阅图1，图1是本发明的液晶显示器10的功能方块图。液晶显示器10包含玻璃基板14、时序控制器30以及源极驱动器(source driver)16。玻璃基板14上设置数个呈矩阵排列的像素(pixel)和栅极驱动(GOA)电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。时序控制器30用来产生时钟信号CK1-CK4以及起始信号STV1、STV2。GOA电路12每隔一固定间隔输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。以一个1024 × 768分辨率的液晶显示器10以及60Hz的更新频率为例，共需要1024 × 768 × 3个像素单元20组合而成，每一个画面的显示时间约为1/60=16.67ms。图1所示的GOA电路12 控制包含N个GOA电路单元SR(1)、…、SR(N)，N等于768。
请参阅图1和图2，图2是本发明第一实施例的GOA电路单元SR(n)的电路图。为了让液晶显示器10两边的非显示区(也就是玻璃基板14放置GOA电路12的区域)变窄，玻璃基板14的两侧都有设置GOA电路12。GOA电路12包含数个串接(cascade-connected)的GOA电路单元SR(n)。较佳地，两个GOA电路12分别包含用于产生奇数扫描信号G(1)、G(3)、…、G(767)的GOA电路单元SR(1)、SR(3)、…、SR (767)，以及用于产生偶数扫描信号G(2)、G(4)、…、G(768)的GOA电路单元SR(2)、SR(4)、…、SR (768)。当GOA电路单元SR(1)接收到启始信号STV1时，就会依据时钟信号CK1和CK2产生扫描信号G(1)。当GOA电路单元SR(2)接收到启始信号STV2时，就会依据时钟信号CK2和CK3产生扫描信号G(2)。接下来，每一级GOA电路单元SR(n)用来依据前两级GOA电路单元SR(n-2)输出的扫描信号G(n-2)、第一时钟信号CKV1、第二时钟信号CKV2，在输出端OUT输出扫描信号G(n)。第一时钟信号CKV1和第二时钟信号CKV2分别表示四个时钟信号CK1-CK4的其中两个时钟信号。四个时钟信号CK1-CK4轮流产生脉冲，且彼此产生脉冲的时间互不重叠。具体来说，GOA电路单元SR(1)、SR(5)、…、SR(N-3)是依据时钟信号CK1和CK2(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)产生扫描信号G(1)、G(5)、…、G(N-3)；GOA电路单元SR(2)、SR(6)、…、SR(N-2)是依据时钟信号CK2和CK3(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)产生扫描信号G(2)、G(6)、…、G(N-2)；GOA电路单元SR(3)、SR(7)、…、SR(N-1)是依据时钟信号CK3和CK4(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)产生扫描信号G(3)、G(7)、…、G(N-1)；GOA电路单元SR(4)、SR(8)、…、SR(N)是依据时钟信号CK4和CK1(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)产生扫描信号G(4)、G(8)、…、G(N)。
每一级GOA电路单元SR(n)包含输入控制模块100、锁存模块200、输出控制模块300、稳压模块400、上拉模块500、下拉维持模块600和驱动模块700。输入控制模块100用来于接收前两级GOA电路单元SR(n-2)输出的扫描信号G(n-2)时导通。锁存模块200电性连接输入控制模块100和第一控制节点Q(n)，用来锁存第一控制节点Q(n)的电平。输出控制模块300电性连接第一控制节点Q(n)，用来依据施加于第一控制节点Q(n)的电压，控制输出的扫描信号G(n)。稳压模块400电性连接锁存模块200，用来防止漏电。上拉模块500电性连接第二控制节点P(n)，用来于接收第二时钟信号CKV2时，使得第二控制节点P(n)处于高电平。下拉维持模块600电性连接输入控制模块100、锁存模块200、输出控制模块300、上拉模块500和稳压模块400，用来维持第二控制节点P(n)在非扫描期间的低电平，以及维持扫描信号G(n)的低电平。驱动模块700电性连接输出端OUT及第二晶体管T2，用来于输出扫描信号G(n)的脉冲时，输出驱动信号TR1以开启第二晶体管T2。
锁存模块200包含第一晶体管T1、第二晶体管T2以及第三晶体管T3。第一晶体管T1的第一控制端电性连接输入控制模块100，其第一输入端电性连接第一固定电压V1，其第一输出端电性连接第一控制节点Q(n)。第二晶体管T2的第二控制端电性连接驱动信号TR1，其第二输入端电性连接第一晶体管T1的第一输出端，其第二输出端电性连接第一控制节点Q(n)。第三晶体管T3的第三控制端和第三输出端皆电性连接第一控制节点Q(n)，其第三输入端电性连接输入控制模块100。
稳压模块400包含第四晶体管T4。第四晶体管T4的第四控制极电性连接第一固定电压V1，其第四输入极电性连接第一晶体管T1的第一控制极，其第四输出极电性连接第二控制节点P(n)。
上拉模块500包含第五晶体管T5。第五晶体管T5的第五控制极电性连接第二时钟信号CKV2，其第五输入极电性连接第一固定电压V1，其第五输出极电性连接第二控制节点P(n)。
下拉维持模块600包含第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和第一电容C1。第六晶体管T6的第六控制极电性连接第二时钟信号CKV2，其第六输入极电性连接第四晶体管T4的第四输出极，其第六输出极电性连接第二固定电压V2。第七晶体管T7的第七控制极电性连接第四晶体管T4的第四输出极，其第七输入极电性连接第二控制节点P(n)，其第七输出极电性连接第二固定电压V2。第八晶体管T8的第八控制极电性连接第二控制节点P(n)，其第八输入极电性连接第一控制节点Q(n)，其第八输出极电性连接第二固定电压V2。第九晶体管T9的第九控制极电性连接第二控制节点P(n)，其第九输入极电性连接输出端OUT，其第九输出极电性连接第二固定电压V2。第一电容C1的两端电性连接第二控制节点P(n)和第二固定电压V2。
输入控制模块100包含第十晶体管T10。第十晶体管T10的第十控制极和第十输入极电性连接前两级GOA电路单元SR(n-2)输出的扫描信号G(n-2)，其第十输出极电性连接第一晶体管T1的第一控制极。
输出控制模块300包含第十一晶体管T11。第十一晶体管T11的第十一控制极电性连接第一控制节点Q(n)，其第十一输入极电性连接第一时钟信号CKV1，其第十一输出极电性连接输出端OUT。
驱动电路700是反相器，其用来反相输出端OUT的扫描信号G(n)以输出驱动信号TR1。驱动电路700包含第十二晶体管T12和第十三晶体管T13，第十二晶体管T12的第十二控制极和第十二输入极皆电性连接第一固定电压V1，其第十二输出极电性连接第二晶体管T2的第二控制极。第十三晶体管T13的第十三控制极电性连接输出端OUT，其第十三输入极电性连接第二晶体管T2的第二控制极，其第十三输出极电性连接第二固定电压V2。
栅极驱动电路SR(n)另包含第二电容C2。第二电容C2的两端电性连接第一控制节点Q(n)和输出端OUT。
图2的GOA电路单元SR(n)的所有晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管。较佳地，所有晶体管T1-T13的控制极、输入极和输出极分别是晶体管T1-T13的栅极、漏极和源极，第一固定电压V1为高电平，第二固定电压V2为低电平。晶体管T1-T13的输入极和输出极也分别可以是晶体管的源极和漏极。
请一并参阅图3，图3是图2所示各种输入信号、输出信号和节点电压的时序图。每一GOA电路单元SR(n)输出扫描信号G(n)的期间，亦即图3所示的t3，称之为扫描期间，其余时间称为非扫描期间。非扫描期间又分为预充电期间t1-t2及等待(idle)期间t5。为便于说明，以下实施例是以采用时钟信号CK1和CK2(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)的GOA电路单元SR(n)为例。
在时段t1时，晶体管T10的第十控制极接收高电平的扫描信号G(n-2)时，晶体管T10将高电平的扫描信号G(n-2)传送至晶体管T1的第一控制极，使得晶体管T1导通。同时，晶体管T6的第六控制极因接收高电平的第一固定电压V1而导通高电平的扫描信号G(n-2)至晶体管T9的第九控制极。因此晶体管T9导通低电平的第二固定电压V2至第二控制节点P(n)。此时，晶体管T5导通低电平的第一时钟信号CKV1至输出端OUT，所以扫描信号G(n)处于低电平。因为驱动模块700会反相扫描信号G(n)以输出高电平的驱动信号TR1，所以晶体管T2会开启。晶体管T1、T2皆开启，将高电平的第一固定电压V1导通至第一控制节点Q(n)。
在时段t2时，晶体管T1和T9皆不导通，此时通过锁存模块200的晶体管T1和T3将第一控制节点Q(n)的电压锁存(hold)在高电平。因为晶体管T1、T2在第一控制节点Q(n)和高电平的第一固定电压V1之间形成直流通路，因此第一控制节点Q(n)的电压不会因漏电而降低。此时，晶体管T5导通低电平的第一时钟信号CKV1至输出端OUT，所以扫描信号G(n)处于低电平。低电平的扫描信号G(n)会输出高电平的驱动信号TR1，使得晶体管T2开启。
在时段t3时，当晶体管T5的第五控制极接收锁存在第一控制节点Q(n)的高电平电压时，将高电平的第一时钟信号CKV1导通至输出端OUT而形成扫描信号G(n)的脉冲。高电平的扫描信号G(n)会输出低电平的驱动信号TR1，使得晶体管T2关闭。因此，第二电容C2会耦合第一控制节点Q(n)的电压，使得扫描信号G(n)脉冲的电平随着第一控制节点Q(n)的电压而上升，达到理想的高电平。高电平的扫描信号G(n)会输出低电平的驱动信号TR1，使得晶体管T2关闭不导通。
在时段t4时，晶体管T5和T6因为高电平的第二时钟信号CKV2而开启，高电平的第一固定电压V1会传送至第二控制节点P(n)。第八晶体管T8的第八控制极和晶体管T9的第九控制极因第二控制节点P(n)处于高电平而开启，使得第一控制节点Q(n)和输出端OUT皆下拉为稳定的低电平。此时扫描信号G(n)处于低电平。低电平的扫描信号G(n)会输出高电平的驱动信号TR1，使得晶体管T2开启。
请参阅图4，图4是本发明第二实施例的GOA电路单元SR(n)的电路图。不同于图2，图4的GOA电路单元SR(n)的所有晶体管皆为P型金氧半导体(P-type metal oxide semiconductor，PMOS)晶体管，第一固定电压V2为低电平，第二固定电压V1为高电平。除了组件的连接与运作模式皆与图5相同之外，用来驱动PMOS晶体管的信号和PMOS晶体管输出信号的电平正好相反于NMOS晶体管，此为本领域技术人员所熟知的，在此不另赘述。此外，本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元。
相较于现有技术，本发明的GOA电路单元SR(n)利用锁存模块200取代电容。因为锁存模块200的第二晶体管T2在扫描信号G(n)没有产生脉冲时开启，使得第一晶体管T1和第三晶体管T3能将第一控制节点Q(n)的电压锁存。同时因为晶体管T1、T2在第一控制节点Q(n)和第一固定电压V1之间形成直流通路，因此第一控制节点Q(n)的电压不会因漏电而变化。另外，由于第二电容C2会耦合第一控制节点Q(n)的电压，使得输出的扫描信号G(n)的脉冲具有理想电平。因此本发明解决现有技术采用电容的GOA电路单元容易发生漏电的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
请参阅图5，图5是本发明第三实施例的GOA电路单元SR(n)的电路图。图2所示的GOA电路单元SR(n)与图5所示的GOA电路单元SR(n)具有相同编号的组件，其功能与运作是相同的，在此不另赘述。不同于图2的GOA电路单元SR(n)，本实施例GOA电路单元SR(n)的第二晶体管T2的第二控制端电性连接驱动信号TR2，且驱动模块800是或非门(NOR gate)电路，其用来依据扫描信号G(n)和施加于第二控制节点P(n)的电压执行或非运算(NOR operation)以输出驱动信号TR2。驱动电路800包含第十二晶体管T12、第十三晶体管T13和第十四晶体管T14。第十二晶体管T12的第十二控制极和第十二输入极皆电性连接第一固定电压V1，其第十二输出极电性连接第二晶体管T2的第二控制极。第十三晶体管T13的第十三控制极电性连接输出端OUT，其第十三输入极电性连接第二晶体管T2的第二控制极，其第十三输出极电性连接第二固定电压V2。第十四晶体管T14的第十四控制极电性连接第二控制节点P(n)，其第十四输入极电性连接第二晶体管T2的第二控制极，其第十四输出极电性连接第二固定电压V2。
图5的GOA电路单元SR(n)的所有晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管。较佳地，所有晶体管T1-T14的控制极、输入极和输出极分别是晶体管T1-T14的栅极、漏极和源极，第一固定电压V1为高电平，第二固定电压V2为低电平。晶体管T1-T14的输入极和输出极也分别可以是晶体管的源极和漏极。
请一并参阅图6，图6是图5所示各种输入信号、输出信号和节点电压的时序图。每一GOA电路单元SR(n)输出扫描信号G(n)的期间，亦即图6所示的t3，称之为扫描期间，其余时间称为非扫描期间。非扫描期间又分为预充电期间t1-t2及等待(idle)期间t5。为便于说明，以下实施例是以采用时钟信号CK1和CK2(分别表示图2的第一时钟信号CKV1和第二时钟信号CKV2)的GOA电路单元SR(n)为例。
在时段t1时，晶体管T10的第十控制极接收高电平的扫描信号G(n-2)时，晶体管T10将高电平的扫描信号G(n-2)传送至晶体管T1的第一控制极，使得晶体管T1导通。同时，晶体管T6的第六控制极因接收高电平的第一固定电压V1而导通高电平的扫描信号G(n-2)至晶体管T9的第九控制极。因此晶体管T9导通低电平的第二固定电压V2至第二控制节点P(n)。此时，晶体管T5导通低电平的第一时钟信号CKV1至输出端OUT，所以扫描信号G(n)处于低电平。因为扫描信号G(n) 为低电平且施加于第二控制节点P(n)的电压亦处于低电平，因此驱动模块800会执行或非运算而输出高电平的驱动信号TR2，所以晶体管T2会开启。此时，晶体管T1、T2皆开启，将高电平的第一固定电压V1导通至第一控制节点Q(n)。
在时段t2时，晶体管T1和T9皆不导通，此时通过锁存模块200的晶体管T1和T3将第一控制节点Q(n)的电压锁存(hold)在高电平。因为晶体管T1、T2在第一控制节点Q(n)和高电平的第一固定电压V1之间形成直流通路，因此第一控制节点Q(n)的电压不会因漏电而降低。此时，晶体管T5导通低电平的第一时钟信号CKV1至输出端OUT，所以扫描信号G(n)处于低电平。因为扫描信号G(n) 为低电平且施加于第二控制节点P(n)的电压亦处于低电平，因此驱动模块800会执行或非运算而输出高电平的驱动信号TR2，所以晶体管T2会开启。
在时段t3时，当晶体管T5的第五控制极接收锁存在第一控制节点Q(n)的高电平电压时，将高电平的第一时钟信号CKV1导通至输出端OUT而形成扫描信号G(n)的脉冲。高电平的扫描信号G(n)会输出低电平的驱动信号TR2，使得晶体管T2关闭。因此，第二电容C2会耦合第一控制节点Q(n)的电压，使得扫描信号G(n)脉冲的电平随着第一控制节点Q(n)的电压而上升，达到理想的高电平。因为扫描信号G(n) 为高电平且施加于第二控制节点P(n)的电压处于低电平，因此驱动模块800会执行或非运算而输出低电平的驱动信号TR2，所以晶体管T2会关闭而不导通。
在时段t4时，晶体管T5和T6因为高电平的第二时钟信号CKV2而开启，高电平的第一固定电压V1会传送至第二控制节点P(n)。第八晶体管T8的第八控制极和晶体管T9的第九控制极因第二控制节点P(n)处于高电平而开启，使得第一控制节点Q(n)和输出端OUT皆下拉为稳定的低电平。
在t4-t5期间，因为扫描信号G(n) 为低电平且施加于第二控制节点P(n)的电压处于高电平，因此驱动模块800会执行或非运算而输出低电平的驱动信号TR2，所以晶体管T2会关闭而不导通。
在非扫描期间t1-t2和t4-t5，第八晶体管T8和第九晶体管T9因第二控制节点P(n)的电压而开启，使得输出控制模块300因第一控制节点Q(n)的电压被下拉为低电平的第二固定电压V2而关闭。同时第九晶体管T9开启而导通低电平的第二固定电压V2至输出端OUT，因此扫描信号G(n)会是稳定的低电平。
请参阅图7，图7是本发明第四实施例的GOA电路单元SR(n)的电路图。不同于图5，图7的GOA电路单元SR(n)的所有晶体管皆为P型金氧半导体(P-type metal oxide semiconductor，PMOS)晶体管，第一固定电压V2为低电平，第二固定电压V1为高电平。除了组件的连接与运作模式皆与图5相同之外，用来驱动PMOS晶体管的信号和PMOS晶体管输出信号的电平正好相反于NMOS晶体管，此为本领域技术人员所熟知的，在此不另赘述。此外，本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元。
相较于现有技术，本发明的GOA电路单元SR(n)利用锁存模块200取代电容。因为锁存模块200的第二晶体管T2在扫描信号G(n)没有产生脉冲时开启，使得第一晶体管T1和第三晶体管T3能将第一控制节点Q(n)的电压锁存。同时因为晶体管T1、T2在第一控制节点Q(n)和第一固定电压V1之间形成直流通路，因此第一控制节点Q(n)的电压不会因漏电而变化。另外，由于第二电容C2会耦合第一控制节点Q(n)的电压，使得输出的扫描信号G(n)的脉冲具有理想电平。此外，在非扫描期间，第八晶体管T8因第二控制节点P(n)的电压而开启，使得输出控制模块300因第一控制节点Q(n)的电压被下拉而关闭，因此扫描信号G(n)为低电平。因此本发明解决现有技术采用电容的GOA电路单元容易发生漏电的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前两级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来于接收所述前两级GOA电路单元输出的扫描信号时导通；
    锁存模块，电性连接所述输入控制模块和第一控制节点，用来锁存所述第一控制节点的电平，其包含：
    第一晶体管，其第一控制端电性连接所述输入控制模块，其第一输入端电性连接第一固定电压，其第一输出端电性连接所述第一控制节点；
    第二晶体管，其第二控制端电性连接驱动信号，其第二输入端电性连接所述第一晶体管的第一输出端，其第二输出端电性连接所述第一控制节点；以及
    第三晶体管，其第三控制端和第三输出端皆电性连接所述第一控制节点，其第三输入端电性连接所述输入控制模块；
    输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；
    稳压模块，电性连接所述锁存模块，用来防止漏电；
    上拉模块，电性连接第二控制节点，用来于接收所述第二时钟信号时，使得所述第二控制节点处于高电平；
    下拉维持模块，电性连接所述输入控制模块、所述锁存模块、所述输出控制模块、所述上拉模块和所述稳压模块，用来维持所述第二控制节点在非扫描期间的低电平，以及维持所述扫描信号的低电平；及
    驱动模块，电性连接所述输出端及所述第二晶体管，用来于输出所述扫描信号的脉冲时，输出所述驱动信号以开启所述第二晶体管。
  2. 如权利要求1所述的栅极驱动电路，其中所述稳压模块包含第四晶体管，其第四控制极电性连接所述第一固定电压，其第四输入极电性连接所述第一晶体管的第一控制极，其第四输出极电性连接所述第二控制节点。
  3. 如权利要求2所述的栅极驱动电路，其中所述上拉模块包含第五晶体管，其第五控制极电性连接所述第二时钟信号，其第五输入极电性连接所述第一固定电压，其第五输出极电性连接所述第二控制节点。
  4. 如权利要求3所述的栅极驱动电路，其中所述下拉维持模块包含：
    第六晶体管，其第六控制极电性连接所述第二时钟信号，其第六输入极电性连接所述第四晶体管的第四输出极，其第六输出极电性连接所述第二固定电压；
    第七晶体管，其第七控制极电性连接所述第四晶体管的第四输出极，其第七输入极电性连接所述第二控制节点，其第七输出极电性连接所述第二固定电压；
    第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述第一控制节点，其第八输出极电性连接所述第二固定电压；
    第九晶体管，其第九控制极电性连接所述第二控制节点，其第九输入极电性连接所述输出端，其第九输出极电性连接所述第二固定电压；及
    第一电容，其两端电性连接所述第二控制节点和所述第二固定电压。
  5. 如权利要求1所述的栅极驱动电路，其中所述输入控制模块包含第十晶体管，其第十控制极和第十输入极电性连接所述前两级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一晶体管的第一控制极。
  6. 如权利要求1所述的栅极驱动电路，其中所述输出控制模块包含第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端。
  7. 如权利要求1所述的栅极驱动电路，其中所述驱动电路是反相器，其用来反相所述输出端的所述扫描信号以输出为所述驱动信号。
  8. 如权利要求1所述的栅极驱动电路，其中所述驱动电路是或非门电路，其电性连接所述输出端和所述第二控制节点，用来依据所述扫描信号和施加于所述第二控制节点的电压执行或非运算以输出所述驱动信号。
  9. 如权利要求1所述的栅极驱动电路，其中所述驱动电路包含：
    第十二晶体管，其第十二控制极和第十二输入极皆电性连接所述第一固定电压，其第十二输出极电性连接所述第二晶体管的所述第二控制极；及
    第十三晶体管，其第十三控制极电性连接所述输出端，其第十三输入极电性连接所述第二晶体管的所述第二控制极，其第十三输出极电性连接所述第二固定电压。
  10. 如权利要求9所述的栅极驱动电路，其中所述驱动电路另包含：
    第十四晶体管，其第十四控制极电性连接所述第二控制节点，其第十四输入极电性连接所述第二晶体管的所述第二控制极，其第十四输出极电性连接所述第二固定电压。
  11. 如权利要求1所述的栅极驱动电路，其另包含：第二电容，其两端电性连接所述第一控制节点和所述输出端。
  12. 一种显示器，其包含源极驱动器以及权利要求1所述的栅极驱动电路，所述源极驱动器用来输出数据信号至数个像素单元使其显示灰阶。
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