WO2017107301A1 - 一种比较器及低功耗振荡器 - Google Patents

一种比较器及低功耗振荡器 Download PDF

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Publication number
WO2017107301A1
WO2017107301A1 PCT/CN2016/074303 CN2016074303W WO2017107301A1 WO 2017107301 A1 WO2017107301 A1 WO 2017107301A1 CN 2016074303 W CN2016074303 W CN 2016074303W WO 2017107301 A1 WO2017107301 A1 WO 2017107301A1
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Prior art keywords
mos transistor
module
input terminal
gate
comparator
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PCT/CN2016/074303
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English (en)
French (fr)
Inventor
左事君
杨智昌
杨孝骏
Original Assignee
深圳创维－Rgb电子有限公司
深圳创维半导体设计中心有限公司
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Application filed by 深圳创维－Rgb电子有限公司, 深圳创维半导体设计中心有限公司 filed Critical 深圳创维－Rgb电子有限公司
Priority to US15/507,573 priority Critical patent/US10141922B2/en
Priority to AU2016304614A priority patent/AU2016304614B2/en
Publication of WO2017107301A1 publication Critical patent/WO2017107301A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
    • H03K5/088—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Definitions

  • the present invention relates to the field of oscillator technologies, and in particular, to a comparator and a low power oscillator.
  • the oscillator circuit is an indispensable module in any electronic system. As the cost pressure continues to increase, the chip area needs to be continuously reduced. Under the premise of ensuring the function, it is necessary to design a simpler circuit structure, which can reduce the module area and reduce power consumption.
  • a conventional oscillator generally requires two comparators, a capacitor, a bias circuit for charging and discharging the capacitor, and a high threshold and a low threshold for the two comparators respectively.
  • a comparator Flip control the bias circuit discharge, the capacitor voltage drops, when the capacitor voltage is lower than the low threshold, the other comparator flips, controls the bias circuit to charge, the voltage rises, and so on, and outputs an oscillating signal.
  • the structure of this oscillator is simple, but the comparator in the oscillator has a single function, the oscillator structure is complex, and the power consumption is high.
  • a comparator includes a current mirror module, a comparison module, and a buffer output module.
  • the current mirror module provides a bias current for the comparison module
  • the comparison module includes a positive input terminal, a first negative input terminal, and a second negative input terminal.
  • the positive input terminal is connected to the external terminal, and the first negative input terminal and the second negative input terminal respectively input a low threshold voltage and a high threshold voltage, and the comparison module compares the voltage of the positive input terminal with the low threshold voltage and the high threshold voltage.
  • the buffer output module On outputting the comparison result to the buffer output module, when the voltage of the positive input terminal is less than the low threshold voltage, the buffer output module outputs a low level to the comparison module; when the voltage of the positive input terminal is greater than the high threshold voltage, the buffer output module outputs a high level To the comparison module.
  • the comparison module includes a first comparison unit, a second comparison unit, and an amplification unit, and the comparison result is output by the second comparison unit to the amplification unit, and the first comparison unit includes the first negative
  • the second comparison unit includes the positive input terminal and the second negative input terminal, and the amplification result is amplified by the amplification unit and output to the buffer output module, when the voltage of the positive input terminal is lower than the low threshold voltage of the first negative input terminal.
  • the buffer output module outputs a low level to the first comparison unit, the first comparison unit is controlled to be turned off; when the voltage of the positive input terminal is greater than the high threshold voltage of the second negative input terminal, the buffer output module outputs a high level to the first comparison.
  • a unit that controls the first comparison unit to be turned on the low threshold voltage being less than the high threshold voltage.
  • the current mirror module includes a first MOS transistor and a second MOS transistor; a source of the first MOS transistor and a source of the second MOS transistor are connected to a VCC power supply end, and the first MOS transistor The gate is connected to the drain of the first MOS transistor, the gate of the second MOS transistor, and the first bias terminal, and the drain of the second MOS transistor is connected to the comparison module.
  • the first comparison unit includes a third MOS transistor and a first switching transistor
  • the second comparison unit includes a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor
  • the amplifying unit includes an eighth MOS transistor and a ninth MOS transistor; a source of the third MOS transistor, a source of the fourth MOS transistor, and a source of the sixth MOS transistor are connected to a drain of the second MOS transistor, a gate of the third MOS transistor is a first negative input terminal of the comparator, a drain of the third MOS transistor is connected to a drain of the first switch transistor, and a gate of the first switch transistor is connected to a buffer output module, a gate of the fourth MOS transistor is a second negative input terminal of the comparator, and a drain of the fourth MOS transistor is connected to a source of the first switch transistor, a drain of the fifth MOS transistor, and a gate of the fifth MOS transistor.
  • a gate of the fifth MOS transistor is connected to a gate of the seventh MOS transistor
  • a gate of the sixth MOS transistor is a positive input terminal of the comparator
  • a drain of the sixth MOS transistor is connected to a gate of the ninth MOS transistor a drain of the seventh MOS transistor
  • a gate of the eighth MOS transistor is connected to a gate of the second MOS transistor
  • a source of the eighth MOS transistor is connected to a VCC power supply terminal
  • a drain of the eighth MOS transistor is connected to a drain Drain and buffered output modules MOS transistor, the source electrode of the fifth MOS transistor, the source of the source of the seventh MOS transistor and a ninth MOS transistor is grounded.
  • a low power oscillator comprising a capacitor and a current biasing module, the low power oscillator further comprising a switching module and a comparator as described above, the capacitor being coupled to the positive input of the comparator, when the capacitor When the voltage is less than the low threshold voltage of the first negative input terminal of the comparator, the comparator outputs a low level to the switch module, and the switch module controls the current bias module to charge the capacitor; when the capacitor voltage is greater than the second negative input of the comparator When the terminal has a high threshold voltage, the comparator outputs a high level to the switch module, and the switch module controls the current bias module to discharge the capacitor, and the low threshold voltage is less than the high threshold voltage.
  • the current biasing module includes a first current mirror unit and a second current mirror unit.
  • the comparator When the capacitor voltage is less than a low threshold voltage, the comparator outputs a low level to the switch module.
  • the first current mirror unit is controlled by the switch module to charge the capacitor; when the capacitor voltage is greater than the high threshold voltage, the comparator outputs a high level to the switch module, and the switch module controls the second current mirror unit to discharge the capacitor.
  • the switch module includes a first switch unit and a second open unit.
  • the comparator When the capacitor voltage is less than a low threshold voltage, the comparator outputs a low level to the switch module, and the first switch unit When the second switch unit is turned off, the first current mirror unit charges the capacitor; when the capacitor voltage is greater than the high threshold voltage, the comparator outputs a high level to the switch module, the first switch unit is turned off, and the second switch The unit is turned on to cause the second current mirror unit to discharge the capacitor.
  • the first switching unit includes a second switching tube
  • the second switching unit includes a third switching tube
  • the source of the second switching tube is connected to the first current mirror unit
  • the drain of the second switch tube is connected to the drain of the third switch tube, and is also connected to the positive input end of the comparator and one end of the capacitor
  • the gate of the second switch tube is connected to the gate of the third switch tube and the comparator
  • the output end of the third switch tube is connected to the second current mirror unit.
  • the first current mirror unit includes a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, and a thirteenth MOS transistor; and a source of the tenth MOS transistor And a source of the twelfth MOS transistor is connected to the VCC power supply end, and a gate of the tenth MOS transistor is connected to a gate of the twelfth MOS transistor, a drain of the tenth MOS transistor, and a source of the eleventh MOS transistor, a gate of the eleventh MOS transistor is connected to a gate of the thirteenth MOS transistor, a drain of the eleventh MOS transistor, and a second current mirror unit, and a drain of the twelfth MOS transistor is connected to the thirteenth MOS
  • the source of the tube, the drain of the thirteenth MOS transistor is connected to the source of the second switching transistor.
  • the second current mirror unit includes a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, and a tenth a MOS transistor; a drain of the fourteenth MOS transistor is connected to the second bias terminal, and is further connected to a gate of the fourteenth MOS transistor, and a gate of the fourteenth MOS transistor is further connected to the sixteenth MOS transistor a gate and a gate of the eighteenth MOS transistor, a source of the fourteenth MOS transistor is connected to a drain of the fifteenth MOS transistor and a gate of the fifteenth MOS transistor, and a gate of the fifteenth MOS transistor
  • the pole is further connected to the gate of the seventeenth MOS transistor and the gate of the nineteenth MOS transistor, and the drain of the sixteenth MOS transistor is connected to the drain of the eleventh MOS transistor, the gate of the eleventh MOS transistor, and a gate of the thirteenth MOS transistor
  • the comparator includes a current mirror module, a comparison module and a buffer output module
  • the low power oscillator includes a capacitor and a current bias.
  • the comparison module includes a positive input terminal, a first negative input terminal and a second negative input terminal, the capacitor being connected to the positive input terminal of the comparator, when the capacitor voltage is less than the first negative of the comparator
  • the comparator outputs a low level to the switch module
  • the switch module controls the current bias module to charge the capacitor
  • the comparator outputs a high level to the switch module, and the switch module controls the current biasing module to discharge the capacitor, thereby realizing periodic charging and discharging of the capacitor through a comparator, and outputting an oscillating signal, thereby reducing the number of comparators.
  • FIG. 1 is a structural block diagram of a comparator provided by the present invention.
  • FIG. 2 is a circuit schematic diagram of a comparator provided by the present invention.
  • FIG. 3 is a structural block diagram of a low power oscillator provided by the present invention.
  • FIG. 4 is a circuit schematic diagram of a low power oscillator provided by the present invention.
  • the object of the present invention is to provide a comparator and a low power oscillator, which can realize the functions of the two conventional comparators through a comparator, simplifying
  • the circuit structure reduces circuit power consumption and product cost.
  • the comparator provided by the present invention includes a current mirror module 10 , a comparison module 20 , and a buffer output module 30 .
  • the current mirror module 10 , the comparison module 20 and the buffer output module 30 are sequentially connected, in particular, the comparison.
  • the device is provided with a positive input terminal P, a first negative input terminal N1 and a second negative input terminal N2.
  • the positive input terminal P is connected to an external voltage, and the first negative input terminal N1 and the second negative input terminal N2 are respectively input low.
  • the threshold voltage and the high threshold voltage are supplied by the current mirror module 10 to the comparison module 20, and the comparison module 20 compares the voltage of the positive input terminal P with the low threshold voltage of the first negative input terminal N1 and the second negative input terminal N2.
  • the high threshold voltage is compared, and the comparison result is output to the buffer output module 30.
  • the buffer output module 30 When the voltage of the positive input terminal P is lower than the low threshold voltage of the first negative input terminal N1, the buffer output module 30 outputs a low level to the comparison module 20;
  • the buffer output module 30 When the voltage of the positive input terminal P is greater than the high threshold voltage of the second negative input terminal N2, the buffer output module 30 outputs a high level to the comparison module 20, thereby realizing the voltage of the positive input terminal and the voltage of the first negative input terminal N1 at the same time.
  • the voltage of the two negative input terminals N2 is compared and the comparison result is output, which enriches the function of the comparator and simplifies the circuit structure.
  • the comparison module 20 includes a first comparison unit 201, a second comparison unit 202, and an amplification unit 203
  • the first comparison unit 201 includes the first negative input terminal N1
  • the second comparison unit 202 includes The positive input terminal P and the second negative input terminal N2
  • the first comparison unit 201, the second comparison unit 202, and the amplification unit 203 are all connected to the current mirror module 10
  • the buffer output module 30 is connected to the first comparison unit 201.
  • the amplifying unit 203, the second comparing unit 202 outputs the comparison result to the amplifying unit 203
  • the amplifying unit 203 amplifies the comparison result and outputs the result to the buffer output module 30.
  • the buffer output module 30 When the voltage of the positive input terminal P is smaller than the first negative input terminal N1 When the threshold voltage is low, the buffer output module 30 outputs a low level to the first comparison unit 201, and controls the first comparison unit 201 to be turned off; when the voltage of the positive input terminal P is greater than the high threshold voltage of the second negative input terminal N2, The buffer output module 30 outputs a high level to the first comparison unit 201, controls the first comparison unit 201 to be turned on, and the low threshold voltage is less than the high threshold voltage.
  • the present invention sets the first comparison unit 201 and the second comparison unit 202 in the comparison module 20, the first comparison unit 201 is connected to the first negative input terminal N1 of the comparator, and the second comparison unit 202 is connected to the positive input of the comparator.
  • the terminal P and the second negative input terminal N2 when the voltage of the positive input terminal P is lower than the low threshold voltage of the first negative input terminal N1, the second comparison unit 202 outputs the comparison result to the amplification unit 203, and the buffer output module 30 outputs low.
  • the buffer output module 30 When the voltage of the positive input terminal P is greater than the high threshold voltage of the second negative input terminal N2, the buffer output module 30 outputs a high level to the first comparison unit 201, and controls the first comparison unit 201 to be turned on, and the first negative input terminal N1 is restarted.
  • the buffer output module 30 When the voltage of the positive input terminal P is less than the low threshold voltage of the first negative input terminal N1, the buffer output module 30 outputs a low level to the first comparison unit 201, and controls the first comparison unit to turn off again 201. , so cycle Complex, thereby achieving simultaneous comparison of the voltage of the positive input terminal P with the low threshold voltage of the first negative input terminal N1 and the high threshold voltage of the second negative input terminal N2, and replacing the conventional two comparators with one comparator, simplifying The circuit structure.
  • the current mirror module 10 includes a first MOS transistor Q1 and a second MOS transistor Q2; the source of the first MOS transistor Q1 and the source of the second MOS transistor Q2 are connected to VCC.
  • the gate of the first MOS transistor Q1 is connected to the drain of the first MOS transistor Q1, the gate of the second MOS transistor Q2, and the first bias terminal BIAS1, and the drain of the second MOS transistor Q2 is connected to the comparison module. 20, wherein the first MOS transistor Q1 and the second MOS transistor Q2 are PMOS transistors, and provide a bias current for the comparison module 20.
  • the first comparison unit 201 includes a third MOS transistor Q3 and a first switching transistor Q21
  • the second comparison unit 202 includes a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, and a seventh MOS transistor.
  • the amplifying unit 203 includes an eighth MOS transistor Q8 and a ninth MOS transistor Q9.
  • the first switching transistor Q21 is an NMOS transistor, and is turned on when its gate is at a high level, and when its gate is at a low level. cutoff.
  • the source of the third MOS transistor Q3, the source of the fourth MOS transistor Q4, and the source of the sixth MOS transistor Q6 are connected to the drain of the second MOS transistor Q2, and the gate of the third MOS transistor Q3 is a comparator.
  • the first negative input terminal N1, the drain of the third MOS transistor Q3 is connected to the drain of the first switching transistor Q21, the gate of the first switching transistor Q21 is connected to the buffer output module 30, and the fourth MOS transistor Q4
  • the gate is a second negative input terminal N2 of the comparator, and the drain of the fourth MOS transistor Q4 is connected to the source of the first switching transistor Q21, the drain of the fifth MOS transistor Q5, and the gate of the fifth MOS transistor Q5.
  • the gate of the fifth MOS transistor Q5 is connected to the gate of the seventh MOS transistor Q7
  • the gate of the sixth MOS transistor Q6 is the positive input terminal P of the comparator
  • the drain of the sixth MOS transistor Q6 is connected to the ninth MOS.
  • a gate of the eighth MOS transistor Q8 is connected to a gate of the second MOS transistor Q2
  • a source of the eighth MOS transistor Q8 is connected to a VCC power supply terminal
  • an eighth The drain of the MOS transistor Q8 is connected to the drain of the ninth MOS transistor Q9 and the buffer output module 30.
  • the source of the fifth MOS transistor Q5, the source of the seventh MOS transistor Q7, and the source of the ninth MOS transistor Q9 are grounded.
  • the third MOS transistor Q3, the fourth MO The S tube Q4, the sixth MOS tube Q6, and the eighth MOS tube Q8 are PMOS tubes
  • the fifth MOS tube Q5, the seventh MOS tube Q7, and the ninth MOS tube Q9 are NMOS tubes.
  • the comparator provided by the present invention provides a bias current by the current mirror formed by the first MOS transistor Q1 and the second MOS transistor Q2, and is composed of a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, and a seventh MOS transistor Q7.
  • a classical differential circuit on the basis of which a third MOS transistor Q3 and a first switching transistor Q21 are added, wherein the third MOS transistor Q3 is identical in size to the fourth MOS transistor Q4 and the sixth MOS transistor Q6, thereby being compatible with the prior art.
  • the comparator provided by the invention adds a negative input terminal, and realizes accurate comparison between the voltage of the positive input terminal and the voltage of the two negative input terminals, and further, the eighth MOS transistor Q8 and the ninth MOS
  • the tube Q9 constitutes the second stage of the comparator, and the gain of the comparison result can be amplified to further ensure the accuracy of the comparison result.
  • the buffer output module 30 includes a first inverter I1 and a second inverter I2.
  • the input end of the first inverter I1 is connected to the drain and the ninth of the eighth MOS transistor Q8.
  • the drain of the MOS transistor Q9, the output end of the first inverter I1 is connected to the input end of the second inverter I2, and the output end of the second inverter I2 is connected to the gate of the first switching transistor Q21, by the first counter
  • the phaser I1 and the second inverter I2 form a buffer stage.
  • the present invention also provides a low power consumption oscillator, as shown in FIGS. 3 and 4, the low power oscillator including a capacitor C1, a current biasing module 40, a switch module 50, and a comparator 60 as described above.
  • the capacitor C1 is connected to the current biasing module 40 and the positive input terminal P of the comparator 60.
  • the current biasing module 40 is connected to the switch module 50.
  • the switch module 50 is also connected to the comparator 60.
  • the comparator 60 When the voltage of the capacitor C1 is less than the comparison When the first negative input terminal N1 of the device 60 has a low threshold voltage VL, the comparator 60 outputs a low level to the switch module 50, and the switch module 50 controls the current bias module 40 to charge the capacitor C1; when the capacitor C1 voltage is greater than When the high negative threshold voltage VH of the second negative input terminal N2 of the comparator 60, the comparator 60 outputs a high level to the switch module 50, and the current biasing module 40 is controlled by the switch module 50 to discharge the capacitor C1, the low threshold The voltage is less than the high threshold voltage.
  • the low power consumption oscillator provided by the present invention provides a positive input P input of the comparator 60 by providing a capacitor C1, a current biasing module 40, a switch module 50, and a comparator 60 having two negative inputs as described above.
  • the capacitor C1 voltage, the first negative input terminal N1 inputs a low threshold voltage VL, the second negative input terminal N2 inputs a high threshold voltage VH, and when the capacitor C1 voltage is less than the low threshold voltage VL, the comparator 60 outputs a low level to the switch module 50.
  • the current biasing module 40 is controlled by the switch module 50 to charge the capacitor C1, and the voltage of the capacitor C1 rises.
  • the comparator 60 When the voltage of the capacitor C1 is greater than the high threshold voltage VH, the comparator 60 outputs a high level to the switch module 50, and the current is controlled by the switch module 50.
  • the bias module 40 discharges the capacitor C1, and the voltage of the capacitor C1 decreases until the voltage of the capacitor C1 is lower than the low threshold voltage VL, the comparator 60 outputs a low level again, and the current biasing module 40 is controlled by the switch module 50 to charge the capacitor C1. Cycling back and forth, periodically charging and discharging the capacitor C1, causing the voltage of the capacitor C1 to oscillate between the low threshold voltage VL and the high threshold voltage VH, generating an oscillating signal, thereby realizing through a comparator The oscillator works properly, reducing circuit power consumption.
  • the current biasing module 40 includes a first current mirror unit 401 and a second current mirror unit 402.
  • the comparator 60 When the voltage of the capacitor C1 is less than the low threshold voltage VL, the comparator 60 outputs a low level to the switch module 50.
  • the first current mirror unit 401 is controlled by the switch module 50 to charge the capacitor C1; when the capacitor C1 voltage is greater than the high threshold voltage VH, the comparator 60 outputs a high level to the switch module 50, and the switch module 50 controls the second current mirror.
  • the unit 402 discharges the capacitor C1, and controls the first current mirror unit 401 and the second current mirror unit 402 to charge and discharge the capacitor C1 through the switch module 50, respectively, so that the capacitor C1 voltage is between the low threshold voltage VL and the high threshold voltage VH. Oscillate to generate an oscillating signal.
  • the switch module 50 includes a first switch unit 501 and a second open unit 502.
  • the comparator 60 When the voltage of the capacitor C1 is less than the low threshold voltage VL, the comparator 60 outputs a low level to the switch module 50, the first switch unit. 501 is turned on, the second switching unit 502 is turned off, so that the first current mirror unit 401 charges the capacitor C1; when the capacitor C1 voltage is greater than the high threshold voltage VH, the comparator 60 outputs a high level to the switch module 50, first The switch unit 501 is turned off, the second switch unit 502 is turned on, the second current mirror unit 402 is discharged to the capacitor C1, and the comparator 60 outputs a high level and a low level according to the comparison result, thereby controlling the first switch unit 501 and the second switch unit 502.
  • the first switching unit 501 includes a second switching transistor Q22
  • the second switching unit 502 includes a third switching transistor Q23.
  • the second switching transistor Q22 is a PMOS transistor. When it is at a high level, it is turned off, and when its gate is at a low level, it is turned on; wherein the third switch tube Q23 is an NMOS transistor, when its gate is at a high level, it is turned on, and when its gate is at a low level, it is turned off.
  • the source of the second switching transistor Q22 is connected to the first current mirror unit 401.
  • the drain of the second switching transistor Q22 is connected to the drain of the third switching transistor Q23, and is also connected to the positive input terminal of the comparator 60 and one end of the capacitor C1.
  • the gate of the second switching transistor Q22 is connected to the gate of the third switching transistor Q23 and the output of the comparator 60.
  • the source of the third switching transistor Q23 is connected to the second current mirror unit 402.
  • the first current mirror unit 401 includes a tenth MOS transistor Q10, an eleventh MOS transistor Q11, a twelfth MOS transistor Q12, and a thirteenth MOS transistor Q13; the source of the tenth MOS transistor Q10 and the twelfth The source of the MOS transistor Q12 is connected to the VCC power supply terminal, and the gate of the tenth MOS transistor Q10 is connected to the gate of the twelfth MOS transistor Q12, the drain of the tenth MOS transistor Q10, and the source of the eleventh MOS transistor Q11.
  • the gate of the eleventh MOS transistor Q11 is connected to the gate of the thirteenth MOS transistor Q13, the drain of the eleventh MOS transistor Q11, and the second current mirror unit 402, and the drain of the twelfth MOS transistor Q12
  • the pole is connected to the source of the thirteenth MOS transistor Q13
  • the drain of the thirteenth MOS transistor Q13 is connected to the source of the second switching transistor Q22, wherein the tenth MOS transistor Q10, the eleventh MOS transistor Q11, and the tenth
  • the second MOS transistor Q12 and the thirteenth MOS transistor Q13 are both PMOS transistors, and the twelfth MOS transistor Q12 and the thirteenth MOS transistor Q13 provide a charging current for the capacitor C1.
  • the second current mirror unit 402 includes a fourteenth MOS transistor Q14, a fifteenth MOS transistor Q15, a sixteenth MOS transistor Q16, a seventeenth MOS transistor Q17, an eighteenth MOS transistor Q18, and a nineteenth MOS transistor Q19;
  • the drain of the fourteenth MOS transistor Q14 is connected to the second bias terminal BIAS2, and is also connected to the gate of the fourteenth MOS transistor Q14, and the gate of the fourteenth MOS transistor Q14 is also connected to the tenth
  • the gate of the MOS transistor Q16 and the gate of the eighteenth MOS transistor Q18, the source of the fourteenth MOS transistor Q14 is connected to the drain of the fifteenth MOS transistor Q15 and the gate of the fifteenth MOS transistor Q15.
  • the gate of the fifteenth MOS transistor Q15 is further connected to the gate of the seventeenth MOS transistor Q17 and the gate of the nineteenth MOS transistor Q19, and the drain of the sixteenth MOS transistor Q16 is connected to the eleventh MOS transistor.
  • a drain of Q11, a gate of the eleventh MOS transistor Q11, and a gate of the thirteenth MOS transistor Q13, and a source of the sixteenth MOS transistor Q16 is connected to a drain of the seventeenth MOS transistor Q17, the first
  • the drain of the eighteen MOS transistor Q18 is connected to the source of the third switching transistor Q23, the source of the eighteenth MOS transistor Q18 is connected to the drain of the nineteenth MOS transistor Q19, and the source of the fifteenth MOS transistor Q15
  • the source of 9 is connected to the other end of the capacitor C1 and the ground, wherein the fourteenth MOS transistor Q14, the fifteenth MOS transistor
  • the positive input terminal P of the comparator 60 inputs the voltage of the capacitor C1, the first negative input terminal N1 inputs a low threshold voltage VL, and the second negative input terminal N2 inputs a high threshold voltage VH.
  • the voltage of the capacitor C1 input from the positive input terminal P is zero, and the buffer output module 30 of the comparator 60 outputs a low level to the first switching transistor Q21, at which time the first switching transistor Q21 is turned off, and the third MOS transistor Q3 is turned off.
  • Inactive that is, the first negative input terminal N1 is not connected to the circuit, and the comparator 60 outputs a low level to the switch module 50.
  • the second switch transistor Q22 is turned on, and the third switch transistor Q23 is turned off.
  • the twelve MOS transistor Q12 and the thirteenth MOS transistor Q13 charge the capacitor C1, and the voltage of the capacitor C1 rises.
  • the buffer output module 30 of the comparator 60 When the voltage of the capacitor C1 rises to be higher than the high threshold voltage VH of the second negative input terminal N2, the buffer output module 30 of the comparator 60 outputs a high level to the first switching transistor Q21, at which time the first switching transistor Q21 is turned on, and the third The MOS transistor Q3 is connected to the circuit, that is, the first negative input terminal N1 is connected to the circuit, and the comparator 60 outputs a high level to the switch module 50, so that the second switch transistor Q22 is turned off, and the third switch transistor Q23 is turned on.
  • the eighteenth MOS transistor Q18 and the nineteenth MOS transistor Q19 discharge the capacitor C1, and the capacitor C1 voltage drops.
  • the comparator 60 compares the voltage of the capacitor C1 of the positive input terminal P with the voltage VL of the first negative input terminal N1, the comparator 60 still outputs a high level, and the eighteenth MOS transistor Q18 and the nineteenth MOS transistor Q19 continue to be capacitors. When C1 is discharged, the voltage of capacitor C1 continues to drop.
  • the buffer output module 30 of the comparator 60 When the voltage of the capacitor C1 drops to be lower than the low threshold voltage VL of the first negative input terminal N1, the buffer output module 30 of the comparator 60 outputs a low level to the first switching transistor Q21 again, and the first switching transistor Q21 is turned off.
  • the third MOS transistor Q3 does not function, that is, the first negative input terminal N1 is not connected to the circuit, and the comparator 60 outputs a low level to the switch module 50, so that the second switch transistor Q22 is turned on, and the third switch transistor Q23 is turned off.
  • the voltage of the capacitor C1 rises, so that the capacitor C1 is periodically charged and discharged, so that the voltage is at a low threshold voltage VL and high.
  • the threshold voltage VH oscillates and an oscillating signal is output.
  • the comparator includes a current mirror module, a comparison module, and a buffer output module
  • the low power oscillator includes a capacitor and a current bias module.
  • the comparison module includes a positive input terminal, a first negative input terminal and a second negative input terminal
  • the capacitor is connected to the positive input terminal of the comparator, when the capacitor voltage is less than the first negative input terminal of the comparator
  • the comparator outputs a low level to the switch module
  • the switch module controls the current bias module to charge the capacitor
  • the switch module controls the current bias module to discharge the capacitor, thereby realizing the periodic charge and discharge of the capacitor through a comparator, and outputting the oscillating signal, reducing the number of comparators, simplifying
  • the circuit structure reduces circuit power consumption and product cost.

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Abstract

本发明公开了一种比较器及低功耗振荡器。其中，所述比较器包括电流镜模块、比较模块和缓冲输出模块，所述低功耗振荡器包括电容、电流偏置模块、开关模块和所述比较器，比较模块包括正输入端、第一负输入端和第二负输入端，所述电容连接比较器的正输入端，当电容电压小于比较器的第一负输入端的低阈值电压时，比较器输出低电平至开关模块，由开关模块控制电流偏置模块给电容充电；当电容电压大于比较器的第二负输入端的高阈值电压时，比较器输出高电平至开关模块，由开关模块控制电流偏置模块给电容放电，从而通过一个比较器即实现了对电容的周期性充放电，并输出振荡信号，减少了比较器的数量，简化了电路结构，降低了电路功耗及产品成本。

Description

一种比较器及低功耗振荡器
技术领域
本发明涉及振荡器技术领域，特别涉及一种比较器及低功耗振荡器。
背景技术
在任何一个电子系统中，振荡器电路都是必不可少的模块。随着成本压力的不断增大，芯片面积需要不断减小，在保证功能的前提下，需要设计更简单的电路结构，能够减小模块的面积并降低功耗。
传统的振荡器一般需要两个比较器，一个电容，一套给电容充放电的偏置电路，给两个比较器分别输入一个高阈值和低阈值，当电容电压大于高阈值时，一个比较器翻转，控制偏置电路放电，电容电压下降，当电容电压小于低阈值时，另一个比较器翻转，控制偏置电路充电，电压上升，如此循环往复，输出振荡信号。这种振荡器的结构原理简单，但是振荡器中的比较器功能单一，振荡器结构复杂，功耗较高。
因而现有技术还有待改进和提高。
发明内容
鉴于上述现有技术的不足之处，本发明的目的在于提供一种比较器及低功耗振荡器，能简化电路结构，降低电路功耗。
为了达到上述目的，本发明采取了以下技术方案：
一种比较器，其包括电流镜模块、比较模块和缓冲输出模块，由电流镜模块为比较模块提供偏置电流，所述比较模块包括正输入端、第一负输入端和第二负输入端，所述正输入端连接外部端，所述第一负输入端和第二负输入端分别输入低阈值电压和高阈值电压，由比较模块将正输入端的电压与低阈值电压和高阈值电压比较，并输出比较结果至缓冲输出模块，当正输入端的电压小于低阈值电压时，缓冲输出模块输出低电平至比较模块；当正输入端的电压大于高阈值电压时，缓冲输出模块输出高电平至比较模块。
所述的比较器中，所述比较模块包括第一比较单元、第二比较单元和放大单元，由第二比较单元将比较结果输出至放大单元，所述第一比较单元包括所述第一负输入端，所述第二比较单元包括所述正输入端和第二负输入端，由放大单元将比较结果放大后输出至缓冲输出模块，当正输入端的电压小于第一负输入端的低阈值电压时，缓冲输出模块输出低电平至第一比较单元，控制第一比较单元关断；当正输入端的电压大于第二负输入端的高阈值电压时，缓冲输出模块输出高电平至第一比较单元，控制第一比较单元开启，所述低阈值电压小于所述高阈值电压。
所述的比较器中，所述电流镜模块包括第一MOS管和第二MOS管；所述第一MOS管的源极和第二MOS管的源极连接VCC供电端，第一MOS管的栅极连接第一MOS管的漏极、第二MOS管的栅极和第一偏置端，所述第二MOS管的漏极连接比较模块。
所述的比较器中，所述第一比较单元包括第三MOS管和第一开关管，所述第二比较单元包括第四MOS管、第五MOS管、第六MOS管和第七MOS管，所述放大单元包括第八MOS管和第九MOS管；所述第三MOS管的源极、第四MOS管的源极和第六MOS管的源极连接第二MOS管的漏极，所述第三MOS管的栅极为比较器的第一负输入端，第三MOS管的漏极连接第一开关管的漏极，所述第一开关管的栅极连接缓冲输出模块，所述第四MOS管的栅极为比较器的第二负输入端，所述第四MOS管的漏极连接第一开关管的源极、第五MOS管的漏极和第五MOS管的栅极，所述第五MOS管的栅极连接第七MOS管的栅极，所述第六MOS管的栅极为比较器的正输入端，第六MOS管的漏极连接第九MOS管的栅极和第七MOS管的漏极，所述第八MOS管的栅极连接第二MOS管的栅极，第八MOS管的源极连接VCC供电端，第八MOS管的漏极连接第九MOS管的漏极和缓冲输出模块，所述第五MOS管的源极、第七MOS管的源极和第九MOS管的源极接地。
一种低功耗振荡器，包括电容和电流偏置模块，所述低功耗振荡器还包括开关模块和如上所述的比较器，所述电容连接所述比较器的正输入端，当电容电压小于比较器的第一负输入端的低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制电流偏置模块给电容充电；当电容电压大于比较器的第二负输入端的高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制电流偏置模块给电容放电，所述低阈值电压小于所述高阈值电压。
所述的低功耗振荡器中，所述电流偏置模块包括第一电流镜单元和第二电流镜单元，当电容电压小于低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制第一电流镜单元给电容充电；当电容电压大于高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制第二电流镜单元给电容放电。
所述的低功耗振荡器中，所述开关模块包括第一开关单元和第二开单元，当电容电压小于低阈值电压时，所述比较器输出低电平至开关模块，第一开关单元开启，第二开关单元关断，使第一电流镜单元给电容充电；当电容电压大于高阈值电压时，所述比较器输出高电平至开关模块，第一开关单元关断，第二开关单元开启，使第二电流镜单元给电容放电。
所述的低功耗振荡器中，所述第一开关单元包括第二开关管，所述第二开关单元包括第三开关管；第二开关管的源极连接第一电流镜单元，所述第二开关管的漏极连接第三开关管的漏极、还连接比较器的正输入端和电容的一端，所述第二开关管的栅极连接第三开关管的栅极和比较器的输出端，所述第三开关管的源极连接第二电流镜单元。
所述的低功耗振荡器中，所述第一电流镜单元包括第十MOS管、第十一MOS管、第十二MOS管和第十三MOS管；所述第十MOS管的源极和第十二MOS管的源极连接VCC供电端，所述第十MOS管的栅极连接第十二MOS管的栅极、第十MOS管的漏极和第十一MOS管的源极，所述第十一MOS管的栅极连接第十三MOS管的栅极、第十一MOS管的漏极和第二电流镜单元，所述第十二MOS管的漏极连接第十三MOS管的源极，所述第十三MOS管的漏极连接第二开关管的源极。
所述的低功耗振荡器中，所述第二电流镜单元包括第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管和第十九MOS管；所述第十四MOS管的漏极连接第二偏置端、还连接第十四MOS管的栅极，所述第十四MOS管的栅极还连接第十六MOS管的栅极及第十八MOS管的栅极，所述第十四MOS管的源极连接第十五MOS管的漏极和第十五MOS管的栅极，所述第十五MOS管的栅极还连接第十七MOS管的栅极及第十九MOS管的栅极，所述第十六MOS管的漏极连接第十一MOS管的漏极、第十一MOS管的栅极和第十三MOS管的栅极，所述第十六MOS管的源极连接第十七MOS管的漏极，所述第十八MOS管的漏极连接第三开关管的源极，所述第十八MOS管的源极连接第十九MOS管的漏极，所述第十五MOS管的源极、第十七MOS管的源极和第十九MOS管的源极连接电容的另一端和地。
相较于现有技术，本发明提供的比较器及低功耗振荡器中，所述比较器包括电流镜模块、比较模块和缓冲输出模块，所述低功耗振荡器包括电容、电流偏置模块、开关模块和所述比较器，比较模块包括正输入端、第一负输入端和第二负输入端，所述电容连接比较器的正输入端，当电容电压小于比较器的第一负输入端的低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制电流偏置模块给电容充电；当电容电压大于比较器的第二负输入端的高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制电流偏置模块给电容放电，从而通过一个比较器即实现了对电容的周期性充放电，并输出振荡信号，减少了比较器的数量，简化了电路结构，降低了电路功耗及产品成本。
附图说明
图1 为本发明提供的比较器的结构框图；
图2 为本发明提供的比较器的电路原理图；
图3 为本发明提供的低功耗振荡器的结构框图；
图4 为本发明提供的低功耗振荡器的电路原理图。
具体实施方式
鉴于现有技术中振荡器的结构复杂、功耗较高等缺点，本发明的目的在于提供一种比较器及低功耗振荡器，能通过一个比较器实现传统的两个比较器的功能，简化了电路结构，降低了电路功耗及产品成本。
为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
请参阅图1，本发明提供的比较器包括电流镜模块10、比较模块20和缓冲输出模块30，所述电流镜模块10、比较模块20和缓冲输出模块30依次连接，特别地，所述比较器设置有正输入端P、第一负输入端N1和第二负输入端N2，所述正输入端P连接外部电压，所述第一负输入端N1和第二负输入端N2分别输入低阈值电压和高阈值电压，由电流镜模块10为比较模块20提供偏置电流，由比较模块20将正输入端P的电压与第一负输入端N1的低阈值电压和第二负输入端N2的高阈值电压比较，并输出比较结果至缓冲输出模块30，当正输入端P的电压小于第一负输入端N1的低阈值电压时，缓冲输出模块30输出低电平至比较模块20；当正输入端P的电压大于第二负输入端N2的高阈值电压时，缓冲输出模块30输出高电平至比较模块20，从而实现了同时将正输入的电压与第一负输入端N1的电压和第二负输入端N2的电压比较并输出比较结果，丰富了比较器的功能，简化了电路结构。
具体地，所述比较模块20包括第一比较单元201、第二比较单元202和放大单元203，所述第一比较单元201包括所述第一负输入端N1，所述第二比较单元202包括所述正输入端P和第二负输入端N2，所述第一比较单元201、第二比较单元202和放大单元203均连接电流镜模块10，所述缓冲输出模块30连接第一比较单元201和放大单元203，由第二比较单元202将比较结果输出至放大单元203，由放大单元203将比较结果放大后输出至缓冲输出模块30，当正输入端P的电压小于第一负输入端N1的低阈值电压时，缓冲输出模块30输出低电平至第一比较单元201，控制第一比较单元201关断；当正输入端P的电压大于第二负输入端N2的高阈值电压时，缓冲输出模块30输出高电平至第一比较单元201，控制第一比较单元201开启，所述低阈值电压小于所述高阈值电压。
本发明通过在比较模块20中设置第一比较单元201和第二比较单元202，所述第一比较单元201连接比较器的第一负输入端N1，第二比较单元202连接比较器的正输入端P和第二负输入端N2，当正输入端P的电压小于第一负输入端N1的低阈值电压时，第二比较单元202将比较结果输出至放大单元203，缓冲输出模块30输出低电平至第一比较单元201，控制第一比较单元201关断，此时第一负输入端N1不起作用，将正输入端P的电压与第二负输入端N2的高阈值电压比较，当正输入端P的电压大于第二负输入端N2的高阈值电压时，缓冲输出模块30输出高电平至第一比较单元201，控制第一比较单元201开启，第一负输入端N1重新接入到电路中，当正输入端P的电压小于第一负输入端N1的低阈值电压时，缓冲输出模块30输出低电平至第一比较单元201，控制第一比较单元再次201关断，如此循环往复，从而实现了同时将正输入端P的电压与第一负输入端N1的低阈值电压和第二负输入端N2的高阈值电压比较，由一个比较器代替传统的两个比较器，简化了电路结构。
进一步地，请一并参阅图2，所述电流镜模块10包括第一MOS管Q1和第二MOS管Q2；所述第一MOS管Q1的源极和第二MOS管Q2的源极连接VCC供电端，第一MOS管Q1的栅极连接第一MOS管Q1的漏极、第二MOS管Q2的栅极和第一偏置端BIAS1，所述第二MOS管Q2的漏极连接比较模块20，其中，所述第一MOS管Q1和第二MOS管Q2为PMOS管，为比较模块20提供偏置电流。
所述第一比较单元201包括第三MOS管Q3和第一开关管Q21，所述第二比较单元202包括第四MOS管Q4、第五MOS管Q5、第六MOS管Q6和第七MOS管Q7，所述放大单元203包括第八MOS管Q8和第九MOS管Q9；其中，所述第一开关管Q21为NMOS管，当其栅极为高电平时导通，当其栅极为低电平时截止。
所述第三MOS管Q3的源极、第四MOS管Q4的源极和第六MOS管Q6的源极连接第二MOS管Q2的漏极，所述第三MOS管Q3的栅极为比较器的第一负输入端N1，第三MOS管Q3的漏极连接第一开关管Q21的漏极，所述第一开关管Q21的栅极连接缓冲输出模块30，所述第四MOS管Q4的栅极为比较器的第二负输入端N2，所述第四MOS管Q4的漏极连接第一开关管Q21的源极、第五MOS管Q5的漏极和第五MOS管Q5的栅极，所述第五MOS管Q5的栅极连接第七MOS管Q7的栅极，所述第六MOS管Q6的栅极为比较器的正输入端P，第六MOS管Q6的漏极连接第九MOS管Q9的栅极和第七MOS管Q7的漏极，所述第八MOS管Q8的栅极连接第二MOS管Q2的栅极，第八MOS管Q8的源极连接VCC供电端，第八MOS管Q8的漏极连接第九MOS管Q9的漏极和缓冲输出模块30，所述第五MOS管Q5的源极、第七MOS管Q7的源极和第九MOS管Q9的源极接地，其中，所述第三MOS管Q3、第四MOS管Q4、第六MOS管Q6和第八MOS管Q8为PMOS管，所述第五MOS管Q5、第七MOS管Q7、第九MOS管Q9为NMOS管。
本发明提供的比较器通过第一MOS管Q1和第二MOS管Q2组成电流镜提供偏置电流，由第四MOS管Q4、第五MOS管Q5、第六MOS管Q6和第七MOS管Q7组成经典差分电路，在此基础上增加第三MOS管Q3和第一开关管Q21，其中第三MOS管Q3与第四MOS管Q4和第六MOS管Q6尺寸相同，从而与现有技术中的比较器相比，本发明提供的比较器增加了一个负输入端，实现了将正输入端的电压同时与两个负输入端的电压进行精确的比较，另外，由第八MOS管Q8和第九MOS管Q9组成比较器第二级，可对比较结果进行增益放大，进一步确保了比较结果的精确性。
请继续参阅图2，所述缓冲输出模块30包括第一反相器I1和第二反相器I2，所述第一反相器I1的输入端连接第八MOS管Q8的漏极和第九MOS管Q9的漏极，第一反相器I1的输出端连接第二反相器I2的输入端，第二反相器I2的输出端连接第一开关管Q21的栅极，由第一反相器I1和第二反相器I2组成缓冲级。
本发明还相应提供一种低功耗振荡器，如图3和图4所示，所述低功耗振荡器包括电容C1、电流偏置模块40、开关模块50和如上所述的比较器60，所述电容C1连接电流偏置模块40和比较器60的正输入端P，所述电流偏置模块40连接开关模块50，所述开关模块50还连接比较器60，当电容C1电压小于比较器60的第一负输入端N1的低阈值电压VL时，所述比较器60输出低电平至开关模块50，由开关模块50控制电流偏置模块40给电容C1充电；当电容C1电压大于比较器60的第二负输入端N2的高阈值电压VH时，所述比较器60输出高电平至开关模块50，由开关模块50控制电流偏置模块40给电容C1放电，所述低阈值电压小于所述高阈值电压。
本发明提供的低功耗振荡器通过设置电容C1、电流偏置模块40、开关模块50和如上所述的、具有两个负输入端的比较器60，所述比较器60的正输入端P输入电容C1电压，第一负输入端N1输入低阈值电压VL，第二负输入端N2输入高阈值电压VH，当电容C1电压小于低阈值电压VL时，比较器60输出低电平至开关模块50，由开关模块50控制电流偏置模块40给电容C1充电，电容C1电压上升；当电容C1电压大于高阈值电压VH时，比较器60输出高电平至开关模块50，由开关模块50控制电流偏置模块40给电容C1放电，电容C1电压下降，直到电容C1电压小于低阈值电压VL时，比较器60再次输出低电平，由开关模块50控制电流偏置模块40给电容C1充电，如此循环往复，对电容C1进行周期性充放电，使电容C1电压在低阈值电压VL和高阈值电压VH之间振荡，产生振荡信号，从而通过一个比较器即实现了振荡器正常工作，降低了电路功耗。
具体地，所述电流偏置模块40包括第一电流镜单元401和第二电流镜单元402，当电容C1电压小于低阈值电压VL时，所述比较器60输出低电平至开关模块50，由开关模块50控制第一电流镜单元401给电容C1充电；当电容C1电压大于高阈值电压VH时，所述比较器60输出高电平至开关模块50，由开关模块50控制第二电流镜单元402给电容C1放电，通过开关模块50控制第一电流镜单元401和第二电流镜单元402分别对电容C1进行充电和放电，使电容C1电压在低阈值电压VL和高阈值电压VH之间振荡，产生振荡信号。
进一步地，所述开关模块50包括第一开关单元501和第二开单元502，当电容C1电压小于低阈值电压VL时，所述比较器60输出低电平至开关模块50，第一开关单元501开启，第二开关单元502关断，使第一电流镜单元401给电容C1充电；当电容C1电压大于高阈值电压VH时，所述比较器60输出高电平至开关模块50，第一开关单元501关断，第二开关单元502开启，使第二电流镜单元402给电容C1放电，由比较器60根据比较结果输出高低电平，从而控制第一开关单元501和第二开关单元502的开启和关断，进而控制第一电流镜单元401和第二电流镜单元402分别对电容C1进行充电和发电，实现了根据输出结果准确控制对电容C1的充放电行为，提高了振荡器工作的可靠性。
请继续参阅图4，所述第一开关单元501包括第二开关管Q22，所述第二开关单元502包括第三开关管Q23；其中，所述第二开关管Q22为PMOS管，当其栅极为高电平时截止，当其栅极为低电平时导通；其中，所述第三开关管Q23为NMOS管，当其栅极为高电平时导通，当其栅极为低电平时截止。
第二开关管Q22的源极连接第一电流镜单元401，所述第二开关管Q22的漏极连接第三开关管Q23的漏极、还连接比较器60的正输入端和电容C1的一端，所述第二开关管Q22的栅极连接第三开关管Q23的栅极和比较器60的输出端，所述第三开关管Q23的源极连接第二电流镜单元402。
所述第一电流镜单元401包括第十MOS管Q10、第十一MOS管Q11、第十二MOS管Q12和第十三MOS管Q13；所述第十MOS管Q10的源极和第十二MOS管Q12的源极连接VCC供电端，所述第十MOS管Q10的栅极连接第十二MOS管Q12的栅极、第十MOS管Q10的漏极和第十一MOS管Q11的源极，所述第十一MOS管Q11的栅极连接第十三MOS管Q13的栅极、第十一MOS管Q11的漏极和第二电流镜单元402，所述第十二MOS管Q12的漏极连接第十三MOS管Q13的源极，所述第十三MOS管Q13的漏极连接第二开关管Q22的源极，其中，第十MOS管Q10、第十一MOS管Q11、第十二MOS管Q12和第十三MOS管Q13均为PMOS管，由第十二MOS管Q12和第十三MOS管Q13为电容C1提供充电电流。
进一步地，所述第二电流镜单元402包括第十四MOS管Q14、第十五MOS管Q15、第十六MOS管Q16、第十七MOS管Q17、第十八MOS管Q18和第十九MOS管Q19；所述第十四MOS管Q14的漏极连接第二偏置端BIAS2、还连接第十四MOS管Q14的栅极，所述第十四MOS管Q14的栅极还连接第十六MOS管Q16的栅极及第十八MOS管Q18的栅极，所述第十四MOS管Q14的源极连接第十五MOS管Q15的漏极和第十五MOS管Q15的栅极，所述第十五MOS管Q15的栅极还连接第十七MOS管Q17的栅极及第十九MOS管Q19的栅极，所述第十六MOS管Q16的漏极连接第十一MOS管Q11的漏极、第十一MOS管Q11的栅极和第十三MOS管Q13的栅极，所述第十六MOS管Q16的源极连接第十七MOS管Q17的漏极，所述第十八MOS管Q18的漏极连接第三开关管Q23的源极，所述第十八MOS管Q18的源极连接第十九MOS管Q19的漏极，所述第十五MOS管Q15的源极、第十七MOS管Q17的源极和第十九MOS管Q19的源极连接电容C1的另一端和地，其中，第十四MOS管Q14、第十五MOS管Q15、第十六MOS管Q16、第十七MOS管Q17、第十八MOS管Q18和第十九MOS管Q19均为NMOS管，由第十八MOS管Q18和第十九MOS管Q19为电容C1提供放电电流。
为更好的理解本发明的技术方案，以下结合图2和图4，举具体实施例对本发明的比较器及低功耗振荡器的工作过程进行详细说明：
比较器60的正输入端P输入电容C1电压，第一负输入端N1输入低阈值电压VL，第二负输入端N2输入高阈值电压VH。
初始状态时，正输入端P输入的电容C1电压为零，比较器60的缓冲输出模块30输出低电平至第一开关管Q21，此时第一开关管Q21关断，第三MOS管Q3不起作用，即第一负输入端N1未接入到电路中，同时比较器60输出低电平至开关模块50，此时第二开关管Q22开启，第三开关管Q23关断，由第十二MOS管Q12和第十三MOS管Q13为电容C1充电，电容C1电压上升。
当电容C1电压上升至大于第二负输入端N2的高阈值电压VH时，比较器60的缓冲输出模块30输出高电平至第一开关管Q21，此时第一开关管Q21开启，第三MOS管Q3接入到电路中，即第一负输入端N1接入到电路中，同时比较器60输出高电平至开关模块50，使第二开关管Q22关断，第三开关管Q23开启，由第十八MOS管Q18和第十九MOS管Q19为电容C1放电，电容C1电压下降，由于第一负输入端N1的低阈值电压VL小于第二负输入端N2的高阈值电压VH，比较器60将正输入端P的电容C1电压与第一负输入端N1的电压VL进行比较，比较器60仍然输出高电平，第十八MOS管Q18和第十九MOS管Q19继续为电容C1放电，电容C1电压继续下降。
当电容C1电压下降至小于第一负输入端N1的低阈值电压VL时，比较器60的缓冲输出模块30再次输出低电平至第一开关管Q21，此时第一开关管Q21关断，第三MOS管Q3不起作用，即第一负输入端N1未接入到电路中，同时比较器60输出低电平至开关模块50，使第二开关管Q22开启，第三开关管Q23关断，由第十二MOS管Q12和第十三MOS管Q13再次为电容C1充电，电容C1电压上升，如此循环往复，对电容C1进行周期性充放电，使其电压在低阈值电压VL和高阈值电压VH间振荡，并输出振荡信号。
综上所述，本发明提供的比较器及低功耗振荡器中，所述比较器包括电流镜模块、比较模块和缓冲输出模块，所述低功耗振荡器包括电容、电流偏置模块、开关模块和所述比较器，比较模块包括正输入端、第一负输入端和第二负输入端，所述电容连接比较器的正输入端，当电容电压小于比较器的第一负输入端的低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制电流偏置模块给电容充电；当电容电压大于比较器的第二负输入端的高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制电流偏置模块给电容放电，从而通过一个比较器即实现了对电容的周期性充放电，并输出振荡信号，减少了比较器的数量，简化了电路结构，降低了电路功耗及产品成本。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围.

Claims (12)

  1. 比较器，其特征在于，包括电流镜模块、比较模块和缓冲输出模块，由一种电流镜模块为比较模块提供偏置电流，所述比较模块包括正输入端、第一负输入端和第二负输入端，所述正输入端连接外部端，所述第一负输入端和第二负输入端分别输入低阈值电压和高阈值电压，由比较模块将正输入端的电压与低阈值电压和高阈值电压比较，并输出比较结果至缓冲输出模块，当正输入端的电压小于低阈值电压时，缓冲输出模块输出低电平至比较模块；当正输入端的电压大于高阈值电压时，缓冲输出模块输出高电平至比较模块。
  2. 根据权利要求1所述的比较器，其特征在于，所述电流镜模块包括第一MOS管和第二MOS管；所述第一MOS管的源极和第二MOS管的源极连接VCC供电端，第一MOS管的栅极连接第一MOS管的漏极、第二MOS管的栅极和第一偏置端，所述第二MOS管的漏极连接比较模块。
  3. 一种比较器，其特征在于，包括电流镜模块、比较模块和缓冲输出模块，由电流镜模块为比较模块提供偏置电流，所述比较模块包括正输入端、第一负输入端和第二负输入端，所述正输入端连接外部端，所述第一负输入端和第二负输入端分别输入低阈值电压和高阈值电压，由比较模块将正输入端的电压与低阈值电压和高阈值电压比较，并输出比较结果至缓冲输出模块，当正输入端的电压小于低阈值电压时，缓冲输出模块输出低电平至比较模块；当正输入端的电压大于高阈值电压时，缓冲输出模块输出高电平至比较模块；
    所述比较模块包括第一比较单元、第二比较单元和放大单元，所述第一比较单元包括所述第一负输入端，所述第二比较单元包括所述正输入端和第二负输入端，由第二比较单元将比较结果输出至放大单元，由放大单元将比较结果放大后输出至缓冲输出模块，当正输入端的电压小于第一负输入端的低阈值电压时，缓冲输出模块输出低电平至第一比较单元，控制第一比较单元关断；当正输入端的电压大于第二负输入端的高阈值电压时，缓冲输出模块输出高电平至第一比较单元，控制第一比较单元开启，所述低阈值电压小于所述高阈值电压。
  4. 根据权利要求3所述的比较器，其特征在于，所述第一比较单元包括第三MOS管和第一开关管，所述第二比较单元包括第四MOS管、第五MOS管、第六MOS管和第七MOS管，所述放大单元包括第八MOS管和第九MOS管；所述第三MOS管的源极、第四MOS管的源极和第六MOS管的源极均连接第二MOS管的漏极，所述第三MOS管的栅极为比较器的第一负输入端，第三MOS管的漏极连接第一开关管的漏极，所述第一开关管的栅极连接缓冲输出模块，所述第四MOS管的栅极为比较器的第二负输入端，所述第四MOS管的漏极连接第一开关管的源极、第五MOS管的漏极和第五MOS管的栅极，所述第五MOS管的栅极连接第七MOS管的栅极，所述第六MOS管的栅极为比较器的正输入端，第六MOS管的漏极连接第九MOS管的栅极和第七MOS管的漏极，所述第八MOS管的栅极连接第二MOS管的栅极，第八MOS管的源极连接VCC供电端，第八MOS管的漏极连接第九MOS管的漏极和缓冲输出模块，所述第五MOS管的源极、第七MOS管的源极和第九MOS管的源极接地。
  5. 根据权利要求3所述的比较器，其特征在于，所述电流镜模块包括第一MOS管和第二MOS管；所述第一MOS管的源极和第二MOS管的源极连接VCC供电端，第一MOS管的栅极连接第一MOS管的漏极、第二MOS管的栅极和第一偏置端，所述第二MOS管的漏极连接比较模块。
  6. 根据权利要求4所述的比较器，其特征在于，所述电流镜模块包括第一MOS管和第二MOS管；所述第一MOS管的源极和第二MOS管的源极连接VCC供电端，第一MOS管的栅极连接第一MOS管的漏极、第二MOS管的栅极和第一偏置端，所述第二MOS管的漏极连接比较模块。
  7. 一种低功耗振荡器，包括电容和电流偏置模块，其特征在于，所述低功耗振荡器还包括开关模块和如权利要求1所述的比较器，所述电容连接所述比较器的正输入端，当电容电压小于比较器的第一负输入端的低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制电流偏置模块给电容充电；当电容电压大于比较器的第二负输入端的高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制电流偏置模块给电容放电，所述低阈值电压小于所述高阈值电压。
  8. 根据权利要求7所述的低功耗振荡器，其特征在于，所述电流偏置模块包括第一电流镜单元和第二电流镜单元，当电容电压小于低阈值电压时，所述比较器输出低电平至开关模块，由开关模块控制第一电流镜单元给电容充电；当电容电压大于高阈值电压时，所述比较器输出高电平至开关模块，由开关模块控制第二电流镜单元给电容放电。
  9. 根据权利要求8所述的低功耗振荡器，其特征在于，所述开关模块包括第一开关单元和第二开单元，当电容电压小于低阈值电压时，所述比较器输出低电平至开关模块，第一开关单元开启、第二开关单元关断，使第一电流镜单元给电容充电；当电容电压大于高阈值电压时，所述比较器输出高电平至开关模块，第一开关单元关断、第二开关单元开启，使第二电流镜单元给电容放电。
  10. 根据权利要求9所述的低功耗振荡器，其特征在于，所述第一开关单元包括第二开关管，所述第二开关单元包括第三开关管；第二开关管的源极连接第一电流镜单元，所述第二开关管的漏极连接第三开关管的漏极、还连接比较器的正输入端和电容的一端，所述第二开关管的栅极连接第三开关管的栅极和比较器的输出端，所述第三开关管的源极连接第二电流镜单元。
  11. 根据权利要求10所述的低功耗振荡器，其特征在于，所述第一电流镜单元包括第十MOS管、第十一MOS管、第十二MOS管和第十三MOS管；所述第十MOS管的源极和第十二MOS管的源极连接VCC供电端，所述第十MOS管的栅极连接第十二MOS管的栅极、第十MOS管的漏极和第十一MOS管的源极，所述第十一MOS管的栅极连接第十三MOS管的栅极、第十一MOS管的漏极和第二电流镜单元，所述第十二MOS管的漏极连接第十三MOS管的源极，所述第十三MOS管的漏极连接第二开关管的源极。
  12. 根据权利要求11所述的低功耗振荡器，其特征在于，所述第二电流镜单元包括第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管和第十九MOS管；所述第十四MOS管的漏极连接第二偏置端、还连接第十四MOS管的栅极，所述第十四MOS管的栅极还连接第十六MOS管的栅极及第十八MOS管的栅极，所述第十四MOS管的源极连接第十五MOS管的漏极和第十五MOS管的栅极，所述第十五MOS管的栅极还连接第十七MOS管的栅极及第十九MOS管的栅极，所述第十六MOS管的漏极连接第十一MOS管的漏极、第十一MOS管的栅极和第十三MOS管的栅极，所述第十六MOS管的源极连接第十七MOS管的漏极，所述第十八MOS管的漏极连接第三开关管的源极，所述第十八MOS管的源极连接第十九MOS管的漏极，所述第十五MOS管的源极、第十七MOS管的源极和第十九MOS管的源极连接电容的另一端和地。
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